From 44b97460395f11be75f58cbfffbb454158bab4c3 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Mon, 10 Nov 2014 22:16:09 -0600 Subject: [PATCH] radeon_hd: Fix Spread Spectrum clock decimal place * As 104Mhz is stores as 10400 on atombios, and 104000 everywhere else... this conversion was going the wrong direction. * Shrink the stored value to 10Khz units to properly compare to the AtomBIOS value --- src/add-ons/accelerants/radeon_hd/pll.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/add-ons/accelerants/radeon_hd/pll.cpp b/src/add-ons/accelerants/radeon_hd/pll.cpp index 077c9c05fb..0eb6ef5366 100644 --- a/src/add-ons/accelerants/radeon_hd/pll.cpp +++ b/src/add-ons/accelerants/radeon_hd/pll.cpp @@ -241,7 +241,7 @@ pll_asic_ss_probe(pll_info* pll, uint32 ssID) continue; } TRACE("%s: ss match found\n", __func__); - if (pll->pixelClock * 10 > B_LENDIAN_TO_HOST_INT32( + if (pll->pixelClock / 10 > B_LENDIAN_TO_HOST_INT32( ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) { TRACE("%s: pixelClock > targetClockRange!\n", __func__); continue; @@ -270,7 +270,7 @@ pll_asic_ss_probe(pll_info* pll, uint32 ssID) continue; } TRACE("%s: ss match found\n", __func__); - if (pll->pixelClock * 10 > B_LENDIAN_TO_HOST_INT32( + if (pll->pixelClock / 10 > B_LENDIAN_TO_HOST_INT32( ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) { TRACE("%s: pixelClock > targetClockRange!\n", __func__); continue; @@ -300,7 +300,7 @@ pll_asic_ss_probe(pll_info* pll, uint32 ssID) continue; } TRACE("%s: ss match found\n", __func__); - if (pll->pixelClock * 10 > B_LENDIAN_TO_HOST_INT32( + if (pll->pixelClock / 10 > B_LENDIAN_TO_HOST_INT32( ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) { TRACE("%s: pixelClock > targetClockRange!\n", __func__); continue;