diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index 4fa30e7e37..8538495d03 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -224,6 +224,8 @@ struct DeviceType {
 			return 7;
 		if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
 			return 8;
+		if (InGroup(INTEL_GROUP_JSL))
+			return 11;
 		if (InFamily(INTEL_FAMILY_LAKE))
 			return 9;
 
@@ -596,12 +598,46 @@ struct intel_free_graphics_memory {
 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe)	(1 << (15 + pipe))
 #define PCH_MASTER_INT_CTL_GLOBAL_BDW				(1 << 31)
 
-#define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe)		(0x44400 + (pipe - 1) * 0x10)
-#define PCH_INTERRUPT_PIPE_MASK_BDW(pipe)		(0x44404 + (pipe - 1) * 0x10)
-#define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe)	(0x44408 + (pipe - 1) * 0x10)
-#define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe)	(0x4440c + (pipe - 1) * 0x10)
+#define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe)		(0x44400 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_ISR
+#define PCH_INTERRUPT_PIPE_MASK_BDW(pipe)		(0x44404 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IMR
+#define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe)	(0x44408 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IIR
+#define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe)	(0x4440c + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IER
+
+#define GEN8_DE_PORT_ISR						0x44440
+#define GEN8_DE_PORT_IMR						0x44444
+#define GEN8_DE_PORT_IIR						0x44448
+#define GEN8_DE_PORT_IER						0x4444c
+#define		GEN8_AUX_CHANNEL_A					(1 << 0)
+#define		GEN9_AUX_CHANNEL_B					(1 << 25)
+#define		GEN9_AUX_CHANNEL_C					(1 << 26)
+#define		GEN9_AUX_CHANNEL_D					(1 << 27)
+#define		CNL_AUX_CHANNEL_F					(1 << 28)
+#define		ICL_AUX_CHANNEL_E					(1 << 29)
+
+#define GEN8_DE_MISC_ISR						0x44460
+#define GEN8_DE_MISC_IMR						0x44464
+#define GEN8_DE_MISC_IIR						0x44468
+#define GEN8_DE_MISC_IER						0x4446c
+#define		GEN8_DE_EDP_PSR						(1 << 19)
+
+#define PCH_INTERRUPT_VBLANK_BDW				(1 << 0)						// GEN8_PIPE_VBLANK
+#define GEN8_PIPE_VSYNC							(1 << 1)
+#define GEN8_PIPE_SCAN_LINE_EVENT				(1 << 2)
+
+#define GEN11_DISPLAY_INT_CTL					0x44200			// same as PCH_MASTER_INT_CTL_BDW
+#define GEN11_GFX_MSTR_IRQ						0x190010
+#define GEN11_MASTER_IRQ						(1 << 31)
+#define GEN11_GT_DW1_IRQ						(1 << 1)
+#define GEN11_GT_DW0_IRQ						(1 << 0)
+
+#define GEN11_GT_INTR_DW0						0x190018
+#define GEN11_GT_INTR_DW1						0x19001c
+
+#define GEN11_GU_MISC_IMR						0x444f4
+#define GEN11_GU_MISC_IIR						0x444f8
+#define GEN11_GU_MISC_IER						0x444fc
+#define 	GEN11_GU_MISC_GSE					(1 << 27)
 
-#define PCH_INTERRUPT_VBLANK_BDW				(1 << 0)
 
 // graphics port control (i.e. G45)
 #define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index 48d6eaa11f..484e8bcea6 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -100,6 +100,14 @@ bdw_enable_interrupts(intel_info& info, pipe_index pipe, bool enable)
 }
 
 
+static void
+gen11_enable_global_interrupts(intel_info& info, bool enable)
+{
+	write32(info, GEN11_GFX_MSTR_IRQ, enable ? GEN11_MASTER_IRQ : 0);
+	read32(info, GEN11_GFX_MSTR_IRQ);
+}
+
+
 static void
 bdw_enable_global_interrupts(intel_info& info, bool enable)
 {
@@ -120,7 +128,7 @@ bdw_check_interrupt(intel_info& info, pipes& which)
 	ASSERT(info.device_type.Generation() >= 12 || !which.HasPipe(INTEL_PIPE_D));
 
 	which.ClearPipe(INTEL_PIPE_ANY);
-	const uint32 interrupt = read32(info, PCH_MASTER_INT_CTL_BDW);
+	uint32 interrupt = read32(info, PCH_MASTER_INT_CTL_BDW);
 	if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_A)) != 0)
 		which.SetPipe(INTEL_PIPE_A);
 	if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_B)) != 0)
@@ -129,6 +137,12 @@ bdw_check_interrupt(intel_info& info, pipes& which)
 		which.SetPipe(INTEL_PIPE_C);
 	if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_D)) != 0)
 		which.SetPipe(INTEL_PIPE_D);
+	interrupt &= ~(PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_A)
+		| PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_B)
+		| PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_C)
+		| PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_D));
+	if (interrupt != 0)
+		dprintf("bdw_check_interrupt %" B_PRIx32 "\n", interrupt);
 	return which.HasPipe(INTEL_PIPE_ANY);
 }
 
@@ -428,9 +442,34 @@ init_interrupt_handler(intel_info &info)
 			status = install_io_interrupt_handler(info.irq,
 				&bdw_interrupt_handler, (void*)&info, 0);
 			if (status == B_OK) {
-				bdw_enable_global_interrupts(info, true);
 				bdw_enable_interrupts(info, INTEL_PIPE_A, true);
 				bdw_enable_interrupts(info, INTEL_PIPE_B, true);
+				if (info.device_type.Generation() >= 11)
+					bdw_enable_interrupts(info, INTEL_PIPE_C, true);
+				bdw_enable_global_interrupts(info, true);
+
+				if (info.device_type.Generation() >= 11) {
+					uint32 mask = GEN8_AUX_CHANNEL_A;
+					mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D;
+					mask |= CNL_AUX_CHANNEL_F;
+					mask |= ICL_AUX_CHANNEL_E;
+					read32(info, GEN8_DE_PORT_ISR);
+					write32(info, GEN8_DE_PORT_IER, mask);
+					write32(info, GEN8_DE_PORT_IMR, ~mask);
+					read32(info, GEN8_DE_PORT_IMR);
+
+					read32(info, GEN8_DE_MISC_ISR);
+					write32(info, GEN8_DE_MISC_IER, GEN8_DE_EDP_PSR);
+					write32(info, GEN8_DE_MISC_IMR, ~GEN8_DE_EDP_PSR);
+					read32(info, GEN8_DE_MISC_IMR);
+
+					read32(info, GEN11_GU_MISC_IIR);
+					write32(info, GEN11_GU_MISC_IER, GEN11_GU_MISC_GSE);
+					write32(info, GEN11_GU_MISC_IMR, ~GEN11_GU_MISC_GSE);
+					read32(info, GEN11_GU_MISC_IMR);
+					// Missing: Hotplug
+					gen11_enable_global_interrupts(info, true);
+				}
 			}
 		} else {
 			status = install_io_interrupt_handler(info.irq,
@@ -660,13 +699,13 @@ intel_extreme_init(intel_info &info)
 		info.shared_info->pll_info.max_frequency = 350000;
 			// 350 MHz RAM DAC speed
 		info.shared_info->pll_info.min_frequency = 25000;		// 25 MHz
-	} else if ((info.device_type.Generation() == 9) &&
+	} else if ((info.device_type.Generation() >= 9) &&
 				info.device_type.InGroup(INTEL_GROUP_SKY)) {
 		info.shared_info->pll_info.reference_frequency = 24000;	// 24 MHz
 		info.shared_info->pll_info.max_frequency = 350000;
 			// 350 MHz RAM DAC speed
 		info.shared_info->pll_info.min_frequency = 25000;		// 25 MHz
-	} else if (info.device_type.Generation() == 9) {
+	} else if (info.device_type.Generation() >= 9) {
 		uint32 refInfo =
 			(read32(info, ICL_DSSM) & ICL_DSSM_REF_FREQ_MASK) >> ICL_DSSM_REF_FREQ_SHIFT;
 		switch (refInfo) {
@@ -774,6 +813,9 @@ intel_extreme_uninit(intel_info &info)
 	if (!info.fake_interrupts && info.shared_info->vblank_sem > 0) {
 		// disable interrupt generation
 		if (info.device_type.Generation() >= 8) {
+			if (info.device_type.Generation() >= 11) {
+				gen11_enable_global_interrupts(info, false);
+			}
 			bdw_enable_global_interrupts(info, false);
 			remove_io_interrupt_handler(info.irq, bdw_interrupt_handler, &info);
 		} else {