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Merge branch 'master' into dev/netservices

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Change-Id: I1eb6c2ea2fd0d794ad6378eab8bbb80ce46dfbb8
This commit is contained in:
Niels Sascha Reedijk
2022-05-08 09:00:42 +01:00
parent cf54474e38 929355add7
commit 46b7da1f4f
1674 changed files with 29293 additions and 32942 deletions
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headers/libs/agg/dbg_new/agg_dbg_new.h
+2 -2
View File
@@ -26,8 +26,8 @@
//#define AGG_DBG_NEW_CHECK_ADDR
void* operator new (unsigned size, const char* file, int line);
void* operator new [] (unsigned size, const char* file, int line);
void* operator new (size_t size, const char* file, int line);
void* operator new [] (size_t size, const char* file, int line);
#define AGG_DBG_NEW_OPERATOR new(__FILE__, __LINE__)
void operator delete(void *ptr) throw();
headers/os/drivers/PCI.h
+3
View File
@@ -182,6 +182,9 @@ struct pci_module_info {
uint16 cap_id,
uint16 *offset
);
status_t (*get_powerstate)(uint8 bus, uint8 device, uint8 function, uint8* state);
status_t (*set_powerstate)(uint8 bus, uint8 device, uint8 function, uint8 newState);
};
#define B_PCI_MODULE_NAME "bus_managers/pci/v1"
headers/os/drivers/config_manager.h
-117
View File
@@ -1,117 +0,0 @@
#ifndef _CONFIG_MANAGER_H
#define _CONFIG_MANAGER_H
#include <module.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
B_ISA_BUS,
B_PCI_BUS,
B_PCMCIA_BUS,
B_UNKNOWN_BUS = 0x80
} bus_type;
typedef struct {
uchar base;
uchar subtype;
uchar interface;
} device_type;
typedef struct {
uint32 mask;
uint32 flags;
uint32 cookie;
} resource_mask_descriptor;
typedef struct {
uint32 minbase;
uint32 maxbase;
uint32 basealign;
uint32 len;
uint32 flags;
uint32 cookie;
} resource_range_descriptor;
typedef enum {
B_IRQ_RESOURCE,
B_DMA_RESOURCE,
B_IO_PORT_RESOURCE,
B_MEMORY_RESOURCE
} resource_type;
typedef struct {
resource_type type;
union {
resource_mask_descriptor m;
resource_range_descriptor r;
uint32 for_padding[7];
} d;
} resource_descriptor;
struct device_configuration {
uint32 flags;
uint32 num_resources;
resource_descriptor resources[0];
};
struct possible_device_configurations {
uint32 flags;
uint32 num_possible;
struct device_configuration possible[0];
};
struct device_info {
uint32 size;
uint32 bus_dependent_info_offset;
bus_type bus;
device_type devtype;
uint32 id[4]; /* unique (per-bus) normally-persistent id for device */
uint32 flags;
status_t config_status;
/* bus-dependent data goes here... */
};
#define B_DEVICE_INFO_ENABLED 1
#define B_DEVICE_INFO_CONFIGURED 2
#define B_DEVICE_INFO_CAN_BE_DISABLED 4
typedef struct config_manager_for_driver_module_info {
module_info minfo;
status_t (*get_next_device_info)(bus_type bus, uint64 *cookie,
struct device_info *info, uint32 len);
status_t (*get_device_info_for)(uint64 device,
struct device_info *info, uint32 len);
status_t (*get_size_of_current_configuration_for)(uint64 device);
status_t (*get_current_configuration_for)(uint64 device,
struct device_configuration *config, uint32 len);
status_t (*get_size_of_possible_configurations_for)(uint64 device);
status_t (*get_possible_configurations_for)(uint64 device,
struct possible_device_configurations *possible,
uint32 len);
/* helper routines for drivers */
status_t (*count_resource_descriptors_of_type)(
const struct device_configuration *config,
resource_type type);
status_t (*get_nth_resource_descriptor_of_type)(
const struct device_configuration *config, uint32 n,
resource_type type, resource_descriptor *descriptor,
uint32 len);
} config_manager_for_driver_module_info;
int config_manager_scan_hardcoded(struct device_info **info, int32 *count);
#define B_CONFIG_MANAGER_FOR_DRIVER_MODULE_NAME "bus_managers/config_manager/driver/v1"
#ifdef __cplusplus
}
#endif
#endif /* _CONFIG_MANAGER_H */
headers/os/drivers/fs_interface.h
-2
View File
@@ -330,8 +330,6 @@ extern status_t remove_vnode(fs_volume* volume, ino_t vnodeID);
extern status_t unremove_vnode(fs_volume* volume, ino_t vnodeID);
extern status_t get_vnode_removed(fs_volume* volume, ino_t vnodeID,
bool* _removed);
extern status_t mark_vnode_busy(fs_volume* volume, ino_t vnodeID, bool busy);
extern status_t change_vnode_id(fs_volume* volume, ino_t vnodeID, ino_t newID);
extern fs_volume* volume_for_vnode(fs_vnode* vnode);
extern status_t check_access_permissions(int accessMode, mode_t mode,
gid_t nodeGroupID, uid_t nodeUserID);
headers/os/drivers/isapnp.h
-2
View File
@@ -1,8 +1,6 @@
#ifndef _ISA_CONFIG_H
#define _ISA_CONFIG_H
#include <config_manager.h>
#ifdef __cplusplus
extern "C" {
#endif
headers/os/drivers/pcmcia/k_compat.h
-1
View File
@@ -25,7 +25,6 @@
#include <Drivers.h>
#include <ByteOrder.h>
#include <SupportDefs.h>
#include <config_manager.h>
#include <stdio.h>
#include <string.h>
headers/os/drivers/usb/USB_cdc.h
+1
View File
@@ -5,6 +5,7 @@
// Reference: http://www.usb.org/developers/devclass_docs/usbcdc11.pdf
#define USB_COMMUNICATION_DEVICE_CLASS 0x02
#define USB_COMMUNICATION_WIRELESS_DEVICE_CLASS 0xe0
#define USB_CDC_COMMUNICATION_INTERFACE_CLASS 0x02
#define USB_CDC_CLASS_VERSION 0x0101
headers/os/drivers/usb/USB_hid_page_consumer.h
+49 -6
View File
@@ -8,8 +8,8 @@
/* Reference:
* HID Usage Page 0x0C: CONSUMER
* HID Usage Tables Ver. 1.12
* http://www.usb.org/developers/devclass_docs/Hut1_12.pdf
* HID Usage Tables Ver. 1.3
* https://usb.org/sites/default/files/hut1_3_0.pdf
*/
// Usage IDs
@@ -50,7 +50,32 @@ enum {
B_HID_UID_CON_BROADCAST_MODE,
B_HID_UID_CON_SNAPSHOT,
B_HID_UID_CON_STILL,
B_HID_UID_CON_PICTURE_IN_PICTURE_TOGGLE,
B_HID_UID_CON_PICTURE_IN_PICTURE_SWAP,
B_HID_UID_CON_RED_MENU_BUTTON,
B_HID_UID_CON_GREEN_MENU_BUTTON,
B_HID_UID_CON_BLUE_MENU_BUTTON,
B_HID_UID_CON_YELLOW_MENU_BUTTON,
B_HID_UID_CON_ASPECT,
B_HID_UID_CON_3D_MODE_SELECT,
B_HID_UID_CON_DISPLAY_BRIGHTNESS_INCREMENT,
B_HID_UID_CON_DISPLAY_BRIGHTNESS_DECREMENT,
B_HID_UID_CON_DISPLAY_BRIGHTNESS,
B_HID_UID_CON_DISPLAY_BACKLIGHT_TOGGLE,
B_HID_UID_CON_DISPLAY_SET_BRIGHTNESS_TO_MINIMUM,
B_HID_UID_CON_DISPLAY_SET_BRIGHTNESS_TO_MAXIMUM,
B_HID_UID_CON_DISPLAY_SET_AUTO_BRIGHTNESS,
B_HID_UID_CON_CAMERA_ACCESS_ENABLED,
B_HID_UID_CON_CAMERA_ACCESS_DISABLED,
B_HID_UID_CON_CAMERA_ACCESS_TOGGLE,
B_HID_UID_CON_KEYBOARD_BRIGHTNESS_INCREMENT,
B_HID_UID_CON_KEYBOARD_BRIGHTNESS_DECREMENT,
B_HID_UID_CON_KEYBOARD_BACKLIGHT_SET_LEVEL,
B_HID_UID_CON_KEYBOARD_BACKLIGHT_OOC,
B_HID_UID_CON_KEYBOARD_BACKLIGHT_SET_MINIMUM,
B_HID_UID_CON_KEYBOARD_BACKLIGHT_SET_MAXIMUM,
B_HID_UID_CON_KEYBOARD_BACKLIGHT_AUTO,
B_HID_UID_CON_SELECTION = 0x80,
B_HID_UID_CON_ASSIGN_SELECTION,
B_HID_UID_CON_MODE_SETUP,
@@ -120,7 +145,18 @@ enum {
B_HID_UID_CON_STOP_EJECT,
B_HID_UID_CON_PLAY_PAUSE,
B_HID_UID_CON_PLAY_SKIP,
B_HID_UID_CON_VOICE_COMMAND,
B_HID_UID_CON_INVOKE_CAPTURE_INTERFACE,
B_HID_UID_CON_START_OR_STOP_GAME_RECORDING,
B_HID_UID_CON_HISTORICAL_GAME_CAPTURE,
B_HID_UID_CON_CAPTURE_GAME_SCREENSHOT,
B_HID_UID_CON_SHOW_OR_HIDE_RECORDING_INDICATOR,
B_HID_UID_CON_START_OR_STOP_MICROPHONE_CAPTURE,
B_HID_UID_CON_START_OR_STOP_CAMERA_CAPTURE,
B_HID_UID_CON_START_OR_STOP_GAME_BROADCAST,
B_HID_UID_CON_START_OR_STOP_VOICE_DICTATION_SESSION,
B_HID_UID_CON_INVOKE_DISMISS_EMOJI_PICKER,
B_HID_UID_CON_VOLUME = 0xe0,
B_HID_UID_CON_BALANCE,
B_HID_UID_CON_MUTE,
@@ -252,7 +288,11 @@ enum {
B_HID_UID_CON_AL_ONLINE_ACTIVITY_BROWSER,
B_HID_UID_CON_AL_RESEARCH_SEARCH_BROWSER,
B_HID_UID_CON_AL_AUDIO_PLAYER,
B_HID_UID_CON_AL_MESSAGE_STATUS,
B_HID_UID_CON_AL_CONTACT_SYNC,
B_HID_UID_CON_AL_NAVIGATION,
B_HID_UID_CON_AL_CONTEXT_AWARE_DESKTOP_ASSISTANT,
B_HID_UID_CON_GENERIC_GUI_APPLICATION_CONTROLS = 0x200,
B_HID_UID_CON_AC_NEW,
B_HID_UID_CON_AC_OPEN,
@@ -393,7 +433,10 @@ enum {
B_HID_UID_CON_AC_MERGE,
B_HID_UID_CON_AC_SPLIT,
B_HID_UID_CON_AC_DISTRIBUTE_HORIZONTALLY,
B_HID_UID_CON_AC_DISTRIBUTE_VERTICALLY
B_HID_UID_CON_AC_DISTRIBUTE_VERTICALLY,
B_HID_UID_CON_AC_NEXT_KEYBOARD_LAYOUT_SELECT,
B_HID_UID_CON_AC_NAVIGATION_GUIDANCE,
B_HID_UID_CON_AC_DESKTOP_SHOW_ALL_WINDOWS
};
headers/os/drivers/usb/USB_hid_page_digitizers.h
+72 -5
View File
@@ -8,8 +8,8 @@
/* Reference:
* HID Usage Page 0x0D: DIGITIZERS
* HID Usage Tables Ver. 1.12
* http://www.usb.org/developers/devclass_docs/Hut1_12.pdf
* HID Usage Tables Ver. 1.3
* https://usb.org/sites/default/files/hut1_3_0.pdf
*/
// Usage IDs
@@ -27,11 +27,11 @@ enum {
B_HID_UID_DIG_ARMATURE,
B_HID_UID_DIG_MULTIPLE_POINT_DIGITIZER,
B_HID_UID_DIG_FREE_SPACE_WAND,
B_HID_UID_DIG_STYLUS = 0x20,
B_HID_UID_DIG_PUCK,
B_HID_UID_DIG_FINGER,
B_HID_UID_DIG_TIP_PRESSURE = 0x30,
B_HID_UID_DIG_BARREL_PRESSURE,
B_HID_UID_DIG_IN_RANGE,
@@ -54,7 +54,74 @@ enum {
B_HID_UID_DIG_SECONDARY_TIP_SWITCH,
B_HID_UID_DIG_BARREL_SWITCH,
B_HID_UID_DIG_ERASER,
B_HID_UID_DIG_TABLET_PICK
B_HID_UID_DIG_TABLET_PICK,
B_HID_UID_DIG_TOUCH_VALID,
B_HID_UID_DIG_WIDTH,
B_HID_UID_DIG_HEIGHT,
B_HID_UID_DIG_CONTACT_IDENTIFIER = 0x51,
B_HID_UID_DIG_DEVICE_MODE,
B_HID_UID_DIG_DEVICE_IDENTIFIER,
B_HID_UID_DIG_CONTACT_COUNT,
B_HID_UID_DIG_CONTACT_COUNT_MAXIMUM,
B_HID_UID_DIG_SCAN_TIME,
B_HID_UID_DIG_SURFACE_SWITCH,
B_HID_UID_DIG_BUTTON_SWITCH,
B_HID_UID_DIG_PAD_TYPE,
B_HID_UID_DIG_SECONDARY_BARREL_SWITCH,
B_HID_UID_DIG_TRANSDUCER_SERIAL_NUMBER,
B_HID_UID_DIG_PREFERRED_COLOR,
B_HID_UID_DIG_PREFERRED_COLOR_IS_LOCKED,
B_HID_UID_DIG_PREFERRED_LINE_WIDTH,
B_HID_UID_DIG_PREFERRED_LINE_WIDTH_IS_LOCKED,
B_HID_UID_DIG_LATENCY_MODE,
B_HID_UID_DIG_GESTURE_CHARACTER_QUALITY,
B_HID_UID_DIG_GESTURE_CHARACTER_ENCODING,
B_HID_UID_DIG_GESTURE_CHARACTER_DATA_LENGTH,
B_HID_UID_DIG_GESTURE_CHARACTER_DATA,
B_HID_UID_DIG_UTF8_CHARACTER_GESTURE_ENCODING,
B_HID_UID_DIG_UTF16_LITTLE_ENDIAN_CHARACTER_GESTURE_ENCODING,
B_HID_UID_DIG_UTF16_BIG_ENDIAN_CHARACTER_GESTURE_ENCODING,
B_HID_UID_DIG_UTF32_LITTLE_ENDIAN_CHARACTER_GESTURE_ENCODING,
B_HID_UID_DIG_UTF32_BIG_ENDIAN_CHARACTER_GESTURE_ENCODING,
B_HID_UID_DIG_CAPACITIVE_HEAT_MAP_PROTOCOL_VENDOR_ID,
B_HID_UID_DIG_CAPACITIVE_HEAT_MAP_PROTOCOL_VERSION,
B_HID_UID_DIG_CAPACITIVE_HEAT_MAP_FRAME_DATA,
B_HID_UID_DIG_GESTURE_CHARACTER_ENABLE,
B_HID_UID_DIG_TRANSDUCER_SERIAL_NUMBER_PART_2,
B_HID_UID_DIG_NO_PREFERRED_COLOR,
B_HID_UID_DIG_PREFERRED_LINE_STYLE,
B_HID_UID_DIG_PREFERRED_LINE_STYLE_IS_LOCKED,
B_HID_UID_DIG_INK,
B_HID_UID_DIG_PENCIL,
B_HID_UID_DIG_HIGHLIGHTER,
B_HID_UID_DIG_CHISEL_MARKER,
B_HID_UID_DIG_BRUSH,
B_HID_UID_DIG_NO_PREFERENCE,
B_HID_UID_DIG_DIGITIZER_DIAGNOSTIC = 0x80,
B_HID_UID_DIG_DIGITIZER_ERROR,
B_HID_UID_DIG_ERR_NORMAL_STATUS,
B_HID_UID_DIG_ERR_TRANSDUCERS_EXCEEDED,
B_HID_UID_DIG_ERR_FULL_TRANS_FEATURES_UNAVAILABLE,
B_HID_UID_DIG_ERR_CHARGE_LOW,
B_HID_UID_DIG_TRANSDUCER_SOFTWARE_INFO = 0x90,
B_HID_UID_DIG_TRANSDUCER_VENDOR_ID,
B_HID_UID_DIG_TRANSDUCER_PRODUCT_ID,
B_HID_UID_DIG_DEVICE_SUPPORTED_PROTOCOLS,
B_HID_UID_DIG_TRANSDUCER_SUPPORTED_PROTOCOLS,
B_HID_UID_DIG_NO_PROTOCOL,
B_HID_UID_DIG_WACOM_AES_PROTOCOL,
B_HID_UID_DIG_USI_PROTOCOL,
B_HID_UID_DIG_MICROSOFT_PEN_PROTOCOL,
B_HID_UID_DIG_SUPPORTED_REPORT_RATES = 0xA0,
B_HID_UID_DIG_REPORT_RATE,
B_HID_UID_DIG_TRANSDUCER_CONNECTED,
B_HID_UID_DIG_SWITCH_DISABLED,
B_HID_UID_DIG_SWITCH_UNIMPLEMENTED,
B_HID_UID_DIG_TRANSDUCER_SWITCHES
};
headers/os/interface/Bitmap.h
+15 -7
View File
@@ -79,20 +79,15 @@ public:
status_t SetDrawingFlags(uint32 flags);
uint32 Flags() const;
void SetBits(const void* data, int32 length,
int32 offset, color_space colorSpace);
// not part of the R5 API
status_t ImportBits(const void* data, int32 length,
int32 bpr, int32 offset,
color_space colorSpace);
status_t ImportBits(const void* data, int32 length,
int32 bpr, color_space colorSpace,
BPoint from, BPoint to, int32 width,
int32 height);
BPoint from, BPoint to, BSize size);
status_t ImportBits(const BBitmap* bitmap);
status_t ImportBits(const BBitmap* bitmap, BPoint from,
BPoint to, int32 width, int32 height);
BPoint to, BSize size);
status_t GetOverlayRestrictions(
overlay_restrictions* restrictions) const;
@@ -111,6 +106,19 @@ public:
BBitmap& operator=(const BBitmap& source);
class Private;
public:
// deprecated
void SetBits(const void* data, int32 length,
int32 offset, color_space colorSpace);
private:
status_t ImportBits(const void* data, int32 length,
int32 bpr, color_space colorSpace,
BPoint from, BPoint to, int32 width, int32 height);
status_t ImportBits(const BBitmap* bitmap, BPoint from,
BPoint to, int32 width, int32 height);
private:
friend class BView;
friend class BApplication;
headers/os/interface/InterfaceDefs.h
+9 -10
View File
@@ -418,20 +418,19 @@ status_t set_screen_space(int32 index, uint32 resolution,
status_t get_scroll_bar_info(scroll_bar_info* info);
status_t set_scroll_bar_info(scroll_bar_info* info);
status_t get_mouse_type(int32* type);
status_t set_mouse_type(int32 type);
status_t get_mouse_type_by_name(BString mouse_name, int32* type);
status_t set_mouse_type_by_name(BString mouse_name, int32 type);
status_t get_mouse_type(int32* type); // deprecated
status_t get_mouse_type(const char* mouse_name, int32* type);
status_t set_mouse_type(const char* mouse_name, int32 type);
status_t get_mouse_map(mouse_map* map);
status_t set_mouse_map(mouse_map* map);
status_t get_click_speed(bigtime_t* speed);
status_t set_click_speed(bigtime_t speed);
status_t get_mouse_speed(int32* speed);
status_t set_mouse_speed(int32 speed);
status_t get_mouse_speed_by_name(BString mouse_name, int32* speed);
status_t set_mouse_speed_by_name(BString mouse_name, int32 speed);
status_t get_mouse_acceleration(int32* speed);
status_t set_mouse_acceleration(int32 speed);
status_t get_mouse_speed(int32* speed); // deprecated
status_t get_mouse_speed(const char* mouse_name, int32* speed);
status_t set_mouse_speed(const char* mouse_name, int32 speed);
status_t get_mouse_acceleration(int32* speed); // deprecated
status_t get_mouse_acceleration(const char* mouse_name, int32* speed);
status_t set_mouse_acceleration(const char* mouse_name, int32 speed);
status_t get_key_repeat_rate(int32* rate);
status_t set_key_repeat_rate(int32 rate);
headers/os/kernel/OS.h
+2 -3
View File
@@ -341,6 +341,8 @@ extern status_t rename_thread(thread_id thread, const char *newName);
extern status_t set_thread_priority(thread_id thread, int32 newPriority);
extern void exit_thread(status_t status);
extern status_t wait_for_thread(thread_id thread, status_t *returnValue);
extern status_t wait_for_thread_etc(thread_id id, uint32 flags, bigtime_t timeout,
status_t *_returnCode);
extern status_t on_exit_thread(void (*callback)(void *), void *data);
extern thread_id find_thread(const char *name);
@@ -384,9 +386,6 @@ extern bigtime_t system_time(void);
extern nanotime_t system_time_nsecs(void);
/* time since booting in nanoseconds */
/* deprecated (is no-op) */
extern status_t set_timezone(const char *timezone);
/* Alarm */
enum {
headers/os/media/MediaRoster.h
+9 -1
View File
@@ -11,7 +11,15 @@
#include <MediaDefs.h>
#include <MediaNode.h>
#include <config_manager.h>
typedef enum {
B_ISA_BUS,
B_PCI_BUS,
B_PCMCIA_BUS,
B_UNKNOWN_BUS = 0x80
} bus_type;
class BBufferGroup;
class BMediaAddOn;
headers/os/media/TimedEventQueue.h
+1 -1
View File
@@ -21,7 +21,7 @@ struct media_timed_event {
bigtime_t inTime, int32 inType,
void* inPointer, uint32 inCleanup,
int32 inData, int64 inBigdata,
char* inUserData, size_t dataSize = 0);
const char* inUserData, size_t dataSize = 0);
media_timed_event(
const media_timed_event& other);
headers/posix/arch/riscv64/signal.h
+2 -3
View File
@@ -10,15 +10,14 @@
* Architecture-specific structure passed to signal handlers
*/
// TODO: gcc7's RISCV doesn't seem real keen on identifying 32 vs 64 yet.
#if defined(__RISCV64__) || defined(__RISCV__)
#if (defined(__riscv) && __riscv_xlen == 64)
struct vregs {
ulong x[31];
ulong pc;
double f[32];
ulong fcsr;
};
#endif /* defined(__RISCV64__) */
#endif /* (defined(__riscv) && __riscv_xlen == 64) */
#endif /* _ARCH_RISCV64_SIGNAL_H_ */
headers/posix/pthread.h
+11 -3
View File
@@ -92,8 +92,10 @@ extern int pthread_mutex_init(pthread_mutex_t *mutex,
extern int pthread_mutex_lock(pthread_mutex_t *mutex);
extern int pthread_mutex_setprioceiling(pthread_mutex_t *mutex,
int newPriorityCeiling, int *_oldPriorityCeiling);
extern int pthread_mutex_clocklock(pthread_mutex_t *mutex,
clockid_t clock_id, const struct timespec *abstime);
extern int pthread_mutex_timedlock(pthread_mutex_t *mutex,
const struct timespec *spec);
const struct timespec *abstime);
extern int pthread_mutex_trylock(pthread_mutex_t *mutex);
extern int pthread_mutex_unlock(pthread_mutex_t *mutex);
@@ -136,6 +138,8 @@ extern int pthread_cond_init(pthread_cond_t *cond,
const pthread_condattr_t *attr);
extern int pthread_cond_broadcast(pthread_cond_t *cond);
extern int pthread_cond_signal(pthread_cond_t *cond);
extern int pthread_cond_clockwait(pthread_cond_t *cond, pthread_mutex_t *mutex,
clockid_t clock_id, const struct timespec *abstime);
extern int pthread_cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex,
const struct timespec *abstime);
extern int pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex);
@@ -158,12 +162,16 @@ extern int pthread_rwlock_init(pthread_rwlock_t *lock,
extern int pthread_rwlock_destroy(pthread_rwlock_t *lock);
extern int pthread_rwlock_rdlock(pthread_rwlock_t *lock);
extern int pthread_rwlock_tryrdlock(pthread_rwlock_t *lock);
extern int pthread_rwlock_clockrdlock(pthread_rwlock_t* rwlock,
clockid_t clock_id, const struct timespec* abstime);
extern int pthread_rwlock_timedrdlock(pthread_rwlock_t *lock,
const struct timespec *timeout);
const struct timespec *abstime);
extern int pthread_rwlock_wrlock(pthread_rwlock_t *lock);
extern int pthread_rwlock_trywrlock(pthread_rwlock_t *lock);
extern int pthread_rwlock_clockwrlock(pthread_rwlock_t* rwlock,
clockid_t clock_id, const struct timespec* abstime);
extern int pthread_rwlock_timedwrlock(pthread_rwlock_t *lock,
const struct timespec *timeout);
const struct timespec *abstime);
extern int pthread_rwlock_unlock(pthread_rwlock_t *lock);
/* rwlock attribute functions */
headers/posix/semaphore.h
+3 -1
View File
@@ -33,7 +33,9 @@ int sem_init(sem_t* semaphore, int shared, unsigned value);
int sem_destroy(sem_t* semaphore);
int sem_post(sem_t* semaphore);
int sem_timedwait(sem_t* semaphore, const struct timespec* timeout);
int sem_clockwait(sem_t* semaphore, clockid_t clock_id,
const struct timespec* abstime);
int sem_timedwait(sem_t* semaphore, const struct timespec* abstime);
int sem_trywait(sem_t* semaphore);
int sem_wait(sem_t* semaphore);
int sem_getvalue(sem_t* semaphore, int* value);
headers/posix/stdc-predef.h
-14
View File
@@ -1,14 +0,0 @@
/*
* Copyright 2021 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _STDC_PREDEF_H
#define _STDC_PREDEF_H
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
# define __STDC_NO_THREADS__ 1
#endif
#endif /* _STDC_PREDEF_H */
headers/posix/threads.h
+71
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@@ -0,0 +1,71 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2011 Ed Schouten <[email protected]>
* Copyright (c) 2022 Dominic Martinez <[email protected]>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#if __GNUC__ > 2 /* not available on gcc2 */
#ifndef _THREADS_H_
#define _THREADS_H_
#include <sys/types.h>
#include <time.h>
typedef pthread_t thrd_t;
typedef int (*thrd_start_t)(void *);
enum {
thrd_busy = 1,
thrd_error = 2,
thrd_nomem = 3,
thrd_success = 4,
thrd_timedout = 5
};
#ifdef __cplusplus
extern "C" {
#endif
int thrd_create(thrd_t *thread, thrd_start_t, void *);
thrd_t thrd_current(void);
int thrd_detach(thrd_t);
int thrd_equal(thrd_t, thrd_t);
_Noreturn void
thrd_exit(int);
int thrd_join(thrd_t, int *);
int thrd_sleep(const struct timespec *, struct timespec *);
void thrd_yield(void);
#ifdef __cplusplus
}
#endif
#endif /* _THREADS_H_ */
#endif /* __GNUC__ > 2 */
headers/posix/time.h
+4
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@@ -25,6 +25,7 @@ typedef __haiku_int64 time_t;
#define CLOCKS_PER_SEC 1000000
#define CLK_TCK CLOCKS_PER_SEC
#define TIME_UTC 1
#define MAX_TIMESTR 70
/* maximum length of a string returned by asctime(), and ctime() */
@@ -110,6 +111,9 @@ int timer_settime(timer_t timerID, int flags,
const struct itimerspec* value, struct itimerspec* oldValue);
int timer_getoverrun(timer_t timerID);
/* C11 timespec */
int timespec_get(struct timespec *ts, int base);
/* special timezone support */
extern void tzset(void);
headers/private/drivers/mmc.h
+2 -2
View File
@@ -110,8 +110,8 @@ typedef struct mmc_device_interface {
// Device attribute paths for the MMC device
static const char* kMmcRcaAttribute = "mmc/rca";
static const char* kMmcTypeAttribute = "mmc/type";
const char* const kMmcRcaAttribute = "mmc/rca";
const char* const kMmcTypeAttribute = "mmc/type";
#endif /* _MMC_H */
headers/private/fs_shell/fssh_api_wrapper.h
-2
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@@ -945,8 +945,6 @@
#define remove_vnode fssh_remove_vnode
#define unremove_vnode fssh_unremove_vnode
#define get_vnode_removed fssh_get_vnode_removed
#define mark_vnode_busy fssh_mark_vnode_busy
#define change_vnode_id fssh_change_vnode_id
#define volume_for_vnode fssh_volume_for_vnode
#define check_access_permissions fssh_check_access_permissions
#define read_pages fssh_read_pages
headers/private/fs_shell/fssh_fs_interface.h
-4
View File
@@ -360,10 +360,6 @@ extern fssh_status_t fssh_unremove_vnode(fssh_fs_volume *volume,
fssh_vnode_id vnodeID);
extern fssh_status_t fssh_get_vnode_removed(fssh_fs_volume *volume,
fssh_vnode_id vnodeID, bool* removed);
extern fssh_status_t fssh_mark_vnode_busy(fssh_fs_volume* volume,
fssh_vnode_id vnodeID, bool busy);
extern fssh_status_t fssh_change_vnode_id(fssh_fs_volume* volume,
fssh_vnode_id vnodeID, fssh_vnode_id newID);
extern fssh_fs_volume* fssh_volume_for_vnode(fssh_fs_vnode *vnode);
extern fssh_status_t fssh_check_access_permissions(int accessMode,
fssh_mode_t mode, fssh_gid_t nodeGroupID,
headers/private/graphics/common/dp.h
+1 -1
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@@ -34,7 +34,7 @@ typedef struct {
} dp_info;
typedef struct {
uint16 address;
uint32 address;
uint8 request;
uint8 reply;
void* buffer;
headers/private/graphics/common/dp_raw.h
+40 -44
View File
@@ -36,7 +36,6 @@
/* *** DPCD Receiver Compatibility Field (0x0000) *** */
/* *** VESA DisplayPort Standard, rev 1.1, p112 *** */
// DPCD Version (0x0)
#define DP_DPCD_SIZE 0xf // Size
#define DP_DPCD_REV 0x0000 // Reg
#define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int
#define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int
@@ -48,43 +47,40 @@
// Use DP_LINK_RATE_* for speed.
// DP Maximum Lane Count (0x2)
#define DP_MAX_LANE_COUNT 0x0002 // Reg
#define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count
#define DP_MAX_LANE_COUNT_1 (1 << 0) // Value
#define DP_MAX_LANE_COUNT_2 (2 << 0) // Value
#define DP_MAX_LANE_COUNT_4 (4 << 0) // Value
#define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1
#define DP_MAX_LANE_COUNT_MASK 0x1f // Count
#define DP_ENHANCED_FRAME_CAP (1 << 7) // Bool, Rev 1.1
// DP Maximum Downspread (0x3)
#define DP_MAX_DOWNSPREAD 0x0003 // Reg
#define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool
#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool
#define DP_MAX_DOWNSPREAD_0_5 (1 << 0) // Bool
#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) // Bool
// DP Number of Receiver Ports (0x4)
#define DP_NORP 0x0004 // Reg
#define DP_NORP_MASK (1 << 0) // Count
#define DP_NORP_MASK 0x1 // Count
// DP Downstream Port Present (0x5)
#define DP_DOWNSTREAMPORT 0x0005 // Reg
#define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool
#define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask
#define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value
#define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool
#define DP_DOWNSTREAMPORT_PRESENT 0x0005 // Reg
#define DP_DWN_STRM_PORT_PRESENT (1 << 0) // Bool
#define DP_DWN_STRM_PORT_TYPE_MASK (3 << 1) // Mask
#define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) // Value
#define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) // Value
#define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) // Value
#define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) // Value
#define DP_FORMAT_CONVERSION (1 << 3) // Bool
#define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) // Bool
// DP Main Link Channel Coding (0x6)
#define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg
#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x0006 // Reg
#define DP_CAP_ANSI_8B10B (1 << 0) // Bool
// DP Downstream Port Count (0x7) (Only 1.1+)
#define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg
#define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count
#define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool
#define DP_DOWN_STREAM_PORT_COUNT 0x0007 // Reg
#define DP_PORT_COUNT_MASK 0xf // Count
#define DP_OUI_SUPPORT (1 << 7) // Bool
// DP Port Capability 0
#define DP_PORT0_CAPABILITY0 0x0008 // Reg
#define DP_PORT1_CAPABILITY0 0x000A // Reg
#define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool
#define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool
// DP Port Capability 1
#define DP_PORT0_CAPABILITY1 0x0009 // Reg
#define DP_PORT1_CAPABILITY1 0x000B // Reg
#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size
#define DP_RECEIVE_PORT_0_CAP_0 0x0008 // Reg
#define DP_RECEIVE_PORT_1_CAP_0 0x000a // Reg
#define DP_LOCAL_EDID_PRESENT (1 << 1) // Bool
#define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) // Bool
// DP Port Buffer Size
#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x0009 // Reg
#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x000b // Reg
// (value + 1) * 32 bytes per lane
/* *** DPCD Link Configuration Field (0x0100) *** */
@@ -100,12 +96,12 @@
#define DP_LANE_COUNT_MASK (31 << 0) // Count
#define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1
// DP Training Pattern (0x0102)
#define DP_TRAIN 0x0102 // Reg
#define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask
#define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value
#define DP_TRAIN_PATTERN_1 (1 << 0) // Value
#define DP_TRAIN_PATTERN_2 (2 << 0) // Value
#define DP_TRAIN_PATTERN_3 (3 << 0) // Value
#define DP_TRAINING_PATTERN_SET 0x0102 // Reg
#define DP_TRAINING_PATTERN_MASK (3 << 0) // Mask
#define DP_TRAINING_PATTERN_DISABLE (0 << 0) // Value
#define DP_TRAINING_PATTERN_1 (1 << 0) // Value
#define DP_TRAINING_PATTERN_2 (2 << 0) // Value
#define DP_TRAINING_PATTERN_3 (3 << 0) // Value
#define DP_TRAIN_QUAL_MASK (3 << 2) // Mask
#define DP_TRAIN_QUAL_NONE (0 << 2) // Value
@@ -120,10 +116,10 @@
#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value
#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value
// DP Training Lane n (0x0103 - 0x0106)
#define DP_TRAIN_LANE0 0x0103 // Reg
#define DP_TRAIN_LANE1 0x0104 // Reg
#define DP_TRAIN_LANE2 0x0105 // Reg
#define DP_TRAIN_LANE3 0x0106 // Reg
#define DP_TRAINING_LANE0_SET 0x0103 // Reg
#define DP_TRAINING_LANE1_SET 0x0104 // Reg
#define DP_TRAINING_LANE2_SET 0x0105 // Reg
#define DP_TRAINING_LANE3_SET 0x0106 // Reg
#define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift
#define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask
@@ -177,10 +173,10 @@
| DP_LANE_STATUS_CHEQ_DONE_B \
| DP_LANE_STATUS_SYMB_LOCK_B)
// DP Lane Align Status (0x0204)
#define DP_LANE_ALIGN 0x0204 // Reg
#define DP_LANE_ALIGN_DONE (1 << 0) // Bool
#define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool
#define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool
#define DP_LANE_ALIGN_STATUS_UPDATED 0x0204 // Reg
#define DP_INTERLANE_ALIGN_DONE (1 << 0) // Bool
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) // Bool
#define DP_LINK_STATUS_UPDATED (1 << 7) // Bool
// DP Sink Status (0x0205)
#define DP_SINK_STATUS 0x0205 // Reg
#define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool
headers/private/graphics/common/i2c.h
+10 -1
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@@ -35,17 +35,26 @@ typedef struct i2c_timing {
} i2c_timing;
struct i2c_bus;
// set signals on bus
typedef status_t (*i2c_set_signals)(void *cookie, int clock, int data);
// read signals from bus
typedef status_t (*i2c_get_signals)(void *cookie, int *clock, int *data);
// send/receive from bus
typedef status_t (*i2c_send_receive)(const struct i2c_bus *bus, uint32 slave_address,
const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer,
size_t readLength);
// i2c bus definition
typedef struct i2c_bus {
void *cookie; // user-defined cookie
// low-level
i2c_timing timing;
i2c_set_signals set_signals; // callback to set signals
i2c_get_signals get_signals; // callback to detect signals
// high-level
i2c_send_receive send_receive;
} i2c_bus;
@@ -54,7 +63,7 @@ extern "C" {
#endif
// send and receive data via i2c bus
status_t i2c_send_receive(const i2c_bus *bus, int slave_address,
status_t i2c_send_receive_callback(const i2c_bus *bus, uint32 slave_address,
const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer,
size_t readLength);
headers/private/graphics/intel_extreme/intel_extreme.h
+377 -41
View File
@@ -53,6 +53,8 @@
#define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake
#define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake
#define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake
#define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake
#define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake
// models
#define INTEL_TYPE_SERVER 0x0004
#define INTEL_TYPE_MOBILE 0x0008
@@ -81,6 +83,7 @@
#define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_BDW (INTEL_GROUP_BDW)
#define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER)
#define INTEL_MODEL_SKY (INTEL_GROUP_SKY)
#define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
@@ -89,6 +92,10 @@
#define INTEL_MODEL_CFL (INTEL_GROUP_CFL)
#define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_CML (INTEL_GROUP_CML)
#define INTEL_MODEL_CMLM (INTEL_GROUP_CML | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_JSL (INTEL_GROUP_JSL)
#define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE)
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID 0x3b00
@@ -107,13 +114,15 @@
#define INTEL_PCH_CMP2_DEVICE_ID 0x0680
#define INTEL_PCH_CMP_V_DEVICE_ID 0xa380
#define INTEL_PCH_ICP_DEVICE_ID 0x3480
#define INTEL_PCH_ICP2_DEVICE_ID 0x3880
#define INTEL_PCH_MCC_DEVICE_ID 0x4b00
#define INTEL_PCH_TGP_DEVICE_ID 0xa080
#define INTEL_PCH_TGP2_DEVICE_ID 0x4380
#define INTEL_PCH_JSP_DEVICE_ID 0x4d80
#define INTEL_PCH_JSP2_DEVICE_ID 0x3880
#define INTEL_PCH_ADP_DEVICE_ID 0x7a80
#define INTEL_PCH_ADP2_DEVICE_ID 0x5180
#define INTEL_PCH_ADP3_DEVICE_ID 0x7a00
#define INTEL_PCH_ADP4_DEVICE_ID 0x5480
#define INTEL_PCH_P2X_DEVICE_ID 0x7100
#define INTEL_PCH_P3X_DEVICE_ID 0x7000
@@ -221,6 +230,10 @@ struct DeviceType {
return 7;
if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
return 8;
if (InGroup(INTEL_GROUP_JSL))
return 11;
if (InGroup(INTEL_GROUP_TGL))
return 12;
if (InFamily(INTEL_FAMILY_LAKE))
return 9;
@@ -272,7 +285,135 @@ struct ring_buffer {
uint8* base;
};
struct overlay_registers;
struct child_device_config {
uint16 handle;
uint16 device_type;
#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5)
#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
uint8 device_id[10];
uint16 addin_offset;
uint8 dvo_port;
uint8 i2c_pin;
uint8 slave_addr;
uint8 ddc_pin;
uint16 edid_ptr;
uint8 dvo_cfg;
struct {
bool efp_routed:1;
bool lane_reversal:1;
bool lspcon:1;
bool iboost:1;
bool hpd_invert:1;
bool use_vbt_vswing:1;
uint8 reserved:2;
bool hdmi_support:1;
bool dp_support:1;
bool tmds_support:1;
uint8 reserved2:5;
uint8 aux_channel;
uint8 dongle_detect;
} __attribute__((packed));
uint8 caps;
uint8 dvo_wiring;
uint8 dvo2_wiring;
uint16 extended_type;
uint8 dvo_function;
bool dp_usb_type_c:1;
bool tbt:1;
uint8 reserved3:2;
uint8 dp_port_trace_length:4;
uint8 dp_gpio_index;
uint8 dp_gpio_pin_num;
uint8 dp_iboost_level:4;
uint8 hdmi_iboost_level:4;
uint8 dp_max_link_rate:3;
uint8 dp_max_link_rate_reserved:5;
} __attribute__((packed));
enum dvo_port {
DVO_PORT_HDMIA,
DVO_PORT_HDMIB,
DVO_PORT_HDMIC,
DVO_PORT_HDMID,
DVO_PORT_LVDS,
DVO_PORT_TV,
DVO_PORT_CRT,
DVO_PORT_DPB,
DVO_PORT_DPC,
DVO_PORT_DPD,
DVO_PORT_DPA,
DVO_PORT_DPE,
DVO_PORT_HDMIE,
DVO_PORT_DPF,
DVO_PORT_HDMIF,
DVO_PORT_DPG,
DVO_PORT_HDMIG,
DVO_PORT_DPH,
DVO_PORT_HDMIH,
DVO_PORT_DPI,
DVO_PORT_HDMII,
};
enum dp_aux_channel {
DP_AUX_A = 0x40,
DP_AUX_B = 0x10,
DP_AUX_C = 0x20,
DP_AUX_D = 0x30,
DP_AUX_E = 0x50,
DP_AUX_F = 0x60,
DP_AUX_G = 0x70,
DP_AUX_H = 0x80,
DP_AUX_I = 0x90
};
enum aux_channel {
AUX_CH_A,
AUX_CH_B,
AUX_CH_C,
AUX_CH_D,
AUX_CH_E,
AUX_CH_F,
AUX_CH_G,
AUX_CH_H,
AUX_CH_I,
};
enum hpd_pin {
HPD_PORT_A,
HPD_PORT_B,
HPD_PORT_C,
HPD_PORT_D,
HPD_PORT_E,
HPD_PORT_TC1,
HPD_PORT_TC2,
HPD_PORT_TC3,
HPD_PORT_TC4,
HPD_PORT_TC5,
HPD_PORT_TC6,
};
struct intel_shared_info {
area_id mode_list_area; // area containing display mode list
@@ -283,6 +424,7 @@ struct intel_shared_info {
uint32 bytes_per_row;
uint32 bits_per_pixel;
uint32 dpms_mode;
uint16 min_brightness;
area_id registers_area; // area of memory mapped registers
uint32 register_blocks[REGISTER_BLOCK_COUNT];
@@ -331,6 +473,9 @@ struct intel_shared_info {
edid1_info vesa_edid_info;
bool has_vesa_edid_info;
uint32 device_config_count;
child_device_config device_configs[10];
};
enum pipe_index {
@@ -341,6 +486,40 @@ enum pipe_index {
INTEL_PIPE_D
};
class pipes {
public:
pipes() : bitmask(0) {}
bool HasPipe(pipe_index pipe)
{
if (pipe == INTEL_PIPE_ANY)
return bitmask != 0;
return (bitmask & (1 << pipe)) != 0;
}
void SetPipe(pipe_index pipe)
{
if (pipe == INTEL_PIPE_ANY) {
bitmask = ~1;
// first bit corresponds to INTEL_PIPE_ANY but it's never used,
// so it should be 0
}
bitmask |= (1 << pipe);
}
void ClearPipe(pipe_index pipe)
{
if (pipe == INTEL_PIPE_ANY)
bitmask = 0;
bitmask &= ~(1 << pipe);
}
private:
uint8 bitmask;
};
//----------------- ioctl() interface ----------------
// magic code for ioctls
@@ -352,7 +531,9 @@ enum {
INTEL_GET_DEVICE_NAME,
INTEL_ALLOCATE_GRAPHICS_MEMORY,
INTEL_FREE_GRAPHICS_MEMORY
INTEL_FREE_GRAPHICS_MEMORY,
INTEL_GET_BRIGHTNESS_LEGACY,
INTEL_SET_BRIGHTNESS_LEGACY
};
// retrieve the area_id of the kernel/accelerant shared info
@@ -376,6 +557,12 @@ struct intel_free_graphics_memory {
addr_t buffer_base;
};
// brightness legacy
struct intel_brightness_legacy {
uint32 magic;
uint8 lpc;
};
//----------------------------------------------------------
// Register definitions, taken from X driver
@@ -489,6 +676,9 @@ struct intel_free_graphics_memory {
#define BDW_GTT_SIZE_4MB (2 << 6)
#define BDW_GTT_SIZE_8MB (3 << 6)
// Gen2, i915GM, i945GM
#define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4
// graphics page translation table
#define INTEL_PAGE_TABLE_CONTROL 0x02020
#define PAGE_TABLE_ENABLED 0x00000001
@@ -554,6 +744,84 @@ struct intel_free_graphics_memory {
#define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
#define PCH_INTERRUPT_GLOBAL_SNB (1 << 31)
#define PCH_MASTER_INT_CTL_BDW 0x44200
#define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe))
#define GEN8_DE_PCH_IRQ (1 << 23)
#define GEN8_DE_PORT_IRQ (1 << 20)
#define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31)
#define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR
#define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR
#define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR
#define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER
#define GEN8_DE_PORT_ISR 0x44440
#define GEN8_DE_PORT_IMR 0x44444
#define GEN8_DE_PORT_IIR 0x44448
#define GEN8_DE_PORT_IER 0x4444c
#define GEN8_AUX_CHANNEL_A (1 << 0)
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define CNL_AUX_CHANNEL_F (1 << 28)
#define ICL_AUX_CHANNEL_E (1 << 29)
#define GEN8_DE_MISC_ISR 0x44460
#define GEN8_DE_MISC_IMR 0x44464
#define GEN8_DE_MISC_IIR 0x44468
#define GEN8_DE_MISC_IER 0x4446c
#define GEN8_DE_EDP_PSR (1 << 19)
#define GEN11_DE_HPD_ISR 0x44470
#define GEN11_DE_HPD_IMR 0x44474
#define GEN11_DE_HPD_IIR 0x44478
#define GEN11_DE_HPD_IER 0x4447c
#define GEN11_DE_TC_HOTPLUG_MASK (0x3f << 16)
#define GEN11_DE_TBT_HOTPLUG_MASK (0x3f)
#define GEN11_TBT_HOTPLUG_CTL 0x44030
#define GEN11_TC_HOTPLUG_CTL 0x44038
#define SHPD_FILTER_CNT 0xc4038
#define SHPD_FILTER_CNT_500_ADJ 0x1d9
#define SDEISR 0xc4000
#define SDEIMR 0xc4004
#define SDEIIR 0xc4008
#define SDEIER 0xc400c
#define SDE_GMBUS_ICP (1 << 23)
#define SHOTPLUG_CTL_DDI 0xc4030
#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_A)))
#define SHOTPLUG_CTL_TC 0xc4034
#define SHOTPLUG_CTL_TC_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_TC1)))
#define PCH_PORT_HOTPLUG SHOTPLUG_CTL_DDI
#define PCH_PORT_HOTPLUG2 0xc403c
#define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK
#define GEN8_PIPE_VSYNC (1 << 1)
#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
#define GEN11_GFX_MSTR_IRQ 0x190010
#define GEN11_MASTER_IRQ (1 << 31)
#define GEN11_DISPLAY_IRQ (1 << 16)
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
#define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW
#define GEN11_DE_HPD_IRQ (1 << 21)
#define GEN11_GT_INTR_DW0 0x190018
#define GEN11_GT_INTR_DW1 0x19001c
#define GEN11_GU_MISC_IMR 0x444f4
#define GEN11_GU_MISC_IIR 0x444f8
#define GEN11_GU_MISC_IER 0x444fc
#define GEN11_GU_MISC_GSE (1 << 27)
// graphics port control (i.e. G45)
#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
@@ -811,6 +1079,26 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30
#define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_SNB_PIPE_A 0
#define INTEL_DISP_PORTA_SNB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29
#define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_IVB_PIPE_A 0
#define INTEL_DISP_PORTA_IVB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_C 2
#define INTEL_DISP_PORT_WIDTH_SHIFT 19
#define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT)
#define INTEL_DISP_PORT_WIDTH_1 0
#define INTEL_DISP_PORT_WIDTH_2 1
#define INTEL_DISP_PORT_WIDTH_4 3
#define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16
#define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT)
#define INTEL_DISP_EDP_PLL_FREQ_270 0
#define INTEL_DISP_EDP_PLL_FREQ_162 1
#define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT)
@@ -832,14 +1120,23 @@ struct intel_free_graphics_memory {
#define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300)
// DP AUX channels
#define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT)
#define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110)
#define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210)
#define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310)
#define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT)
#define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT)
#define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT)
#define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT)
#define DP_AUX_CH_CTL(aux) \
(_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux)
#define DP_AUX_CH_DATA(aux, i) \
(_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4)
#define _PCH_DPB_AUX_CH_CTL (0x4110 | REGS_SOUTH_TRANSCODER_PORT)
#define _PCH_DPB_AUX_CH_DATA1 (0x4114 | REGS_SOUTH_TRANSCODER_PORT)
#define _PCH_DPC_AUX_CH_CTL (0x4210 | REGS_SOUTH_TRANSCODER_PORT)
#define _PCH_DPC_AUX_CH_DATA1 (0x4214 | REGS_SOUTH_TRANSCODER_PORT)
#define PCH_DP_AUX_CH_CTL(aux) \
(_PCH_DPB_AUX_CH_CTL + (_PCH_DPC_AUX_CH_CTL - _PCH_DPB_AUX_CH_CTL) * (aux - AUX_CH_B))
#define PCH_DP_AUX_CH_DATA(aux, i) \
(_PCH_DPB_AUX_CH_DATA1 + (_PCH_DPC_AUX_CH_DATA1 - _PCH_DPB_AUX_CH_DATA1) * (aux - AUX_CH_B) \
+ i * 4)
#define INTEL_DP_AUX_CTL_BUSY (1 << 31)
#define INTEL_DP_AUX_CTL_DONE (1 << 30)
@@ -857,6 +1154,7 @@ struct intel_free_graphics_memory {
#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
#define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
// planes
@@ -1021,8 +1319,30 @@ struct intel_free_graphics_memory {
#define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED)
#define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14)
// gpu power wells
#define INTEL_PWR_WELL_CTL_2 (0x5404 | REGS_NORTH_SHARED)
// gpu power wells (confirmed skylake)
#define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED)
#define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED)
#define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i)))
#define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i)))
#define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS
#define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER
#define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED)
#define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED)
// gpu pll enable registers (confirmed skylake)
#define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED)
#define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED)
#define WRPLL_PLL_ENABLE (1 << 31)
// TODO: on IronLake this is in the north shared block at 0x41000
#define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL)
@@ -1062,11 +1382,26 @@ struct intel_free_graphics_memory {
#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
// Backlight control registers
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED)
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED)
#define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED)
// These have moved around, initially they were per pipe, then they were moved in the "north" part
// of the PCH with a single backlight control (independant of pipes), and then moved again to the
// "south" part of the PCH, with a simplified register layout.
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
// Kaby Lake/Sunrisepoint
#define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31
#define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period
// Devices after Cannonlake have a new register layout, with separate registers for the period
// and duty cycle instead of having two 16bit values in a 32bit register
#define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
#define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
#define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
#define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT)
// Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be
// programmed for use on either pipe)
#define BLM_LEGACY_MODE (1 << 16)
// ring buffer commands
@@ -1196,31 +1531,31 @@ struct intel_free_graphics_memory {
#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
//FDI PIPE M/N DATA AND LINK VALUES (refreshrate)
#define PCH_FDI_PIPE_A_DATA_M1 0x0030
#define PCH_FDI_PIPE_A_DATA_M2 0x0038
#define PCH_FDI_PIPE_B_DATA_M1 0x1030
#define PCH_FDI_PIPE_B_DATA_M2 0x1038
#define PCH_FDI_PIPE_C_DATA_M1 0x2030
#define PCH_FDI_PIPE_C_DATA_M2 0x2038
#define PCH_FDI_PIPE_A_DATA_N1 0x0034
#define PCH_FDI_PIPE_A_DATA_N2 0x003c
#define PCH_FDI_PIPE_B_DATA_N1 0x1034
#define PCH_FDI_PIPE_B_DATA_N2 0x103c
#define PCH_FDI_PIPE_C_DATA_N1 0x2034
#define PCH_FDI_PIPE_C_DATA_N2 0x203c
#define PCH_FDI_PIPE_A_LINK_M1 0x0040
#define PCH_FDI_PIPE_A_LINK_M2 0x0048
#define PCH_FDI_PIPE_B_LINK_M1 0x1040
#define PCH_FDI_PIPE_B_LINK_M2 0x1048
#define PCH_FDI_PIPE_C_LINK_M1 0x2040
#define PCH_FDI_PIPE_C_LINK_M2 0x2048
#define PCH_FDI_PIPE_A_LINK_N1 0x0044
#define PCH_FDI_PIPE_A_LINK_N2 0x004c
#define PCH_FDI_PIPE_B_LINK_N1 0x1044
#define PCH_FDI_PIPE_B_LINK_N2 0x104c
#define PCH_FDI_PIPE_C_LINK_N1 0x2044
#define PCH_FDI_PIPE_C_LINK_N2 0x204c
// FDI/PIPE M/N DATA AND LINK VALUES (refreshrate)
#define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT)
#define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT)
#define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25)
#define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0)
@@ -1480,4 +1815,5 @@ struct hardware_status {
uint32 store[1008];
};
#endif /* INTEL_EXTREME_H */
headers/private/graphics/intel_extreme/lock.h
+2 -2
View File
@@ -12,10 +12,10 @@
#include <OS.h>
typedef struct lock {
struct lock {
sem_id sem;
int32 count;
} lock;
};
static inline status_t
headers/private/graphics/vesa/vesa_info.h
+16 -1
View File
@@ -23,8 +23,15 @@ struct vesa_mode {
uint8 bits_per_pixel;
};
enum bios_type_enum {
kUnknownBiosType = 0,
kIntelBiosType,
kNVidiaBiosType,
kAtomBiosType1,
kAtomBiosType2
};
struct vesa_shared_info {
int32 type;
area_id mode_list_area; // area containing display mode list
uint32 mode_count;
display_mode current_mode;
@@ -40,7 +47,14 @@ struct vesa_shared_info {
edid1_info edid_info;
bool has_edid;
bios_type_enum bios_type;
uint16 mode_table_offset;
// Atombios only: offset to the table of video modes in the bios, used for patching in
// extra video modes.
uint32 dpms_capabilities;
char name[32];
uint32 vram_size;
};
//----------------- ioctl() interface ----------------
@@ -53,6 +67,7 @@ enum {
VESA_GET_DPMS_MODE,
VESA_SET_DPMS_MODE,
VESA_SET_INDEXED_COLORS,
VESA_SET_CUSTOM_DISPLAY_MODE,
VGA_PLANAR_BLIT,
};
headers/private/kernel/arch/arm/arch_cpu.h
+1 -14
View File
@@ -11,23 +11,9 @@
// TODO: Could be 32-bits sometimes?
#if __ARM_ARCH__ <= 5
#define isb() __asm__ __volatile__("" : : : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("" : : : "memory")
#elif __ARM_ARCH__ == 6
#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
: : "r" (0) : "memory")
#else /* ARMv7+ */
#define isb() __asm__ __volatile__("isb" : : : "memory")
#define dsb() __asm__ __volatile__("dsb" : : : "memory")
#define dmb() __asm__ __volatile__("dmb" : : : "memory")
#endif
#define set_ac()
#define clear_ac()
@@ -98,6 +84,7 @@ extern addr_t arm_get_fp(void);
extern int mmu_read_c1(void);
extern int mmu_write_c1(int val);
void arch_cpu_invalidate_TLB_page(addr_t page);
static inline void
arch_cpu_pause(void)
headers/private/kernel/arch/arm/arch_kernel_args.h
+1
View File
@@ -32,6 +32,7 @@ typedef struct {
uint32 phys_pgdir;
uint32 vir_pgdir;
uint32 next_pagetable;
uint32 last_pagetable;
// The virtual ranges we want to keep in the kernel.
uint32 num_virtual_ranges_to_keep;
headers/private/kernel/arch/arm/arch_thread_types.h
+11
View File
@@ -37,4 +37,15 @@ struct arch_fork_arg {
char dummy;
};
#ifdef __cplusplus
extern "C" {
#endif
void arch_return_to_userland(struct iframe *);
#ifdef __cplusplus
}
#endif
#endif /* KERNEL_ARCH_ARM_THREAD_TYPES_H */
headers/private/kernel/arch/arm/arm_mmu.h
+19 -16
View File
@@ -43,26 +43,26 @@
// found it in the cortex A8 reference... so I set t to 0
// page table must obviously be on multiple of 1KB
/*
* L2-Page descriptors... now things get really complicated...
* there are three different types of pages large pages (64KB) and small(4KB)
* and "small extended".
* only small extende is used by now....
* and there is a new and a old format of page table entries
* I will use the old format...
*/
#define ARM_MMU_L2_TYPE_LARGE 0x1
#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
#define ARM_MMU_L2_TYPE_SMALLEXT 0x3
/* for new format entries (cortex-a8) */
#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
#define ARM_MMU_L2_FLAG_XN 0x001
#define ARM_MMU_L2_FLAG_B 0x004
#define ARM_MMU_L2_FLAG_C 0x008
#define ARM_MMU_L2_FLAG_AP0 0x010
#define ARM_MMU_L2_FLAG_AP1 0x020
#define ARM_MMU_L2_FLAG_TEX0 0x040
#define ARM_MMU_L2_FLAG_TEX1 0x080
#define ARM_MMU_L2_FLAG_TEX2 0x100
#define ARM_MMU_L2_FLAG_AP2 0x200
#define ARM_MMU_L2_FLAG_S 0x400
#define ARM_MMU_L2_FLAG_NG 0x800
// for B C and TEX see ARM arm B4-11
#define ARM_MMU_L2_FLAG_B 0x4
#define ARM_MMU_L2_FLAG_C 0x8
#define ARM_MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
#define ARM_MMU_L2_FLAG_AP_RW 0x30
#define ARM_MMU_L2_FLAG_AP_KRW 0x010
// allow read and write for kernel only
#define ARM_MMU_L2_FLAG_AP_RW 0x030
// allow read and write for user and system
#define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096
@@ -96,4 +96,7 @@
#define ARM_PTE_ADDRESS_MASK 0xfffff000
#define ARM_PTE_TYPE_MASK 0x00000003
#define ARM_PTE_PROTECTION_MASK 0x00000231 // AP[2:0], XN
#define ARM_PTE_MEMORY_TYPE_MASK 0x000001cc // TEX, B, C
#endif /* _ARCH_ARM_ARM_MMU_H */
headers/private/kernel/arch/arm64/arch_hypervisor.h
+85
View File
@@ -0,0 +1,85 @@
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_HYPERVISOR_H_
#define _MACHINE_HYPERVISOR_H_
/*
* These registers are only useful when in hypervisor context,
* e.g. specific to EL2, or controlling the hypervisor.
*/
/*
* Architecture feature trap register
*/
#define CPTR_RES0 0x7fefc800
#define CPTR_RES1 0x000033ff
#define CPTR_TFP 0x00000400
#define CPTR_TTA 0x00100000
#define CPTR_TCPAC 0x80000000
/*
* Hypervisor Config Register
*/
#define HCR_VM 0x0000000000000001
#define HCR_SWIO 0x0000000000000002
#define HCR_PTW 0x0000000000000004
#define HCR_FMO 0x0000000000000008
#define HCR_IMO 0x0000000000000010
#define HCR_AMO 0x0000000000000020
#define HCR_VF 0x0000000000000040
#define HCR_VI 0x0000000000000080
#define HCR_VSE 0x0000000000000100
#define HCR_FB 0x0000000000000200
#define HCR_BSU_MASK 0x0000000000000c00
#define HCR_DC 0x0000000000001000
#define HCR_TWI 0x0000000000002000
#define HCR_TWE 0x0000000000004000
#define HCR_TID0 0x0000000000008000
#define HCR_TID1 0x0000000000010000
#define HCR_TID2 0x0000000000020000
#define HCR_TID3 0x0000000000040000
#define HCR_TSC 0x0000000000080000
#define HCR_TIDCP 0x0000000000100000
#define HCR_TACR 0x0000000000200000
#define HCR_TSW 0x0000000000400000
#define HCR_TPC 0x0000000000800000
#define HCR_TPU 0x0000000001000000
#define HCR_TTLB 0x0000000002000000
#define HCR_TVM 0x0000000004000000
#define HCR_TGE 0x0000000008000000
#define HCR_TDZ 0x0000000010000000
#define HCR_HCD 0x0000000020000000
#define HCR_TRVM 0x0000000040000000
#define HCR_RW 0x0000000080000000
#define HCR_CD 0x0000000100000000
#define HCR_ID 0x0000000200000000
#endif
headers/private/kernel/arch/arm64/arch_kernel.h
+3
View File
@@ -23,5 +23,8 @@
#define USER_STACK_REGION 0x70000000
#define USER_STACK_REGION_SIZE ((USER_TOP - USER_STACK_REGION) + 1)
// Kernel physical memory map area.
#define KERNEL_PMAP_BASE 0xffffff0000000000
#define KERNEL_PMAP_SIZE 0x8000000000
#endif /* _KERNEL_ARCH_ARM64_ARCH_KERNEL_H_ */
headers/private/kernel/arch/arm64/arch_kernel_args.h
+11 -4
View File
@@ -11,6 +11,7 @@
#include <util/FixedWidthPointer.h>
#include <boot/interrupt_controller.h>
#include <boot/uart.h>
@@ -18,11 +19,17 @@
typedef struct {
uint64 phys_pgdir;
uint64 vir_pgdir;
uint64 next_pagetable;
// needed for UEFI, otherwise kernel acpi support can't find ACPI root
FixedWidthPointer<void> acpi_root;
// TODO: Deal with this later in the port
// FixedWidthPointer<void> fdt;
// uart_info uart;
FixedWidthPointer<void> acpi_root;
FixedWidthPointer<void> fdt;
uart_info uart;
intc_info interrupt_controller;
} _PACKED arch_kernel_args;
#endif /* KERNEL_ARCH_ARM64_KERNEL_ARGS_H */
headers/private/kernel/arch/arm64/arch_pte.h
+127
View File
@@ -0,0 +1,127 @@
/*-
* Copyright (c) 2014 Andrew Turner
* Copyright (c) 2014-2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Andrew Turner under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_PTE_H_
#define _MACHINE_PTE_H_
#ifndef LOCORE
typedef uint64_t pd_entry_t; /* page directory entry */
typedef uint64_t pt_entry_t; /* page table entry */
#endif
/* Block and Page attributes */
/* TODO: Add the upper attributes */
#define ATTR_MASK_H UINT64_C(0xfff0000000000000)
#define ATTR_MASK_L UINT64_C(0x0000000000000fff)
#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
/* Bits 58:55 are reserved for software */
#define ATTR_SW_DIRTY (1UL << 56)
#define ATTR_UXN (1UL << 54)
#define ATTR_PXN (1UL << 53)
#define ATTR_XN (ATTR_PXN | ATTR_UXN)
#define ATTR_CONTIGUOUS (1UL << 52)
#define ATTR_DBM (1UL << 51)
#define ATTR_nG (1 << 11)
#define ATTR_AF (1 << 10)
#define ATTR_SH(x) ((x) << 8)
#define ATTR_SH_MASK ATTR_SH(3)
#define ATTR_SH_NS 0 /* Non-shareable */
#define ATTR_SH_OS 2 /* Outer-shareable */
#define ATTR_SH_IS 3 /* Inner-shareable */
#define ATTR_AP_RW_BIT (1 << 7)
#define ATTR_AP(x) ((x) << 6)
#define ATTR_AP_MASK ATTR_AP(3)
#define ATTR_AP_RW (0 << 1)
#define ATTR_AP_RO (1 << 1)
#define ATTR_AP_USER (1 << 0)
#define ATTR_NS (1 << 5)
#define ATTR_IDX(x) ((x) << 2)
#define ATTR_IDX_MASK (7 << 2)
#define ATTR_DEFAULT (ATTR_AF | ATTR_SH(ATTR_SH_IS))
#define ATTR_DESCR_MASK 3
/* Level 0 table, 512GiB per entry */
#define L0_SHIFT 39
#define L0_SIZE (1ul << L0_SHIFT)
#define L0_OFFSET (L0_SIZE - 1ul)
#define L0_INVAL 0x0 /* An invalid address */
/* 0x1 Level 0 doesn't support block translation */
/* 0x2 also marks an invalid address */
#define L0_TABLE 0x3 /* A next-level table */
/* Level 1 table, 1GiB per entry */
#define L1_SHIFT 30
#define L1_SIZE (1 << L1_SHIFT)
#define L1_OFFSET (L1_SIZE - 1)
#define L1_INVAL L0_INVAL
#define L1_BLOCK 0x1
#define L1_TABLE L0_TABLE
/* Level 2 table, 2MiB per entry */
#define L2_SHIFT 21
#define L2_SIZE (1 << L2_SHIFT)
#define L2_OFFSET (L2_SIZE - 1)
#define L2_INVAL L1_INVAL
#define L2_BLOCK L1_BLOCK
#define L2_TABLE L1_TABLE
#define L2_BLOCK_MASK UINT64_C(0xffffffe00000)
/* Level 3 table, 4KiB per entry */
#define L3_SHIFT 12
#define L3_SIZE (1 << L3_SHIFT)
#define L3_OFFSET (L3_SIZE - 1)
#define L3_SHIFT 12
#define L3_INVAL 0x0
/* 0x1 is reserved */
/* 0x2 also marks an invalid address */
#define L3_PAGE 0x3
#define L0_ENTRIES_SHIFT 9
#define L0_ENTRIES (1 << L0_ENTRIES_SHIFT)
#define L0_ADDR_MASK (L0_ENTRIES - 1)
#define Ln_ENTRIES_SHIFT 9
#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
#define Ln_TABLE_MASK ((1 << 12) - 1)
#define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
#endif /* !_MACHINE_PTE_H_ */
/* End of pte.h */
headers/private/kernel/arch/arm64/arch_uart_linflex.h
+554
View File
@@ -0,0 +1,554 @@
/*
* Copyright 2022 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Oliver Ruiz Dorantes, [email protected]
*/
#ifndef __DEV_UART_LINFLEX_H
#define __DEV_UART_LINFLEX_H
#include <sys/types.h>
#include <ByteOrder.h>
#include <SupportDefs.h>
#include <arch/generic/debug_uart.h>
#define UART_KIND_LINFLEX "linflex"
namespace LINFlexRegisters {
typedef union { /* LINFLEX LIN Control 1 (Base+0x0000) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 CCD:1;
vuint32 CFD:1;
vuint32 LASE:1;
vuint32 AWUM:1;
vuint32 MBL:4;
vuint32 BF:1;
vuint32 SFTM:1;
vuint32 LBKM:1;
vuint32 MME:1;
vuint32 SBDT:1;
vuint32 RBLM:1;
vuint32 SLEEP:1;
vuint32 INIT:1;
#endif
#if __BYTE_ORDER == __LITTLE_ENDIAN
vuint32 INIT:1;
vuint32 SLEEP:1;
vuint32 RBLM:1;
vuint32 SBDT:1;
vuint32 MME:1;
vuint32 LBKM:1;
vuint32 SFTM:1;
vuint32 BF:1;
vuint32 MBL:4;
vuint32 AWUM:1;
vuint32 LASE:1;
vuint32 CFD:1;
vuint32 CCD:1;
vuint32 :16;
#endif
} B;
} LINCR1_register;
typedef union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 SZIE:1;
vuint32 OCIE:1;
vuint32 BEIE:1;
vuint32 CEIE:1;
vuint32 HEIE:1;
vuint32:2;
vuint32 FEIE:1;
vuint32 BOIE:1;
vuint32 LSIE:1;
vuint32 WUIE:1;
vuint32 DBFIE:1;
vuint32 DBEIE:1;
vuint32 DRIE:1;
vuint32 DTIE:1;
vuint32 HRIE:1;
#endif
} B;
} LINIER_register;
typedef union { /* LINFLEX LIN Status (Base+0x0008) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 LINS:4;
vuint32:2;
vuint32 RMB:1;
vuint32:1;
vuint32 RBSY:1;
vuint32 RPS:1;
vuint32 WUF:1;
vuint32 DBFF:1;
vuint32 DBEF:1;
vuint32 DRF:1;
vuint32 DTF:1;
vuint32 HRF:1;
#endif
} B;
} LINSR_register;
typedef union { /* LINFLEX LIN Error Status (Base+0x000C) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 SZF:1;
vuint32 OCF:1;
vuint32 BEF:1;
vuint32 CEF:1;
vuint32 SFEF:1;
vuint32 BDEF:1;
vuint32 IDPEF:1;
vuint32 FEF:1;
vuint32 BOF:1;
vuint32:6;
vuint32 NF:1;
#endif
} B;
} LINESR_register;
typedef union { /* LINFLEX UART Mode Control (Base+0x0010) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32:1;
vuint32 TDFL:2;
vuint32:1;
vuint32 RDFL:2;
vuint32 RFBM:1;
vuint32 TFBM:1;
vuint32 WL1:1;
vuint32 PC1:1;
vuint32 RXEN:1;
vuint32 TXEN:1;
vuint32 PC0:1;
vuint32 PCE:1;
vuint32 WL:1;
vuint32 UART:1;
#endif
#if __BYTE_ORDER == __LITTLE_ENDIAN
vuint32 UART:1;
vuint32 WL:1;
vuint32 PCE:1;
vuint32 PC0:1;
vuint32 TXEN:1;
vuint32 RXEN:1;
vuint32 PC1:1;
vuint32 WL1:1;
vuint32 TFBM:1;
vuint32 RFBM:1;
vuint32 RDFL:2;
vuint32:1;
vuint32 TDFL:2;
vuint32:1;
vuint32 :16;
#endif
} B;
} UARTCR_register;
typedef union { /* LINFLEX UART Mode Status (Base+0x0014) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 SZF:1;
vuint32 OCF:1;
vuint32 PE:4; /*Can check all 4 RX'd bytes at once with array*/
vuint32 RMB:1;
vuint32 FEF:1;
vuint32 BOF:1;
vuint32 RPS:1;
vuint32 WUF:1;
vuint32:2;
vuint32 DRF:1;
vuint32 DTF:1;
vuint32 NF:1;
#endif
#if __BYTE_ORDER == __LITTLE_ENDIAN
vuint32 NF:1;
vuint32 DTF:1;
vuint32 DRF:1;
vuint32:2;
vuint32 WUF:1;
vuint32 RPS:1;
vuint32 BOF:1;
vuint32 FEF:1;
vuint32 RMB:1;
vuint32 PE:4; /*Can check all 4 RX'd bytes at once with array*/
vuint32 OCF:1;
vuint32 SZF:1;
vuint32 :16;
#endif
} B;
} UARTSR_register;
typedef union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32:5;
vuint32 LTOM:1;
vuint32 IOT:1;
vuint32 TOCE:1;
vuint32 CNT:8;
#endif
} B;
} LINTCSR_register;
typedef union { /* LINFLEX LIN Output Compare (Base+0x001C) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :16;
vuint32 OC2:8;
vuint32 OC1:8;
#endif
} B;
} LINOCR_register;
typedef union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 :20;
vuint32 RTO:4;
vuint32:1;
vuint32 HTO:7;
#endif
} B;
} LINTOCR_register;
typedef union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:28;
vuint32 DIV_F:4;
#endif
} B;
} LINFBRR_register;
typedef union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:19;
vuint32 DIV_M:13;
#endif
} B;
} LINIBRR_register;
typedef union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:24;
vuint32 CF:8;
#endif
} B;
} LINCFR_register;
typedef union { /* LINFLEX LIN Control 2 (Base+0x0030) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:17;
vuint32 IOBE:1;
vuint32 IOPE:1;
vuint32 WURQ:1;
vuint32 DDRQ:1;
vuint32 DTRQ:1;
vuint32 ABRQ:1;
vuint32 HTRQ:1;
vuint32:8;
#endif
} B;
} LINCR2_register;
typedef union { /* LINFLEX Buffer Identifier (Base+0x0034) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:16;
vuint32 DFL:6;
vuint32 DIR:1;
vuint32 CCS:1;
vuint32:2;
vuint32 ID:6;
#endif
} B;
} BIDR_register;
typedef union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 DATA3:8;
vuint32 DATA2:8;
vuint32 DATA1:8;
vuint32 DATA0:8;
#endif
} B;
} BDRL_register;
typedef union { /* LINFLEX Buffer Data MSB (Base+0x003C */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32 DATA7:8;
vuint32 DATA6:8;
vuint32 DATA5:8;
vuint32 DATA4:8;
#endif
} B;
} BDRM_register;
typedef union { /* LINFLEX Identifier Filter Enable (+0x0040) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:24;
vuint32 FACT:8;
#endif
} B;
} IFER_register;
typedef union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:28;
vuint32 IFMI:4;
#endif
} B;
} IFMI_register;
typedef union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:28;
vuint32 IFM:4;
#endif
} B;
} IFMR_register;
typedef union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:16;
vuint32:3;
vuint32 DFL:3;
vuint32 DIR:1;
vuint32 CCS:1;
vuint32:2;
vuint32 ID:6;
#endif
} B;
} IFCR_register;
typedef union { /* LINFLEX Global Counter (+0x008C) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:26;
vuint32 TDFBM:1;
vuint32 RDFBM:1;
vuint32 TDLIS:1;
vuint32 RDLIS:1;
vuint32 STOP:1;
vuint32 SR:1;
#endif
} B;
} GCR_register;
typedef union { /* LINFLEX UART preset timeout (+0x0090) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:20;
vuint32 PTO:12;
#endif
} B;
} UARTPTO_register;
typedef union { /* LINFLEX UART current timeout (+0x0094) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:20;
vuint32 CTO:12;
#endif
} B;
} UARTCTO_register;
typedef union { /* LINFLEX DMA Tx Enable (+0x0098) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:16;
vuint32 DTE15:1;
vuint32 DTE14:1;
vuint32 DTE13:1;
vuint32 DTE12:1;
vuint32 DTE11:1;
vuint32 DTE10:1;
vuint32 DTE9:1;
vuint32 DTE8:1;
vuint32 DTE7:1;
vuint32 DTE6:1;
vuint32 DTE5:1;
vuint32 DTE4:1;
vuint32 DTE3:1;
vuint32 DTE2:1;
vuint32 DTE1:1;
vuint32 DTE0:1;
#endif
} B;
} DMATXE_register;
typedef union { /* LINFLEX DMA RX Enable (+0x009C) */
vuint32 R;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
vuint32:16;
vuint32 DRE15:1;
vuint32 DRE14:1;
vuint32 DRE13:1;
vuint32 DRE12:1;
vuint32 DRE11:1;
vuint32 DRE10:1;
vuint32 DRE9:1;
vuint32 DRE8:1;
vuint32 DRE7:1;
vuint32 DRE6:1;
vuint32 DRE5:1;
vuint32 DRE4:1;
vuint32 DRE3:1;
vuint32 DRE2:1;
vuint32 DRE1:1;
vuint32 DRE0:1;
#endif
} B;
} DMARXE_register;
// Helper to deal with w1c (Write 1 to clear) register fields
template<typename REG>
REG BitfieldRegister() {
REG reg;
reg.R = 0;
return reg;
}
typedef struct {
LINCR1_register LINCR1; /* LINFLEX LIN Control 1 (Base+0x0000) */
LINIER_register LINIER; /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
LINSR_register LINSR; /* LINFLEX LIN Status (Base+0x0008) */
LINESR_register LINESR; /* LINFLEX LIN Error Status (Base+0x000C) */
UARTCR_register UARTCR; /* LINFLEX UART Mode Control (Base+0x0010) */
UARTSR_register UARTSR; /* LINFLEX UART Mode Status (Base+0x0014) */
LINTCSR_register LINTCSR; /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
LINOCR_register LINOCR; /* LINFLEX LIN Output Compare (Base+0x001C) */
LINTOCR_register LINTOCR; /* LINFLEX LIN Timeout Control (Base+0x0020) */
LINFBRR_register LINFBRR; /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
LINIBRR_register LINIBRR; /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
LINCFR_register LINCFR; /* LINFLEX LIN Checksum Field (Base+0x002C) */
LINCR2_register LINCR2; /* LINFLEX LIN Control 2 (Base+0x0030) */
BIDR_register BIDR; /* LINFLEX Buffer Identifier (Base+0x0034) */
BDRL_register BDRL; /* LINFLEX Buffer Data LSB (Base+0x0038) */
BDRM_register BDRM; /* LINFLEX Buffer Data MSB (Base+0x003C */
IFER_register IFER; /* LINFLEX Identifier Filter Enable (+0x0040) */
IFMI_register IFMI; /* LINFLEX Identifier Filter Match Index (+0x0044)*/
IFMR_register IFMR; /* LINFLEX Identifier Filter Mode (Base+0x0048) */
IFCR_register IFCR[16]; /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
GCR_register GCR; /* LINFLEX Global Counter (+0x008C) */
UARTPTO_register UARTPTO; /* LINFLEX UART preset timeout (+0x0090) */
UARTCTO_register UARTCTO; /* LINFLEX UART current timeout (+0x0094) */
DMATXE_register DMATXE; /* LINFLEX DMA Tx Enable (+0x0098) */
DMARXE_register DMARXE; /* LINFLEX DMA RX Enable (+0x009C) */
} LINFlex;
}
class ArchUARTlinflex : public DebugUART {
public:
ArchUARTlinflex(addr_t base, int64 clock);
~ArchUARTlinflex();
void InitEarly();
void InitPort(uint32 baud);
void Enable();
void Disable();
int PutChar(char c);
int GetChar(bool wait);
void FlushTx();
void FlushRx();
private:
template<typename TO, typename TA>
void Out(TA* reg, TO value) {
*(volatile TO*)(reg) = value;
}
template<typename TI, typename TA>
TI In(TA* reg) {
return *(volatile TI*)(reg);
}
virtual void Barrier();
LINFlexRegisters::LINFlex* LinflexCell() {
return reinterpret_cast<LINFlexRegisters::LINFlex*>(Base());
}
};
ArchUARTlinflex *arch_get_uart_linflex(addr_t base, int64 clock);
#endif
headers/private/kernel/arch/riscv64/arch_kernel.h
+1 -2
View File
@@ -14,8 +14,7 @@
// memory layout
#define KERNEL_LOAD_BASE 0x80000000
#define KERNEL_LOAD_BASE_64_BIT 0xffffffc000000000
#define KERNEL_LOAD_BASE 0xffffffc000000000
#if (defined(__riscv) && __riscv_xlen == 64)
headers/private/kernel/arch/x86/arch_hpet.h
+15 -12
View File
@@ -95,21 +95,24 @@ struct hpet_regs {
};
typedef struct acpi_hpet_addr {
uint8 address_space;
uint8 register_width;
uint8 register_offset;
uint8 reserved;
uint64 address;
} _PACKED acpi_hpet_addr;
typedef struct acpi_hpet {
acpi_descriptor_header header; /* "HPET" signature and acpi header */
uint16 vendor_id;
uint8 legacy_capable : 1;
uint8 reserved1 : 1;
uint8 countersize : 1;
uint8 comparators : 5;
uint8 hw_revision;
struct hpet_addr {
uint8 address_space;
uint8 register_width;
uint8 register_offset;
uint8 reserved;
uint64 address;
} hpet_address;
uint8 comparators : 5;
uint8 countersize : 1;
uint8 reserved1 : 1;
uint8 legacy_capable : 1;
uint16 vendor_id;
acpi_hpet_addr hpet_address;
uint8 number;
uint16 min_tick;
} _PACKED acpi_hpet;
headers/private/kernel/arch/x86/arch_kernel.h
+8 -4
View File
@@ -18,11 +18,15 @@
#ifdef _BOOT_MODE
// 32-bit and 64-bit kernel load addresses.
#ifdef _BOOT_PLATFORM_BIOS
#define KERNEL_LOAD_BASE_32_BIT 0x80000000
#define KERNEL_LOAD_BASE_64_BIT 0xffffffff80000000ll
#define KERNEL_FIXUP_FOR_LONG_MODE (KERNEL_LOAD_BASE_64_BIT - KERNEL_LOAD_BASE_32_BIT)
#elif __x86_64__
#define KERNEL_LOAD_BASE 0xffffffff80000000ll
#else
#define KERNEL_LOAD_BASE 0x80000000
#define KERNEL_LOAD_BASE_64_BIT 0xffffffff80000000ll
#endif
#elif defined(__x86_64__)
headers/private/kernel/arch/x86/arch_thread_types.h
+2
View File
@@ -48,6 +48,8 @@ struct arch_thread {
uintptr_t* current_stack;
uintptr_t instruction_pointer;
uint64 user_gs_base;
#else
struct farcall current_stack;
struct farcall interrupt_stack;
headers/private/kernel/boot/arch/arm/arch_cpu.h
+62 -4
View File
@@ -1,9 +1,9 @@
/*
* Copyright 2013-2020 Haiku, Inc. All rights reserved.
* Copyright 2013-2022 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef EFI_BOOT_PLATFORM_EFI_ARCH_CPU_H
#define EFI_BOOT_PLATFORM_EFI_ARCH_CPU_H
#ifndef BOOT_ARCH_CPU_H
#define BOOT_ARCH_CPU_H
#include <SupportDefs.h>
@@ -17,9 +17,67 @@ extern "C" {
status_t boot_arch_cpu_init(void);
void arch_ucode_load(BootVolume& volume);
bigtime_t system_time();
void spin(bigtime_t microseconds);
static inline uint32
cpu_read_CPSR(void)
{
uint32 res;
asm volatile("MRS %0, CPSR": "=r" (res));
return res;
}
static inline uint32
mmu_read_SCTLR(void)
{
uint32 res;
asm volatile("MRC p15, 0, %0, c1, c0, 0": "=r" (res));
return res;
}
static inline uint32
mmu_read_TTBR0(void)
{
uint32 res;
asm volatile("MRC p15, 0, %0, c2, c0, 0": "=r" (res));
return res;
}
static inline uint32
mmu_read_TTBR1(void)
{
uint32 res;
asm volatile("MRC p15, 0, %0, c2, c0, 1": "=r" (res));
return res;
}
static inline uint32
mmu_read_TTBCR(void)
{
uint32 res;
asm volatile("MRC p15, 0, %0, c2, c0, 2": "=r" (res));
return res;
}
static inline uint32
mmu_read_DACR(void)
{
uint32 res;
asm volatile("MRC p15, 0, %0, c3, c0, 0": "=r" (res));
return res;
}
#ifdef __cplusplus
}
#endif
#endif /* EFI_BOOT_PLATFORM_EFI_ARCH_CPU_H */
#endif /* BOOT_ARCH_CPU_H */
headers/private/kernel/boot/arch/x86/arch_hpet.h
+21
View File
@@ -0,0 +1,21 @@
/*
* Copyright 2008, Dustin Howett, [email protected]. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef BOOT_ARCH_HPET_H
#define BOOT_ARCH_HPET_H
#include <SupportDefs.h>
#include <arch/x86/arch_hpet.h>
#ifdef __cplusplus
extern "C" {
#endif
void hpet_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOOT_ARCH_HPET_H */
headers/private/kernel/boot/elf.h
+3
View File
@@ -90,6 +90,9 @@ extern status_t boot_elf_resolve_symbol(preloaded_elf32_image* image,
Elf32_Sym* symbol, Elf32_Addr* symbolAddress);
extern status_t boot_elf_resolve_symbol(preloaded_elf64_image* image,
Elf64_Sym* symbol, Elf64_Addr* symbolAddress);
extern Elf32_Addr boot_elf32_get_relocation(Elf32_Addr resolveAddress);
extern void boot_elf32_set_relocation(Elf32_Addr resolveAddress,
Elf32_Addr finalAddress);
extern void boot_elf64_set_relocation(Elf64_Addr resolveAddress,
Elf64_Addr finalAddress);
#endif
headers/private/kernel/boot/interrupt_controller.h
+1
View File
@@ -14,6 +14,7 @@
#define INTC_KIND_GICV2 "gicv2"
#define INTC_KIND_OMAP3 "omap3"
#define INTC_KIND_PXA "pxa"
#define INTC_KIND_SUN4I "sun4i"
typedef struct {
headers/private/kernel/boot/platform/efi/arch_dtb.h
+16
View File
@@ -0,0 +1,16 @@
/*
* Copyright 2021 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef KERNEL_BOOT_PLATFORM_EFI_ARCH_DTB_H
#define KERNEL_BOOT_PLATFORM_EFI_ARCH_DTB_H
#include <SupportDefs.h>
void arch_handle_fdt(const void* fdt, int node);
void arch_dtb_set_kernel_args(void);
#endif /* KERNEL_BOOT_PLATFORM_EFI_ARCH_DTB_H */
headers/private/kernel/boot/platform/efi/arch_smp.h
+3 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2013-2021 Haiku, Inc. All rights reserved.
* Copyright 2013-2022 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef KERNEL_BOOT_PLATFORM_EFI_ARCH_SMP_H
@@ -32,9 +32,9 @@ int arch_smp_get_current_cpu(void);
void arch_smp_init_other_cpus(void);
#ifdef __riscv
platform_cpu_info* arch_smp_find_cpu(uint32 phandle);
void arch_smp_boot_other_cpus(uint64 satp, uint64 kernel_entry);
void arch_smp_boot_other_cpus(uint64 satp, uint64 kernelEntry, addr_t virtKernelArgs);
#else
void arch_smp_boot_other_cpus(uint32 pml4, uint64 kernel_entry);
void arch_smp_boot_other_cpus(uint32 pml4, uint64 kernelEntry, addr_t virtKernelArgs);
#endif
void arch_smp_add_safemode_menus(Menu *menu);
void arch_smp_init(void);
headers/private/kernel/condition_variable.h
+7 -8
View File
@@ -17,6 +17,8 @@
#include <util/OpenHashTable.h>
struct mutex;
struct recursive_lock;
struct ConditionVariable;
@@ -31,9 +33,7 @@ public:
status_t Wait(const void* object, uint32 flags = 0,
bigtime_t timeout = 0);
inline status_t WaitStatus() const { return fWaitStatus; }
inline ConditionVariable* Variable() const { return fVariable; }
ConditionVariable* Variable() const;
private:
inline void _AddToLockedVariable(ConditionVariable* variable);
@@ -63,15 +63,13 @@ public:
static void NotifyOne(const void* object, status_t result);
static void NotifyAll(const void* object, status_t result);
// (both methods) caller must ensure that
// the variable is not unpublished
// concurrently
void Add(ConditionVariableEntry* entry);
// Convenience methods, no ConditionVariableEntry required.
status_t Wait(uint32 flags = 0, bigtime_t timeout = 0);
// all-in one, i.e. doesn't need a
// ConditionVariableEntry
status_t Wait(mutex* lock, uint32 flags = 0, bigtime_t timeout = 0);
status_t Wait(recursive_lock* lock, uint32 flags = 0, bigtime_t timeout = 0);
const void* Object() const { return fObject; }
const char* ObjectType() const { return fObjectType; }
@@ -80,6 +78,7 @@ public:
void Dump() const;
private:
static void _Notify(const void* object, bool all, status_t result);
void _Notify(bool all, status_t result);
void _NotifyLocked(bool all, status_t result);
headers/private/kernel/heap.h
-4
View File
@@ -66,10 +66,6 @@ void* memalign(size_t alignment, size_t size) _ALIGNED_BY_ARG(1);
void deferred_free(void* block);
void* malloc_referenced(size_t size);
void* malloc_referenced_acquire(void* data);
void malloc_referenced_release(void* data);
void heap_add_area(heap_allocator* heap, area_id areaID, addr_t base,
size_t size);
heap_allocator* heap_create_allocator(const char* name, addr_t base,
headers/private/kernel/platform/efi/protocol/block-io.h
+2
View File
@@ -43,8 +43,10 @@ struct efi_block_io_media {
bool LogicalPartition;
bool ReadOnly;
bool WriteCaching;
uint8_t pad1[3];
uint32_t BlockSize;
uint32_t IoAlign;
uint8_t pad2[4];
uint64_t LastBlock;
// present in rev2
headers/private/kernel/posix/realtime_sem.h
+2 -1
View File
@@ -32,7 +32,8 @@ status_t _user_realtime_sem_unlink(const char* name);
status_t _user_realtime_sem_get_value(sem_id semID, int* value);
status_t _user_realtime_sem_post(sem_id semID);
status_t _user_realtime_sem_wait(sem_id semID, bigtime_t timeout);
status_t _user_realtime_sem_wait(sem_id semID, uint32 flags,
bigtime_t timeout);
__END_DECLS
headers/private/kernel/thread.h
+2 -2
View File
@@ -127,8 +127,6 @@ thread_id thread_create_thread(const ThreadCreationAttributes& attributes,
thread_id spawn_kernel_thread_etc(thread_func, const char *name, int32 priority,
void *args, team_id team);
status_t wait_for_thread_etc(thread_id id, uint32 flags, bigtime_t timeout,
status_t *_returnCode);
status_t select_thread(int32 object, struct select_info *info, bool kernel);
status_t deselect_thread(int32 object, struct select_info *info, bool kernel);
@@ -147,6 +145,8 @@ status_t _user_resume_thread(thread_id thread);
status_t _user_rename_thread(thread_id thread, const char *name);
thread_id _user_spawn_thread(struct thread_creation_attributes* attributes);
status_t _user_wait_for_thread(thread_id id, status_t *_returnCode);
status_t _user_wait_for_thread_etc(thread_id id, uint32 flags, bigtime_t timeout,
status_t *_returnCode);
status_t _user_snooze_etc(bigtime_t timeout, int timebase, uint32 flags,
bigtime_t* _remainingTime);
status_t _user_kill_thread(thread_id thread);
headers/private/kernel/thread_types.h
+7 -7
View File
@@ -66,9 +66,6 @@ struct select_info;
struct user_thread; // defined in libroot/user_thread.h
struct VMAddressSpace;
struct xsi_sem_context; // defined in xsi_semaphore.cpp
struct LockedPages;
typedef DoublyLinkedList<LockedPages> LockedPagesList;
namespace Scheduler {
struct ThreadData;
@@ -201,6 +198,12 @@ typedef int32 (*thread_entry_func)(thread_func, void *);
namespace BKernel {
struct GroupsArray : KernelReferenceable {
int count;
gid_t groups[];
};
template<typename IDType>
struct TeamThreadIteratorEntry
: DoublyLinkedListLinkImpl<TeamThreadIteratorEntry<IDType> > {
@@ -242,8 +245,6 @@ struct Team : TeamThreadIteratorEntry<team_id>, KernelReferenceable,
struct team_death_entry *death_entry; // protected by fLock
struct list dead_threads;
LockedPagesList locked_pages_list;
// protected by the team's fLock
team_dead_children dead_children;
team_job_control_children stopped_children;
@@ -287,8 +288,7 @@ struct Team : TeamThreadIteratorEntry<team_id>, KernelReferenceable,
gid_t saved_set_gid;
gid_t real_gid;
gid_t effective_gid;
gid_t* supplementary_groups;
int supplementary_group_count;
BReference<GroupsArray> supplementary_groups;
// Exit status information. Set when the first terminal event occurs,
// immutable afterwards. Protected by fLock.
headers/private/kernel/util/Bitmap.h
+31 -26
View File
@@ -1,82 +1,87 @@
/*
* Copyright 2013 Haiku, Inc. All rights reserved.
* Copyright 2013-2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Paweł Dziepak, [email protected]
* Augustin Cavalier <waddlesplash>
*/
#ifndef KERNEL_UTIL_BITMAP_H
#define KERNEL_UTIL_BITMAP_H
#include <debug.h>
#ifdef _KERNEL_MODE
# include <debug.h>
#else
# include <Debug.h>
#endif
#include <SupportDefs.h>
namespace BKernel {
class Bitmap {
public:
Bitmap(int bitCount);
Bitmap(size_t bitCount);
~Bitmap();
inline status_t GetInitStatus();
status_t InitCheck();
inline bool Get(int index) const;
inline void Set(int index);
inline void Clear(int index);
status_t Resize(size_t bitCount);
void Shift(ssize_t bitCount);
int GetHighestSet() const;
inline bool Get(size_t index) const;
inline void Set(size_t index);
inline void Clear(size_t index);
ssize_t GetHighestSet() const;
private:
status_t fInitStatus;
int fElementsCount;
int fSize;
size_t fElementsCount;
size_t fSize;
addr_t* fBits;
static const int kBitsPerElement;
static const int kBitsPerElement = (sizeof(addr_t) * 8);
};
status_t
Bitmap::GetInitStatus()
{
return fInitStatus;
}
bool
Bitmap::Get(int index) const
Bitmap::Get(size_t index) const
{
ASSERT(index < fSize);
const int kArrayElement = index / kBitsPerElement;
const size_t kArrayElement = index / kBitsPerElement;
const addr_t kBitMask = addr_t(1) << (index % kBitsPerElement);
return fBits[kArrayElement] & kBitMask;
}
void
Bitmap::Set(int index)
Bitmap::Set(size_t index)
{
ASSERT(index < fSize);
const int kArrayElement = index / kBitsPerElement;
const size_t kArrayElement = index / kBitsPerElement;
const addr_t kBitMask = addr_t(1) << (index % kBitsPerElement);
fBits[kArrayElement] |= kBitMask;
}
void
Bitmap::Clear(int index)
Bitmap::Clear(size_t index)
{
ASSERT(index < fSize);
const int kArrayElement = index / kBitsPerElement;
const size_t kArrayElement = index / kBitsPerElement;
const addr_t kBitMask = addr_t(1) << (index % kBitsPerElement);
fBits[kArrayElement] &= ~addr_t(kBitMask);
}
} // namespace BKernel
using BKernel::Bitmap;
#endif // KERNEL_UTIL_BITMAP_H
headers/private/kernel/util/atomic.h
+1 -1
View File
@@ -53,7 +53,7 @@ atomic_pointer_set(PointerType** _pointer, const PointerType* set)
template<typename PointerType> PointerType*
atomic_pointer_get(PointerType** _pointer)
atomic_pointer_get(PointerType* const* _pointer)
{
ASSERT((addr_t(_pointer) & (sizeof(PointerType*) - 1)) == 0);
#if LONG_MAX == INT_MAX
headers/private/libroot/locale/ICUCollateData.h
+1 -1
View File
@@ -33,7 +33,7 @@ public:
status_t Wcscoll(const wchar_t* a, const wchar_t* b,
int& out);
status_t Wcsxfrm(wchar_t* out, const wchar_t* in,
size_t size, size_t& outSize);
size_t outSize, size_t& requiredSize);
private:
status_t _ToUnicodeString(const char* in,
headers/private/libroot/locale/ICULocaleBackend.h
+1 -1
View File
@@ -64,7 +64,7 @@ public:
virtual status_t Wcscoll(const wchar_t* a, const wchar_t* b,
int& out);
virtual status_t Wcsxfrm(wchar_t* out, const wchar_t* in,
size_t size, size_t& outSize);
size_t outSize, size_t& requiredSize);
virtual status_t TZSet(const char* timeZoneID, const char* tz);
virtual status_t Localtime(const time_t* inTime,
headers/private/libroot/locale/LocaleBackend.h
+1 -1
View File
@@ -147,7 +147,7 @@ public:
virtual status_t Wcscoll(const wchar_t* a, const wchar_t* b,
int& out) = 0;
virtual status_t Wcsxfrm(wchar_t* out, const wchar_t* in,
size_t size, size_t& outSize) = 0;
size_t outSize, size_t& requiredSize) = 0;
virtual status_t TZSet(const char* timeZoneID,
const char* tz) = 0;
headers/private/libroot/time_private.h
+8
View File
@@ -67,6 +67,14 @@ timeval_to_timespec(const timeval& val, timespec& spec)
}
static inline bool
timeval_to_bigtime(const timeval& val, bigtime_t& _time)
{
timespec spec;
return timeval_to_timespec(val, spec) && timespec_to_bigtime(spec, _time);
}
static inline void
timespec_to_timeval(const timespec& spec, timeval& val)
{
headers/private/shared/AutoLocker.h
+8 -1
View File
@@ -155,10 +155,17 @@ public:
}
}
inline void Detach()
inline Lockable* Get()
{
return fLockable;
}
inline Lockable* Detach()
{
Lockable* res = fLockable;
fLockable = NULL;
fLocked = false;
return res;
}
inline AutoLocker<Lockable, Locking>& operator=(Lockable* lockable)
headers/private/shared/ExpressionParser.h
+2
View File
@@ -50,6 +50,8 @@ class ExpressionParser {
int64 EvaluateToInt64(const char* expressionString);
double EvaluateToDouble(const char* expressionString);
status_t SetSeparators(BString decimal, BString group);
private:
struct Token;
class Tokenizer;
headers/private/storage/DiskScannerAddOn.h
+1
View File
@@ -11,6 +11,7 @@ class BDiskScannerParameterEditor;
class BPartition;
class BSession;
class BString;
class BView;
// BDiskScannerPartitionAddOn
class BDiskScannerPartitionAddOn {
headers/private/system/arch/arm/arch_commpage_defs.h
+7 -5
View File
@@ -1,15 +1,17 @@
/*
* Copyright 2022, Haiku Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright 2007, Travis Geiselbrecht. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _SYSTEM_ARCH_M68K_COMMPAGE_DEFS_H
#define _SYSTEM_ARCH_M68K_COMMPAGE_DEFS_H
#ifndef _SYSTEM_ARCH_ARM_COMMPAGE_DEFS_H
#define _SYSTEM_ARCH_ARM_COMMPAGE_DEFS_H
#ifndef _SYSTEM_COMMPAGE_DEFS_H
# error Must not be included directly. Include <commpage_defs.h> instead!
#endif
//#define COMMPAGE_ENTRY_M68K_SYSCALL (COMMPAGE_ENTRY_FIRST_ARCH_SPECIFIC + 0)
//#define COMMPAGE_ENTRY_M68K_MEMCPY (COMMPAGE_ENTRY_FIRST_ARCH_SPECIFIC + 1)
#define COMMPAGE_ENTRY_ARM_THREAD_EXIT (COMMPAGE_ENTRY_FIRST_ARCH_SPECIFIC + 0)
#endif /* _SYSTEM_ARCH_M68K_COMMPAGE_DEFS_H */
#endif /* _SYSTEM_ARCH_ARM_COMMPAGE_DEFS_H */
headers/private/system/arch/arm/arch_cpu_defs.h
+13
View File
@@ -1,4 +1,7 @@
/*
* Copyright 2022, Haiku Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright 2010, Ingo Weinhold, ingo_weinhold@gmx.de.
* Distributed under the terms of the MIT License.
*/
@@ -8,5 +11,15 @@
#define SPINLOCK_PAUSE() do {} while (false)
#define CPSR_MODE_MASK 0x1f
#define CPSR_MODE_USR 0x10
#define CPSR_MODE_SVC 0x13
#define CPSR_MODE_SYS 0x1f
#define CPSR_T 0x20
#define CPSR_F 0x40
#define CPSR_I 0x80
#define FSR_WNR 0x800
#endif /* _SYSTEM_ARCH_ARM_DEFS_H */
headers/private/system/arch/arm/arch_elf.h
+1 -4
View File
@@ -6,7 +6,6 @@
#define _KERNEL_ARCH_ARM_ELF_H
/* ARM relocs. */
#define R_ARM_NONE 0 /* No reloc */
#define R_ARM_PC24 1 /* PC relative 26 bit branch */
@@ -50,9 +49,7 @@
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255
#define TLS_DTV_OFFSET 0
#endif /* _KERNEL_ARCH_M68K_ELF_H */
headers/private/system/arch/arm64/arch_elf.h
+2
View File
@@ -26,4 +26,6 @@
#define R_AARCH64_TLSDESC 1031 /* Identify the TLS descriptor */
#define R_AARCH64_IRELATIVE 1032 /* STT_GNU_IFUNC relocation. */
#define TLS_DTV_OFFSET 0
#endif /* _KERNEL_ARCH_ARM64_ELF_H */
headers/private/system/arch/m68k/arch_elf.h
+2
View File
@@ -34,4 +34,6 @@
#define R_68K_GNU_VTINHERIT 23
#define R_68K_GNU_VTENTRY 24
#define TLS_DTV_OFFSET 0
#endif /* _KERNEL_ARCH_M68K_ELF_H */
headers/private/system/arch/mipsel/arch_elf.h
+2
View File
@@ -49,5 +49,7 @@
#define R_MIPSEL_SECTOFF_HA 36
#define R_MIPSEL_ADDR30 37
#define TLS_DTV_OFFSET 0
#endif /* _SYSTEM_ARCH_MIPSEL_ELF_H */
headers/private/system/arch/ppc/arch_elf.h
+2
View File
@@ -46,4 +46,6 @@
#define R_PPC_SECTOFF_HA 36
#define R_PPC_ADDR30 37
#define TLS_DTV_OFFSET 0
#endif /* _KERNEL_ARCH_PPC_ELF_H */
headers/private/system/arch/riscv64/arch_cpu_defs.h
+1 -1
View File
@@ -37,7 +37,7 @@ struct MstatusReg {
uint64 mpp: 2; // previous mode (machine)
uint64 fs: 2; // FPU status
uint64 xs: 2; // extensions status
uint64 mprv: 1; // modify privelege
uint64 mprv: 1; // modify privilege
uint64 sum: 1; // permit supervisor user memory access
uint64 mxr: 1; // make executable readable
uint64 tvm: 1; // trap virtual memory
headers/private/system/arch/riscv64/arch_elf.h
+3
View File
@@ -62,4 +62,7 @@
#define R_RISCV_32_PCREL 57
#define R_RISCV_IRELATIVE 58
#define TLS_DTV_OFFSET 0x800
#endif /* _SYSTEM_ARCH_RISCV64_ELF_H */
headers/private/system/arch/sparc/arch_elf.h
+2
View File
@@ -69,4 +69,6 @@
#define R_SPARC_SIZE32 86
#define R_SPARC_SIZE64 87
#define TLS_DTV_OFFSET 0
#endif /* _KERNEL_ARCH_SPARC_ELF_H */
headers/private/system/arch/x86/arch_elf.h
+2
View File
@@ -50,6 +50,8 @@
#define R_386_IRELATIVE 42 /* PLT entry resolved indirectly at runtime */
#define R_386_GOT32X 43
#define TLS_DTV_OFFSET 0
#ifdef _BOOT_MODE
# include "../x86_64/arch_elf.h"
#endif
headers/private/system/arch/x86/arch_thread_defs.h
+13
View File
@@ -0,0 +1,13 @@
/*
* Copyright 2022, The Haiku Team. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _X86_THREAD_DEFS_H
#define _X86_THREAD_DEFS_H
#define THREAD_SYSCALLS "thread"
#define THREAD_SET_GS_BASE 1
#endif /* _X86_THREAD_DEFS_H */
headers/private/system/arch/x86_64/arch_elf.h
+2
View File
@@ -52,6 +52,8 @@
#define R_X86_64_REX_GOTPCRELX 41 /* Load from 32 bit signed pc relative offset to GOT entry
with REX prefix, relaxable. */
#define TLS_DTV_OFFSET 0
#if defined(_BOOT_MODE) || defined(ELF32_COMPAT)
# include "../x86/arch_elf.h"
headers/private/system/syscalls.h
+4 -1
View File
@@ -112,7 +112,8 @@ extern status_t _kern_realtime_sem_unlink(const char* name);
extern status_t _kern_realtime_sem_get_value(sem_id semID, int* value);
extern status_t _kern_realtime_sem_post(sem_id semID);
extern status_t _kern_realtime_sem_wait(sem_id semID, bigtime_t timeout);
extern status_t _kern_realtime_sem_wait(sem_id semID, uint32 flags,
bigtime_t timeout);
/* POSIX XSI semaphore syscalls */
extern int _kern_xsi_semget(key_t key, int numSems, int flags);
@@ -166,6 +167,8 @@ extern status_t _kern_cancel_thread(thread_id threadID,
extern void _kern_thread_yield(void);
extern status_t _kern_wait_for_thread(thread_id thread,
status_t *_returnCode);
extern status_t _kern_wait_for_thread_etc(thread_id thread, uint32 flags,
bigtime_t timeout, status_t *_returnCode);
extern bool _kern_has_data(thread_id thread);
extern status_t _kern_send_data(thread_id thread, int32 code,
const void *buffer, size_t bufferSize);
headers/private/system/user_runtime.h
+1 -1
View File
@@ -15,7 +15,7 @@
#define MAGIC_APP_NAME "_APP_"
#define MAX_PROCESS_ARGS_SIZE (128 * 1024)
#define MAX_PROCESS_ARGS_SIZE (256 * 1024)
// maximal total size needed for process arguments and environment strings
headers/private/virtio/virtio.h
+3 -2
View File
@@ -28,10 +28,11 @@
#define VIRTIO_FEATURE_TRANSPORT_MASK ((1 << 28) - 1)
#define VIRTIO_FEATURE_NOTIFY_ON_EMPTY (1 << 24)
#define VIRTIO_FEATURE_NOTIFY_ON_EMPTY (1 << 24)
#define VIRTIO_FEATURE_ANY_LAYOUT (1 << 27)
#define VIRTIO_FEATURE_RING_INDIRECT_DESC (1 << 28)
#define VIRTIO_FEATURE_RING_EVENT_IDX (1 << 29)
#define VIRTIO_FEATURE_BAD_FEATURE (1 << 30)
#define VIRTIO_FEATURE_BAD_FEATURE (1 << 30)
#define VIRTIO_VIRTQUEUES_MAX_COUNT 8
headers/tools/cppunit/cppunit/config-auto.h
+26 -22
View File
@@ -1,62 +1,66 @@
#ifndef _INCLUDE_CPPUNIT_CONFIG_AUTO_H
#define _INCLUDE_CPPUNIT_CONFIG_AUTO_H 1
/* include/cppunit/config-auto.h. Generated automatically at end of configure. */
/* config/config.h. Generated automatically by configure. */
/* config/config.h.in. Generated automatically from configure.in by autoheader. */
/* define if library uses string::compare(string,pos,n) */
#ifndef CPPUNIT_FUNC_STRING_COMPARE_STRING_FIRST
#define CPPUNIT_FUNC_STRING_COMPARE_STRING_FIRST 1
#ifndef CPPUNIT_FUNC_STRING_COMPARE_STRING_FIRST
#define CPPUNIT_FUNC_STRING_COMPARE_STRING_FIRST 1
#endif
/* define if the library defines strstream */
#ifndef CPPUNIT_HAVE_CLASS_STRSTREAM
#define CPPUNIT_HAVE_CLASS_STRSTREAM 1
#ifndef CPPUNIT_HAVE_CLASS_STRSTREAM
#define CPPUNIT_HAVE_CLASS_STRSTREAM 1
#endif
/* Define if you have the <cmath> header file. */
#ifndef CPPUNIT_HAVE_CMATH
#define CPPUNIT_HAVE_CMATH 1
#ifndef CPPUNIT_HAVE_CMATH
#define CPPUNIT_HAVE_CMATH 1
#endif
/* Define if you have the <dlfcn.h> header file. */
/* #undef CPPUNIT_HAVE_DLFCN_H */
/* define to 1 if the compiler implements namespaces */
#ifndef CPPUNIT_HAVE_NAMESPACES
#define CPPUNIT_HAVE_NAMESPACES 1
#ifndef CPPUNIT_HAVE_NAMESPACES
#define CPPUNIT_HAVE_NAMESPACES 1
#endif
/* define if the compiler supports Run-Time Type Identification */
#ifndef CPPUNIT_HAVE_RTTI
#define CPPUNIT_HAVE_RTTI 1
#ifndef CPPUNIT_HAVE_RTTI
#define CPPUNIT_HAVE_RTTI 1
#endif
/* define if the compiler has stringstream */
#ifndef CPPUNIT_HAVE_SSTREAM
#define CPPUNIT_HAVE_SSTREAM 1
#ifndef CPPUNIT_HAVE_SSTREAM
#if __GNUC__ >= 4
#define CPPUNIT_HAVE_SSTREAM 1
#else
/* #undef CPPUNIT_HAVE_SSTREAM */
#endif
#endif
/* Define if you have the <strstream> header file. */
#ifndef CPPUNIT_HAVE_STRSTREAM
#define CPPUNIT_HAVE_STRSTREAM 1
#ifndef CPPUNIT_HAVE_STRSTREAM
#define CPPUNIT_HAVE_STRSTREAM 1
#endif
/* Name of package */
#ifndef CPPUNIT_PACKAGE
#define CPPUNIT_PACKAGE "cppunit"
#ifndef CPPUNIT_PACKAGE
#define CPPUNIT_PACKAGE "cppunit"
#endif
/* Define to 1 to use type_info::name() for class names */
#ifndef CPPUNIT_USE_TYPEINFO_NAME
#define CPPUNIT_USE_TYPEINFO_NAME CPPUNIT_HAVE_RTTI
#ifndef CPPUNIT_USE_TYPEINFO_NAME
#define CPPUNIT_USE_TYPEINFO_NAME CPPUNIT_HAVE_RTTI
#endif
/* Version number of package */
#ifndef CPPUNIT_VERSION
#define CPPUNIT_VERSION "1.8.0"
#ifndef CPPUNIT_VERSION
#define CPPUNIT_VERSION "1.8.0"
#endif
/* _INCLUDE_CPPUNIT_CONFIG_AUTO_H */
#endif