pre-work style cleanup; no functional change

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41028 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/accelerants/radeon_hd/accelerant.cpp

@@ -118,8 +118,8 @@ init_common(int device, bool isClone)
 	status_t status = sharedCloner.InitCheck();
 	if (status < B_OK) {
 		free(gInfo);
-		TRACE(("radeon_init_accelerant() failed shared area%i, %i\n", data.shared_info_area,
+		TRACE(("radeon_init_accelerant() failed shared area%i, %i\n",
-			gInfo->shared_info_area));
+			data.shared_info_area, gInfo->shared_info_area));
 		return status;
 	}
 

src/add-ons/accelerants/radeon_hd/accelerant.h

@@ -50,12 +50,14 @@ read32(uint32 offset)
 	return *(volatile uint32 *)(gInfo->regs + offset);
 }
 
+
 inline void
 write32(uint32 offset, uint32 value)
 {
 	*(volatile uint32 *)(gInfo->regs + offset) = value;
 }
 
+
 // modes.cpp
 extern status_t create_mode_list(void);
 

src/add-ons/accelerants/radeon_hd/engine.cpp

@@ -30,8 +30,8 @@ static engine_token sEngineToken = {1, 0 /*B_2D_ACCELERATION*/, NULL};
 
 
 status_t
-radeon_acquire_engine(uint32 capabilities, uint32 maxWait, sync_token *syncToken,
+radeon_acquire_engine(uint32 capabilities, uint32 maxWait,
-	engine_token **_engineToken)
+	sync_token *syncToken, engine_token **_engineToken)
 {
 	TRACE(("radeon_acquire_engine()\n"));
 	*_engineToken = &sEngineToken;

src/add-ons/accelerants/radeon_hd/mode.cpp

@@ -38,23 +38,26 @@ static display_mode gDisplayMode;
 status_t
 create_mode_list(void)
 {
+	// TODO : Read active monitor EDID
+
+	/* Populate modeline with temporary example */
 	gDisplayMode.timing.pixel_clock = 71500;
-	gDisplayMode.timing.h_display = 1366;					/* in pixels (not character clocks) */
+	gDisplayMode.timing.h_display = 1366;	// In Pixels
 	gDisplayMode.timing.h_sync_start = 1406;
 	gDisplayMode.timing.h_sync_end = 1438;
 	gDisplayMode.timing.h_total = 1510;
-	gDisplayMode.timing.v_display = 768;					/* in lines */
+	gDisplayMode.timing.v_display = 768;	// In Pixels
 	gDisplayMode.timing.v_sync_start = 771;
 	gDisplayMode.timing.v_sync_end = 777;
 	gDisplayMode.timing.v_total = 789;
-	gDisplayMode.timing.flags = 0;						/* sync polarity, etc. */
+	gDisplayMode.timing.flags = 0;			// Polarity, ex: B_POSITIVE_HSYNC
 
-	gDisplayMode.space = B_RGB32_LITTLE;				/* pixel configuration */
+	gDisplayMode.space = B_RGB32_LITTLE;	// Pixel configuration
-	gDisplayMode.virtual_width = 1366;		/* in pixels */
+	gDisplayMode.virtual_width = 1366;		// In Pixels
-	gDisplayMode.virtual_height = 768;		/* in lines */
+	gDisplayMode.virtual_height = 768;		// In Pixels
-	gDisplayMode.h_display_start = 0;	/* first displayed pixel in line */
+	gDisplayMode.h_display_start = 0;
-	gDisplayMode.v_display_start = 0;	/* first displayed line */
+	gDisplayMode.v_display_start = 0;
-	gDisplayMode.flags = 0;				/* mode flags (Some drivers use this */
+	gDisplayMode.flags = 0;					// Mode flags (Some drivers use this
 
 	gInfo->mode_list = &gDisplayMode;
 	gInfo->shared_info->mode_count = 1;
@@ -196,6 +199,7 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode,
 		bytesPerRow = (bytesPerRow + 63) & ~63;
 }
 
+
 #define D1_REG_OFFSET 0x0000
 #define D2_REG_OFFSET 0x0800
 
@@ -222,7 +226,7 @@ DxModeSet(display_mode *mode)
 	write32(regOffset + D1CRTC_H_SYNC_A,
 		(displayTiming.h_sync_end - displayTiming.h_sync_start) << 16);
 //	write32(regOffset + D1CRTC_H_SYNC_A_CNTL, Mode->Flags & V_NHSYNC);
-    //!!!write32(regOffset + D1CRTC_H_SYNC_A_CNTL, V_NHSYNC);
+//!	write32(regOffset + D1CRTC_H_SYNC_A_CNTL, V_NHSYNC);
 
 	/* Vertical */
 	write32(regOffset + D1CRTC_V_TOTAL, displayTiming.v_total - 1);
@@ -245,9 +249,11 @@ DxModeSet(display_mode *mode)
 	write32(regOffset + D1CRTC_V_SYNC_A,
 		(displayTiming.v_sync_end - displayTiming.v_sync_start) << 16);
 //	write32(regOffset + D1CRTC_V_SYNC_A_CNTL, Mode->Flags & V_NVSYNC);
-    //!!!write32(regOffset + D1CRTC_V_SYNC_A_CNTL, V_NVSYNC);
+//!	write32(regOffset + D1CRTC_V_SYNC_A_CNTL, V_NVSYNC);
 
-    /* set D1CRTC_HORZ_COUNT_BY2_EN to 0; should only be set to 1 on 30bpp DVI modes */
+	/*	set D1CRTC_HORZ_COUNT_BY2_EN to 0;
+		should only be set to 1 on 30bpp DVI modes
+	*/
 	write32AtMask(regOffset + D1CRTC_COUNT_CONTROL, 0x0, 0x1);
 
 }

src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp

@@ -39,9 +39,12 @@
 static status_t device_open(const char *name, uint32 flags, void **_cookie);
 static status_t device_close(void *data);
 static status_t device_free(void *data);
-static status_t device_ioctl(void *data, uint32 opcode, void *buffer, size_t length);
+static status_t device_ioctl(void *data, uint32 opcode,
-static status_t device_read(void *data, off_t offset, void *buffer, size_t *length);
+	void *buffer, size_t length);
-static status_t device_write(void *data, off_t offset, const void *buffer, size_t *length);
+static status_t device_read(void *data, off_t offset,
+	void *buffer, size_t *length);
+static status_t device_write(void *data, off_t offset,
+	const void *buffer, size_t *length);
 
 
 device_hooks gDeviceHooks = {
@@ -207,7 +210,8 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength)
 
 
 static status_t
-device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length)
+device_read(void */*data*/, off_t /*pos*/,
+	void */*buffer*/, size_t *_length)
 {
 	*_length = 0;
 	return B_NOT_ALLOWED;
@@ -215,7 +219,8 @@ device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length)
 
 
 static status_t
-device_write(void */*data*/, off_t /*pos*/, const void */*buffer*/, size_t *_length)
+device_write(void */*data*/, off_t /*pos*/,
+	const void */*buffer*/, size_t *_length)
 {
 	*_length = 0;
 	return B_NOT_ALLOWED;

src/add-ons/kernel/drivers/graphics/radeon_hd/driver.h

@@ -50,4 +50,6 @@ set_pci_config(pci_info* info, uint8 offset, uint8 size, uint32 value)
 		size, value);
 }
 
+
 #endif  /* DRIVER_H */
+

src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp

@@ -42,8 +42,9 @@
 status_t
 radeon_hd_init(radeon_info &info)
 {
-	// memory mapped I/O
+	TRACE((DEVICE_NAME ": radeon_hd_init() called\n"));
 
+	// memory mapped I/O
 	AreaKeeper sharedCreator;
 	info.shared_area = sharedCreator.Create("radeon hd shared info",
 		(void **)&info.shared_info, B_ANY_KERNEL_ADDRESS,
@@ -86,9 +87,10 @@ radeon_hd_init(radeon_info &info)
 
 	info.shared_info->registers_area = info.registers_area;
 	info.shared_info->frame_buffer_offset = 0;
-	info.shared_info->physical_graphics_memory = info.pci->u.h0.base_registers[RHD_FB_BAR];
+	info.shared_info->physical_graphics_memory
+		= info.pci->u.h0.base_registers[RHD_FB_BAR];
 
-	TRACE((DEVICE_NAME "radeon_hd_init() completed successfully!\n"));
+	TRACE((DEVICE_NAME ": radeon_hd_init() completed successfully!\n"));
 	return B_OK;
 }