diff --git a/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c b/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c new file mode 100644 index 0000000000..51f316de3d --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c @@ -0,0 +1,2690 @@ +/* $OpenBSD: if_rge.c,v 1.21 2022/12/21 02:31:09 kevlo Exp $ */ + +/* + * Copyright (c) 2019, 2020 Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "bpfilter.h" +#include "vlan.h" +#include "kstat.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#if NBPFILTER > 0 +#include +#endif + +#if NKSTAT > 0 +#include +#endif + +#include +#include + +#include + +#include +#include +#include + +#include + +#ifdef RGE_DEBUG +#define DPRINTF(x) do { if (rge_debug > 0) printf x; } while (0) +int rge_debug = 0; +#else +#define DPRINTF(x) +#endif + +int rge_match(struct device *, void *, void *); +void rge_attach(struct device *, struct device *, void *); +int rge_activate(struct device *, int); +int rge_intr(void *); +int rge_encap(struct rge_queues *, struct mbuf *, int); +int rge_ioctl(struct ifnet *, u_long, caddr_t); +void rge_start(struct ifqueue *); +void rge_watchdog(struct ifnet *); +int rge_init(struct ifnet *); +void rge_stop(struct ifnet *); +int rge_ifmedia_upd(struct ifnet *); +void rge_ifmedia_sts(struct ifnet *, struct ifmediareq *); +int rge_allocmem(struct rge_softc *); +int rge_newbuf(struct rge_queues *); +void rge_discard_rxbuf(struct rge_queues *, int); +void rge_rx_list_init(struct rge_queues *); +void rge_tx_list_init(struct rge_queues *); +void rge_fill_rx_ring(struct rge_queues *); +int rge_rxeof(struct rge_queues *); +int rge_txeof(struct rge_queues *); +void rge_reset(struct rge_softc *); +void rge_iff(struct rge_softc *); +void rge_set_phy_power(struct rge_softc *, int); +void rge_phy_config(struct rge_softc *); +void rge_phy_config_mac_cfg2(struct rge_softc *); +void rge_phy_config_mac_cfg3(struct rge_softc *); +void rge_phy_config_mac_cfg4(struct rge_softc *); +void rge_phy_config_mac_cfg5(struct rge_softc *); +void rge_phy_config_mcu(struct rge_softc *, uint16_t); +void rge_set_macaddr(struct rge_softc *, const uint8_t *); +void rge_get_macaddr(struct rge_softc *, uint8_t *); +void rge_hw_init(struct rge_softc *); +void rge_disable_phy_ocp_pwrsave(struct rge_softc *); +void rge_patch_phy_mcu(struct rge_softc *, int); +void rge_add_media_types(struct rge_softc *); +void rge_config_imtype(struct rge_softc *, int); +void rge_disable_hw_im(struct rge_softc *); +void rge_disable_sim_im(struct rge_softc *); +void rge_setup_sim_im(struct rge_softc *); +void rge_setup_intr(struct rge_softc *, int); +void rge_exit_oob(struct rge_softc *); +void rge_write_csi(struct rge_softc *, uint32_t, uint32_t); +uint32_t rge_read_csi(struct rge_softc *, uint32_t); +void rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t); +uint16_t rge_read_mac_ocp(struct rge_softc *, uint16_t); +void rge_write_ephy(struct rge_softc *, uint16_t, uint16_t); +uint16_t rge_read_ephy(struct rge_softc *, uint16_t); +void rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t); +uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t); +void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t); +uint16_t rge_read_phy_ocp(struct rge_softc *, uint16_t); +int rge_get_link_status(struct rge_softc *); +void rge_txstart(void *); +void rge_tick(void *); +void rge_link_state(struct rge_softc *); +#ifndef SMALL_KERNEL +int rge_wol(struct ifnet *, int); +void rge_wol_power(struct rge_softc *); +#endif + +#if NKSTAT > 0 +void rge_kstat_attach(struct rge_softc *); +#endif + +static const struct { + uint16_t reg; + uint16_t val; +} rtl8125_mac_cfg2_mcu[] = { + RTL8125_MAC_CFG2_MCU +}, rtl8125_mac_cfg3_mcu[] = { + RTL8125_MAC_CFG3_MCU +}, rtl8125_mac_cfg4_mcu[] = { + RTL8125_MAC_CFG4_MCU +}, rtl8125_mac_cfg5_mcu[] = { + RTL8125_MAC_CFG5_MCU +}; + +const struct cfattach rge_ca = { + sizeof(struct rge_softc), rge_match, rge_attach, NULL, rge_activate +}; + +struct cfdriver rge_cd = { + NULL, "rge", DV_IFNET +}; + +const struct pci_matchid rge_devices[] = { + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000 }, + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125 } +}; + +int +rge_match(struct device *parent, void *match, void *aux) +{ + return (pci_matchbyid((struct pci_attach_args *)aux, rge_devices, + nitems(rge_devices))); +} + +void +rge_attach(struct device *parent, struct device *self, void *aux) +{ + struct rge_softc *sc = (struct rge_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr = NULL; + struct ifnet *ifp; + struct rge_queues *q; + pcireg_t reg; + uint32_t hwrev; + uint8_t eaddr[ETHER_ADDR_LEN]; + int offset; + + pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); + + /* + * Map control/status registers. + */ + if (pci_mapreg_map(pa, RGE_PCI_BAR2, PCI_MAPREG_TYPE_MEM | + PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle, + NULL, &sc->rge_bsize, 0)) { + if (pci_mapreg_map(pa, RGE_PCI_BAR1, PCI_MAPREG_TYPE_MEM | + PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag, + &sc->rge_bhandle, NULL, &sc->rge_bsize, 0)) { + if (pci_mapreg_map(pa, RGE_PCI_BAR0, PCI_MAPREG_TYPE_IO, + 0, &sc->rge_btag, &sc->rge_bhandle, NULL, + &sc->rge_bsize, 0)) { + printf(": can't map mem or i/o space\n"); + return; + } + } + } + + q = malloc(sizeof(struct rge_queues), M_DEVBUF, M_NOWAIT | M_ZERO); + if (q == NULL) { + printf(": unable to allocate queue memory\n"); + return; + } + q->q_sc = sc; + q->q_index = 0; + + sc->sc_queues = q; + sc->sc_nqueues = 1; + + /* + * Allocate interrupt. + */ + if (pci_intr_map_msi(pa, &ih) == 0) + sc->rge_flags |= RGE_FLAG_MSI; + else if (pci_intr_map(pa, &ih) != 0) { + printf(": couldn't map interrupt\n"); + return; + } + intrstr = pci_intr_string(pc, ih); + sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, rge_intr, + sc, sc->sc_dev.dv_xname); + if (sc->sc_ih == NULL) { + printf(": couldn't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + return; + } + printf(": %s", intrstr); + + sc->sc_dmat = pa->pa_dmat; + sc->sc_pc = pa->pa_pc; + sc->sc_tag = pa->pa_tag; + + /* Determine hardware revision */ + hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV; + switch (hwrev) { + case 0x60800000: + sc->rge_type = MAC_CFG2; + break; + case 0x60900000: + sc->rge_type = MAC_CFG3; + break; + case 0x64000000: + sc->rge_type = MAC_CFG4; + break; + case 0x64100000: + sc->rge_type = MAC_CFG5; + break; + default: + printf(": unknown version 0x%08x\n", hwrev); + return; + } + + rge_config_imtype(sc, RGE_IMTYPE_SIM); + + /* + * PCI Express check. + */ + if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, + &offset, NULL)) { + /* Disable PCIe ASPM and ECPM. */ + reg = pci_conf_read(pa->pa_pc, pa->pa_tag, + offset + PCI_PCIE_LCSR); + reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 | + PCI_PCIE_LCSR_ECPM); + pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCI_PCIE_LCSR, + reg); + } + + rge_exit_oob(sc); + rge_hw_init(sc); + + rge_get_macaddr(sc, eaddr); + printf(", address %s\n", ether_sprintf(eaddr)); + + memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN); + + rge_set_phy_power(sc, 1); + rge_phy_config(sc); + + if (rge_allocmem(sc)) + return; + + ifp = &sc->sc_arpcom.ac_if; + ifp->if_softc = sc; + strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_xflags = IFXF_MPSAFE; + ifp->if_ioctl = rge_ioctl; + ifp->if_qstart = rge_start; + ifp->if_watchdog = rge_watchdog; + ifq_set_maxlen(&ifp->if_snd, RGE_TX_LIST_CNT - 1); + ifp->if_hardmtu = RGE_JUMBO_MTU; + + ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | + IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; + +#if NVLAN > 0 + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; +#endif + +#ifndef SMALL_KERNEL + ifp->if_capabilities |= IFCAP_WOL; + ifp->if_wol = rge_wol; + rge_wol(ifp, 0); +#endif + timeout_set(&sc->sc_timeout, rge_tick, sc); + task_set(&sc->sc_task, rge_txstart, sc); + + /* Initialize ifmedia structures. */ + ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd, + rge_ifmedia_sts); + rge_add_media_types(sc); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); + sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media; + + if_attach(ifp); + ether_ifattach(ifp); + +#if NKSTAT > 0 + rge_kstat_attach(sc); +#endif +} + +int +rge_activate(struct device *self, int act) +{ +#ifndef SMALL_KERNEL + struct rge_softc *sc = (struct rge_softc *)self; +#endif + int rv = 0; + + switch (act) { + case DVACT_POWERDOWN: + rv = config_activate_children(self, act); +#ifndef SMALL_KERNEL + rge_wol_power(sc); +#endif + break; + default: + rv = config_activate_children(self, act); + break; + } + return (rv); +} + +int +rge_intr(void *arg) +{ + struct rge_softc *sc = arg; + struct rge_queues *q = sc->sc_queues; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + uint32_t status; + int claimed = 0, rv; + + if (!(ifp->if_flags & IFF_RUNNING)) + return (0); + + /* Disable interrupts. */ + RGE_WRITE_4(sc, RGE_IMR, 0); + + if (!(sc->rge_flags & RGE_FLAG_MSI)) { + if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0) + return (0); + } + + status = RGE_READ_4(sc, RGE_ISR); + if (status) + RGE_WRITE_4(sc, RGE_ISR, status); + + if (status & RGE_ISR_PCS_TIMEOUT) + claimed = 1; + + rv = 0; + if (status & sc->rge_intrs) { + rv |= rge_rxeof(q); + rv |= rge_txeof(q); + + if (status & RGE_ISR_SYSTEM_ERR) { + KERNEL_LOCK(); + rge_init(ifp); + KERNEL_UNLOCK(); + } + claimed = 1; + } + + if (sc->rge_timerintr) { + if (!rv) { + /* + * Nothing needs to be processed, fallback + * to use TX/RX interrupts. + */ + rge_setup_intr(sc, RGE_IMTYPE_NONE); + + /* + * Recollect, mainly to avoid the possible + * race introduced by changing interrupt + * masks. + */ + rge_rxeof(q); + rge_txeof(q); + } else + RGE_WRITE_4(sc, RGE_TIMERCNT, 1); + } else if (rv) { + /* + * Assume that using simulated interrupt moderation + * (hardware timer based) could reduce the interrupt + * rate. + */ + rge_setup_intr(sc, RGE_IMTYPE_SIM); + } + + RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); + + return (claimed); +} + +int +rge_encap(struct rge_queues *q, struct mbuf *m, int idx) +{ + struct rge_softc *sc = q->q_sc; + struct rge_tx_desc *d = NULL; + struct rge_txq *txq; + bus_dmamap_t txmap; + uint32_t cmdsts, cflags = 0; + int cur, error, i, last, nsegs; + + /* + * Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested. + * Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not + * take affect. + */ + if ((m->m_pkthdr.csum_flags & + (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { + cflags |= RGE_TDEXTSTS_IPCSUM; + if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) + cflags |= RGE_TDEXTSTS_TCPCSUM; + if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) + cflags |= RGE_TDEXTSTS_UDPCSUM; + } + + txq = &q->q_tx.rge_txq[idx]; + txmap = txq->txq_dmamap; + + error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT); + switch (error) { + case 0: + break; + case EFBIG: /* mbuf chain is too fragmented */ + if (m_defrag(m, M_DONTWAIT) == 0 && + bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, + BUS_DMA_NOWAIT) == 0) + break; + + /* FALLTHROUGH */ + default: + return (0); + } + + bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, + BUS_DMASYNC_PREWRITE); + + nsegs = txmap->dm_nsegs; + + /* Set up hardware VLAN tagging. */ +#if NVLAN > 0 + if (m->m_flags & M_VLANTAG) + cflags |= swap16(m->m_pkthdr.ether_vtag) | RGE_TDEXTSTS_VTAG; +#endif + + cur = idx; + cmdsts = RGE_TDCMDSTS_SOF; + + for (i = 0; i < txmap->dm_nsegs; i++) { + d = &q->q_tx.rge_tx_list[cur]; + + d->rge_extsts = htole32(cflags); + d->rge_addrlo = htole32(RGE_ADDR_LO(txmap->dm_segs[i].ds_addr)); + d->rge_addrhi = htole32(RGE_ADDR_HI(txmap->dm_segs[i].ds_addr)); + + cmdsts |= txmap->dm_segs[i].ds_len; + + if (cur == RGE_TX_LIST_CNT - 1) + cmdsts |= RGE_TDCMDSTS_EOR; + + d->rge_cmdsts = htole32(cmdsts); + + last = cur; + cmdsts = RGE_TDCMDSTS_OWN; + cur = RGE_NEXT_TX_DESC(cur); + } + + /* Set EOF on the last descriptor. */ + d->rge_cmdsts |= htole32(RGE_TDCMDSTS_EOF); + + /* Transfer ownership of packet to the chip. */ + d = &q->q_tx.rge_tx_list[idx]; + + d->rge_cmdsts |= htole32(RGE_TDCMDSTS_OWN); + + bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, + cur * sizeof(struct rge_tx_desc), sizeof(struct rge_tx_desc), + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* Update info of TX queue and descriptors. */ + txq->txq_mbuf = m; + txq->txq_descidx = last; + + return (nsegs); +} + +int +rge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct rge_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + int s, error = 0; + + s = splnet(); + + switch (cmd) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + if (!(ifp->if_flags & IFF_RUNNING)) + rge_init(ifp); + break; + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING) + error = ENETRESET; + else + rge_init(ifp); + } else { + if (ifp->if_flags & IFF_RUNNING) + rge_stop(ifp); + } + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); + break; + case SIOCGIFRXR: + error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, + NULL, RGE_JUMBO_FRAMELEN, &sc->sc_queues->q_rx.rge_rx_ring); + break; + default: + error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); + } + + if (error == ENETRESET) { + if (ifp->if_flags & IFF_RUNNING) + rge_iff(sc); + error = 0; + } + + splx(s); + return (error); +} + +void +rge_start(struct ifqueue *ifq) +{ + struct ifnet *ifp = ifq->ifq_if; + struct rge_softc *sc = ifp->if_softc; + struct rge_queues *q = sc->sc_queues; + struct mbuf *m; + int free, idx, used; + int queued = 0; + + if (!LINK_STATE_IS_UP(ifp->if_link_state)) { + ifq_purge(ifq); + return; + } + + /* Calculate free space. */ + idx = q->q_tx.rge_txq_prodidx; + free = q->q_tx.rge_txq_considx; + if (free <= idx) + free += RGE_TX_LIST_CNT; + free -= idx; + + for (;;) { + if (RGE_TX_NSEGS >= free + 2) { + ifq_set_oactive(&ifp->if_snd); + break; + } + + m = ifq_dequeue(ifq); + if (m == NULL) + break; + + used = rge_encap(q, m, idx); + if (used == 0) { + m_freem(m); + continue; + } + + KASSERT(used <= free); + free -= used; + +#if NBPFILTER > 0 + if (ifp->if_bpf) + bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); +#endif + + idx += used; + if (idx >= RGE_TX_LIST_CNT) + idx -= RGE_TX_LIST_CNT; + + queued++; + } + + if (queued == 0) + return; + + /* Set a timeout in case the chip goes out to lunch. */ + ifp->if_timer = 5; + + q->q_tx.rge_txq_prodidx = idx; + ifq_serialize(ifq, &sc->sc_task); +} + +void +rge_watchdog(struct ifnet *ifp) +{ + struct rge_softc *sc = ifp->if_softc; + + printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + + rge_init(ifp); +} + +int +rge_init(struct ifnet *ifp) +{ + struct rge_softc *sc = ifp->if_softc; + struct rge_queues *q = sc->sc_queues; + uint32_t val; + int i; + + rge_stop(ifp); + + /* Set MAC address. */ + rge_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); + + /* Set Maximum frame size. */ + RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); + + /* Initialize RX and TX descriptors lists. */ + rge_rx_list_init(q); + rge_tx_list_init(q); + + /* Load the addresses of the RX and TX lists into the chip. */ + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + RGE_CLRBIT_1(sc, 0xf1, 0x80); + RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); + RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_RDY_TO_L23); + + /* Clear interrupt moderation timer. */ + for (i = 0; i < 64; i++) + RGE_WRITE_4(sc, RGE_INTMITI(i), 0); + + /* Set the initial RX and TX configurations. */ + RGE_WRITE_4(sc, RGE_RXCFG, RGE_RXCFG_CONFIG); + RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG); + + val = rge_read_csi(sc, 0x70c) & ~0xff000000; + rge_write_csi(sc, 0x70c, val | 0x27000000); + + /* Enable hardware optimization function. */ + val = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x78) & ~0x00007000; + pci_conf_write(sc->sc_pc, sc->sc_tag, 0x78, val | 0x00005000); + + RGE_WRITE_2(sc, 0x0382, 0x221b); + + RGE_WRITE_1(sc, RGE_RSS_CTRL, 0); + + val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c; + RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2); + + RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN); + + rge_write_mac_ocp(sc, 0xc140, 0xffff); + rge_write_mac_ocp(sc, 0xc142, 0xffff); + + RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); + + val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700; + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) + rge_write_mac_ocp(sc, 0xe614, val | 0x0400); + else + rge_write_mac_ocp(sc, 0xe614, val | 0x0200); + + val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00; + rge_write_mac_ocp(sc, 0xe63e, val | + ((fls(sc->sc_nqueues) - 1) & 0x03) << 10); + + RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030); + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) + RGE_MAC_SETBIT(sc, 0xe63e, 0x0020); + + RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001); + RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001); + RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c); + + val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff; + rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033); + + val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0; + rge_write_mac_ocp(sc, 0xeb50, val | 0x0040); + + val = rge_read_mac_ocp(sc, 0xe056) & ~0x00f0; + rge_write_mac_ocp(sc, 0xe056, val | 0x0030); + + RGE_WRITE_1(sc, RGE_TDFNR, 0x10); + + RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_TX_10M_PS_EN); + + RGE_MAC_CLRBIT(sc, 0xe040, 0x1000); + + val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003; + rge_write_mac_ocp(sc, 0xea1c, val | 0x0001); + + val = rge_read_mac_ocp(sc, 0xe0c0) & ~0x4f0f; + rge_write_mac_ocp(sc, 0xe0c0, val | 0x4403); + + RGE_MAC_SETBIT(sc, 0xe052, 0x0068); + RGE_MAC_CLRBIT(sc, 0xe052, 0x0080); + + val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff; + rge_write_mac_ocp(sc, 0xd430, val | 0x047f); + + RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN); + + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) + RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01); + + /* Disable EEE plus. */ + RGE_MAC_CLRBIT(sc, 0xe080, 0x0002); + + RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004); + + RGE_MAC_SETBIT(sc, 0xeb54, 0x0001); + DELAY(1); + RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001); + + RGE_CLRBIT_4(sc, 0x1880, 0x0030); + + rge_write_mac_ocp(sc, 0xe098, 0xc302); + + if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) + RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); + + RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM); + + for (i = 0; i < 10; i++) { + if (!(rge_read_mac_ocp(sc, 0xe00e) & 0x2000)) + break; + DELAY(1000); + } + + /* Disable RXDV gate. */ + RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); + DELAY(2000); + + rge_ifmedia_upd(ifp); + + /* Enable transmit and receive. */ + RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); + + /* Program promiscuous mode and multicast filters. */ + rge_iff(sc); + + RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); + + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + /* Enable interrupts. */ + rge_setup_intr(sc, RGE_IMTYPE_SIM); + + ifp->if_flags |= IFF_RUNNING; + ifq_clr_oactive(&ifp->if_snd); + + timeout_add_sec(&sc->sc_timeout, 1); + + return (0); +} + +/* + * Stop the adapter and free any mbufs allocated to the RX and TX lists. + */ +void +rge_stop(struct ifnet *ifp) +{ + struct rge_softc *sc = ifp->if_softc; + struct rge_queues *q = sc->sc_queues; + int i; + + timeout_del(&sc->sc_timeout); + + ifp->if_timer = 0; + ifp->if_flags &= ~IFF_RUNNING; + sc->rge_timerintr = 0; + + RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | + RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | + RGE_RXCFG_ERRPKT); + + RGE_WRITE_4(sc, RGE_IMR, 0); + RGE_WRITE_4(sc, RGE_ISR, 0); + + /* Clear timer interrupts. */ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + RGE_WRITE_4(sc, RGE_TIMERINT1, 0); + RGE_WRITE_4(sc, RGE_TIMERINT2, 0); + RGE_WRITE_4(sc, RGE_TIMERINT3, 0); + + rge_reset(sc); + + intr_barrier(sc->sc_ih); + ifq_barrier(&ifp->if_snd); + ifq_clr_oactive(&ifp->if_snd); + + if (q->q_rx.rge_head != NULL) { + m_freem(q->q_rx.rge_head); + q->q_rx.rge_head = q->q_rx.rge_tail = NULL; + } + + /* Free the TX list buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + if (q->q_tx.rge_txq[i].txq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat, + q->q_tx.rge_txq[i].txq_dmamap); + m_freem(q->q_tx.rge_txq[i].txq_mbuf); + q->q_tx.rge_txq[i].txq_mbuf = NULL; + } + } + + /* Free the RX list buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat, + q->q_rx.rge_rxq[i].rxq_dmamap); + m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); + q->q_rx.rge_rxq[i].rxq_mbuf = NULL; + } + } +} + +/* + * Set media options. + */ +int +rge_ifmedia_upd(struct ifnet *ifp) +{ + struct rge_softc *sc = ifp->if_softc; + struct ifmedia *ifm = &sc->sc_media; + int anar, gig, val; + + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return (EINVAL); + + /* Disable Gigabit Lite. */ + RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); + RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); + + val = rge_read_phy_ocp(sc, 0xa5d4); + val &= ~RGE_ADV_2500TFDX; + + anar = gig = 0; + switch (IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_AUTO: + anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + val |= RGE_ADV_2500TFDX; + break; + case IFM_2500_T: + anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + val |= RGE_ADV_2500TFDX; + ifp->if_baudrate = IF_Mbps(2500); + break; + case IFM_1000_T: + anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + ifp->if_baudrate = IF_Gbps(1); + break; + case IFM_100_TX: + gig = rge_read_phy(sc, 0, MII_100T2CR) & + ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); + anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? + ANAR_TX | ANAR_TX_FD | ANAR_10_FD | ANAR_10 : + ANAR_TX | ANAR_10_FD | ANAR_10; + ifp->if_baudrate = IF_Mbps(100); + break; + case IFM_10_T: + gig = rge_read_phy(sc, 0, MII_100T2CR) & + ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); + anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? + ANAR_10_FD | ANAR_10 : ANAR_10; + ifp->if_baudrate = IF_Mbps(10); + break; + default: + printf("%s: unsupported media type\n", sc->sc_dev.dv_xname); + return (EINVAL); + } + + rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC); + rge_write_phy(sc, 0, MII_100T2CR, gig); + rge_write_phy_ocp(sc, 0xa5d4, val); + rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | + BMCR_STARTNEG); + + return (0); +} + +/* + * Report current media status. + */ +void +rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct rge_softc *sc = ifp->if_softc; + uint16_t status = 0; + + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + + if (rge_get_link_status(sc)) { + ifmr->ifm_status |= IFM_ACTIVE; + + status = RGE_READ_2(sc, RGE_PHYSTAT); + if ((status & RGE_PHYSTAT_FDX) || + (status & RGE_PHYSTAT_2500MBPS)) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + + if (status & RGE_PHYSTAT_10MBPS) + ifmr->ifm_active |= IFM_10_T; + else if (status & RGE_PHYSTAT_100MBPS) + ifmr->ifm_active |= IFM_100_TX; + else if (status & RGE_PHYSTAT_1000MBPS) + ifmr->ifm_active |= IFM_1000_T; + else if (status & RGE_PHYSTAT_2500MBPS) + ifmr->ifm_active |= IFM_2500_T; + } +} + +/* + * Allocate memory for RX/TX rings. + */ +int +rge_allocmem(struct rge_softc *sc) +{ + struct rge_queues *q = sc->sc_queues; + int error, i; + + /* Allocate DMA'able memory for the TX ring. */ + error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1, + RGE_TX_LIST_SZ, 0, BUS_DMA_NOWAIT, &q->q_tx.rge_tx_list_map); + if (error) { + printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname); + return (error); + } + error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0, + &q->q_tx.rge_tx_listseg, 1, &q->q_tx.rge_tx_listnseg, + BUS_DMA_NOWAIT| BUS_DMA_ZERO); + if (error) { + printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname); + return (error); + } + + /* Load the map for the TX ring. */ + error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg, RGE_TX_LIST_SZ, + (caddr_t *)&q->q_tx.rge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); + if (error) { + printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg); + return (error); + } + error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map, + q->q_tx.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); + bus_dmamem_unmap(sc->sc_dmat, + (caddr_t)q->q_tx.rge_tx_list, RGE_TX_LIST_SZ); + bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg); + return (error); + } + + /* Create DMA maps for TX buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, + RGE_TX_NSEGS, RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT, + &q->q_tx.rge_txq[i].txq_dmamap); + if (error) { + printf("%s: can't create DMA map for TX\n", + sc->sc_dev.dv_xname); + return (error); + } + } + + /* Allocate DMA'able memory for the RX ring. */ + error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1, + RGE_RX_LIST_SZ, 0, BUS_DMA_NOWAIT, &q->q_rx.rge_rx_list_map); + if (error) { + printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname); + return (error); + } + error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0, + &q->q_rx.rge_rx_listseg, 1, &q->q_rx.rge_rx_listnseg, + BUS_DMA_NOWAIT| BUS_DMA_ZERO); + if (error) { + printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname); + return (error); + } + + /* Load the map for the RX ring. */ + error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg, RGE_RX_LIST_SZ, + (caddr_t *)&q->q_rx.rge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); + if (error) { + printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg); + return (error); + } + error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map, + q->q_rx.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); + bus_dmamem_unmap(sc->sc_dmat, + (caddr_t)q->q_rx.rge_rx_list, RGE_RX_LIST_SZ); + bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg); + return (error); + } + + /* Create DMA maps for RX buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1, + RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT, + &q->q_rx.rge_rxq[i].rxq_dmamap); + if (error) { + printf("%s: can't create DMA map for RX\n", + sc->sc_dev.dv_xname); + return (error); + } + } + + return (error); +} + +/* + * Initialize the RX descriptor and attach an mbuf cluster. + */ +int +rge_newbuf(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct mbuf *m; + struct rge_rx_desc *r; + struct rge_rxq *rxq; + bus_dmamap_t rxmap; + int idx; + + m = MCLGETL(NULL, M_DONTWAIT, RGE_JUMBO_FRAMELEN); + if (m == NULL) + return (ENOBUFS); + + m->m_len = m->m_pkthdr.len = RGE_JUMBO_FRAMELEN; + + idx = q->q_rx.rge_rxq_prodidx; + rxq = &q->q_rx.rge_rxq[idx]; + rxmap = rxq->rxq_dmamap; + + if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) { + m_freem(m); + return (ENOBUFS); + } + + bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, + BUS_DMASYNC_PREREAD); + + /* Map the segments into RX descriptors. */ + r = &q->q_rx.rge_rx_list[idx]; + + rxq->rxq_mbuf = m; + + r->hi_qword1.rx_qword4.rge_extsts = 0; + r->hi_qword0.rge_addr = htole64(rxmap->dm_segs[0].ds_addr); + + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(rxmap->dm_segs[0].ds_len); + if (idx == RGE_RX_LIST_CNT - 1) + r->hi_qword1.rx_qword4.rge_cmdsts |= htole32(RGE_RDCMDSTS_EOR); + + r->hi_qword1.rx_qword4.rge_cmdsts |= htole32(RGE_RDCMDSTS_OWN); + + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, + idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + q->q_rx.rge_rxq_prodidx = RGE_NEXT_RX_DESC(idx); + + return (0); +} + +void +rge_discard_rxbuf(struct rge_queues *q, int idx) +{ + struct rge_softc *sc = q->q_sc; + struct rge_rx_desc *r; + + r = &q->q_rx.rge_rx_list[idx]; + + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(RGE_JUMBO_FRAMELEN); + r->hi_qword1.rx_qword4.rge_extsts = 0; + if (idx == RGE_RX_LIST_CNT - 1) + r->hi_qword1.rx_qword4.rge_cmdsts |= htole32(RGE_RDCMDSTS_EOR); + r->hi_qword1.rx_qword4.rge_cmdsts |= htole32(RGE_RDCMDSTS_OWN); + + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, + idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +void +rge_rx_list_init(struct rge_queues *q) +{ + memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ); + + q->q_rx.rge_rxq_prodidx = q->q_rx.rge_rxq_considx = 0; + q->q_rx.rge_head = q->q_rx.rge_tail = NULL; + + if_rxr_init(&q->q_rx.rge_rx_ring, 2, RGE_RX_LIST_CNT - 1); + rge_fill_rx_ring(q); +} + +void +rge_fill_rx_ring(struct rge_queues *q) +{ + struct if_rxring *rxr = &q->q_rx.rge_rx_ring; + int slots; + + for (slots = if_rxr_get(rxr, RGE_RX_LIST_CNT); slots > 0; slots--) { + if (rge_newbuf(q) == ENOBUFS) + break; + } + if_rxr_put(rxr, slots); +} + +void +rge_tx_list_init(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + int i; + + memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ); + + for (i = 0; i < RGE_TX_LIST_CNT; i++) + q->q_tx.rge_txq[i].txq_mbuf = NULL; + + bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0, + q->q_tx.rge_tx_list_map->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + q->q_tx.rge_txq_prodidx = q->q_tx.rge_txq_considx = 0; +} + +int +rge_rxeof(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct mbuf_list ml = MBUF_LIST_INITIALIZER(); + struct mbuf *m; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct if_rxring *rxr = &q->q_rx.rge_rx_ring; + struct rge_rx_desc *cur_rx; + struct rge_rxq *rxq; + uint32_t rxstat, extsts; + int i, total_len, rx = 0; + + for (i = q->q_rx.rge_rxq_considx; if_rxr_inuse(rxr) > 0; + i = RGE_NEXT_RX_DESC(i)) { + /* Invalidate the descriptor memory. */ + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, + i * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + cur_rx = &q->q_rx.rge_rx_list[i]; + + if (RGE_OWN(cur_rx)) + break; + + rxstat = letoh32(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); + extsts = letoh32(cur_rx->hi_qword1.rx_qword4.rge_extsts); + + total_len = RGE_RXBYTES(cur_rx); + rxq = &q->q_rx.rge_rxq[i]; + m = rxq->rxq_mbuf; + rxq->rxq_mbuf = NULL; + if_rxr_put(rxr, 1); + rx = 1; + + /* Invalidate the RX mbuf and unload its map. */ + bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0, + rxq->rxq_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap); + + if ((rxstat & (RGE_RDCMDSTS_SOF | RGE_RDCMDSTS_EOF)) != + (RGE_RDCMDSTS_SOF | RGE_RDCMDSTS_EOF)) { + ifp->if_ierrors++; + m_freem(m); + rge_discard_rxbuf(q, i); + continue; + } + + if (rxstat & RGE_RDCMDSTS_RXERRSUM) { + ifp->if_ierrors++; + /* + * If this is part of a multi-fragment packet, + * discard all the pieces. + */ + if (q->q_rx.rge_head != NULL) { + m_freem(q->q_rx.rge_head); + q->q_rx.rge_head = q->q_rx.rge_tail = NULL; + } + m_freem(m); + rge_discard_rxbuf(q, i); + continue; + } + + if (q->q_rx.rge_head != NULL) { + m->m_len = total_len; + /* + * Special case: if there's 4 bytes or less + * in this buffer, the mbuf can be discarded: + * the last 4 bytes is the CRC, which we don't + * care about anyway. + */ + if (m->m_len <= ETHER_CRC_LEN) { + q->q_rx.rge_tail->m_len -= + (ETHER_CRC_LEN - m->m_len); + m_freem(m); + } else { + m->m_len -= ETHER_CRC_LEN; + m->m_flags &= ~M_PKTHDR; + q->q_rx.rge_tail->m_next = m; + } + m = q->q_rx.rge_head; + q->q_rx.rge_head = q->q_rx.rge_tail = NULL; + m->m_pkthdr.len = total_len - ETHER_CRC_LEN; + } else + m->m_pkthdr.len = m->m_len = + (total_len - ETHER_CRC_LEN); + + /* Check IP header checksum. */ + if (!(extsts & RGE_RDEXTSTS_IPCSUMERR) && + (extsts & RGE_RDEXTSTS_IPV4)) + m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; + + /* Check TCP/UDP checksum. */ + if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && + (((extsts & RGE_RDEXTSTS_TCPPKT) && + !(extsts & RGE_RDEXTSTS_TCPCSUMERR)) || + ((extsts & RGE_RDEXTSTS_UDPPKT) && + !(extsts & RGE_RDEXTSTS_UDPCSUMERR)))) + m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | + M_UDP_CSUM_IN_OK; + +#if NVLAN > 0 + if (extsts & RGE_RDEXTSTS_VTAG) { + m->m_pkthdr.ether_vtag = + ntohs(extsts & RGE_RDEXTSTS_VLAN_MASK); + m->m_flags |= M_VLANTAG; + } +#endif + + ml_enqueue(&ml, m); + } + + if (ifiq_input(&ifp->if_rcv, &ml)) + if_rxr_livelocked(rxr); + + q->q_rx.rge_rxq_considx = i; + rge_fill_rx_ring(q); + + return (rx); +} + +int +rge_txeof(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct rge_txq *txq; + uint32_t txstat; + int cons, idx, prod; + int free = 0; + + prod = q->q_tx.rge_txq_prodidx; + cons = q->q_tx.rge_txq_considx; + + while (prod != cons) { + txq = &q->q_tx.rge_txq[cons]; + idx = txq->txq_descidx; + + bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, + idx * sizeof(struct rge_tx_desc), + sizeof(struct rge_tx_desc), + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + txstat = letoh32(q->q_tx.rge_tx_list[idx].rge_cmdsts); + + if (txstat & RGE_TDCMDSTS_OWN) { + free = 2; + break; + } + + bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0, + txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); + m_freem(txq->txq_mbuf); + txq->txq_mbuf = NULL; + + if (txstat & (RGE_TDCMDSTS_EXCESSCOLL | RGE_TDCMDSTS_COLL)) + ifp->if_collisions++; + if (txstat & RGE_TDCMDSTS_TXERR) + ifp->if_oerrors++; + + bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, + idx * sizeof(struct rge_tx_desc), + sizeof(struct rge_tx_desc), + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + cons = RGE_NEXT_TX_DESC(idx); + free = 1; + } + + if (free == 0) + return (0); + + q->q_tx.rge_txq_considx = cons; + + if (ifq_is_oactive(&ifp->if_snd)) + ifq_restart(&ifp->if_snd); + else if (free == 2) + ifq_serialize(&ifp->if_snd, &sc->sc_task); + else + ifp->if_timer = 0; + + return (1); +} + +void +rge_reset(struct rge_softc *sc) +{ + int i; + + /* Enable RXDV gate. */ + RGE_SETBIT_1(sc, RGE_PPSW, 0x08); + DELAY(2000); + + for (i = 0; i < 3000; i++) { + DELAY(50); + if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY | + RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY | + RGE_MCUCMD_TXFIFO_EMPTY)) + break; + } + if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) { + for (i = 0; i < 3000; i++) { + DELAY(50); + if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103) + break; + } + } + + DELAY(2000); + + /* Soft reset. */ + RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); + + for (i = 0; i < RGE_TIMEOUT; i++) { + DELAY(100); + if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET)) + break; + } + if (i == RGE_TIMEOUT) + printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); +} + +void +rge_iff(struct rge_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct arpcom *ac = &sc->sc_arpcom; + struct ether_multi *enm; + struct ether_multistep step; + uint32_t hashes[2]; + uint32_t rxfilt; + int h = 0; + + rxfilt = RGE_READ_4(sc, RGE_RXCFG); + rxfilt &= ~(RGE_RXCFG_ALLPHYS | RGE_RXCFG_MULTI); + ifp->if_flags &= ~IFF_ALLMULTI; + + /* + * Always accept frames destined to our station address. + * Always accept broadcast frames. + */ + rxfilt |= RGE_RXCFG_INDIV | RGE_RXCFG_BROAD; + + if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { + ifp->if_flags |= IFF_ALLMULTI; + rxfilt |= RGE_RXCFG_MULTI; + if (ifp->if_flags & IFF_PROMISC) + rxfilt |= RGE_RXCFG_ALLPHYS; + hashes[0] = hashes[1] = 0xffffffff; + } else { + rxfilt |= RGE_RXCFG_MULTI; + /* Program new filter. */ + memset(hashes, 0, sizeof(hashes)); + + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + h = ether_crc32_be(enm->enm_addrlo, + ETHER_ADDR_LEN) >> 26; + + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + + ETHER_NEXT_MULTI(step, enm); + } + } + + RGE_WRITE_4(sc, RGE_RXCFG, rxfilt); + RGE_WRITE_4(sc, RGE_MAR0, swap32(hashes[1])); + RGE_WRITE_4(sc, RGE_MAR4, swap32(hashes[0])); +} + +void +rge_set_phy_power(struct rge_softc *sc, int on) +{ + int i; + + if (on) { + RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); + + rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN); + + for (i = 0; i < RGE_TIMEOUT; i++) { + if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) + break; + DELAY(1000); + } + } else { + rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN); + RGE_CLRBIT_1(sc, RGE_PMCH, 0x80); + RGE_CLRBIT_1(sc, RGE_PPSW, 0x40); + } +} + +void +rge_phy_config(struct rge_softc *sc) +{ + /* Read microcode version. */ + rge_write_phy_ocp(sc, 0xa436, 0x801e); + sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438); + + switch (sc->rge_type) { + case MAC_CFG2: + rge_phy_config_mac_cfg2(sc); + break; + case MAC_CFG3: + rge_phy_config_mac_cfg3(sc); + break; + case MAC_CFG4: + rge_phy_config_mac_cfg4(sc); + break; + case MAC_CFG5: + rge_phy_config_mac_cfg5(sc); + break; + default: + break; /* Can't happen. */ + } + + rge_write_phy(sc, 0x0a5b, 0x12, + rge_read_phy(sc, 0x0a5b, 0x12) & ~0x8000); + + /* Disable EEE. */ + RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { + RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); + RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); + } + RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006); + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); + RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); + + rge_patch_phy_mcu(sc, 1); + RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); + RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); + rge_patch_phy_mcu(sc, 0); +} + +void +rge_phy_config_mac_cfg2(struct rge_softc *sc) +{ + uint16_t val; + int i; + + for (i = 0; i < nitems(rtl8125_mac_cfg2_ephy); i++) + rge_write_ephy(sc, rtl8125_mac_cfg2_ephy[i].reg, + rtl8125_mac_cfg2_ephy[i].val); + + rge_phy_config_mcu(sc, RGE_MAC_CFG2_MCODE_VER); + + val = rge_read_phy_ocp(sc, 0xad40) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad40, val | 0x0084); + RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); + val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad16, val | 0x0006); + val = rge_read_phy_ocp(sc, 0xad32) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad32, val | 0x0006); + RGE_PHY_CLRBIT(sc, 0xac08, 0x1100); + val = rge_read_phy_ocp(sc, 0xac8a) & ~0xf000; + rge_write_phy_ocp(sc, 0xac8a, val | 0x7000); + RGE_PHY_SETBIT(sc, 0xad18, 0x0400); + RGE_PHY_SETBIT(sc, 0xad1a, 0x03ff); + RGE_PHY_SETBIT(sc, 0xad1c, 0x03ff); + + rge_write_phy_ocp(sc, 0xa436, 0x80ea); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xc400); + rge_write_phy_ocp(sc, 0xa436, 0x80eb); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; + rge_write_phy_ocp(sc, 0xa438, val | 0x0300); + rge_write_phy_ocp(sc, 0xa436, 0x80f8); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1c00); + rge_write_phy_ocp(sc, 0xa436, 0x80f1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x3000); + rge_write_phy_ocp(sc, 0xa436, 0x80fe); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa500); + rge_write_phy_ocp(sc, 0xa436, 0x8102); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5000); + rge_write_phy_ocp(sc, 0xa436, 0x8105); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x3300); + rge_write_phy_ocp(sc, 0xa436, 0x8100); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x7000); + rge_write_phy_ocp(sc, 0xa436, 0x8104); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xf000); + rge_write_phy_ocp(sc, 0xa436, 0x8106); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x6500); + rge_write_phy_ocp(sc, 0xa436, 0x80dc); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xed00); + rge_write_phy_ocp(sc, 0xa436, 0x80df); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + rge_write_phy_ocp(sc, 0xa436, 0x80e1); + RGE_PHY_CLRBIT(sc, 0xa438, 0x0100); + val = rge_read_phy_ocp(sc, 0xbf06) & ~0x003f; + rge_write_phy_ocp(sc, 0xbf06, val | 0x0038); + rge_write_phy_ocp(sc, 0xa436, 0x819f); + rge_write_phy_ocp(sc, 0xa438, 0xd0b6); + rge_write_phy_ocp(sc, 0xbc34, 0x5555); + val = rge_read_phy_ocp(sc, 0xbf0a) & ~0x0e00; + rge_write_phy_ocp(sc, 0xbf0a, val | 0x0a00); + RGE_PHY_CLRBIT(sc, 0xa5c0, 0x0400); + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); +} + +void +rge_phy_config_mac_cfg3(struct rge_softc *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg3_a438_value[] = + { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff, + 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; + + static const uint16_t mac_cfg3_b88e_value[] = + { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, + 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, + 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, + 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, + 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050, + 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 }; + + for (i = 0; i < nitems(rtl8125_mac_cfg3_ephy); i++) + rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg, + rtl8125_mac_cfg3_ephy[i].val); + + val = rge_read_ephy(sc, 0x002a) & ~0x7000; + rge_write_ephy(sc, 0x002a, val | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); + RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); + rge_write_ephy(sc, 0x0002, 0x6042); + rge_write_ephy(sc, 0x0006, 0x0014); + val = rge_read_ephy(sc, 0x006a) & ~0x7000; + rge_write_ephy(sc, 0x006a, val | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); + RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); + rge_write_ephy(sc, 0x0042, 0x6042); + rge_write_ephy(sc, 0x0046, 0x0014); + + rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER); + + RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); + val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); + val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; + rge_write_phy_ocp(sc, 0xad32, val | 0x0006); + RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); + RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); + val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; + rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; + rge_write_phy_ocp(sc, 0xad40, val | 0x0040); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; + rge_write_phy_ocp(sc, 0xad40, val | 0x0004); + RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); + RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); + val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; + rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); + rge_write_phy_ocp(sc, 0xad4c, 0x00a8); + rge_write_phy_ocp(sc, 0xac5c, 0x01ff); + val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); + rge_write_phy_ocp(sc, 0xb87c, 0x8157); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + rge_write_phy_ocp(sc, 0xb87c, 0x8159); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN + + 32); + rge_write_phy_ocp(sc, 0xb87c, 0x80a2); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + rge_write_phy_ocp(sc, 0xb87c, 0x809c); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + + rge_write_phy_ocp(sc, 0xa436, 0x81b3); + for (i = 0; i < nitems(mac_cfg3_a438_value); i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); + for (i = 0; i < 26; i++) + rge_write_phy_ocp(sc, 0xa438, 0); + rge_write_phy_ocp(sc, 0xa436, 0x8257); + rge_write_phy_ocp(sc, 0xa438, 0x020f); + rge_write_phy_ocp(sc, 0xa436, 0x80ea); + rge_write_phy_ocp(sc, 0xa438, 0x7843); + + rge_patch_phy_mcu(sc, 1); + RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); + RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); + for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) { + rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); + rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); + } + RGE_PHY_SETBIT(sc, 0xb896, 0x0001); + rge_patch_phy_mcu(sc, 0); + + RGE_PHY_SETBIT(sc, 0xd068, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81a2); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; + rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); + RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); + RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); +} + +void +rge_phy_config_mac_cfg4(struct rge_softc *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg4_b87c_value[] = + { 0x8013, 0x0700, 0x8fb9, 0x2801, 0x8fba, 0x0100, 0x8fbc, 0x1900, + 0x8fbe, 0xe100, 0x8fc0, 0x0800, 0x8fc2, 0xe500, 0x8fc4, 0x0f00, + 0x8fc6, 0xf100, 0x8fc8, 0x0400, 0x8fca, 0xf300, 0x8fcc, 0xfd00, + 0x8fce, 0xff00, 0x8fd0, 0xfb00, 0x8fd2, 0x0100, 0x8fd4, 0xf400, + 0x8fd6, 0xff00, 0x8fd8, 0xf600, 0x813d, 0x390e, 0x814f, 0x790e, + 0x80b0, 0x0f31 }; + + for (i = 0; i < nitems(rtl8125_mac_cfg4_ephy); i++) + rge_write_ephy(sc, rtl8125_mac_cfg4_ephy[i].reg, + rtl8125_mac_cfg4_ephy[i].val); + + rge_write_phy_ocp(sc, 0xbf86, 0x9000); + RGE_PHY_SETBIT(sc, 0xc402, 0x0400); + RGE_PHY_CLRBIT(sc, 0xc402, 0x0400); + rge_write_phy_ocp(sc, 0xbd86, 0x1010); + rge_write_phy_ocp(sc, 0xbd88, 0x1010); + val = rge_read_phy_ocp(sc, 0xbd4e) & ~0x0c00; + rge_write_phy_ocp(sc, 0xbd4e, val | 0x0800); + val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; + rge_write_phy_ocp(sc, 0xbf46, val | 0x0700); + + rge_phy_config_mcu(sc, RGE_MAC_CFG4_MCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + RGE_PHY_SETBIT(sc, 0xbc08, 0x000c); + rge_write_phy_ocp(sc, 0xa436, 0x8fff); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0400); + for (i = 0; i < 6; i++) { + rge_write_phy_ocp(sc, 0xb87c, 0x8560 + i * 2); + if (i < 3) + rge_write_phy_ocp(sc, 0xb87e, 0x19cc); + else + rge_write_phy_ocp(sc, 0xb87e, 0x147d); + } + rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); + rge_write_phy_ocp(sc, 0xb87e, 0x0907); + val = rge_read_phy_ocp(sc, 0xacda) & ~0xff00; + rge_write_phy_ocp(sc, 0xacda, val | 0xff00); + val = rge_read_phy_ocp(sc, 0xacde) & ~0xf000; + rge_write_phy_ocp(sc, 0xacde, val | 0xf000); + rge_write_phy_ocp(sc, 0xb87c, 0x80d6); + rge_write_phy_ocp(sc, 0xb87e, 0x2801); + rge_write_phy_ocp(sc, 0xb87c, 0x80F2); + rge_write_phy_ocp(sc, 0xb87e, 0x2801); + rge_write_phy_ocp(sc, 0xb87c, 0x80f4); + rge_write_phy_ocp(sc, 0xb87e, 0x6077); + rge_write_phy_ocp(sc, 0xb506, 0x01e7); + rge_write_phy_ocp(sc, 0xac8c, 0x0ffc); + rge_write_phy_ocp(sc, 0xac46, 0xb7b4); + rge_write_phy_ocp(sc, 0xac50, 0x0fbc); + rge_write_phy_ocp(sc, 0xac3c, 0x9240); + rge_write_phy_ocp(sc, 0xac4E, 0x0db4); + rge_write_phy_ocp(sc, 0xacc6, 0x0707); + rge_write_phy_ocp(sc, 0xacc8, 0xa0d3); + rge_write_phy_ocp(sc, 0xad08, 0x0007); + for (i = 0; i < nitems(mac_cfg4_b87c_value); i += 2) { + rge_write_phy_ocp(sc, 0xb87c, mac_cfg4_b87c_value[i]); + rge_write_phy_ocp(sc, 0xb87e, mac_cfg4_b87c_value[i + 1]); + } + RGE_PHY_SETBIT(sc, 0xbf4c, 0x0002); + RGE_PHY_SETBIT(sc, 0xbcca, 0x0300); + rge_write_phy_ocp(sc, 0xb87c, 0x8141); + rge_write_phy_ocp(sc, 0xb87e, 0x320e); + rge_write_phy_ocp(sc, 0xb87c, 0x8153); + rge_write_phy_ocp(sc, 0xb87e, 0x720e); + RGE_PHY_CLRBIT(sc, 0xa432, 0x0040); + rge_write_phy_ocp(sc, 0xb87c, 0x8529); + rge_write_phy_ocp(sc, 0xb87e, 0x050e); + RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN + + 32); + rge_write_phy_ocp(sc, 0xa436, 0x816c); + rge_write_phy_ocp(sc, 0xa438, 0xc4a0); + rge_write_phy_ocp(sc, 0xa436, 0x8170); + rge_write_phy_ocp(sc, 0xa438, 0xc4a0); + rge_write_phy_ocp(sc, 0xa436, 0x8174); + rge_write_phy_ocp(sc, 0xa438, 0x04a0); + rge_write_phy_ocp(sc, 0xa436, 0x8178); + rge_write_phy_ocp(sc, 0xa438, 0x04a0); + rge_write_phy_ocp(sc, 0xa436, 0x817c); + rge_write_phy_ocp(sc, 0xa438, 0x0719); + rge_write_phy_ocp(sc, 0xa436, 0x8ff4); + rge_write_phy_ocp(sc, 0xa438, 0x0400); + rge_write_phy_ocp(sc, 0xa436, 0x8ff1); + rge_write_phy_ocp(sc, 0xa438, 0x0404); + rge_write_phy_ocp(sc, 0xbf4a, 0x001b); + for (i = 0; i < 6; i++) { + rge_write_phy_ocp(sc, 0xb87c, 0x8033 + i * 4); + if (i == 2) + rge_write_phy_ocp(sc, 0xb87e, 0xfc32); + else + rge_write_phy_ocp(sc, 0xb87e, 0x7c13); + } + rge_write_phy_ocp(sc, 0xb87c, 0x8145); + rge_write_phy_ocp(sc, 0xb87e, 0x370e); + rge_write_phy_ocp(sc, 0xb87c, 0x8157); + rge_write_phy_ocp(sc, 0xb87e, 0x770e); + rge_write_phy_ocp(sc, 0xb87c, 0x8169); + rge_write_phy_ocp(sc, 0xb87e, 0x0d0a); + rge_write_phy_ocp(sc, 0xb87c, 0x817b); + rge_write_phy_ocp(sc, 0xb87e, 0x1d0a); + rge_write_phy_ocp(sc, 0xa436, 0x8217); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5000); + rge_write_phy_ocp(sc, 0xa436, 0x821a); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5000); + rge_write_phy_ocp(sc, 0xa436, 0x80da); + rge_write_phy_ocp(sc, 0xa438, 0x0403); + rge_write_phy_ocp(sc, 0xa436, 0x80dc); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x80b3); + rge_write_phy_ocp(sc, 0xa438, 0x0384); + rge_write_phy_ocp(sc, 0xa436, 0x80b7); + rge_write_phy_ocp(sc, 0xa438, 0x2007); + rge_write_phy_ocp(sc, 0xa436, 0x80ba); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x6c00); + rge_write_phy_ocp(sc, 0xa436, 0x80b5); + rge_write_phy_ocp(sc, 0xa438, 0xf009); + rge_write_phy_ocp(sc, 0xa436, 0x80bd); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x9f00); + rge_write_phy_ocp(sc, 0xa436, 0x80c7); + rge_write_phy_ocp(sc, 0xa438, 0xf083); + rge_write_phy_ocp(sc, 0xa436, 0x80dd); + rge_write_phy_ocp(sc, 0xa438, 0x03f0); + rge_write_phy_ocp(sc, 0xa436, 0x80df); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x80cb); + rge_write_phy_ocp(sc, 0xa438, 0x2007); + rge_write_phy_ocp(sc, 0xa436, 0x80ce); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x6c00); + rge_write_phy_ocp(sc, 0xa436, 0x80c9); + rge_write_phy_ocp(sc, 0xa438, 0x8009); + rge_write_phy_ocp(sc, 0xa436, 0x80d1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x8000); + rge_write_phy_ocp(sc, 0xa436, 0x80a3); + rge_write_phy_ocp(sc, 0xa438, 0x200a); + rge_write_phy_ocp(sc, 0xa436, 0x80a5); + rge_write_phy_ocp(sc, 0xa438, 0xf0ad); + rge_write_phy_ocp(sc, 0xa436, 0x809f); + rge_write_phy_ocp(sc, 0xa438, 0x6073); + rge_write_phy_ocp(sc, 0xa436, 0x80a1); + rge_write_phy_ocp(sc, 0xa438, 0x000b); + rge_write_phy_ocp(sc, 0xa436, 0x80a9); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xc000); + rge_patch_phy_mcu(sc, 1); + RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); + RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); + rge_write_phy_ocp(sc, 0xb88e, 0xc23e); + rge_write_phy_ocp(sc, 0xb890, 0x0000); + rge_write_phy_ocp(sc, 0xb88e, 0xc240); + rge_write_phy_ocp(sc, 0xb890, 0x0103); + rge_write_phy_ocp(sc, 0xb88e, 0xc242); + rge_write_phy_ocp(sc, 0xb890, 0x0507); + rge_write_phy_ocp(sc, 0xb88e, 0xc244); + rge_write_phy_ocp(sc, 0xb890, 0x090b); + rge_write_phy_ocp(sc, 0xb88e, 0xc246); + rge_write_phy_ocp(sc, 0xb890, 0x0c0e); + rge_write_phy_ocp(sc, 0xb88e, 0xc248); + rge_write_phy_ocp(sc, 0xb890, 0x1012); + rge_write_phy_ocp(sc, 0xb88e, 0xc24a); + rge_write_phy_ocp(sc, 0xb890, 0x1416); + RGE_PHY_SETBIT(sc, 0xb896, 0x0001); + rge_patch_phy_mcu(sc, 0); + RGE_PHY_SETBIT(sc, 0xa86a, 0x0001); + RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001); + rge_write_phy_ocp(sc, 0xbfa0, 0xd70d); + rge_write_phy_ocp(sc, 0xbfa2, 0x4100); + rge_write_phy_ocp(sc, 0xbfa4, 0xe868); + rge_write_phy_ocp(sc, 0xbfa6, 0xdc59); + rge_write_phy_ocp(sc, 0xb54c, 0x3c18); + RGE_PHY_CLRBIT(sc, 0xbfa4, 0x0020); + rge_write_phy_ocp(sc, 0xa436, 0x817d); + RGE_PHY_SETBIT(sc, 0xa438, 0x1000); +} + +void +rge_phy_config_mac_cfg5(struct rge_softc *sc) +{ + uint16_t val; + int i; + + for (i = 0; i < nitems(rtl8125_mac_cfg5_ephy); i++) + rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg, + rtl8125_mac_cfg5_ephy[i].val); + + rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac46, val | 0x0090); + val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; + rge_write_phy_ocp(sc, 0xad30, val | 0x0001); + RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN + + 32); + rge_write_phy_ocp(sc, 0xb87c, 0x80f5); + rge_write_phy_ocp(sc, 0xb87e, 0x760e); + rge_write_phy_ocp(sc, 0xb87c, 0x8107); + rge_write_phy_ocp(sc, 0xb87e, 0x360e); + rge_write_phy_ocp(sc, 0xb87c, 0x8551); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); + val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; + rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); + for (i = 0; i < 10; i++) { + rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); + rge_write_phy_ocp(sc, 0xa438, 0x2417); + } + RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); + val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); + rge_write_phy_ocp(sc, 0xa436, 0x8170); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; + rge_write_phy_ocp(sc, 0xa438, val | 0xd800); +} + +void +rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version) +{ + if (sc->rge_mcodever != mcode_version) { + int i; + + rge_patch_phy_mcu(sc, 1); + + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { + rge_write_phy_ocp(sc, 0xa436, 0x8024); + if (sc->rge_type == MAC_CFG2) + rge_write_phy_ocp(sc, 0xa438, 0x8600); + else + rge_write_phy_ocp(sc, 0xa438, 0x8601); + rge_write_phy_ocp(sc, 0xa436, 0xb82e); + rge_write_phy_ocp(sc, 0xa438, 0x0001); + + RGE_PHY_SETBIT(sc, 0xb820, 0x0080); + } + + if (sc->rge_type == MAC_CFG2) { + for (i = 0; i < nitems(rtl8125_mac_cfg2_mcu); i++) { + rge_write_phy_ocp(sc, + rtl8125_mac_cfg2_mcu[i].reg, + rtl8125_mac_cfg2_mcu[i].val); + } + } else if (sc->rge_type == MAC_CFG3) { + for (i = 0; i < nitems(rtl8125_mac_cfg3_mcu); i++) { + rge_write_phy_ocp(sc, + rtl8125_mac_cfg3_mcu[i].reg, + rtl8125_mac_cfg3_mcu[i].val); + } + } else if (sc->rge_type == MAC_CFG4) { + for (i = 0; i < nitems(rtl8125_mac_cfg4_mcu); i++) { + rge_write_phy_ocp(sc, + rtl8125_mac_cfg4_mcu[i].reg, + rtl8125_mac_cfg4_mcu[i].val); + } + } else if (sc->rge_type == MAC_CFG5) { + for (i = 0; i < nitems(rtl8125_mac_cfg5_mcu); i++) { + rge_write_phy_ocp(sc, + rtl8125_mac_cfg5_mcu[i].reg, + rtl8125_mac_cfg5_mcu[i].val); + } + } + + if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { + RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); + + rge_write_phy_ocp(sc, 0xa436, 0); + rge_write_phy_ocp(sc, 0xa438, 0); + RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); + rge_write_phy_ocp(sc, 0xa436, 0x8024); + rge_write_phy_ocp(sc, 0xa438, 0); + } + + rge_patch_phy_mcu(sc, 0); + + /* Write microcode version. */ + rge_write_phy_ocp(sc, 0xa436, 0x801e); + rge_write_phy_ocp(sc, 0xa438, mcode_version); + } +} + +void +rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) +{ + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_WRITE_4(sc, RGE_MAC0, + addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); + RGE_WRITE_4(sc, RGE_MAC4, + addr[5] << 8 | addr[4]); + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); +} + +void +rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) +{ + *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0); + *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1); +} + +void +rge_hw_init(struct rge_softc *sc) +{ + int i; + + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); + RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_CLRBIT_1(sc, 0xf1, 0x80); + + /* Disable UPS. */ + RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); + + /* Configure MAC MCU. */ + rge_write_mac_ocp(sc, 0xfc38, 0); + + for (i = 0xfc28; i < 0xfc38; i += 2) + rge_write_mac_ocp(sc, i, 0); + + DELAY(3000); + rge_write_mac_ocp(sc, 0xfc26, 0); + + if (sc->rge_type == MAC_CFG3) { + for (i = 0; i < nitems(rtl8125_mac_bps); i++) { + rge_write_mac_ocp(sc, rtl8125_mac_bps[i].reg, + rtl8125_mac_bps[i].val); + } + } else if (sc->rge_type == MAC_CFG5) { + for (i = 0; i < nitems(rtl8125b_mac_bps); i++) { + rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, + rtl8125b_mac_bps[i].val); + } + } + + /* Disable PHY power saving. */ + rge_disable_phy_ocp_pwrsave(sc); + + /* Set PCIe uncorrectable error status. */ + rge_write_csi(sc, 0x108, + rge_read_csi(sc, 0x108) | 0x00100000); + +} + +void +rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) +{ + if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { + rge_patch_phy_mcu(sc, 1); + rge_write_phy_ocp(sc, 0xc416, 0); + rge_write_phy_ocp(sc, 0xc416, 0x0500); + rge_patch_phy_mcu(sc, 0); + } +} + +void +rge_patch_phy_mcu(struct rge_softc *sc, int set) +{ + int i; + + if (set) + RGE_PHY_SETBIT(sc, 0xb820, 0x0010); + else + RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); + + for (i = 0; i < 1000; i++) { + if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) == 0x0040) + break; + DELAY(100); + } + if (i == 1000) { + DPRINTF(("timeout waiting to patch phy mcu\n")); + return; + } +} + +void +rge_add_media_types(struct rge_softc *sc) +{ + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); +} + +void +rge_config_imtype(struct rge_softc *sc, int imtype) +{ + switch (imtype) { + case RGE_IMTYPE_NONE: + sc->rge_intrs = RGE_INTRS; + break; + case RGE_IMTYPE_SIM: + sc->rge_intrs = RGE_INTRS_TIMER; + break; + default: + panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); + } +} + +void +rge_disable_hw_im(struct rge_softc *sc) +{ + RGE_WRITE_2(sc, RGE_IM, 0); +} + +void +rge_disable_sim_im(struct rge_softc *sc) +{ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + sc->rge_timerintr = 0; +} + +void +rge_setup_sim_im(struct rge_softc *sc) +{ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); + RGE_WRITE_4(sc, RGE_TIMERCNT, 1); + sc->rge_timerintr = 1; +} + +void +rge_setup_intr(struct rge_softc *sc, int imtype) +{ + rge_config_imtype(sc, imtype); + + /* Enable interrupts. */ + RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); + + switch (imtype) { + case RGE_IMTYPE_NONE: + rge_disable_sim_im(sc); + rge_disable_hw_im(sc); + break; + case RGE_IMTYPE_SIM: + rge_disable_hw_im(sc); + rge_setup_sim_im(sc); + break; + default: + panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); + } +} + +void +rge_exit_oob(struct rge_softc *sc) +{ + int i; + + RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | + RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | + RGE_RXCFG_ERRPKT); + + /* Disable RealWoW. */ + rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); + + rge_reset(sc); + + /* Disable OOB. */ + RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); + + RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) + break; + } + + rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); + rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); + rge_write_mac_ocp(sc, 0xc01e, 0x5555); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) + break; + } + + if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { + printf("%s: rge_exit_oob(): rtl8125_is_ups_resume!!\n", + sc->sc_dev.dv_xname); + for (i = 0; i < RGE_TIMEOUT; i++) { + if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) + break; + DELAY(1000); + } + RGE_MAC_CLRBIT(sc, 0xd408, 0x0100); + if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) + RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); + } +} + +void +rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) +{ + int i; + + RGE_WRITE_4(sc, RGE_CSIDR, val); + RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | + (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)) + break; + } + + DELAY(20); +} + +uint32_t +rge_read_csi(struct rge_softc *sc, uint32_t reg) +{ + int i; + + RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | + (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT)); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY) + break; + } + + DELAY(20); + + return (RGE_READ_4(sc, RGE_CSIDR)); +} + +void +rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + + tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; + tmp += val; + tmp |= RGE_MACOCP_BUSY; + RGE_WRITE_4(sc, RGE_MACOCP, tmp); +} + +uint16_t +rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + + val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_MACOCP, val); + + return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK); +} + +void +rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + int i; + + tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; + tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK); + RGE_WRITE_4(sc, RGE_EPHYAR, tmp); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY)) + break; + } + + DELAY(20); +} + +uint16_t +rge_read_ephy(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + int i; + + val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_EPHYAR, val); + + for (i = 0; i < 10; i++) { + DELAY(100); + val = RGE_READ_4(sc, RGE_EPHYAR); + if (val & RGE_EPHYAR_BUSY) + break; + } + + DELAY(20); + + return (val & RGE_EPHYAR_DATA_MASK); +} + +void +rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) +{ + uint16_t off, phyaddr; + + phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); + phyaddr <<= 4; + + off = addr ? reg : 0x10 + (reg % 8); + + phyaddr += (off - 16) << 1; + + rge_write_phy_ocp(sc, phyaddr, val); +} + +uint16_t +rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) +{ + uint16_t off, phyaddr; + + phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); + phyaddr <<= 4; + + off = addr ? reg : 0x10 + (reg % 8); + + phyaddr += (off - 16) << 1; + + return (rge_read_phy_ocp(sc, phyaddr)); +} + +void +rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + int i; + + tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; + tmp |= RGE_PHYOCP_BUSY | val; + RGE_WRITE_4(sc, RGE_PHYOCP, tmp); + + for (i = 0; i < RGE_TIMEOUT; i++) { + DELAY(1); + if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY)) + break; + } +} + +uint16_t +rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + int i; + + val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_PHYOCP, val); + + for (i = 0; i < RGE_TIMEOUT; i++) { + DELAY(1); + val = RGE_READ_4(sc, RGE_PHYOCP); + if (val & RGE_PHYOCP_BUSY) + break; + } + + return (val & RGE_PHYOCP_DATA_MASK); +} + +int +rge_get_link_status(struct rge_softc *sc) +{ + return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0); +} + +void +rge_txstart(void *arg) +{ + struct rge_softc *sc = arg; + + RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START); +} + +void +rge_tick(void *arg) +{ + struct rge_softc *sc = arg; + int s; + + s = splnet(); + rge_link_state(sc); + splx(s); + + timeout_add_sec(&sc->sc_timeout, 1); +} + +void +rge_link_state(struct rge_softc *sc) +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int link = LINK_STATE_DOWN; + + if (rge_get_link_status(sc)) + link = LINK_STATE_UP; + + if (ifp->if_link_state != link) { + ifp->if_link_state = link; + if_link_state_change(ifp); + } +} + +#ifndef SMALL_KERNEL +int +rge_wol(struct ifnet *ifp, int enable) +{ + struct rge_softc *sc = ifp->if_softc; + + if (enable) { + if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) { + printf("%s: power management is disabled, " + "cannot do WOL\n", sc->sc_dev.dv_xname); + return (ENOTSUP); + } + + } + + rge_iff(sc); + + if (enable) + RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001); + else + RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001); + + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST | + RGE_CFG5_WOL_MCAST | RGE_CFG5_WOL_BCAST); + RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC); + if (enable) + RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE); + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + return (0); +} + +void +rge_wol_power(struct rge_softc *sc) +{ + /* Disable RXDV gate. */ + RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); + DELAY(2000); + + RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN); + RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN); +} +#endif + +#if NKSTAT > 0 + +#define RGE_DTCCR_CMD (1U << 3) +#define RGE_DTCCR_LO 0x10 +#define RGE_DTCCR_HI 0x14 + +struct rge_kstats { + struct kstat_kv tx_ok; + struct kstat_kv rx_ok; + struct kstat_kv tx_er; + struct kstat_kv rx_er; + struct kstat_kv miss_pkt; + struct kstat_kv fae; + struct kstat_kv tx_1col; + struct kstat_kv tx_mcol; + struct kstat_kv rx_ok_phy; + struct kstat_kv rx_ok_brd; + struct kstat_kv rx_ok_mul; + struct kstat_kv tx_abt; + struct kstat_kv tx_undrn; +}; + +static const struct rge_kstats rge_kstats_tpl = { + .tx_ok = KSTAT_KV_UNIT_INITIALIZER("TxOk", + KSTAT_KV_T_COUNTER64, KSTAT_KV_U_PACKETS), + .rx_ok = KSTAT_KV_UNIT_INITIALIZER("RxOk", + KSTAT_KV_T_COUNTER64, KSTAT_KV_U_PACKETS), + .tx_er = KSTAT_KV_UNIT_INITIALIZER("TxEr", + KSTAT_KV_T_COUNTER64, KSTAT_KV_U_PACKETS), + .rx_er = KSTAT_KV_UNIT_INITIALIZER("RxEr", + KSTAT_KV_T_COUNTER32, KSTAT_KV_U_PACKETS), + .miss_pkt = KSTAT_KV_UNIT_INITIALIZER("MissPkt", + KSTAT_KV_T_COUNTER16, KSTAT_KV_U_PACKETS), + .fae = KSTAT_KV_UNIT_INITIALIZER("FAE", + KSTAT_KV_T_COUNTER16, KSTAT_KV_U_PACKETS), + .tx_1col = KSTAT_KV_UNIT_INITIALIZER("Tx1Col", + KSTAT_KV_T_COUNTER32, KSTAT_KV_U_PACKETS), + .tx_mcol = KSTAT_KV_UNIT_INITIALIZER("TxMCol", + KSTAT_KV_T_COUNTER32, KSTAT_KV_U_PACKETS), + .rx_ok_phy = KSTAT_KV_UNIT_INITIALIZER("RxOkPhy", + KSTAT_KV_T_COUNTER64, KSTAT_KV_U_PACKETS), + .rx_ok_brd = KSTAT_KV_UNIT_INITIALIZER("RxOkBrd", + KSTAT_KV_T_COUNTER64, KSTAT_KV_U_PACKETS), + .rx_ok_mul = KSTAT_KV_UNIT_INITIALIZER("RxOkMul", + KSTAT_KV_T_COUNTER32, KSTAT_KV_U_PACKETS), + .tx_abt = KSTAT_KV_UNIT_INITIALIZER("TxAbt", + KSTAT_KV_T_COUNTER16, KSTAT_KV_U_PACKETS), + .tx_undrn = KSTAT_KV_UNIT_INITIALIZER("TxUndrn", + KSTAT_KV_T_COUNTER16, KSTAT_KV_U_PACKETS), +}; + +struct rge_kstat_softc { + struct rge_stats *rge_ks_sc_stats; + + bus_dmamap_t rge_ks_sc_map; + bus_dma_segment_t rge_ks_sc_seg; + int rge_ks_sc_nsegs; + + struct rwlock rge_ks_sc_rwl; +}; + +static int +rge_kstat_read(struct kstat *ks) +{ + struct rge_softc *sc = ks->ks_softc; + struct rge_kstat_softc *rge_ks_sc = ks->ks_ptr; + bus_dmamap_t map; + uint64_t cmd; + uint32_t reg; + uint8_t command; + int tmo; + + command = RGE_READ_1(sc, RGE_CMD); + if (!ISSET(command, RGE_CMD_RXENB) || command == 0xff) + return (ENETDOWN); + + map = rge_ks_sc->rge_ks_sc_map; + cmd = map->dm_segs[0].ds_addr | RGE_DTCCR_CMD; + + bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, + BUS_DMASYNC_PREREAD); + + RGE_WRITE_4(sc, RGE_DTCCR_HI, cmd >> 32); + bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_HI, 8, + BUS_SPACE_BARRIER_WRITE); + RGE_WRITE_4(sc, RGE_DTCCR_LO, cmd); + bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_LO, 4, + BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); + + tmo = 1000; + do { + reg = RGE_READ_4(sc, RGE_DTCCR_LO); + if (!ISSET(reg, RGE_DTCCR_CMD)) + break; + + delay(10); + bus_space_barrier(sc->rge_btag, sc->rge_bhandle, + RGE_DTCCR_LO, 4, BUS_SPACE_BARRIER_READ); + } while (--tmo); + + bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, + BUS_DMASYNC_POSTREAD); + + if (ISSET(reg, RGE_DTCCR_CMD)) + return (EIO); + + nanouptime(&ks->ks_updated); + + return (0); +} + +static int +rge_kstat_copy(struct kstat *ks, void *dst) +{ + struct rge_kstat_softc *rge_ks_sc = ks->ks_ptr; + struct rge_stats *rs = rge_ks_sc->rge_ks_sc_stats; + struct rge_kstats *kvs = dst; + + *kvs = rge_kstats_tpl; + kstat_kv_u64(&kvs->tx_ok) = lemtoh64(&rs->rge_tx_ok); + kstat_kv_u64(&kvs->rx_ok) = lemtoh64(&rs->rge_rx_ok); + kstat_kv_u64(&kvs->tx_er) = lemtoh64(&rs->rge_tx_er); + kstat_kv_u32(&kvs->rx_er) = lemtoh32(&rs->rge_rx_er); + kstat_kv_u16(&kvs->miss_pkt) = lemtoh16(&rs->rge_miss_pkt); + kstat_kv_u16(&kvs->fae) = lemtoh16(&rs->rge_fae); + kstat_kv_u32(&kvs->tx_1col) = lemtoh32(&rs->rge_tx_1col); + kstat_kv_u32(&kvs->tx_mcol) = lemtoh32(&rs->rge_tx_mcol); + kstat_kv_u64(&kvs->rx_ok_phy) = lemtoh64(&rs->rge_rx_ok_phy); + kstat_kv_u64(&kvs->rx_ok_brd) = lemtoh64(&rs->rge_rx_ok_brd); + kstat_kv_u32(&kvs->rx_ok_mul) = lemtoh32(&rs->rge_rx_ok_mul); + kstat_kv_u16(&kvs->tx_abt) = lemtoh16(&rs->rge_tx_abt); + kstat_kv_u16(&kvs->tx_undrn) = lemtoh16(&rs->rge_tx_undrn); + + return (0); +} + +void +rge_kstat_attach(struct rge_softc *sc) +{ + struct rge_kstat_softc *rge_ks_sc; + struct kstat *ks; + + rge_ks_sc = malloc(sizeof(*rge_ks_sc), M_DEVBUF, M_NOWAIT); + if (rge_ks_sc == NULL) { + printf("%s: cannot allocate kstat softc\n", + sc->sc_dev.dv_xname); + return; + } + + if (bus_dmamap_create(sc->sc_dmat, + sizeof(struct rge_stats), 1, sizeof(struct rge_stats), 0, + BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, + &rge_ks_sc->rge_ks_sc_map) != 0) { + printf("%s: cannot create counter dma memory map\n", + sc->sc_dev.dv_xname); + goto free; + } + + if (bus_dmamem_alloc(sc->sc_dmat, + sizeof(struct rge_stats), RGE_STATS_ALIGNMENT, 0, + &rge_ks_sc->rge_ks_sc_seg, 1, &rge_ks_sc->rge_ks_sc_nsegs, + BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) { + printf("%s: cannot allocate counter dma memory\n", + sc->sc_dev.dv_xname); + goto destroy; + } + + if (bus_dmamem_map(sc->sc_dmat, + &rge_ks_sc->rge_ks_sc_seg, rge_ks_sc->rge_ks_sc_nsegs, + sizeof(struct rge_stats), (caddr_t *)&rge_ks_sc->rge_ks_sc_stats, + BUS_DMA_NOWAIT) != 0) { + printf("%s: cannot map counter dma memory\n", + sc->sc_dev.dv_xname); + goto freedma; + } + + if (bus_dmamap_load(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map, + (caddr_t)rge_ks_sc->rge_ks_sc_stats, sizeof(struct rge_stats), + NULL, BUS_DMA_NOWAIT) != 0) { + printf("%s: cannot load counter dma memory\n", + sc->sc_dev.dv_xname); + goto unmap; + } + + ks = kstat_create(sc->sc_dev.dv_xname, 0, "re-stats", 0, + KSTAT_T_KV, 0); + if (ks == NULL) { + printf("%s: cannot create re-stats kstat\n", + sc->sc_dev.dv_xname); + goto unload; + } + + ks->ks_datalen = sizeof(rge_kstats_tpl); + + rw_init(&rge_ks_sc->rge_ks_sc_rwl, "rgestats"); + kstat_set_wlock(ks, &rge_ks_sc->rge_ks_sc_rwl); + ks->ks_softc = sc; + ks->ks_ptr = rge_ks_sc; + ks->ks_read = rge_kstat_read; + ks->ks_copy = rge_kstat_copy; + + kstat_install(ks); + + sc->sc_kstat = ks; + + return; + +unload: + bus_dmamap_unload(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map); +unmap: + bus_dmamem_unmap(sc->sc_dmat, + (caddr_t)rge_ks_sc->rge_ks_sc_stats, sizeof(struct rge_stats)); +freedma: + bus_dmamem_free(sc->sc_dmat, &rge_ks_sc->rge_ks_sc_seg, 1); +destroy: + bus_dmamap_destroy(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map); +free: + free(rge_ks_sc, M_DEVBUF, sizeof(*rge_ks_sc)); +} +#endif /* NKSTAT > 0 */ diff --git a/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rgereg.h b/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rgereg.h new file mode 100644 index 0000000000..6cedaf8e41 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rgereg.h @@ -0,0 +1,5359 @@ +/* $OpenBSD: if_rgereg.h,v 1.9 2022/12/21 02:31:09 kevlo Exp $ */ + +/* + * Copyright (c) 2019, 2020 Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RGE_PCI_BAR0 PCI_MAPREG_START +#define RGE_PCI_BAR1 (PCI_MAPREG_START + 4) +#define RGE_PCI_BAR2 (PCI_MAPREG_START + 8) + +#define RGE_MAC0 0x0000 +#define RGE_MAC4 0x0004 +#define RGE_MAR0 0x0008 +#define RGE_MAR4 0x000c +#define RGE_TXDESC_ADDR_LO 0x0020 +#define RGE_TXDESC_ADDR_HI 0x0024 +#define RGE_CMD 0x0037 +#define RGE_IMR 0x0038 +#define RGE_ISR 0x003c +#define RGE_TXCFG 0x0040 +#define RGE_RXCFG 0x0044 +#define RGE_TIMERCNT 0x0048 +#define RGE_EECMD 0x0050 +#define RGE_CFG0 0x0051 +#define RGE_CFG1 0x0052 +#define RGE_CFG2 0x0053 +#define RGE_CFG3 0x0054 +#define RGE_CFG4 0x0055 +#define RGE_CFG5 0x0056 +#define RGE_TDFNR 0x0057 +#define RGE_TIMERINT0 0x0058 +#define RGE_TIMERINT1 0x005c +#define RGE_CSIDR 0x0064 +#define RGE_CSIAR 0x0068 +#define RGE_PHYSTAT 0x006c +#define RGE_PMCH 0x006f +#define RGE_EPHYAR 0x0080 +#define RGE_TIMERINT2 0x008c +#define RGE_TXSTART 0x0090 +#define RGE_MACOCP 0x00b0 +#define RGE_PHYOCP 0x00b8 +#define RGE_DLLPR 0x00d0 +#define RGE_TWICMD 0x00d2 +#define RGE_MCUCMD 0x00d3 +#define RGE_RXMAXSIZE 0x00da +#define RGE_CPLUSCMD 0x00e0 +#define RGE_IM 0x00e2 +#define RGE_RXDESC_ADDR_LO 0x00e4 +#define RGE_RXDESC_ADDR_HI 0x00e8 +#define RGE_PPSW 0x00f2 +#define RGE_TIMERINT3 0x00f4 +#define RGE_INTMITI(i) (0x0a00 + (i) * 4) +#define RGE_PHYBASE 0x0a40 +#define RGE_ADDR0 0x19e0 +#define RGE_ADDR1 0x19e4 +#define RGE_RSS_CTRL 0x4500 +#define RGE_RXQUEUE_CTRL 0x4800 +#define RGE_EEE_TXIDLE_TIMER 0x6048 + +/* Flags for register RGE_CMD */ +#define RGE_CMD_RXBUF_EMPTY 0x01 +#define RGE_CMD_TXENB 0x04 +#define RGE_CMD_RXENB 0x08 +#define RGE_CMD_RESET 0x10 + +/* Flags for register RGE_ISR */ +#define RGE_ISR_RX_OK 0x00000001 +#define RGE_ISR_RX_ERR 0x00000002 +#define RGE_ISR_TX_OK 0x00000004 +#define RGE_ISR_TX_ERR 0x00000008 +#define RGE_ISR_RX_DESC_UNAVAIL 0x00000010 +#define RGE_ISR_LINKCHG 0x00000020 +#define RGE_ISR_RX_FIFO_OFLOW 0x00000040 +#define RGE_ISR_TX_DESC_UNAVAIL 0x00000080 +#define RGE_ISR_SWI 0x00000100 +#define RGE_ISR_PCS_TIMEOUT 0x00004000 +#define RGE_ISR_SYSTEM_ERR 0x00008000 + +#define RGE_INTRS \ + (RGE_ISR_RX_OK | RGE_ISR_RX_ERR | RGE_ISR_TX_OK | \ + RGE_ISR_TX_ERR | RGE_ISR_LINKCHG | \ + RGE_ISR_TX_DESC_UNAVAIL | RGE_ISR_PCS_TIMEOUT | RGE_ISR_SYSTEM_ERR) + +#define RGE_INTRS_TIMER \ + (RGE_ISR_RX_ERR | RGE_ISR_TX_ERR | RGE_ISR_PCS_TIMEOUT | \ + RGE_ISR_SYSTEM_ERR) + +/* Flags for register RGE_TXCFG */ +#define RGE_TXCFG_HWREV 0x7cf00000 + +/* Flags for register RGE_RXCFG */ +#define RGE_RXCFG_ALLPHYS 0x00000001 +#define RGE_RXCFG_INDIV 0x00000002 +#define RGE_RXCFG_MULTI 0x00000004 +#define RGE_RXCFG_BROAD 0x00000008 +#define RGE_RXCFG_RUNT 0x00000010 +#define RGE_RXCFG_ERRPKT 0x00000020 +#define RGE_RXCFG_VLANSTRIP 0x00c00000 + +/* Flags for register RGE_EECMD */ +#define RGE_EECMD_WRITECFG 0xc0 + +/* Flags for register RGE_CFG1 */ +#define RGE_CFG1_PM_EN 0x01 +#define RGE_CFG1_SPEED_DOWN 0x10 + +/* Flags for register RGE_CFG2 */ +#define RGE_CFG2_PMSTS_EN 0x20 +#define RGE_CFG2_CLKREQ_EN 0x80 + +/* Flags for register RGE_CFG3 */ +#define RGE_CFG3_RDY_TO_L23 0x02 +#define RGE_CFG3_WOL_LINK 0x10 +#define RGE_CFG3_WOL_MAGIC 0x20 + +/* Flags for register RGE_CFG5 */ +#define RGE_CFG5_PME_STS 0x01 +#define RGE_CFG5_WOL_LANWAKE 0x02 +#define RGE_CFG5_WOL_UCAST 0x10 +#define RGE_CFG5_WOL_MCAST 0x20 +#define RGE_CFG5_WOL_BCAST 0x40 + +/* Flags for register RGE_CSIAR */ +#define RGE_CSIAR_BYTE_EN 0x0000000f +#define RGE_CSIAR_BYTE_EN_SHIFT 12 +#define RGE_CSIAR_ADDR_MASK 0x00000fff +#define RGE_CSIAR_BUSY 0x80000000 + +/* Flags for register RGE_PHYSTAT */ +#define RGE_PHYSTAT_FDX 0x0001 +#define RGE_PHYSTAT_LINK 0x0002 +#define RGE_PHYSTAT_10MBPS 0x0004 +#define RGE_PHYSTAT_100MBPS 0x0008 +#define RGE_PHYSTAT_1000MBPS 0x0010 +#define RGE_PHYSTAT_RXFLOW 0x0020 +#define RGE_PHYSTAT_TXFLOW 0x0040 +#define RGE_PHYSTAT_2500MBPS 0x0400 + +/* Flags for register RGE_EPHYAR */ +#define RGE_EPHYAR_DATA_MASK 0x0000ffff +#define RGE_EPHYAR_BUSY 0x80000000 +#define RGE_EPHYAR_ADDR_MASK 0x0000007f +#define RGE_EPHYAR_ADDR_SHIFT 16 + +/* Flags for register RGE_TXSTART */ +#define RGE_TXSTART_START 0x0001 + +/* Flags for register RGE_MACOCP */ +#define RGE_MACOCP_DATA_MASK 0x0000ffff +#define RGE_MACOCP_BUSY 0x80000000 +#define RGE_MACOCP_ADDR_SHIFT 16 + +/* Flags for register RGE_PHYOCP */ +#define RGE_PHYOCP_DATA_MASK 0x0000ffff +#define RGE_PHYOCP_BUSY 0x80000000 +#define RGE_PHYOCP_ADDR_SHIFT 16 + +/* Flags for register RGE_DLLPR. */ +#define RGE_DLLPR_PFM_EN 0x40 +#define RGE_DLLPR_TX_10M_PS_EN 0x80 + +/* Flags for register RGE_MCUCMD */ +#define RGE_MCUCMD_RXFIFO_EMPTY 0x10 +#define RGE_MCUCMD_TXFIFO_EMPTY 0x20 +#define RGE_MCUCMD_IS_OOB 0x80 + +/* Flags for register RGE_CPLUSCMD */ +#define RGE_CPLUSCMD_RXCSUM 0x0020 + +#define RGE_TX_NSEGS 32 +#define RGE_TX_LIST_CNT 1024 +#define RGE_RX_LIST_CNT 1024 +#define RGE_ALIGN 256 +#define RGE_TX_LIST_SZ (sizeof(struct rge_tx_desc) * RGE_TX_LIST_CNT) +#define RGE_RX_LIST_SZ (sizeof(struct rge_rx_desc) * RGE_RX_LIST_CNT) +#define RGE_NEXT_TX_DESC(x) (((x) + 1) % RGE_TX_LIST_CNT) +#define RGE_NEXT_RX_DESC(x) (((x) + 1) % RGE_RX_LIST_CNT) +#define RGE_ADDR_LO(y) ((uint64_t) (y) & 0xffffffff) +#define RGE_ADDR_HI(y) ((uint64_t) (y) >> 32) +#define RGE_OWN(x) \ + (letoh32((x)->hi_qword1.rx_qword4.rge_cmdsts) & RGE_RDCMDSTS_OWN) +#define RGE_RXBYTES(x) \ + (letoh32((x)->hi_qword1.rx_qword4.rge_cmdsts) & RGE_RDCMDSTS_FRAGLEN) + +#define RGE_ADV_2500TFDX 0x0080 + +/* Tx descriptor */ +struct rge_tx_desc { + uint32_t rge_cmdsts; + uint32_t rge_extsts; + uint32_t rge_addrlo; + uint32_t rge_addrhi; + uint32_t reserved[4]; +}; + +#define RGE_TDCMDSTS_COLL 0x000f0000 +#define RGE_TDCMDSTS_EXCESSCOLL 0x00100000 +#define RGE_TDCMDSTS_TXERR 0x00800000 +#define RGE_TDCMDSTS_EOF 0x10000000 +#define RGE_TDCMDSTS_SOF 0x20000000 +#define RGE_TDCMDSTS_EOR 0x40000000 +#define RGE_TDCMDSTS_OWN 0x80000000 + +#define RGE_TDEXTSTS_VTAG 0x00020000 +#define RGE_TDEXTSTS_IPCSUM 0x20000000 +#define RGE_TDEXTSTS_TCPCSUM 0x40000000 +#define RGE_TDEXTSTS_UDPCSUM 0x80000000 + +/* Rx descriptor */ +struct rge_rx_desc { + union { + struct { + uint32_t rsvd0; + uint32_t rsvd1; + } rx_qword0; + } lo_qword0; + + union { + struct { + uint32_t rss; + uint16_t length; + uint16_t hdr_info; + } rx_qword1; + + struct { + uint32_t rsvd2; + uint32_t rsvd3; + } rx_qword2; + } lo_qword1; + + union { + uint64_t rge_addr; + + struct { + uint64_t timestamp; + } rx_timestamp; + + struct { + uint32_t rsvd4; + uint32_t rsvd5; + } rx_qword3; + } hi_qword0; + + union { + struct { + uint32_t rge_extsts; + uint32_t rge_cmdsts; + } rx_qword4; + + struct { + uint16_t rsvd6; + uint16_t rsvd7; + uint32_t rsvd8; + } rx_ptp; + } hi_qword1; +}; + +#define RGE_RDCMDSTS_RXERRSUM 0x00100000 +#define RGE_RDCMDSTS_EOF 0x01000000 +#define RGE_RDCMDSTS_SOF 0x02000000 +#define RGE_RDCMDSTS_EOR 0x40000000 +#define RGE_RDCMDSTS_OWN 0x80000000 +#define RGE_RDCMDSTS_FRAGLEN 0x00003fff + +#define RGE_RDEXTSTS_VTAG 0x00010000 +#define RGE_RDEXTSTS_VLAN_MASK 0x0000ffff +#define RGE_RDEXTSTS_TCPCSUMERR 0x01000000 +#define RGE_RDEXTSTS_UDPCSUMERR 0x02000000 +#define RGE_RDEXTSTS_IPCSUMERR 0x04000000 +#define RGE_RDEXTSTS_TCPPKT 0x10000000 +#define RGE_RDEXTSTS_UDPPKT 0x20000000 +#define RGE_RDEXTSTS_IPV4 0x40000000 +#define RGE_RDEXTSTS_IPV6 0x80000000 + + /* + * Statistics counter structure + */ +struct rge_stats { + uint64_t rge_tx_ok; + uint64_t rge_rx_ok; + uint64_t rge_tx_er; + uint32_t rge_rx_er; + uint16_t rge_miss_pkt; + uint16_t rge_fae; + uint32_t rge_tx_1col; + uint32_t rge_tx_mcol; + uint64_t rge_rx_ok_phy; + uint64_t rge_rx_ok_brd; + uint32_t rge_rx_ok_mul; + uint16_t rge_tx_abt; + uint16_t rge_tx_undrn; +} __packed __aligned(sizeof(uint64_t)); + +#define RGE_STATS_ALIGNMENT 64 + +struct rge_txq { + struct mbuf *txq_mbuf; + bus_dmamap_t txq_dmamap; + int txq_descidx; +}; + +struct rge_rxq { + struct mbuf *rxq_mbuf; + bus_dmamap_t rxq_dmamap; +}; + +struct rge_tx { + struct rge_txq rge_txq[RGE_TX_LIST_CNT]; + int rge_txq_prodidx; + int rge_txq_considx; + + bus_dma_segment_t rge_tx_listseg; + int rge_tx_listnseg; + bus_dmamap_t rge_tx_list_map; + struct rge_tx_desc *rge_tx_list; +}; + +struct rge_rx { + struct rge_rxq rge_rxq[RGE_RX_LIST_CNT]; + int rge_rxq_prodidx; + int rge_rxq_considx; + + struct if_rxring rge_rx_ring; + bus_dma_segment_t rge_rx_listseg; + int rge_rx_listnseg; + bus_dmamap_t rge_rx_list_map; + struct rge_rx_desc *rge_rx_list; + + struct mbuf *rge_head; + struct mbuf *rge_tail; +}; + +struct rge_queues { + struct rge_softc *q_sc; + void *q_ihc; + int q_index; + char q_name[16]; + pci_intr_handle_t q_ih; + struct rge_tx q_tx; + struct rge_rx q_rx; +}; + +/* Microcode version */ +#define RGE_MAC_CFG2_MCODE_VER 0x0b11 +#define RGE_MAC_CFG3_MCODE_VER 0x0b33 +#define RGE_MAC_CFG4_MCODE_VER 0x0b17 +#define RGE_MAC_CFG5_MCODE_VER 0x0b55 + +enum rge_mac_type { + MAC_CFG_UNKNOWN = 1, + MAC_CFG2, + MAC_CFG3, + MAC_CFG4, + MAC_CFG5 +}; + +#define RGE_TIMEOUT 100 + +#define RGE_JUMBO_FRAMELEN 9216 +#define RGE_JUMBO_MTU \ + (RGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \ + ETHER_VLAN_ENCAP_LEN) + +#define RGE_TXCFG_CONFIG 0x03000700 +#define RGE_RXCFG_CONFIG 0x41c00700 + +struct kstat; + +struct rge_softc { + struct device sc_dev; + struct arpcom sc_arpcom; /* Ethernet common data */ + void *sc_ih; /* interrupt vectoring */ + bus_space_handle_t rge_bhandle; /* bus space handle */ + bus_space_tag_t rge_btag; /* bus space tag */ + bus_size_t rge_bsize; + bus_dma_tag_t sc_dmat; + pci_chipset_tag_t sc_pc; + pcitag_t sc_tag; + struct ifmedia sc_media; /* media info */ + enum rge_mac_type rge_type; + + struct rge_queues *sc_queues; + unsigned int sc_nqueues; + + struct task sc_task; + + struct timeout sc_timeout; /* tick timeout */ + + uint16_t rge_mcodever; + uint32_t rge_flags; +#define RGE_FLAG_MSI 0x00000001 + + uint32_t rge_intrs; + int rge_timerintr; +#define RGE_IMTYPE_NONE 0 +#define RGE_IMTYPE_SIM 1 + + struct kstat *sc_kstat; +}; + +/* + * Register space access macros. + */ +#define RGE_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val) +#define RGE_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val) +#define RGE_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val) + +#define RGE_READ_4(sc, reg) \ + bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg) +#define RGE_READ_2(sc, reg) \ + bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg) +#define RGE_READ_1(sc, reg) \ + bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg) + +#define RGE_SETBIT_4(sc, reg, val) \ + RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val)) +#define RGE_SETBIT_2(sc, reg, val) \ + RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val)) +#define RGE_SETBIT_1(sc, reg, val) \ + RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val)) + +#define RGE_CLRBIT_4(sc, reg, val) \ + RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val)) +#define RGE_CLRBIT_2(sc, reg, val) \ + RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val)) +#define RGE_CLRBIT_1(sc, reg, val) \ + RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val)) + +#define RGE_EPHY_SETBIT(sc, reg, val) \ + rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val)) + +#define RGE_EPHY_CLRBIT(sc, reg, val) \ + rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val)) + +#define RGE_PHY_SETBIT(sc, reg, val) \ + rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val)) + +#define RGE_PHY_CLRBIT(sc, reg, val) \ + rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val)) + +#define RGE_MAC_SETBIT(sc, reg, val) \ + rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val)) + +#define RGE_MAC_CLRBIT(sc, reg, val) \ + rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val)) + +static const struct { + uint16_t reg; + uint16_t val; +} rtl8125_mac_bps[] = { + { 0xf800, 0xe008 }, { 0xf802, 0xe01e }, { 0xf804, 0xe02e }, + { 0xf806, 0xe054 }, { 0xf808, 0xe057 }, { 0xf80a, 0xe059 }, + { 0xf80c, 0xe0c2 }, { 0xf80e, 0xe0cb }, { 0xf810, 0x9996 }, + { 0xf812, 0x49d1 }, { 0xf814, 0xf005 }, { 0xf816, 0x49d4 }, + { 0xf818, 0xf10a }, { 0xf81a, 0x49d8 }, { 0xf81c, 0xf108 }, + { 0xf81e, 0xc00f }, { 0xf820, 0x7100 }, { 0xf822, 0x209c }, + { 0xf824, 0x249c }, { 0xf826, 0xc009 }, { 0xf828, 0x9900 }, + { 0xf82a, 0xe004 }, { 0xf82c, 0xc006 }, { 0xf82e, 0x1900 }, + { 0xf830, 0x9900 }, { 0xf832, 0xc602 }, { 0xf834, 0xbe00 }, + { 0xf836, 0x5a48 }, { 0xf838, 0xe0c2 }, { 0xf83a, 0x0004 }, + { 0xf83c, 0xe10a }, { 0xf83e, 0xc60f }, { 0xf840, 0x73c4 }, + { 0xf842, 0x49b3 }, { 0xf844, 0xf106 }, { 0xf846, 0x73c2 }, + { 0xf848, 0xc608 }, { 0xf84a, 0xb406 }, { 0xf84c, 0xc609 }, + { 0xf84e, 0xff80 }, { 0xf850, 0xc605 }, { 0xf852, 0xb406 }, + { 0xf854, 0xc605 }, { 0xf856, 0xff80 }, { 0xf858, 0x0544 }, + { 0xf85a, 0x0568 }, { 0xf85c, 0xe906 }, { 0xf85e, 0xcde8 }, + { 0xf860, 0xc724 }, { 0xf862, 0xc624 }, { 0xf864, 0x9ee2 }, + { 0xf866, 0x1e01 }, { 0xf868, 0x9ee0 }, { 0xf86a, 0x76e0 }, + { 0xf86c, 0x49e0 }, { 0xf86e, 0xf1fe }, { 0xf870, 0x76e6 }, + { 0xf872, 0x486d }, { 0xf874, 0x4868 }, { 0xf876, 0x9ee4 }, + { 0xf878, 0x1e03 }, { 0xf87a, 0x9ee0 }, { 0xf87c, 0x76e0 }, + { 0xf87e, 0x49e0 }, { 0xf880, 0xf1fe }, { 0xf882, 0xc615 }, + { 0xf884, 0x9ee2 }, { 0xf886, 0x1e01 }, { 0xf888, 0x9ee0 }, + { 0xf88a, 0x76e0 }, { 0xf88c, 0x49e0 }, { 0xf88e, 0xf1fe }, + { 0xf890, 0x76e6 }, { 0xf892, 0x486f }, { 0xf894, 0x9ee4 }, + { 0xf896, 0x1e03 }, { 0xf898, 0x9ee0 }, { 0xf89a, 0x76e0 }, + { 0xf89c, 0x49e0 }, { 0xf89e, 0xf1fe }, { 0xf8a0, 0x7196 }, + { 0xf8a2, 0xc702 }, { 0xf8a4, 0xbf00 }, { 0xf8a6, 0x5a44 }, + { 0xf8a8, 0xeb0e }, { 0xf8aa, 0x0070 }, { 0xf8ac, 0x00c3 }, + { 0xf8ae, 0x1bc0 }, { 0xf8b0, 0xc602 }, { 0xf8b2, 0xbe00 }, + { 0xf8b4, 0x0e26 }, { 0xf8b6, 0xc602 }, { 0xf8b8, 0xbe00 }, + { 0xf8ba, 0x0eba }, { 0xf8bc, 0x1501 }, { 0xf8be, 0xf02a }, + { 0xf8c0, 0x1500 }, { 0xf8c2, 0xf15d }, { 0xf8c4, 0xc661 }, + { 0xf8c6, 0x75c8 }, { 0xf8c8, 0x49d5 }, { 0xf8ca, 0xf00a }, + { 0xf8cc, 0x49d6 }, { 0xf8ce, 0xf008 }, { 0xf8d0, 0x49d7 }, + { 0xf8d2, 0xf006 }, { 0xf8d4, 0x49d8 }, { 0xf8d6, 0xf004 }, + { 0xf8d8, 0x75d2 }, { 0xf8da, 0x49d9 }, { 0xf8dc, 0xf150 }, + { 0xf8de, 0xc553 }, { 0xf8e0, 0x77a0 }, { 0xf8e2, 0x75c8 }, + { 0xf8e4, 0x4855 }, { 0xf8e6, 0x4856 }, { 0xf8e8, 0x4857 }, + { 0xf8ea, 0x4858 }, { 0xf8ec, 0x48da }, { 0xf8ee, 0x48db }, + { 0xf8f0, 0x49fe }, { 0xf8f2, 0xf002 }, { 0xf8f4, 0x485a }, + { 0xf8f6, 0x49ff }, { 0xf8f8, 0xf002 }, { 0xf8fa, 0x485b }, + { 0xf8fc, 0x9dc8 }, { 0xf8fe, 0x75d2 }, { 0xf900, 0x4859 }, + { 0xf902, 0x9dd2 }, { 0xf904, 0xc643 }, { 0xf906, 0x75c0 }, + { 0xf908, 0x49d4 }, { 0xf90a, 0xf033 }, { 0xf90c, 0x49d0 }, + { 0xf90e, 0xf137 }, { 0xf910, 0xe030 }, { 0xf912, 0xc63a }, + { 0xf914, 0x75c8 }, { 0xf916, 0x49d5 }, { 0xf918, 0xf00e }, + { 0xf91a, 0x49d6 }, { 0xf91c, 0xf00c }, { 0xf91e, 0x49d7 }, + { 0xf920, 0xf00a }, { 0xf922, 0x49d8 }, { 0xf924, 0xf008 }, + { 0xf926, 0x75d2 }, { 0xf928, 0x49d9 }, { 0xf92a, 0xf005 }, + { 0xf92c, 0xc62e }, { 0xf92e, 0x75c0 }, { 0xf930, 0x49d7 }, + { 0xf932, 0xf125 }, { 0xf934, 0xc528 }, { 0xf936, 0x77a0 }, + { 0xf938, 0xc627 }, { 0xf93a, 0x75c8 }, { 0xf93c, 0x4855 }, + { 0xf93e, 0x4856 }, { 0xf940, 0x4857 }, { 0xf942, 0x4858 }, + { 0xf944, 0x48da }, { 0xf946, 0x48db }, { 0xf948, 0x49fe }, + { 0xf94a, 0xf002 }, { 0xf94c, 0x485a }, { 0xf94e, 0x49ff }, + { 0xf950, 0xf002 }, { 0xf952, 0x485b }, { 0xf954, 0x9dc8 }, + { 0xf956, 0x75d2 }, { 0xf958, 0x4859 }, { 0xf95a, 0x9dd2 }, + { 0xf95c, 0xc616 }, { 0xf95e, 0x75c0 }, { 0xf960, 0x4857 }, + { 0xf962, 0x9dc0 }, { 0xf964, 0xc613 }, { 0xf966, 0x75c0 }, + { 0xf968, 0x49da }, { 0xf96a, 0xf003 }, { 0xf96c, 0x49d0 }, + { 0xf96e, 0xf107 }, { 0xf970, 0xc60b }, { 0xf972, 0xc50e }, + { 0xf974, 0x48d9 }, { 0xf976, 0x9dc0 }, { 0xf978, 0x4859 }, + { 0xf97a, 0x9dc0 }, { 0xf97c, 0xc608 }, { 0xf97e, 0xc702 }, + { 0xf980, 0xbf00 }, { 0xf982, 0x3ae0 }, { 0xf984, 0xe860 }, + { 0xf986, 0xb400 }, { 0xf988, 0xb5d4 }, { 0xf98a, 0xe908 }, + { 0xf98c, 0xe86c }, { 0xf98e, 0x1200 }, { 0xf990, 0xc409 }, + { 0xf992, 0x6780 }, { 0xf994, 0x48f1 }, { 0xf996, 0x8f80 }, + { 0xf998, 0xc404 }, { 0xf99a, 0xc602 }, { 0xf99c, 0xbe00 }, + { 0xf99e, 0x10aa }, { 0xf9a0, 0xc010 }, { 0xf9a2, 0xea7c }, + { 0xf9a4, 0xc602 }, { 0xf9a6, 0xbe00 }, { 0xf9a8, 0x0000 }, + { 0xfc26, 0x8000 }, { 0xfc2a, 0x0540 }, { 0xfc2e, 0x0e24 }, + { 0xfc30, 0x0eb8 }, { 0xfc32, 0x3a5c }, { 0xfc34, 0x10a8 }, + { 0xfc48, 0x007a } +}, rtl8125b_mac_bps[] = { + { 0xf800, 0xe008 }, { 0xf802, 0xe013 }, { 0xf804, 0xe01e }, + { 0xf806, 0xe02f }, { 0xf808, 0xe035 }, { 0xf80a, 0xe04f }, + { 0xf80c, 0xe053 }, { 0xf80e, 0xe055 }, { 0xf810, 0x740a }, + { 0xf812, 0x4846 }, { 0xf814, 0x4847 }, { 0xf816, 0x9c0a }, + { 0xf818, 0xc607 }, { 0xf81a, 0x74c0 }, { 0xf81c, 0x48c6 }, + { 0xf81e, 0x9cc0 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 }, + { 0xf824, 0x13f0 }, { 0xf826, 0xe054 }, { 0xf828, 0x72ca }, + { 0xf82a, 0x4826 }, { 0xf82c, 0x4827 }, { 0xf82e, 0x9aca }, + { 0xf830, 0xc607 }, { 0xf832, 0x72c0 }, { 0xf834, 0x48a6 }, + { 0xf836, 0x9ac0 }, { 0xf838, 0xc602 }, { 0xf83a, 0xbe00 }, + { 0xf83c, 0x081c }, { 0xf83e, 0xe054 }, { 0xf840, 0xc60f }, + { 0xf842, 0x74c4 }, { 0xf844, 0x49cc }, { 0xf846, 0xf109 }, + { 0xf848, 0xc60c }, { 0xf84a, 0x74ca }, { 0xf84c, 0x48c7 }, + { 0xf84e, 0x9cca }, { 0xf850, 0xc609 }, { 0xf852, 0x74c0 }, + { 0xf854, 0x4846 }, { 0xf856, 0x9cc0 }, { 0xf858, 0xc602 }, + { 0xf85a, 0xbe00 }, { 0xf85c, 0x2494 }, { 0xf85e, 0xe092 }, + { 0xf860, 0xe0c0 }, { 0xf862, 0xe054 }, { 0xf864, 0x7420 }, + { 0xf866, 0x48c0 }, { 0xf868, 0x9c20 }, { 0xf86a, 0x7444 }, + { 0xf86c, 0xc602 }, { 0xf86e, 0xbe00 }, { 0xf870, 0x12dc }, + { 0xf872, 0x733a }, { 0xf874, 0x21b5 }, { 0xf876, 0x25bc }, + { 0xf878, 0x1304 }, { 0xf87a, 0xf111 }, { 0xf87c, 0x1b12 }, + { 0xf87e, 0x1d2a }, { 0xf880, 0x3168 }, { 0xf882, 0x3ada }, + { 0xf884, 0x31ab }, { 0xf886, 0x1a00 }, { 0xf888, 0x9ac0 }, + { 0xf88a, 0x1300 }, { 0xf88c, 0xf1fb }, { 0xf88e, 0x7620 }, + { 0xf890, 0x236e }, { 0xf892, 0x276f }, { 0xf894, 0x1a3c }, + { 0xf896, 0x22a1 }, { 0xf898, 0x41b5 }, { 0xf89a, 0x9ee2 }, + { 0xf89c, 0x76e4 }, { 0xf89e, 0x486f }, { 0xf8a0, 0x9ee4 }, + { 0xf8a2, 0xc602 }, { 0xf8a4, 0xbe00 }, { 0xf8a6, 0x4a26 }, + { 0xf8a8, 0x733a }, { 0xf8aa, 0x49bb }, { 0xf8ac, 0xc602 }, + { 0xf8ae, 0xbe00 }, { 0xf8b0, 0x47a2 }, { 0xf8b2, 0xc602 }, + { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x0000 }, { 0xf8b8, 0xc602 }, + { 0xf8ba, 0xbe00 }, { 0xf8bc, 0x0000 }, { 0xfc26, 0x8000 }, + { 0xfc28, 0x13e6 }, { 0xfc2a, 0x0812 }, { 0xfc2c, 0x248c }, + { 0xfc2e, 0x12da }, { 0xfc30, 0x4a20 }, { 0xfc32, 0x47a0 }, + { 0xfc48, 0x003f } +}; + +static const struct { + uint16_t reg; + uint16_t val; +} rtl8125_mac_cfg2_ephy[] = { + { 0x0001, 0xa812 }, { 0x0009, 0x520c }, { 0x0004, 0xd000 }, + { 0x000d, 0xf702 }, { 0x000a, 0x8653 }, { 0x0006, 0x001e }, + { 0x0008, 0x3595 }, { 0x0020, 0x9455 }, { 0x0021, 0x99ff }, + { 0x0002, 0x6046 }, { 0x0029, 0xfe00 }, { 0x0023, 0xab62 }, + { 0x0041, 0xa80c }, { 0x0049, 0x520c }, { 0x0044, 0xd000 }, + { 0x004d, 0xf702 }, { 0x004a, 0x8653 }, { 0x0046, 0x001e }, + { 0x0048, 0x3595 }, { 0x0060, 0x9455 }, { 0x0061, 0x99ff }, + { 0x0042, 0x6046 }, { 0x0069, 0xfe00 }, { 0x0063, 0xab62 } +}, rtl8125_mac_cfg3_ephy[] = { + { 0x0004, 0xd000 }, { 0x000a, 0x8653 }, { 0x0023, 0xab66 }, + { 0x0020, 0x9455 }, { 0x0021, 0x99ff }, { 0x0029, 0xfe04 }, + { 0x0044, 0xd000 }, { 0x004a, 0x8653 }, { 0x0063, 0xab66 }, + { 0x0060, 0x9455 }, { 0x0061, 0x99ff }, { 0x0069, 0xfe04 } +}, rtl8125_mac_cfg4_ephy[] = { + { 0x0006, 0x001f }, { 0x000a, 0xb66b }, { 0x0001, 0xa852 }, + { 0x0024, 0x0008 }, { 0x002f, 0x6052 }, { 0x000d, 0xf716 }, + { 0x0020, 0xd477 }, { 0x0021, 0x4477 }, { 0x0022, 0x0013 }, + { 0x0023, 0xbb66 }, { 0x000b, 0xa909 }, { 0x0029, 0xff04 }, + { 0x001b, 0x1ea0 }, { 0x0046, 0x001f }, { 0x004a, 0xb66b }, + { 0x0041, 0xa84a }, { 0x0064, 0x000c }, { 0x006f, 0x604a }, + { 0x004d, 0xf716 }, { 0x0060, 0xd477 }, { 0x0061, 0x4477 }, + { 0x0062, 0x0013 }, { 0x0063, 0xbb66 }, { 0x004b, 0xa909 }, + { 0x0069, 0xff04 }, { 0x005b, 0x1ea0 } +}, rtl8125_mac_cfg5_ephy[] = { + { 0x000b, 0xa908 }, { 0x0022, 0x0023 }, { 0x001e, 0x28eb }, + { 0x004b, 0xa908 }, { 0x0062, 0x0023 }, { 0x005e, 0x28eb } +}; + +#define RTL8125_MAC_CFG2_MCU \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8013 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8021 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8042 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0xa088 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a50 }, \ + { 0xa438, 0x8008 }, \ + { 0xa438, 0xd014 }, \ + { 0xa438, 0xd1a3 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x401a }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x40c2 }, \ + { 0xa438, 0x60a6 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f8b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a86 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a6c }, \ + { 0xa438, 0x8080 }, \ + { 0xa438, 0xd019 }, \ + { 0xa438, 0xd1a2 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x401a }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x40c4 }, \ + { 0xa438, 0x60a6 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f8b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a86 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a84 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0x8970 }, \ + { 0xa438, 0x0c07 }, \ + { 0xa438, 0x0901 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xcf09 }, \ + { 0xa438, 0xd705 }, \ + { 0xa438, 0x4000 }, \ + { 0xa438, 0xceff }, \ + { 0xa438, 0xaf0a }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1213 }, \ + { 0xa438, 0x8401 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x8580 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1253 }, \ + { 0xa438, 0xd064 }, \ + { 0xa438, 0xd181 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4018 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc50f }, \ + { 0xa438, 0xd706 }, \ + { 0xa438, 0x2c59 }, \ + { 0xa438, 0x804d }, \ + { 0xa438, 0xc60f }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xc605 }, \ + { 0xa438, 0xae02 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x10fd }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x10f4 }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x1252 }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x1206 }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x0a78 }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x0a60 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x0a4f }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0x3f00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8066 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8089 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80a0 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80b2 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80c2 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x62db }, \ + { 0xa438, 0x655c }, \ + { 0xa438, 0xd73e }, \ + { 0xa438, 0x60e9 }, \ + { 0xa438, 0x614a }, \ + { 0xa438, 0x61ab }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0501 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0505 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0509 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x653c }, \ + { 0xa438, 0xd73e }, \ + { 0xa438, 0x60e9 }, \ + { 0xa438, 0x614a }, \ + { 0xa438, 0x61ab }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0502 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0506 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x050a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0xd73e }, \ + { 0xa438, 0x60e9 }, \ + { 0xa438, 0x614a }, \ + { 0xa438, 0x61ab }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0505 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0506 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0504 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x050c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0xd73e }, \ + { 0xa438, 0x60e9 }, \ + { 0xa438, 0x614a }, \ + { 0xa438, 0x61ab }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0509 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x050a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x050c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0508 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0304 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xd73e }, \ + { 0xa438, 0x60e9 }, \ + { 0xa438, 0x614a }, \ + { 0xa438, 0x61ab }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0501 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0321 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0502 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0321 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0504 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0321 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0508 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0321 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0346 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0x8208 }, \ + { 0xa438, 0x609d }, \ + { 0xa438, 0xa50f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x001a }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x001a }, \ + { 0xa438, 0x607d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00ab }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00ab }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x60fd }, \ + { 0xa438, 0xa50f }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xaa0f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x017b }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0a05 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x017b }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x60fd }, \ + { 0xa438, 0xa50f }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xaa0f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x01e0 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0a05 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x01e0 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x60fd }, \ + { 0xa438, 0xa50f }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xaa0f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0231 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0503 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0a05 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0231 }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0x0221 }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0x01ce }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0x00a6 }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0x000d }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x0308 }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x029f }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x007f }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8017 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8029 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8054 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x805a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8064 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80a7 }, \ + { 0xa438, 0x9430 }, \ + { 0xa438, 0x9480 }, \ + { 0xa438, 0xb408 }, \ + { 0xa438, 0xd120 }, \ + { 0xa438, 0xd057 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x064b }, \ + { 0xa438, 0xcb80 }, \ + { 0xa438, 0x9906 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0567 }, \ + { 0xa438, 0xcb94 }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8406 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x8dff }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e4 }, \ + { 0xa438, 0xa840 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0773 }, \ + { 0xa438, 0xcb91 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd139 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd140 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xb404 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07dc }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xa110 }, \ + { 0xa438, 0xa2a0 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4045 }, \ + { 0xa438, 0xa180 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0742 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07ec }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f74 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0742 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb6 }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07dc }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x064b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07c0 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fa7 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0481 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x94bc }, \ + { 0xa438, 0x870c }, \ + { 0xa438, 0xa190 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa280 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x8220 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x078e }, \ + { 0xa438, 0xcb92 }, \ + { 0xa438, 0xa840 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd140 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd150 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x60a0 }, \ + { 0xa438, 0x6121 }, \ + { 0xa438, 0x61a2 }, \ + { 0xa438, 0x6223 }, \ + { 0xa438, 0xf02f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d10 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf00f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d20 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf00a }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d30 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf005 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d40 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e4 }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xa008 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4046 }, \ + { 0xa438, 0xa002 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0742 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07f7 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f74 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0742 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb5 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e4 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x3ad4 }, \ + { 0xa438, 0x0537 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x8840 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x064b }, \ + { 0xa438, 0x8301 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0xa70c }, \ + { 0xa438, 0x9402 }, \ + { 0xa438, 0x890c }, \ + { 0xa438, 0x8840 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x064b }, \ + { 0xa436, 0xa10e }, \ + { 0xa438, 0x0642 }, \ + { 0xa436, 0xa10c }, \ + { 0xa438, 0x0686 }, \ + { 0xa436, 0xa10a }, \ + { 0xa438, 0x0788 }, \ + { 0xa436, 0xa108 }, \ + { 0xa438, 0x047b }, \ + { 0xa436, 0xa106 }, \ + { 0xa438, 0x065c }, \ + { 0xa436, 0xa104 }, \ + { 0xa438, 0x0769 }, \ + { 0xa436, 0xa102 }, \ + { 0xa438, 0x0565 }, \ + { 0xa436, 0xa100 }, \ + { 0xa438, 0x06f9 }, \ + { 0xa436, 0xa110 }, \ + { 0xa438, 0x00ff }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8530 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x3caf }, \ + { 0xa438, 0x8593 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x9caf }, \ + { 0xa438, 0x85a5 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x5afb }, \ + { 0xa438, 0xe083 }, \ + { 0xa438, 0xfb0c }, \ + { 0xa438, 0x020d }, \ + { 0xa438, 0x021b }, \ + { 0xa438, 0x10bf }, \ + { 0xa438, 0x86d7 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86da }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbe0 }, \ + { 0xa438, 0x83fc }, \ + { 0xa438, 0x0c02 }, \ + { 0xa438, 0x0d02 }, \ + { 0xa438, 0x1b10 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xda02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xdd02 }, \ + { 0xa438, 0x5afb }, \ + { 0xa438, 0xe083 }, \ + { 0xa438, 0xfd0c }, \ + { 0xa438, 0x020d }, \ + { 0xa438, 0x021b }, \ + { 0xa438, 0x10bf }, \ + { 0xa438, 0x86dd }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86e0 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbe0 }, \ + { 0xa438, 0x83fe }, \ + { 0xa438, 0x0c02 }, \ + { 0xa438, 0x0d02 }, \ + { 0xa438, 0x1b10 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xe002 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xaf2f }, \ + { 0xa438, 0xbd02 }, \ + { 0xa438, 0x2cac }, \ + { 0xa438, 0x0286 }, \ + { 0xa438, 0x65af }, \ + { 0xa438, 0x212b }, \ + { 0xa438, 0x022c }, \ + { 0xa438, 0x6002 }, \ + { 0xa438, 0x86b6 }, \ + { 0xa438, 0xaf21 }, \ + { 0xa438, 0x0cd1 }, \ + { 0xa438, 0x03bf }, \ + { 0xa438, 0x8710 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x870d }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x8719 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x8716 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x871f }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x871c }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x8728 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x8725 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x8707 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbad }, \ + { 0xa438, 0x281c }, \ + { 0xa438, 0xd100 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x0a02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x1302 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x2b02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xae1a }, \ + { 0xa438, 0xd101 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x0a02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x1302 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x2b02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xd101 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x3402 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x3102 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x3d02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x3a02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4302 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4002 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4c02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4902 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xd100 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x2e02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x3702 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4602 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xbf87 }, \ + { 0xa438, 0x4f02 }, \ + { 0xa438, 0x5ab7 }, \ + { 0xa438, 0xaf35 }, \ + { 0xa438, 0x7ff8 }, \ + { 0xa438, 0xfaef }, \ + { 0xa438, 0x69bf }, \ + { 0xa438, 0x86e3 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x86fb }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86e6 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x86fe }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86e9 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x8701 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86ec }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x8704 }, \ + { 0xa438, 0x025a }, \ + { 0xa438, 0xb7bf }, \ + { 0xa438, 0x86ef }, \ + { 0xa438, 0x0262 }, \ + { 0xa438, 0x7cbf }, \ + { 0xa438, 0x86f2 }, \ + { 0xa438, 0x0262 }, \ + { 0xa438, 0x7cbf }, \ + { 0xa438, 0x86f5 }, \ + { 0xa438, 0x0262 }, \ + { 0xa438, 0x7cbf }, \ + { 0xa438, 0x86f8 }, \ + { 0xa438, 0x0262 }, \ + { 0xa438, 0x7cef }, \ + { 0xa438, 0x96fe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x6273 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xf202 }, \ + { 0xa438, 0x6273 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xf502 }, \ + { 0xa438, 0x6273 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xf802 }, \ + { 0xa438, 0x6273 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefc }, \ + { 0xa438, 0x0420 }, \ + { 0xa438, 0xb540 }, \ + { 0xa438, 0x53b5 }, \ + { 0xa438, 0x4086 }, \ + { 0xa438, 0xb540 }, \ + { 0xa438, 0xb9b5 }, \ + { 0xa438, 0x40c8 }, \ + { 0xa438, 0xb03a }, \ + { 0xa438, 0xc8b0 }, \ + { 0xa438, 0xbac8 }, \ + { 0xa438, 0xb13a }, \ + { 0xa438, 0xc8b1 }, \ + { 0xa438, 0xba77 }, \ + { 0xa438, 0xbd26 }, \ + { 0xa438, 0xffbd }, \ + { 0xa438, 0x2677 }, \ + { 0xa438, 0xbd28 }, \ + { 0xa438, 0xffbd }, \ + { 0xa438, 0x2840 }, \ + { 0xa438, 0xbd26 }, \ + { 0xa438, 0xc8bd }, \ + { 0xa438, 0x2640 }, \ + { 0xa438, 0xbd28 }, \ + { 0xa438, 0xc8bd }, \ + { 0xa438, 0x28bb }, \ + { 0xa438, 0xa430 }, \ + { 0xa438, 0x98b0 }, \ + { 0xa438, 0x1eba }, \ + { 0xa438, 0xb01e }, \ + { 0xa438, 0xdcb0 }, \ + { 0xa438, 0x1e98 }, \ + { 0xa438, 0xb09e }, \ + { 0xa438, 0xbab0 }, \ + { 0xa438, 0x9edc }, \ + { 0xa438, 0xb09e }, \ + { 0xa438, 0x98b1 }, \ + { 0xa438, 0x1eba }, \ + { 0xa438, 0xb11e }, \ + { 0xa438, 0xdcb1 }, \ + { 0xa438, 0x1e98 }, \ + { 0xa438, 0xb19e }, \ + { 0xa438, 0xbab1 }, \ + { 0xa438, 0x9edc }, \ + { 0xa438, 0xb19e }, \ + { 0xa438, 0x11b0 }, \ + { 0xa438, 0x1e22 }, \ + { 0xa438, 0xb01e }, \ + { 0xa438, 0x33b0 }, \ + { 0xa438, 0x1e11 }, \ + { 0xa438, 0xb09e }, \ + { 0xa438, 0x22b0 }, \ + { 0xa438, 0x9e33 }, \ + { 0xa438, 0xb09e }, \ + { 0xa438, 0x11b1 }, \ + { 0xa438, 0x1e22 }, \ + { 0xa438, 0xb11e }, \ + { 0xa438, 0x33b1 }, \ + { 0xa438, 0x1e11 }, \ + { 0xa438, 0xb19e }, \ + { 0xa438, 0x22b1 }, \ + { 0xa438, 0x9e33 }, \ + { 0xa438, 0xb19e }, \ + { 0xa436, 0xb85e }, \ + { 0xa438, 0x2f71 }, \ + { 0xa436, 0xb860 }, \ + { 0xa438, 0x20d9 }, \ + { 0xa436, 0xb862 }, \ + { 0xa438, 0x2109 }, \ + { 0xa436, 0xb864 }, \ + { 0xa438, 0x34e7 }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0x000f } + +#define RTL8125_MAC_CFG3_MCU \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8093 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8097 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x809d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80a1 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80aa }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x607b }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0xf00e }, \ + { 0xa438, 0x42da }, \ + { 0xa438, 0xf01e }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x615b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf01c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf024 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf02c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf034 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac11 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa410 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4779 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf034 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac22 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa420 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4559 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf023 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac44 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa440 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4339 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf012 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac88 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa480 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4119 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5fac }, \ + { 0xa438, 0xc48f }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x141b }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x121a }, \ + { 0xa438, 0xd0b4 }, \ + { 0xa438, 0xd1bb }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0898 }, \ + { 0xa438, 0xd0b4 }, \ + { 0xa438, 0xd1bb }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a0e }, \ + { 0xa438, 0xd064 }, \ + { 0xa438, 0xd18a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0b7e }, \ + { 0xa438, 0x401c }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xa804 }, \ + { 0xa438, 0x8804 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x053b }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0648 }, \ + { 0xa438, 0xc520 }, \ + { 0xa438, 0xa201 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x252d }, \ + { 0xa438, 0x1646 }, \ + { 0xa438, 0xd708 }, \ + { 0xa438, 0x4006 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1646 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0308 }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0x0307 }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0x1645 }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x0647 }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x053a }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x0b7c }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x0a0c }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x0896 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x11a1 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0xff00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8015 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0xad02 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x02d7 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00ed }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0509 }, \ + { 0xa438, 0xc100 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x008f }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x008d }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x00eb }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x0103 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8018 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8024 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8055 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8072 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80dc }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xfffd }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xfffd }, \ + { 0xa438, 0x8301 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0xa70c }, \ + { 0xa438, 0x9402 }, \ + { 0xa438, 0x890c }, \ + { 0xa438, 0x8840 }, \ + { 0xa438, 0xa380 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xcb91 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd139 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd140 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xb404 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e0 }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xa110 }, \ + { 0xa438, 0xa2a0 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4085 }, \ + { 0xa438, 0xa180 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x8280 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07f0 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f74 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb6 }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e0 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xd158 }, \ + { 0xa438, 0xd04d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x03d4 }, \ + { 0xa438, 0x94bc }, \ + { 0xa438, 0x870c }, \ + { 0xa438, 0x8380 }, \ + { 0xa438, 0xd10d }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07c4 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xa190 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa280 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xa220 }, \ + { 0xa438, 0xd130 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07c4 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xbb80 }, \ + { 0xa438, 0xd1c4 }, \ + { 0xa438, 0xd074 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x604b }, \ + { 0xa438, 0xa90c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0556 }, \ + { 0xa438, 0xcb92 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd116 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd119 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x60a0 }, \ + { 0xa438, 0x6241 }, \ + { 0xa438, 0x63e2 }, \ + { 0xa438, 0x6583 }, \ + { 0xa438, 0xf054 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d10 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf02f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d50 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf02a }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d20 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf021 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d60 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf01c }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d30 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf013 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d70 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf00e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d40 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf005 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d80 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e8 }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5ff4 }, \ + { 0xa438, 0xa008 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4046 }, \ + { 0xa438, 0xa002 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07fb }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x7f6f }, \ + { 0xa438, 0x7f4e }, \ + { 0xa438, 0x7f2d }, \ + { 0xa438, 0x7f0c }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e8 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb5 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x3ad4 }, \ + { 0xa438, 0x0556 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xd1f5 }, \ + { 0xa438, 0xd049 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x01ec }, \ + { 0xa436, 0xa10e }, \ + { 0xa438, 0x01ea }, \ + { 0xa436, 0xa10c }, \ + { 0xa438, 0x06a9 }, \ + { 0xa436, 0xa10a }, \ + { 0xa438, 0x078a }, \ + { 0xa436, 0xa108 }, \ + { 0xa438, 0x03d2 }, \ + { 0xa436, 0xa106 }, \ + { 0xa438, 0x067f }, \ + { 0xa436, 0xa104 }, \ + { 0xa438, 0x0665 }, \ + { 0xa436, 0xa102 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa100 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa110 }, \ + { 0xa438, 0x00fc }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8530 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x3caf }, \ + { 0xa438, 0x8545 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x45af }, \ + { 0xa438, 0x8545 }, \ + { 0xa438, 0xee82 }, \ + { 0xa438, 0xf900 }, \ + { 0xa438, 0x0103 }, \ + { 0xa438, 0xaf03 }, \ + { 0xa438, 0xb7f8 }, \ + { 0xa438, 0xe0a6 }, \ + { 0xa438, 0x00e1 }, \ + { 0xa438, 0xa601 }, \ + { 0xa438, 0xef01 }, \ + { 0xa438, 0x58f0 }, \ + { 0xa438, 0xa080 }, \ + { 0xa438, 0x37a1 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0xae16 }, \ + { 0xa438, 0xa185 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x11a1 }, \ + { 0xa438, 0x8702 }, \ + { 0xa438, 0xae0c }, \ + { 0xa438, 0xa188 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x07a1 }, \ + { 0xa438, 0x8902 }, \ + { 0xa438, 0xae02 }, \ + { 0xa438, 0xae1c }, \ + { 0xa438, 0xe0b4 }, \ + { 0xa438, 0x62e1 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0x6901 }, \ + { 0xa438, 0xe4b4 }, \ + { 0xa438, 0x62e5 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0xe0b4 }, \ + { 0xa438, 0x62e1 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0x6901 }, \ + { 0xa438, 0xe4b4 }, \ + { 0xa438, 0x62e5 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0xfc04 }, \ + { 0xa436, 0xb85e }, \ + { 0xa438, 0x03b3 }, \ + { 0xa436, 0xb860 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb862 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb864 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0x0001 } + +#define RTL8125_MAC_CFG4_MCU \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x3700 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0001 }, \ + { 0xb820, 0x0090 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8025 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8044 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8083 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808d }, \ + { 0xa438, 0xd712 }, \ + { 0xa438, 0x4077 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x4159 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x6099 }, \ + { 0xa438, 0x7f44 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1a14 }, \ + { 0xa438, 0x9040 }, \ + { 0xa438, 0x9201 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1b1a }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x2425 }, \ + { 0xa438, 0x1a14 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x3ce5 }, \ + { 0xa438, 0x1afb }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1b00 }, \ + { 0xa438, 0xd712 }, \ + { 0xa438, 0x4077 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x4159 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x60b9 }, \ + { 0xa438, 0x2421 }, \ + { 0xa438, 0x1c17 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1a14 }, \ + { 0xa438, 0x9040 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1c2c }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x2425 }, \ + { 0xa438, 0x1a14 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x3ce5 }, \ + { 0xa438, 0x1c0f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1c13 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0x6072 }, \ + { 0xa438, 0x8401 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xa401 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x146e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0b77 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x665d }, \ + { 0xa438, 0x653e }, \ + { 0xa438, 0x641f }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x62c4 }, \ + { 0xa438, 0x6185 }, \ + { 0xa438, 0x6066 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x165a }, \ + { 0xa438, 0xc101 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x7fa6 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807d }, \ + { 0xa438, 0xc102 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x2569 }, \ + { 0xa438, 0x8058 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807d }, \ + { 0xa438, 0xc104 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x7fa4 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807d }, \ + { 0xa438, 0xc120 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x7fbf }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807d }, \ + { 0xa438, 0xc140 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x7fbe }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x807d }, \ + { 0xa438, 0xc180 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1945 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x7fbd }, \ + { 0xa438, 0xc100 }, \ + { 0xa438, 0xcb00 }, \ + { 0xa438, 0xd708 }, \ + { 0xa438, 0x6018 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x165a }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14f6 }, \ + { 0xa438, 0xd014 }, \ + { 0xa438, 0xd1e3 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1356 }, \ + { 0xa438, 0xd705 }, \ + { 0xa438, 0x5fbe }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1559 }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x1557 }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x1677 }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x0b75 }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x1c17 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x1b04 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0x1f00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x817f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x82ab }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x83f8 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8444 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8454 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8459 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8465 }, \ + { 0xa438, 0xcb11 }, \ + { 0xa438, 0xa50c }, \ + { 0xa438, 0x8310 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x4076 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x0903 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6083 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a7d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a4d }, \ + { 0xa438, 0xcb12 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5f84 }, \ + { 0xa438, 0xd102 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x60f3 }, \ + { 0xa438, 0xd413 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xd410 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xcb13 }, \ + { 0xa438, 0xa108 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8108 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa910 }, \ + { 0xa438, 0xa780 }, \ + { 0xa438, 0xd14a }, \ + { 0xa438, 0xd048 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x6255 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f74 }, \ + { 0xa438, 0x6326 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x5f07 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0xa004 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8004 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8001 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x0902 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5fab }, \ + { 0xa438, 0xba08 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f8b }, \ + { 0xa438, 0x9a08 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x6535 }, \ + { 0xa438, 0xd40d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xcb14 }, \ + { 0xa438, 0xa004 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8004 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8001 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa780 }, \ + { 0xa438, 0xd14a }, \ + { 0xa438, 0xd048 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x6206 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x5f47 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0xa004 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8004 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8001 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x0902 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8064 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0xd40e }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xb920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5fac }, \ + { 0xa438, 0x9920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f8c }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x6073 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x4216 }, \ + { 0xa438, 0xa004 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8004 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8001 }, \ + { 0xa438, 0xd120 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x8504 }, \ + { 0xa438, 0xcb21 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f9f }, \ + { 0xa438, 0x8301 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x40e0 }, \ + { 0xa438, 0xd196 }, \ + { 0xa438, 0xd04d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xcb22 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a6d }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0xa640 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x8910 }, \ + { 0xa438, 0x8720 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6083 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a7d }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0f14 }, \ + { 0xa438, 0xcb23 }, \ + { 0xa438, 0x8fc0 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0xaf40 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0x0cc0 }, \ + { 0xa438, 0x0f80 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0xafc0 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x5dee }, \ + { 0xa438, 0xcb24 }, \ + { 0xa438, 0x8f1f }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x7f6e }, \ + { 0xa438, 0xa111 }, \ + { 0xa438, 0xa215 }, \ + { 0xa438, 0xa401 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0xcb25 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x8640 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b43 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b86 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xb920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5fac }, \ + { 0xa438, 0x9920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f8c }, \ + { 0xa438, 0xcb26 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5f82 }, \ + { 0xa438, 0x8111 }, \ + { 0xa438, 0x8205 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0xcb27 }, \ + { 0xa438, 0xd404 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6083 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d02 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d02 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a7d }, \ + { 0xa438, 0xa710 }, \ + { 0xa438, 0xa104 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8104 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a42 }, \ + { 0xa438, 0x8001 }, \ + { 0xa438, 0xa120 }, \ + { 0xa438, 0xaa0f }, \ + { 0xa438, 0x8110 }, \ + { 0xa438, 0xa284 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xd193 }, \ + { 0xa438, 0xd046 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xcb28 }, \ + { 0xa438, 0xa110 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fa8 }, \ + { 0xa438, 0x8110 }, \ + { 0xa438, 0x8284 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8710 }, \ + { 0xa438, 0xb804 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f82 }, \ + { 0xa438, 0x9804 }, \ + { 0xa438, 0xcb29 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5f85 }, \ + { 0xa438, 0xa710 }, \ + { 0xa438, 0xb820 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f65 }, \ + { 0xa438, 0x9820 }, \ + { 0xa438, 0xcb2a }, \ + { 0xa438, 0xa190 }, \ + { 0xa438, 0xa284 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xd13d }, \ + { 0xa438, 0xd04a }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x3444 }, \ + { 0xa438, 0x8149 }, \ + { 0xa438, 0xa220 }, \ + { 0xa438, 0xd1a0 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x3444 }, \ + { 0xa438, 0x8151 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x5f51 }, \ + { 0xa438, 0xcb2f }, \ + { 0xa438, 0xa302 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd708 }, \ + { 0xa438, 0x5f63 }, \ + { 0xa438, 0xd411 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0x8302 }, \ + { 0xa438, 0xd409 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xb920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5fac }, \ + { 0xa438, 0x9920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7f8c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x5fa3 }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a4 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0xb808 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7fa3 }, \ + { 0xa438, 0x9808 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0433 }, \ + { 0xa438, 0xcb15 }, \ + { 0xa438, 0xa508 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6083 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a7d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a4d }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f9f }, \ + { 0xa438, 0x8301 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x40e0 }, \ + { 0xa438, 0xd115 }, \ + { 0xa438, 0xd04f }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xd413 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a37 }, \ + { 0xa438, 0xcb16 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a6d }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0xa640 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x8720 }, \ + { 0xa438, 0xd17a }, \ + { 0xa438, 0xd04c }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0f14 }, \ + { 0xa438, 0xcb17 }, \ + { 0xa438, 0x8fc0 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0xaf40 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0x0cc0 }, \ + { 0xa438, 0x0f80 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0xafc0 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a25 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x61ce }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5db4 }, \ + { 0xa438, 0xcb18 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x8640 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b43 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xffd6 }, \ + { 0xa438, 0x8f1f }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x7f8e }, \ + { 0xa438, 0xa131 }, \ + { 0xa438, 0xaa0f }, \ + { 0xa438, 0xa2d5 }, \ + { 0xa438, 0xa407 }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x8310 }, \ + { 0xa438, 0xa308 }, \ + { 0xa438, 0x8308 }, \ + { 0xa438, 0xcb19 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x8640 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b43 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b86 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xb920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a5e }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 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0xb602 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x7e02 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xa100 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x25a1 }, \ + { 0xa438, 0x041d }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xf1bf }, \ + { 0xa438, 0x8675 }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x48e1 }, \ + { 0xa438, 0x8ff2 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x7802 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xf3bf }, \ + { 0xa438, 0x867b }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x48ae }, \ + { 0xa438, 0x29a1 }, \ + { 0xa438, 0x070b }, \ + { 0xa438, 0xae24 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x8102 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xad28 }, \ + { 0xa438, 0x1be1 }, \ + { 0xa438, 0x8ff4 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x7502 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xf5bf }, \ + { 0xa438, 0x8678 }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x48e1 }, \ + { 0xa438, 0x8ff6 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x7b02 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0xaf09 }, \ + { 0xa438, 0x8420 }, \ + { 0xa438, 0xbc32 }, \ + { 0xa438, 0x20bc }, \ + { 0xa438, 0x3e76 }, \ + { 0xa438, 0xbc08 }, \ + { 0xa438, 0xfda6 }, \ + { 0xa438, 0x1a00 }, \ + { 0xa438, 0xb64e }, \ + { 0xa438, 0xd101 }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xa402 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xa702 }, \ + { 0xa438, 0x54c0 }, \ + { 0xa438, 0xd10f }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xaa02 }, \ + { 0xa438, 0x4f48 }, \ + { 0xa438, 0x024d }, \ + { 0xa438, 0x6abf }, \ + { 0xa438, 0x85ad }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x67bf }, \ + { 0xa438, 0x8ff7 }, \ + { 0xa438, 0xddbf }, \ + { 0xa438, 0x85b0 }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x67bf }, \ + { 0xa438, 0x8ff8 }, \ + { 0xa438, 0xddbf }, \ + { 0xa438, 0x85b3 }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x67bf }, \ + { 0xa438, 0x8ff9 }, \ + { 0xa438, 0xddbf }, \ + { 0xa438, 0x85b6 }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x67bf }, \ + { 0xa438, 0x8ffa }, \ + { 0xa438, 0xddd1 }, \ + { 0xa438, 0x00bf }, \ + { 0xa438, 0x85aa }, \ + { 0xa438, 0x024f }, \ + { 0xa438, 0x4802 }, \ + { 0xa438, 0x4d6a }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xad02 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0xfbdd }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xb002 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0xfcdd }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xb302 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0xfddd }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xb602 }, \ + { 0xa438, 0x4f67 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0xfedd }, \ + { 0xa438, 0xbf85 }, \ + { 0xa438, 0xa702 }, \ + { 0xa438, 0x54b7 }, \ + { 0xa438, 0xaf00 }, \ + { 0xa438, 0x8800 }, \ + { 0xa436, 0xb818 }, \ + { 0xa438, 0x38b8 }, \ + { 0xa436, 0xb81a }, \ + { 0xa438, 0x0444 }, \ + { 0xa436, 0xb81c }, \ + { 0xa438, 0x40ee }, \ + { 0xa436, 0xb81e }, \ + { 0xa438, 0x3c1a }, \ + { 0xa436, 0xb850 }, \ + { 0xa438, 0x0981 }, \ + { 0xa436, 0xb852 }, \ + { 0xa438, 0x0085 }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb884 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb832 }, \ + { 0xa438, 0x003f }, \ + { 0xa436, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x0000 }, \ + { 0xb820, 0x0000 }, \ + { 0xa436, 0x801e }, \ + { 0xa438, 0x0021 } + +#define RTL8125_MAC_CFG5_MCU \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x3701 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0001 }, \ + { 0xb820, 0x0090 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8024 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8057 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8063 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8068 }, \ + { 0xa438, 0xd093 }, \ + { 0xa438, 0xd1c4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x5fbc }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9f1 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0fc9 }, \ + { 0xa438, 0xbb50 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0xa202 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x8c0f }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1519 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1548 }, \ + { 0xa438, 0x2f70 }, \ + { 0xa438, 0x802a }, \ + { 0xa438, 0x2f73 }, \ + { 0xa438, 0x156a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x155c }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0xa202 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1551 }, \ + { 0xa438, 0xc0c1 }, \ + { 0xa438, 0xc0c0 }, \ + { 0xa438, 0xd05a }, \ + { 0xa438, 0xd1ba }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x2529 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0xd0a7 }, \ + { 0xa438, 0xd1b9 }, \ + { 0xa438, 0xa208 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x080e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x408b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a65 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a6b }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0915 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0909 }, \ + { 0xa438, 0x228f }, \ + { 0xa438, 0x8038 }, \ + { 0xa438, 0x9801 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x5d61 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0x2005 }, \ + { 0xa438, 0x091a }, \ + { 0xa438, 0x3bd9 }, \ + { 0xa438, 0x0919 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0916 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14c5 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x3181 }, \ + { 0xa438, 0x8061 }, \ + { 0xa438, 0x60ad }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x5fba }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0cc7 }, \ + { 0xa438, 0xd096 }, \ + { 0xa438, 0xd1a9 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0c94 }, \ + { 0xa438, 0xa802 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0xa801 }, \ + { 0xa438, 0xc004 }, \ + { 0xa438, 0xd710 }, \ + { 0xa438, 0x4000 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1e79 }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0x1e78 }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0x0c93 }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x0cc5 }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x0915 }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x020a }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x155b }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x1542 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x0fc7 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0xff00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6090 }, \ + { 0xa438, 0x60d1 }, \ + { 0xa438, 0xc95c }, \ + { 0xa438, 0xf007 }, \ + { 0xa438, 0x60b1 }, \ + { 0xa438, 0xc95a }, \ + { 0xa438, 0xf004 }, \ + { 0xa438, 0xc956 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xc94e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00cd }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6090 }, \ + { 0xa438, 0x60d1 }, \ + { 0xa438, 0xc95c }, \ + { 0xa438, 0xf007 }, \ + { 0xa438, 0x60b1 }, \ + { 0xa438, 0xc95a }, \ + { 0xa438, 0xf004 }, \ + { 0xa438, 0xc956 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xc94e }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0132 }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x012f }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x00cc }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x0103 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8020 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8035 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0xd107 }, \ + { 0xa438, 0xd042 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x8280 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6065 }, \ + { 0xa438, 0xd125 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd12b }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x077f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c50 }, \ + { 0xa438, 0xd104 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0aa8 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a2e }, \ + { 0xa438, 0xcb9b }, \ + { 0xa438, 0xd110 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b7b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x081b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x7fb8 }, \ + { 0xa438, 0xa718 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x074e }, \ + { 0xa436, 0xa10e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa10c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa10a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa108 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa106 }, \ + { 0xa438, 0x074d }, \ + { 0xa436, 0xa104 }, \ + { 0xa438, 0x0818 }, \ + { 0xa436, 0xa102 }, \ + { 0xa438, 0x0a2c }, \ + { 0xa436, 0xa100 }, \ + { 0xa438, 0x077e }, \ + { 0xa436, 0xa110 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8625 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0x3daf }, \ + { 0xa438, 0x8689 }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x69af }, \ + { 0xa438, 0x8887 }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x9caf }, \ + { 0xa438, 0x889c }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x9caf }, \ + { 0xa438, 0x889c }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x49d7 }, \ + { 0xa438, 0x0040 }, \ + { 0xa438, 0x0277 }, \ + { 0xa438, 0x7daf }, \ + { 0xa438, 0x2727 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7205 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7208 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x71f3 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x71f6 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7229 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x722c }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7217 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x721a }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x721d }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7211 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7220 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7214 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x722f }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7223 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7232 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7226 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfae0 }, \ + { 0xa438, 0x85b3 }, \ + { 0xa438, 0x3802 }, \ + { 0xa438, 0xad27 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x8830 }, \ + { 0xa438, 0x1f66 }, \ + { 0xa438, 0xef65 }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x1f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00da }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x2f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00db }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4202 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1b03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4502 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1a03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4802 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x3f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00da }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x4f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00db }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4b02 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1b03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4e02 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1a03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5102 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef56 }, \ + { 0xa438, 0xd020 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5402 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5702 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5a02 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0xa0ef }, \ + { 0xa438, 0x0348 }, \ + { 0xa438, 0x0a28 }, \ + { 0xa438, 0x05ef }, \ + { 0xa438, 0x201b }, \ + { 0xa438, 0x01ad }, \ + { 0xa438, 0x2735 }, \ + { 0xa438, 0x1f44 }, \ + { 0xa438, 0xe085 }, \ + { 0xa438, 0x88e1 }, \ + { 0xa438, 0x8589 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5d02 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe085 }, \ + { 0xa438, 0x8ee1 }, \ + { 0xa438, 0x858f }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6002 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe085 }, \ + { 0xa438, 0x94e1 }, \ + { 0xa438, 0x8595 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6302 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe085 }, \ + { 0xa438, 0x9ae1 }, \ + { 0xa438, 0x859b }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6602 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x3cbf }, \ + { 0xa438, 0x883f }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x9cad }, \ + { 0xa438, 0x2835 }, \ + { 0xa438, 0x1f44 }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xf8e1 }, \ + { 0xa438, 0x8ff9 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x5d02 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xfae1 }, \ + { 0xa438, 0x8ffb }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6002 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xfce1 }, \ + { 0xa438, 0x8ffd }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6302 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xfee1 }, \ + { 0xa438, 0x8fff }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x6602 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x3ce1 }, \ + { 0xa438, 0x85a1 }, \ + { 0xa438, 0x1b21 }, \ + { 0xa438, 0xad37 }, \ + { 0xa438, 0x341f }, \ + { 0xa438, 0x44e0 }, \ + { 0xa438, 0x858a }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x8bbf }, \ + { 0xa438, 0x885d }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x8590 }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x91bf }, \ + { 0xa438, 0x8860 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x8596 }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x97bf }, \ + { 0xa438, 0x8863 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x859c }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x9dbf }, \ + { 0xa438, 0x8866 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7dae }, \ + { 0xa438, 0x401f }, \ + { 0xa438, 0x44e0 }, \ + { 0xa438, 0x858c }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x8dbf }, \ + { 0xa438, 0x885d }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x8592 }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x93bf }, \ + { 0xa438, 0x8860 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x8598 }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x99bf }, \ + { 0xa438, 0x8863 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7de0 }, \ + { 0xa438, 0x859e }, \ + { 0xa438, 0xe185 }, \ + { 0xa438, 0x9fbf }, \ + { 0xa438, 0x8866 }, \ + { 0xa438, 0x026e }, \ + { 0xa438, 0x7dae }, \ + { 0xa438, 0x0ce1 }, \ + { 0xa438, 0x85b3 }, \ + { 0xa438, 0x3904 }, \ + { 0xa438, 0xac2f }, \ + { 0xa438, 0x04ee }, \ + { 0xa438, 0x85b3 }, \ + { 0xa438, 0x00af }, \ + { 0xa438, 0x39d9 }, \ + { 0xa438, 0x22ac }, \ + { 0xa438, 0xeaf0 }, \ + { 0xa438, 0xacf6 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xfaf0 }, \ + { 0xa438, 0xacf8 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xfcf0 }, \ + { 0xa438, 0xad00 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xfef0 }, \ + { 0xa438, 0xacf0 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xf4f0 }, \ + { 0xa438, 0xacf2 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xb0f0 }, \ + { 0xa438, 0xacae }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xacf0 }, \ + { 0xa438, 0xacaa }, \ + { 0xa438, 0xa100 }, \ + { 0xa438, 0x0ce1 }, \ + { 0xa438, 0x8ff7 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xaf26 }, \ + { 0xa438, 0xe9e1 }, \ + { 0xa438, 0x8ff6 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xaf26 }, \ + { 0xa438, 0xf520 }, \ + { 0xa438, 0xac86 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x3f02 }, \ + { 0xa438, 0x6e9c }, \ + { 0xa438, 0xad28 }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x3324 }, \ + { 0xa438, 0xad38 }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x32e6 }, \ + { 0xa438, 0xaf32 }, \ + { 0xa438, 0xfb00 }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8ff6 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0x0705 }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8ff8 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0x19cc }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8ffa }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0x28e3 }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8ffc }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0x1047 }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8ffe }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0x0a45 }, \ + { 0xa436, 0xb85e }, \ + { 0xa438, 0x271e }, \ + { 0xa436, 0xb860 }, \ + { 0xa438, 0x3846 }, \ + { 0xa436, 0xb862 }, \ + { 0xa438, 0x26e6 }, \ + { 0xa436, 0xb864 }, \ + { 0xa438, 0x32e3 }, \ + { 0xa436, 0xb886 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb888 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb88a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb88c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb838 }, \ + { 0xa438, 0x000f }, \ + { 0xb820, 0x0010 }, \ + { 0xa436, 0x846e }, \ + { 0xa438, 0xaf84 }, \ + { 0xa438, 0x86af }, \ + { 0xa438, 0x8690 }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0xa4af }, \ + { 0xa438, 0x86a4 }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0xa4af }, \ + { 0xa438, 0x86a4 }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0xa4af }, \ + { 0xa438, 0x86a4 }, \ + { 0xa438, 0xee82 }, \ + { 0xa438, 0x5f00 }, \ + { 0xa438, 0x0284 }, \ + { 0xa438, 0x90af }, \ + { 0xa438, 0x0441 }, \ + { 0xa438, 0xf8e0 }, \ + { 0xa438, 0x8ff3 }, \ + { 0xa438, 0xa000 }, \ + { 0xa438, 0x0502 }, \ + { 0xa438, 0x84a4 }, \ + { 0xa438, 0xae06 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0x0302 }, \ + { 0xa438, 0x84c8 }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xef59 }, \ + { 0xa438, 0xe080 }, \ + { 0xa438, 0x15ad }, \ + { 0xa438, 0x2702 }, \ + { 0xa438, 0xae03 }, \ + { 0xa438, 0xaf84 }, \ + { 0xa438, 0xc3bf }, \ + { 0xa438, 0x53ca }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ad }, \ + { 0xa438, 0x2807 }, \ + { 0xa438, 0x0285 }, \ + { 0xa438, 0x2cee }, \ + { 0xa438, 0x8ff3 }, \ + { 0xa438, 0x01ef }, \ + { 0xa438, 0x95fd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfaef }, \ + { 0xa438, 0x69bf }, \ + { 0xa438, 0x53ca }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ac }, \ + { 0xa438, 0x2822 }, \ + { 0xa438, 0xd480 }, \ + { 0xa438, 0x00bf }, \ + { 0xa438, 0x8684 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x8687 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868a }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868d }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9ee }, \ + { 0xa438, 0x8ff3 }, \ + { 0xa438, 0x00af }, \ + { 0xa438, 0x8526 }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xf4e1 }, \ + { 0xa438, 0x8ff5 }, \ + { 0xa438, 0xe28f }, \ + { 0xa438, 0xf6e3 }, \ + { 0xa438, 0x8ff7 }, \ + { 0xa438, 0x1b45 }, \ + { 0xa438, 0xac27 }, \ + { 0xa438, 0x0eee }, \ + { 0xa438, 0x8ff4 }, \ + { 0xa438, 0x00ee }, \ + { 0xa438, 0x8ff5 }, \ + { 0xa438, 0x0002 }, \ + { 0xa438, 0x852c }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x26e0 }, \ + { 0xa438, 0x8ff4 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xf52c }, \ + { 0xa438, 0x0001 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xf4e5 }, \ + { 0xa438, 0x8ff5 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xef59 }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xa18b }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x85da }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x7202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xf8e5 }, \ + { 0xa438, 0x8ff9 }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x7502 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfae5 }, \ + { 0xa438, 0x8ffb }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x7802 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfce5 }, \ + { 0xa438, 0x8ffd }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x7b02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfee5 }, \ + { 0xa438, 0x8fff }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x6c02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xa102 }, \ + { 0xa438, 0x13ee }, \ + { 0xa438, 0x8ffc }, \ + { 0xa438, 0x80ee }, \ + { 0xa438, 0x8ffd }, \ + { 0xa438, 0x00ee }, \ + { 0xa438, 0x8ffe }, \ + { 0xa438, 0x80ee }, \ + { 0xa438, 0x8fff }, \ + { 0xa438, 0x00af }, \ + { 0xa438, 0x8599 }, \ + { 0xa438, 0xa101 }, \ + { 0xa438, 0x0cbf }, \ + { 0xa438, 0x534c }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x0303 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x77bf }, \ + { 0xa438, 0x5322 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x8b02 }, \ + { 0xa438, 0xae03 }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0x64e0 }, \ + { 0xa438, 0x8ff8 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xf9bf }, \ + { 0xa438, 0x8684 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9e0 }, \ + { 0xa438, 0x8ffa }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x8687 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9e0 }, \ + { 0xa438, 0x8ffc }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xfdbf }, \ + { 0xa438, 0x868a }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9e0 }, \ + { 0xa438, 0x8ffe }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xffbf }, \ + { 0xa438, 0x868d }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9af }, \ + { 0xa438, 0x867f }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xa144 }, \ + { 0xa438, 0x3cbf }, \ + { 0xa438, 0x547b }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ff8 }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xf9bf }, \ + { 0xa438, 0x547e }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffa }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x5481 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffc }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xfdbf }, \ + { 0xa438, 0x5484 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffe }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xffbf }, \ + { 0xa438, 0x5322 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x4448 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0xa7bf }, \ + { 0xa438, 0x5322 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x313c }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x7b02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xf8e5 }, \ + { 0xa438, 0x8ff9 }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x7e02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfae5 }, \ + { 0xa438, 0x8ffb }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x8102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfce5 }, \ + { 0xa438, 0x8ffd }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfee5 }, \ + { 0xa438, 0x8fff }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xa131 }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x85a7 }, \ + { 0xa438, 0xd480 }, \ + { 0xa438, 0x00bf }, \ + { 0xa438, 0x8684 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x8687 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868a }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868d }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9ef }, \ + { 0xa438, 0x95fd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf0d1 }, \ + { 0xa438, 0x2af0 }, \ + { 0xa438, 0xd12c }, \ + { 0xa438, 0xf0d1 }, \ + { 0xa438, 0x44f0 }, \ + { 0xa438, 0xd146 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xa102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xa102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xd101 }, \ + { 0xa438, 0xaf06 }, \ + { 0xa438, 0xa570 }, \ + { 0xa438, 0xce42 }, \ + { 0xa436, 0xb818 }, \ + { 0xa438, 0x043d }, \ + { 0xa436, 0xb81a }, \ + { 0xa438, 0x06a3 }, \ + { 0xa436, 0xb81c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb81e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb850 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb852 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb884 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb832 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x0000 }, \ + { 0xb820, 0x0000 }, \ + { 0xa436, 0x801e }, \ + { 0xa438, 0x0019 }