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fix a few missed style corrections in BeceemCPU; style cleanup in BeceemDDR; no functional change

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@40850 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-03-06 18:26:19 +00:00
parent 1687edd0fd
commit 4b7b79d52f
4 changed files with 1008 additions and 1028 deletions
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src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
+14 -22
View File
@@ -43,11 +43,10 @@ BeceemCPU::CPURun()
} }
// Adjust clock register contents to start cpu // Adjust clock register contents to start cpu
if (fWmxDevice->CPUFlashBoot) { if (fWmxDevice->CPUFlashBoot)
clockRegister &= (~(1<<30)); clockRegister &= ~(1 << 30);
} else { else
clockRegister |= (1 << 30); clockRegister |= (1 << 30);
}
// Write new clock register contents // Write new clock register contents
if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1, if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
@@ -66,8 +65,7 @@ BeceemCPU::CPUReset()
unsigned int value = 0; unsigned int value = 0;
unsigned int uiResetValue = 0; unsigned int uiResetValue = 0;
if (fWmxDevice->deviceChipID >= T3LPB) if (fWmxDevice->deviceChipID >= T3LPB) {
{
BizarroReadRegister(SYS_CFG, sizeof(value), &value); BizarroReadRegister(SYS_CFG, sizeof(value), &value);
BizarroReadRegister(SYS_CFG, sizeof(value), &value); BizarroReadRegister(SYS_CFG, sizeof(value), &value);
// SYS_CFG register is write protected hence for modifying // SYS_CFG register is write protected hence for modifying
@@ -85,23 +83,20 @@ BeceemCPU::CPUReset()
} }
/* Reset the UMA-B Device */ /* Reset the UMA-B Device */
if (fWmxDevice->deviceChipID >= T3LPB) if (fWmxDevice->deviceChipID >= T3LPB) {
{
// Reset UMA-B // Reset UMA-B
// TODO : USB reset needs implimented // TODO : USB reset needs implimented
/* /*
if (usb_reset_device(psIntfAdapter->udev) != B_OK) if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
{
TRACE_ALWAYS("Error: USB Reset failed\n"); TRACE_ALWAYS("Error: USB Reset failed\n");
retrun B_ERROR; retrun B_ERROR;
} }
*/ */
if (fWmxDevice->deviceChipID == BCS220_2 || if (fWmxDevice->deviceChipID == BCS220_2
fWmxDevice->deviceChipID == BCS220_2BC || || fWmxDevice->deviceChipID == BCS220_2BC
fWmxDevice->deviceChipID == BCS250_BC || || fWmxDevice->deviceChipID == BCS250_BC
fWmxDevice->deviceChipID == BCS220_3) || fWmxDevice->deviceChipID == BCS220_3) {
{
if (BizarroReadRegister(HPM_CONFIG_LDO145, if (BizarroReadRegister(HPM_CONFIG_LDO145,
sizeof(value), &value) != B_OK) { sizeof(value), &value) != B_OK) {
TRACE_ALWAYS("Error: USB read failed during reset\n"); TRACE_ALWAYS("Error: USB read failed during reset\n");
@@ -120,8 +115,7 @@ BeceemCPU::CPUReset()
} }
// TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048 // TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
if (fWmxDevice->CPUFlashBoot) if (fWmxDevice->CPUFlashBoot) {
{
// In flash boot mode MIPS state register has reverse polarity. // In flash boot mode MIPS state register has reverse polarity.
// So just or with setting bit 30. // So just or with setting bit 30.
// Make the MIPS in Reset state. // Make the MIPS in Reset state.
@@ -140,17 +134,15 @@ BeceemCPU::CPUReset()
} }
} }
if (fWmxDevice->deviceChipID >= T3LPB) if (fWmxDevice->deviceChipID >= T3LPB) {
{
uiResetValue = 0; uiResetValue = 0;
// WA for SYSConfig Issue. // WA for SYSConfig Issue.
BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue); BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
if (uiResetValue & (1<<4)) if (uiResetValue & (1 << 4)) {
{
uiResetValue = 0; uiResetValue = 0;
BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue); BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
// Read SYSCFG Twice to make it writable. // Read SYSCFG Twice to make it writable.
uiResetValue &= (~(1<<4)); uiResetValue &= ~(1 << 4);
if (BizarroWriteRegister(SYS_CFG, if (BizarroWriteRegister(SYS_CFG,
sizeof(uiResetValue), &uiResetValue) != B_OK) { sizeof(uiResetValue), &uiResetValue) != B_OK) {
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h
+1 -3
View File
@@ -16,9 +16,7 @@
#define CLOCK_RESET_CNTRL_REG_1 0x0F00000C #define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
class BeceemCPU class BeceemCPU {
{
public: public:
BeceemCPU(); BeceemCPU();
status_t CPUInit(WIMAX_DEVICE* swmxdevice); status_t CPUInit(WIMAX_DEVICE* swmxdevice);
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
+76 -105
View File
@@ -9,8 +9,8 @@
*/ */
#include "Settings.h"
#include "BeceemDDR.h" #include "BeceemDDR.h"
#include "Settings.h"
BeceemDDR::BeceemDDR() BeceemDDR::BeceemDDR()
@@ -22,65 +22,56 @@ BeceemDDR::BeceemDDR()
status_t status_t
BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice) BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
{ {
pwmxdevice = swmxdevice; fWmxDevice = swmxdevice;
PDDR_SETTING psDDRSetting = NULL; PDDR_SETTING psDDRSetting = NULL;
unsigned int HostDrvrConfig6 = pwmxdevice->vendorcfg.HostDrvrConfig6; unsigned int chipID = fWmxDevice->deviceChipID;
unsigned int uiHostDrvrCfg6 = 0;
unsigned int ChipID = pwmxdevice->deviceChipID;
unsigned long RegCount=0; unsigned long registerCount = 0;
unsigned long value = 0; unsigned long value = 0;
unsigned int uiResetValue = 0; unsigned int uiResetValue = 0;
unsigned int uiClockSetting = 0; unsigned int uiClockSetting = 0;
int retval = B_OK; int retval = B_OK;
unsigned int DDRSetting = 0; // Grab the Config6 metric from the vendor config and convert endianness
bool PmuMode = 0; unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
bool MipsConfig = 0; vendorConfig6raw &= ~(htonl(1 << 15));
bool PLLConfig = 0; unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
HostDrvrConfig6 &= ~(htonl(1 << 15)); // Read our vendor provided Config6 metric and populate memory settings
uiHostDrvrCfg6 = ntohl(HostDrvrConfig6); unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
DDRSetting = (ntohl(HostDrvrConfig6) >>8)&0x0F ; switch (chipID) {
PmuMode = (uiHostDrvrCfg6>>24)&0x03;
MipsConfig = (uiHostDrvrCfg6>>20)&0x01;
PLLConfig = (uiHostDrvrCfg6>>19)&0x01;
switch (ChipID)
{
case 0xbece3200: case 0xbece3200:
switch (DDRSetting) switch (vendorDDRSetting) {
{
case DDR_80_MHZ: case DDR_80_MHZ:
psDDRSetting = asT3LP_DDRSetting80MHz; psDDRSetting = asT3LP_DDRSetting80MHz;
RegCount=(sizeof(asT3LP_DDRSetting80MHz)/ registerCount = sizeof(asT3LP_DDRSetting80MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_100_MHZ: case DDR_100_MHZ:
psDDRSetting = asT3LP_DDRSetting100MHz; psDDRSetting = asT3LP_DDRSetting100MHz;
RegCount=(sizeof(asT3LP_DDRSetting100MHz)/ registerCount = sizeof(asT3LP_DDRSetting100MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_133_MHZ: case DDR_133_MHZ:
psDDRSetting = asT3LP_DDRSetting133MHz; psDDRSetting = asT3LP_DDRSetting133MHz;
RegCount=(sizeof(asT3LP_DDRSetting133MHz)/ registerCount = sizeof(asT3LP_DDRSetting133MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
if(MipsConfig == MIPS_200_MHZ)
{ if (vendorMipsConfig == MIPS_200_MHZ)
uiClockSetting = 0x03F13652; uiClockSetting = 0x03F13652;
}
else else
{
uiClockSetting = 0x03F1365B; uiClockSetting = 0x03F1365B;
}
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
break; break;
case T3LPB: case T3LPB:
case BCS220_2: case BCS220_2:
case BCS220_2BC: case BCS220_2BC:
@@ -88,10 +79,9 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
case BCS220_3 : case BCS220_3 :
// We need to check current value and additionally set bit 2 and // We need to check current value and additionally set bit 2 and
// bit 6 to 1 for BBIC 2mA drive // bit 6 to 1 for BBIC 2mA drive
if( (ChipID != BCS220_2) && if ((chipID != BCS220_2)
(ChipID != BCS220_2BC) && && (chipID != BCS220_2BC)
(ChipID != BCS220_3) ) && (chipID != BCS220_3)) {
{
retval = BizarroReadRegister((unsigned int)0x0f000830, retval = BizarroReadRegister((unsigned int)0x0f000830,
sizeof(uiResetValue), &uiResetValue); sizeof(uiResetValue), &uiResetValue);
@@ -109,48 +99,42 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval; return retval;
} }
} }
switch(DDRSetting)
{ switch(vendorDDRSetting) {
case DDR_80_MHZ: case DDR_80_MHZ:
TRACE("Debug: DDR 80MHz\n"); TRACE("Debug: DDR 80MHz\n");
psDDRSetting = asT3LPB_DDRSetting80MHz; psDDRSetting = asT3LPB_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/ registerCount = sizeof(asT3B_DDRSetting80MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_100_MHZ: case DDR_100_MHZ:
TRACE("Debug: DDR 100MHz\n"); TRACE("Debug: DDR 100MHz\n");
psDDRSetting = asT3LPB_DDRSetting100MHz; psDDRSetting = asT3LPB_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/ registerCount = sizeof(asT3B_DDRSetting100MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_133_MHZ: case DDR_133_MHZ:
TRACE("Debug: DDR 133MHz\n"); TRACE("Debug: DDR 133MHz\n");
psDDRSetting = asT3LPB_DDRSetting133MHz; psDDRSetting = asT3LPB_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/ registerCount = sizeof(asT3B_DDRSetting133MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
if(MipsConfig == MIPS_200_MHZ) if (vendorMipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F13652; uiClockSetting = 0x03F13652;
}
else else
{
uiClockSetting = 0x03F1365B; uiClockSetting = 0x03F1365B;
}
break; break;
case DDR_160_MHZ: case DDR_160_MHZ:
TRACE("Debug: DDR 160MHz\n"); TRACE("Debug: DDR 160MHz\n");
psDDRSetting = asT3LPB_DDRSetting160MHz; psDDRSetting = asT3LPB_DDRSetting160MHz;
RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING); registerCount = sizeof(asT3LPB_DDRSetting160MHz)
/ sizeof(DDR_SETTING);
if(MipsConfig == MIPS_200_MHZ) if (vendorMipsConfig == MIPS_200_MHZ) {
{
TRACE("Debug: MIPS 200Mhz\n"); TRACE("Debug: MIPS 200Mhz\n");
uiClockSetting = 0x03F137D2; uiClockSetting = 0x03F137D2;
} } else {
else
{
uiClockSetting = 0x03F137DB; uiClockSetting = 0x03F137DB;
} }
} }
@@ -161,108 +145,97 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
case 0xbece0121: case 0xbece0121:
case 0xbece0130: case 0xbece0130:
case 0xbece0300: case 0xbece0300:
switch (DDRSetting) switch (vendorDDRSetting) {
{
case DDR_80_MHZ: case DDR_80_MHZ:
psDDRSetting = asT3_DDRSetting80MHz; psDDRSetting = asT3_DDRSetting80MHz;
RegCount = (sizeof(asT3_DDRSetting80MHz)/ registerCount = sizeof(asT3_DDRSetting80MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_100_MHZ: case DDR_100_MHZ:
psDDRSetting = asT3_DDRSetting100MHz; psDDRSetting = asT3_DDRSetting100MHz;
RegCount = (sizeof(asT3_DDRSetting100MHz)/ registerCount = sizeof(asT3_DDRSetting100MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_133_MHZ: case DDR_133_MHZ:
psDDRSetting = asT3_DDRSetting133MHz; psDDRSetting = asT3_DDRSetting133MHz;
RegCount = (sizeof(asT3_DDRSetting133MHz)/ registerCount = sizeof(asT3_DDRSetting133MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
case 0xbece0310: case 0xbece0310:
{ {
switch (DDRSetting) switch (vendorDDRSetting) {
{
case DDR_80_MHZ: case DDR_80_MHZ:
psDDRSetting = asT3B_DDRSetting80MHz; psDDRSetting = asT3B_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/ registerCount = sizeof(asT3B_DDRSetting80MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_100_MHZ: case DDR_100_MHZ:
psDDRSetting = asT3B_DDRSetting100MHz; psDDRSetting = asT3B_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/ registerCount = sizeof(asT3B_DDRSetting100MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
break; break;
case DDR_133_MHZ: case DDR_133_MHZ:
if(PLLConfig == PLL_266_MHZ)//266Mhz PLL selected. if (vendorPLLConfig == PLL_266_MHZ) {
{ // 266Mhz PLL selected.
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ, memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
sizeof(asDPLL_266MHZ)); sizeof(asDPLL_266MHZ));
psDDRSetting = asT3B_DDRSetting133MHz; psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/ registerCount = sizeof(asT3B_DDRSetting133MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
}
else } else {
{
psDDRSetting = asT3B_DDRSetting133MHz; psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/ registerCount = sizeof(asT3B_DDRSetting133MHz)
sizeof(DDR_SETTING)); / sizeof(DDR_SETTING);
if(MipsConfig == MIPS_200_MHZ)
{ if (vendorMipsConfig == MIPS_200_MHZ)
uiClockSetting = 0x07F13652; uiClockSetting = 0x07F13652;
}
else else
{
uiClockSetting = 0x07F1365B; uiClockSetting = 0x07F1365B;
} }
}
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
break; break;
} }
default: default:
return -EINVAL; return -EINVAL;
} }
value = 0; value = 0;
TRACE("Debug: Register count is %lu\n", RegCount); TRACE("Debug: Register count is %lu\n", registerCount);
while(RegCount && !retval) while (registerCount && !retval) {
{
if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG) if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
{
value = uiClockSetting; value = uiClockSetting;
}
else else
{
value = psDDRSetting->ulRegValue; value = psDDRSetting->ulRegValue;
}
retval = BizarroWriteRegister(psDDRSetting->ulRegAddress, retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
sizeof(value), (unsigned int*)&value); sizeof(value), (unsigned int*)&value);
if (B_OK != retval) { if (B_OK != retval) {
TRACE_ALWAYS( TRACE_ALWAYS(
"%s:%d BizarroWriteRegister failed at 0x%x on Register #%d.\n", "%s:%d BizarroWriteRegister failed at 0x%x on Register #%d.\n",
__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress, RegCount); __FUNCTION__, __LINE__, psDDRSetting->ulRegAddress,
registerCount);
break; break;
} }
RegCount--; registerCount--;
psDDRSetting++; psDDRSetting++;
} }
if(ChipID >= 0xbece3300 ) if (chipID >= 0xbece3300) {
{
snooze(3); snooze(3);
if( (ChipID != BCS220_2)&& if ((chipID != BCS220_2)
(ChipID != BCS220_2BC)&& && (chipID != BCS220_2BC)
(ChipID != BCS220_3)) && (chipID != BCS220_3)) {
{
/* drive MDDR to half in case of UMA-B: */ /* drive MDDR to half in case of UMA-B: */
uiResetValue = 0x01010001; uiResetValue = 0x01010001;
retval = BizarroWriteRegister((unsigned int)0x0F007018, retval = BizarroWriteRegister((unsigned int)0x0F007018,
@@ -310,8 +283,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
* UMA-B chip id. we will change this when we will have an * UMA-B chip id. we will change this when we will have an
* internal PMU. * internal PMU.
*/ */
if(PmuMode == HYBRID_MODE_7C) if (vendorPmuMode == HYBRID_MODE_7C) {
{
TRACE("Debug: Hybrid Power Mode 7C\n"); TRACE("Debug: Hybrid Power Mode 7C\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00, retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue); sizeof(uiResetValue), &uiResetValue);
@@ -358,9 +330,8 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
__FUNCTION__, __LINE__); __FUNCTION__, __LINE__);
return retval; return retval;
} }
} } else if (vendorPmuMode == HYBRID_MODE_6) {
else if(PmuMode == HYBRID_MODE_6 )
{
TRACE("Debug: Hybrid Power Mode 6\n"); TRACE("Debug: Hybrid Power Mode 6\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00, retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue); sizeof(uiResetValue), &uiResetValue);
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h
+104 -85
View File
@@ -7,14 +7,14 @@
* *
* Description: Wrangle Beceem volatile DDR memory. * Description: Wrangle Beceem volatile DDR memory.
*/ */
#ifndef _USB_BECEEM_DDR_H_ #ifndef _USB_BECEEM_DDR_H_
#define _USB_BECEEM_DDR_H_ #define _USB_BECEEM_DDR_H_
#include <ByteOrder.h>
#include <ByteOrder.h>
#include "DeviceStruct.h" #include "DeviceStruct.h"
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00 #define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820 #define MIPS_CLOCK_REG 0x0f000820
@@ -32,20 +32,25 @@
#define DDR_180_MHZ 6 // Not Used (Reserved for future) #define DDR_180_MHZ 6 // Not Used (Reserved for future)
#define DDR_200_MHZ 7 // Not Used (Reserved for future) #define DDR_200_MHZ 7 // Not Used (Reserved for future)
class BeceemDDR
{
class BeceemDDR {
public: public:
WIMAX_DEVICE* pwmxdevice;
BeceemDDR(); BeceemDDR();
status_t DDRInit(WIMAX_DEVICE* swmxdevice); status_t DDRInit(WIMAX_DEVICE* swmxdevice);
WIMAX_DEVICE* fWmxDevice;
// yuck. These are in a child class class // yuck. These are in a child class class
virtual status_t ReadRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; }; virtual status_t ReadRegister(unsigned int reg, size_t size,
virtual status_t WriteRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; }; uint32_t* buffer) { return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; }; virtual status_t WriteRegister(unsigned int reg, size_t size,
virtual status_t BizarroWriteRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; }; uint32_t* buffer) { return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
{ return NULL; };
virtual status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
{ return NULL; };
}; };
@@ -60,26 +65,29 @@ typedef enum ePMU_MODES
HYBRID_MODE_6 = 2 HYBRID_MODE_6 = 2
}PMU_MODE; }PMU_MODE;
/* /*
* DDR Init maps, taken from Beceem GPL Linux Driver * DDR Init maps, taken from Beceem GPL Linux Driver
*/ */
typedef struct _DDR_SETTING typedef struct _DDR_SETTING
{ {
unsigned long ulRegAddress; unsigned long ulRegAddress;
unsigned long ulRegValue; unsigned long ulRegValue;
} DDR_SETTING, *PDDR_SETTING; } DDR_SETTING, *PDDR_SETTING;
typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE; typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
//DDR INIT-133Mhz
// DDR INIT 133Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000 #define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007212}, {0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF}, {0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF1B00}, {0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002}, {0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
@@ -99,13 +107,13 @@ static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007}, {0x0F007024, 0x02000007},
{0x0F007028, 0x02020202}, {0x0F007028, 0x02020202},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000}, {0x0F007030, 0x05000000},
{0x0F007034, 0x00000003}, {0x0F007034, 0x00000003},
{0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x110a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018}, {0x0F00703C, 0x02101010}, // ROB - 0x02101010, 0x02101018},
{0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200}, {0x0F007040, 0x45751200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x110a0d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x081b0306}, {0x0F007048, 0x081b0306},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c}, {0x0F007050, 0x0000001c},
@@ -124,14 +132,16 @@ static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007084, 0x00000000}, {0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller // # Enable BW improvement within memory controller
{0x0F007094, 0x00000104}, {0x0F007094, 0x00000104},
//# Enable 2 ports within X-bar // # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
// # Enable start bit within memory controller // # Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
// 80Mhz // 80Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000 #define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000820, 0x07f1ffff}, {0x0f000820, 0x07f1ffff},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
@@ -178,18 +188,20 @@ static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0F007080, 0x00000000}, {0x0F007080, 0x00000000},
{0x0F007084, 0x00000000}, {0x0F007084, 0x00000000},
{0x0F007094, 0x00000104}, {0x0F007094, 0x00000104},
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
// 100Mhz // 100Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000 #define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007008}, {0x0F000800, 0x00007008},
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13E3F}, {0x0f000820, 0x07F13E3F},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
// 0x0f000840, 0x0FFF1800, // 0x0f000840, 0x0FFF1800,
{0x0f000840, 0x0FFF1B00}, {0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002}, {0x0f000870, 0x00000002},
@@ -198,7 +210,7 @@ static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F00a084, 0x1Cffffff}, {0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C}, {0x0F00a04C, 0x0000000C},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
// Memcontroller Default values // Memcontroller Default values
{0x0F007000, 0x00010001}, {0x0F007000, 0x00010001},
@@ -235,14 +247,15 @@ static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F00707C, 0x00000000}, {0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000}, {0x0F007080, 0x00000000},
{0x0F007084, 0x00000000}, {0x0F007084, 0x00000000},
//# Enable BW improvement within memory controller // Enable BW improvement within memory controller
{0x0F007094, 0x00000104}, {0x0F007094, 0x00000104},
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
// Net T3B DDR Settings // Net T3B DDR Settings
//DDR INIT-133Mhz // DDR INIT 133Mhz
static DDR_SET_NODE asDPLL_266MHZ[] = { static DDR_SET_NODE asDPLL_266MHZ[] = {
{0x0F000800, 0x00007212}, {0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF}, {0x0f000820, 0x07F13FFF},
@@ -253,6 +266,8 @@ static DDR_SET_NODE asDPLL_266MHZ[] = {
{0x0f000840, 0x0FFF1B00}, {0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002} {0x0f000870, 0x00000002}
}; };
#if 0 #if 0
static DDR_SET_NODE asDPLL_800MHZ[] = { static DDR_SET_NODE asDPLL_800MHZ[] = {
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
@@ -265,22 +280,23 @@ static DDR_SET_NODE asDPLL_800MHZ[] = {
}; };
#endif #endif
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13652}, {0x0f000820, 0x07F13652},
{0x0f000840, 0x0FFF0800}, {0x0f000840, 0x0FFF0800},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff}, {0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
// Memcontroller Default values // Memcontroller Default values
{0x0F007000, 0x00010001}, {0x0F007000, 0x00010001},
@@ -294,13 +310,13 @@ static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007}, {0x0F007024, 0x02000007},
{0x0F007028, 0x02020202}, {0x0F007028, 0x02020202},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000}, {0x0F007030, 0x05000000},
{0x0F007034, 0x00000003}, {0x0F007034, 0x00000003},
{0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x130a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018}, {0x0F00703C, 0x02101012}, // ROB - 0x02101010, 0x02101018},
{0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200}, {0x0F007040, 0x457D1200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x11130d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x040D0306}, {0x0F007048, 0x040D0306},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c}, {0x0F007050, 0x0000001c},
@@ -323,8 +339,9 @@ static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
{0x0F007018, 0x01010000}, {0x0F007018, 0x01010000},
}; };
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13FFF}, {0x0f000820, 0x07F13FFF},
{0x0f000840, 0x0FFF1F00}, {0x0f000840, 0x0FFF1F00},
@@ -372,13 +389,14 @@ static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
{0x0F007080, 0x00000000}, {0x0F007080, 0x00000000},
{0x0F007084, 0x00000000}, {0x0F007084, 0x00000000},
{0x0F007094, 0x00000104}, {0x0F007094, 0x00000104},
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
// 100Mhz // 100Mhz
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95}, {0x0f000810, 0x00000F95},
{0x0f000820, 0x07F1369B}, {0x0f000820, 0x07F1369B},
{0x0f000840, 0x0FFF0800}, {0x0f000840, 0x0FFF0800},
@@ -388,7 +406,7 @@ static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff}, {0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
// Memcontroller Default values // Memcontroller Default values
{0x0F007000, 0x00010001}, {0x0F007000, 0x00010001},
@@ -433,11 +451,11 @@ static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LP_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000820, 0x03F1365B}, {0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95}, {0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000}, {0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
@@ -457,13 +475,13 @@ static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007}, {0x0F007024, 0x02000007},
{0x0F007028, 0x02020200}, {0x0F007028, 0x02020200},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000}, {0x0F007030, 0x05000000},
{0x0F007034, 0x00000003}, {0x0F007034, 0x00000003},
{0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x200a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018, {0x0F00703C, 0x02101020}, // ROB - 0x02101010, 0x02101018,
{0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200, {0x0F007040, 0x45711200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x110D0D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306}, {0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c}, {0x0F007050, 0x0100001c},
@@ -483,15 +501,16 @@ static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007088, 0x01000001}, {0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101}, {0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000}, {0x0F007090, 0x00000000},
//# Enable BW improvement within memory controller // Enable BW improvement within memory controller
{0x0F007094, 0x00040000}, {0x0F007094, 0x00040000},
{0x0F007098, 0x00000000}, {0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104}, {0x0F0070c8, 0x00000104},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95}, {0x0f000810, 0x00002F95},
@@ -499,7 +518,7 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000840, 0x0fff0000}, {0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000}, {0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
@@ -517,13 +536,13 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007}, {0x0F007024, 0x00000007},
{0x0F007028, 0x01020200}, {0x0F007028, 0x01020200},
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000}, {0x0F007030, 0x06000000},
{0x0F007034, 0x00000004}, {0x0F007034, 0x00000004},
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018, {0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200, {0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305}, {0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c}, {0x0F007050, 0x0100001c},
@@ -546,12 +565,13 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F007094, 0x00010000}, {0x0F007094, 0x00010000},
{0x0F007098, 0x00000000}, {0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104}, {0x0F0070C8, 0x00000104},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x07F13FFF}, {0x0f000820, 0x07F13FFF},
@@ -608,13 +628,9 @@ static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
}; };
// T3 LP-B (UMA-B)
///T3 LP-B (UMA-B)
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F137DB}, {0x0f000820, 0x03F137DB},
{0x0f000810, 0x01842795}, {0x0f000810, 0x01842795},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
@@ -622,7 +638,7 @@ static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
{0x0f000840, 0x0FFF0400}, {0x0f000840, 0x0FFF0400},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory {0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
@@ -675,12 +691,12 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F1365B}, {0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95}, {0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000}, {0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
@@ -696,13 +712,13 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007}, {0x0F007024, 0x02000007},
{0x0F007028, 0x02020200}, {0x0F007028, 0x02020200},
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000}, {0x0F007030, 0x05000000},
{0x0F007034, 0x00000003}, {0x0F007034, 0x00000003},
{0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x190a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018, {0x0F00703C, 0x02101017}, // ROB - 0x02101010, 0x02101018,
{0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200, {0x0F007040, 0x45171200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x11290D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306}, {0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c}, {0x0F007050, 0x0100001c},
@@ -722,15 +738,16 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0F007088, 0x01000001}, {0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101}, {0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000}, {0x0F007090, 0x00000000},
//# Enable BW improvement within memory controller // Enable BW improvement within memory controller
{0x0F007094, 0x00040000}, {0x0F007094, 0x00040000},
{0x0F007098, 0x00000000}, {0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104}, {0x0F0070c8, 0x00000104},
//# Enable 2 ports within X-bar // Enable 2 ports within Xbar
//# Enable start bit within memory controller // Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95}, {0x0f000810, 0x00002F95},
@@ -738,11 +755,11 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000840, 0x0fff0000}, {0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD}, {0x0f000880, 0x000003DD},
// Changed source for X-bar and MIPS clock to APLL // Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000}, {0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
// Memcontroller Default values // Memcontroller Default values
@@ -757,13 +774,13 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107 {0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007}, {0x0F007024, 0x00000007},
{0x0F007028, 0x01020200}, {0x0F007028, 0x01020200},
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a {0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000}, {0x0F007030, 0x06000000},
{0x0F007034, 0x00000004}, {0x0F007034, 0x00000004},
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200 {0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018, {0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200, {0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00 {0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305}, {0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000}, {0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c}, {0x0F007050, 0x0100001c},
@@ -786,14 +803,15 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0F007094, 0x00010000}, {0x0F007094, 0x00010000},
{0x0F007098, 0x00000000}, {0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104}, {0x0F0070C8, 0x00000104},
//# Enable 2 ports within X-bar // # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
// # Enable start bit within memory controller // # Enable start bit within memory controller
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000820, 0x07F13FFF}, {0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95}, {0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000}, {0x0f000860, 0x00000000},
@@ -801,7 +819,7 @@ static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000840, 0x0FFF1F00}, {0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff}, {0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000}, {0x0F00a040, 0x1f000000},
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz {0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory {0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000}, {0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016}, {0x0F00A000, 0x00000016},
@@ -848,5 +866,6 @@ static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0F007018, 0x01010000} {0x0F007018, 0x01010000}
}; };
#endif // _USB_BECEEM_DDR_H_ #endif // _USB_BECEEM_DDR_H_