changed pci to gPci, plus some clean

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22309 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
2007-09-25 17:41:26 +00:00
parent 2b14cdd11c
commit 4d97d99317
2 changed files with 14 additions and 17 deletions
@@ -32,7 +32,7 @@ status_t fwohci_pci_detach(int index);
pci_info *pciInfo[MAX_CARDS];
fwohci_softc_t *gFwohci_softc[MAX_CARDS];
struct firewire_softc *gFirewire_softc[MAX_CARDS];
pci_module_info *pci;
pci_module_info *gPci;
dpc_module_info *gDpc;
struct supported_device{
@@ -74,7 +74,8 @@ struct supported_device supported_devices[] = {
};
static int find_device_name(pci_info *info)
static int
find_device_name(pci_info *info)
{
struct supported_device *device;
for (device = supported_devices; device->name; device++) {
@@ -148,7 +149,7 @@ fw_module_init(void)
if (!info)
return B_NO_MEMORY;
if ((status = get_module(B_PCI_MODULE_NAME,(module_info **)&pci)) != B_OK) {
if ((status = get_module(B_PCI_MODULE_NAME,(module_info **)&gPci)) != B_OK) {
TRACE("pci module unavailable\n");
free(info);
return status;
@@ -164,7 +165,7 @@ fw_module_init(void)
memset(gFwohci_softc, 0, sizeof(gFwohci_softc));
// find devices
for (i = 0, found = 0; (status = pci->get_nth_pci_info(i, info)) == B_OK; i++) {
for (i = 0, found = 0; (status = gPci->get_nth_pci_info(i, info)) == B_OK; i++) {
if (find_device_name(info)
|| ((info->class_base == PCI_serial_bus)
&& (info->class_sub == PCI_firewire)
@@ -203,9 +204,6 @@ fw_module_init(void)
TRACE("found %d cards\n", found);
free(info);
// if (!found)
// goto err_found;
if ((status = initialize_timer()) != B_OK) {
ERROR("timer init failed\n");
goto err_timer;
@@ -222,7 +220,6 @@ fw_module_init(void)
err_pci:
terminate_timer();
err_timer:
err_found:
err_outofmem:
for (i = 0; i < found; i++) {
free(gFirewire_softc[i]);
@@ -61,7 +61,7 @@
#define PCIM_CMD_BUSMASTEREN 0x0004
#define PCIM_CMD_MWRICEN 0x0010
#define PCIM_CMD_IOS 0x0001
extern pci_module_info *pci;
extern pci_module_info *gPci;
extern pci_info *pciInfo[MAX_CARDS];
extern fwohci_softc_t *gFwohci_softc[MAX_CARDS];
extern struct firewire_softc *gFirewire_softc[MAX_CARDS];
@@ -143,14 +143,14 @@ fwohci_pci_attach(int index)
mtx_init(FW_GMTX(&sc->fc), "firewire", NULL, MTX_DEF);
val = pci->read_pci_config(info->bus, info->device, info->function,
val = gPci->read_pci_config(info->bus, info->device, info->function,
PCI_command, 2);
val |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
#if 1 /* for broken hardware */
val &= ~PCIM_CMD_MWRICEN;
#endif
pci->write_pci_config(info->bus, info->device, info->function,
gPci->write_pci_config(info->bus, info->device, info->function,
PCI_command, 2, val);
/*
@@ -161,28 +161,28 @@ fwohci_pci_attach(int index)
info->u.h0.interrupt_pin == 0)
info->u.h0.interrupt_pin = 3;
latency = olatency = pci->read_pci_config(info->bus, info->device, info->function,
latency = olatency = gPci->read_pci_config(info->bus, info->device, info->function,
PCI_latency, 1);
#define DEF_LATENCY 0x20
if (olatency < DEF_LATENCY) {
latency = DEF_LATENCY;
pci->write_pci_config(info->bus, info->device, info->function,
gPci->write_pci_config(info->bus, info->device, info->function,
PCI_latency, 1, latency);
}
cache_line = ocache_line = pci->read_pci_config(info->bus, info->device,
cache_line = ocache_line = gPci->read_pci_config(info->bus, info->device,
info->function, PCI_line_size, 1);
#define DEF_CACHE_LINE 8
if (ocache_line < DEF_CACHE_LINE) {
cache_line = DEF_CACHE_LINE;
pci->write_pci_config(info->bus, info->device, info->function,
gPci->write_pci_config(info->bus, info->device, info->function,
PCI_line_size, 1, cache_line);
}
TRACE("latency timer %x -> %x.\n", olatency, latency);
TRACE("cache size %x -> %x.\n", ocache_line, cache_line);
// get IRQ
sc->irq = pci->read_pci_config(info->bus, info->device, info->function,
sc->irq = gPci->read_pci_config(info->bus, info->device, info->function,
PCI_interrupt_line, 1);
if (sc->irq == 0 || sc->irq == 0xff) {
ERROR("no IRQ assigned\n");
@@ -191,7 +191,7 @@ fwohci_pci_attach(int index)
TRACE("IRQ %d\n", sc->irq);
// map registers into memory
// val = pci->read_pci_config(info->bus, info->device, info->function, 0x14, 4);
// val = gPci->read_pci_config(info->bus, info->device, info->function, 0x14, 4);
// val &= PCI_address_memory_32_mask;
// TRACE("hardware register address %p\n", (void *) val);
TRACE("hardware register address %x\n", info->u.h0.base_registers[0]);