From 4ee41b26a00408835f410ee25b3241093c7f40d9 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <kallisti5@unixzen.com>
Date: Wed, 22 Feb 2012 06:31:53 -0600
Subject: [PATCH] radeon_hd: Disable spread spectrum

* SS requires complex pll adjustments that we don't do atm
---
 .../accelerants/radeon_hd/accelerant.cpp      |  3 ++
 src/add-ons/accelerants/radeon_hd/gpu.cpp     | 33 +++++++++++++++++++
 src/add-ons/accelerants/radeon_hd/gpu.h       |  1 +
 3 files changed, 37 insertions(+)

diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.cpp b/src/add-ons/accelerants/radeon_hd/accelerant.cpp
index 9fd4da4713..a77847517d 100644
--- a/src/add-ons/accelerants/radeon_hd/accelerant.cpp
+++ b/src/add-ons/accelerants/radeon_hd/accelerant.cpp
@@ -263,6 +263,9 @@ radeon_init_accelerant(int device)
 
 	radeon_init_bios(gInfo->rom);
 
+	// disable spread spectrum as it requires lots of extra calculations
+	radeon_gpu_ss_disable();
+
 	// find GPIO pins from AtomBIOS
 	gpio_probe();
 
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp b/src/add-ons/accelerants/radeon_hd/gpu.cpp
index fa26593b1f..3d3829e498 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.cpp
+++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp
@@ -524,3 +524,36 @@ radeon_gpu_irq_setup()
 
 	return B_ERROR;
 }
+
+
+status_t
+radeon_gpu_ss_disable()
+{
+	TRACE("%s called\n", __func__);
+
+	radeon_shared_info &info = *gInfo->shared_info;
+	uint32 ssControl;
+
+	if (info.chipsetID >= RADEON_CEDAR) {
+		// PLL1
+		ssControl = Read32(OUT, EVERGREEN_P1PLL_SS_CNTL);
+		ssControl &= ~EVERGREEN_PxPLL_SS_EN;
+		Write32(OUT, EVERGREEN_P1PLL_SS_CNTL, ssControl);
+		// PLL2
+		ssControl = Read32(OUT, EVERGREEN_P2PLL_SS_CNTL);
+		ssControl &= ~EVERGREEN_PxPLL_SS_EN;
+		Write32(OUT, EVERGREEN_P2PLL_SS_CNTL, ssControl);
+	} else if (info.chipsetID >= RADEON_RS600) {
+		// PLL1
+		ssControl = Read32(OUT, AVIVO_P1PLL_INT_SS_CNTL);
+		ssControl &= ~1;
+		Write32(OUT, AVIVO_P1PLL_INT_SS_CNTL, ssControl);
+		// PLL2
+		ssControl = Read32(OUT, AVIVO_P2PLL_INT_SS_CNTL);
+		ssControl &= ~1;
+		Write32(OUT, AVIVO_P2PLL_INT_SS_CNTL, ssControl);
+	} else
+		return B_ERROR;
+
+	return B_OK;
+}
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.h b/src/add-ons/accelerants/radeon_hd/gpu.h
index 6ca5087c57..324ba28c7c 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.h
+++ b/src/add-ons/accelerants/radeon_hd/gpu.h
@@ -176,6 +176,7 @@ void radeon_gpu_mc_resume(struct gpu_state *gpuState);
 uint32 radeon_gpu_mc_idlecheck();
 status_t radeon_gpu_mc_setup();
 status_t radeon_gpu_irq_setup();
+status_t radeon_gpu_ss_disable();
 
 
 #endif