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added NV04(TNT1) DMA workaround code. TNT1 now also works with DMA acceleration. TNT2-M64 has been confirmed up also. This means all cards should work now! (Except for a NV40 artifact on blits..).

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Still some finetuning to do.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11293 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-02-08 20:30:56 +00:00
parent e7b37d0211
commit 4f985adf3a
1 changed files with 10 additions and 12 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+10 -12
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@@ -328,22 +328,20 @@ status_t nv_acc_init_dma()
/* DMA access type is READ_AND_WRITE; /* DMA access type is READ_AND_WRITE;
* table is located at end of cardRAM (b12-31): * table is located at end of cardRAM (b12-31):
* It's adress needs to be at a 4kb boundary! */ * It's adress needs to be at a 4kb boundary! */
/* NVM DMA is broken on TNT1, so we use PCI-transfers back to the gfxRAM here */
if (si->ps.card_type == NV04)
{
/* DMA target node is PCI */
ACCW(PR_CTX0_C, 0x00023002);
/* point at the DMA buffer via main system memory */
ACCW(PR_CTX2_C, (ACCR(PR_CTX2_C) +
(((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000)));
}
} }
if (si->ps.card_arch == NV04A) if (si->ps.card_arch == NV04A)
{ {
/*
if(TNT1)
{
//cmd buffer DMA update: look at the DMA cmd buffer on cardRAM via main mem...
PR_CTX0_C |= 0x00020000; //select NV_DMA_TARGET_NODE_PCI
PR_CTX2_C += pNv->FbAddress; //set main mem adress ptr to the buf (workaround!)
//info: pNv->FbAddress = pNv->PciInfo->memBase[1] & 0xff800000;
//membase[1] is the virtual (high) adress where the buffer is really mapped probably..
}
*/
/* do a explicit engine reset */ /* do a explicit engine reset */
ACCW(DEBUG0, 0x000001ff); ACCW(DEBUG0, 0x000001ff);