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radeon_hd: Clean up DP training

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* Few tweaks to DP training
* Check for TP3 support and go with TP3 if needed
* Make training more verbose
* Fix DP snoose on ce
This commit is contained in:
Alexander von Gluck IV
2014-02-26 17:17:44 -06:00
parent ad64943039
commit 5006aac272
2 changed files with 16 additions and 12 deletions
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src/add-ons/accelerants/radeon_hd/displayport.cpp
+15 -11
View File
@@ -665,6 +665,7 @@ dp_set_tp(uint32 connectorIndex, int trainingPattern)
radeon_shared_info &info = *gInfo->shared_info; radeon_shared_info &info = *gInfo->shared_info;
dp_info* dp = &gConnector[connectorIndex]->dpInfo; dp_info* dp = &gConnector[connectorIndex]->dpInfo;
pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
int rawTrainingPattern = 0; int rawTrainingPattern = 0;
@@ -681,8 +682,7 @@ dp_set_tp(uint32 connectorIndex, int trainingPattern)
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
break; break;
} }
// TODO: PixelClock 0 ok? encoder_dig_setup(connectorIndex, pll->pixelClock, rawTrainingPattern);
encoder_dig_setup(connectorIndex, 0, rawTrainingPattern);
} else { } else {
ERROR("%s: TODO: dp_encoder_service\n", __func__); ERROR("%s: TODO: dp_encoder_service\n", __func__);
return; return;
@@ -779,26 +779,30 @@ dp_link_train_cr(uint32 connectorIndex)
status_t status_t
dp_link_train_ce(uint32 connectorIndex) dp_link_train_ce(uint32 connectorIndex, bool tp3Support)
{ {
TRACE("%s\n", __func__); TRACE("%s\n", __func__);
dp_info* dp = &gConnector[connectorIndex]->dpInfo; dp_info* dp = &gConnector[connectorIndex]->dpInfo;
// TODO: DisplayPort: Supports TP3? if (tp3Support)
dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_2); dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_3);
else
dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_2);
dp->trainingAttempts = 0; dp->trainingAttempts = 0;
bool channelEqual = false; bool channelEqual = false;
while (1) { while (1) {
if (dp->trainingReadInterval == 0) if (dp->trainingReadInterval == 0)
snooze(100); snooze(400);
else else
snooze(1000 * 4 * dp->trainingReadInterval); snooze(1000 * 4 * dp->trainingReadInterval);
if (!dp_get_link_status(connectorIndex)) if (!dp_get_link_status(connectorIndex)) {
ERROR("%s: ERROR: Unable to get link status!\n", __func__);
break; break;
}
if (dp_clock_equalization_ok(dp)) { if (dp_clock_equalization_ok(dp)) {
channelEqual = true; channelEqual = true;
@@ -879,9 +883,9 @@ dp_link_train(uint8 crtcID)
uint8 sandbox = dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT); uint8 sandbox = dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT);
radeon_shared_info &info = *gInfo->shared_info; radeon_shared_info &info = *gInfo->shared_info;
//bool dpTPS3Supported = false; bool dpTPS3Supported = false;
//if (info.dceMajor >= 5 && (sandbox & DP_TPS3_SUPPORTED) != 0) if (info.dceMajor >= 5 && (sandbox & DP_TPS3_SUPPORTED) != 0)
// dpTPS3Supported = true; dpTPS3Supported = true;
// *** DisplayPort link training initialization // *** DisplayPort link training initialization
@@ -923,7 +927,7 @@ dp_link_train(uint8 crtcID)
dpcd_reg_write(connectorIndex, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED); dpcd_reg_write(connectorIndex, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED);
dp_link_train_cr(connectorIndex); dp_link_train_cr(connectorIndex);
dp_link_train_ce(connectorIndex); dp_link_train_ce(connectorIndex, dpTPS3Supported);
// *** DisplayPort link training finish // *** DisplayPort link training finish
snooze(400); snooze(400);
src/add-ons/accelerants/radeon_hd/displayport.h
+1 -1
View File
@@ -44,7 +44,7 @@ void dp_setup_connectors();
status_t dp_link_train(uint8 crtcID); status_t dp_link_train(uint8 crtcID);
status_t dp_link_train_cr(uint32 connectorIndex); status_t dp_link_train_cr(uint32 connectorIndex);
status_t dp_link_train_ce(uint32 connectorIndex); status_t dp_link_train_ce(uint32 connectorIndex, bool tp3Support);
bool dp_is_dp12_capable(uint32 connectorIndex); bool dp_is_dp12_capable(uint32 connectorIndex);