intel_extreme: DPLL configuration for Tiger Lake

The DPLL selection registers have changed again somewhere between
Skylake and Tiger Lake. Our code was trying to read/write the Skylake
registers on hardware where they don't exist anymore.

Introduce the new Tiger Lake registers and implement enough of it to get
things working on my machine (but probably only on my machine). Also
add a bit of specialization of DisplayPort which I think was not done
correctly on previous hardware either: for DisplayPort, the link rate is
selected from a handful of allowed frequencies, instead of closely
matching the pixel clock.

Things left TODO:
- Write a proper PLL allocation system to ensure each display gets
  assigned its own PLL (unless multiple displays use the same timings).
  For now it is hardcoded to what I want on my machine.
- Fix the DisplayPort PLL computation to use the values from Intel
  datasheets, not the ones used by my machine which are somehow
  different.
- Fix the DisplayPort PLL computation to select one of the several
  available frequencies, allowing resolutions higher than Full HD which
  require higher clocks.
- Fix DisplayPort link training or whatever must happen after the PLL is
  set up, since changing the PLL results in a non-working display and we
  don't get it back.

Unfortunately this still isn't enough to bring up both displays to life
at the same time. I think it is not very far, but the secondary display
(as decided by the BIOS) remains off for now even after successfully
setting it all up.

Early testing on other machines is welcome.

Change-Id: I37209bb14f32c99944bdc8ef6eef75e2550e18ed
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7367
Reviewed-by: Alexander von Gluck <[email protected]>
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>

headers/private/graphics/intel_extreme/intel_extreme.h

@@ -929,6 +929,85 @@ struct intel_brightness_legacy {
 #define LCPLL_CLK_FREQ_337_5_BDW		(2 << 26)
 #define LCPLL_CD_SOURCE_FCLK			(1 << 21)
 
+// Tigerlake PLLs
+#define TGL_DPCLKA_CFGCR0				0x164280
+#define TGL_DPCLKA_DDIC_CLOCK_OFF		(1 << 24)
+#define TGL_DPCLKA_TC6_CLOCK_OFF		(1 << 23)
+#define TGL_DPCLKA_TC5_CLOCK_OFF		(1 << 22)
+#define TGL_DPCLKA_TC4_CLOCK_OFF		(1 << 21)
+#define TGL_DPCLKA_TC3_CLOCK_OFF		(1 << 14)
+#define TGL_DPCLKA_TC2_CLOCK_OFF		(1 << 13)
+#define TGL_DPCLKA_TC1_CLOCK_OFF		(1 << 12)
+#define TGL_DPCLKA_DDIB_CLOCK_OFF		(1 << 11)
+#define TGL_DPCLKA_DDIA_CLOCK_OFF		(1 << 10)
+#define TGL_DPCLKA_DDIC_CLOCK_SELECT	(3 << 4)
+#define TGL_DPCLKA_DDIB_CLOCK_SELECT	(3 << 2)
+#define TGL_DPCLKA_DDIB_CLOCK_SELECT_SHIFT	2
+#define TGL_DPCLKA_DDIA_CLOCK_SELECT	(3 << 0)
+
+#define TGL_DPLL0_CFGCR0				0x164284
+#define TGL_DPLL1_CFGCR0				0x16428C
+#define TGL_TBTPLL_CFGCR0				0x16429C
+#define TGL_DPLL4_CFGCR0				0x164294
+#define TGL_DPLL_DCO_FRACTION			(0x7FFF << 10)
+#define TGL_DPLL_DCO_FRACTION_SHIFT		10
+#define TGL_DPLL_DCO_INTEGER			(0x3FF << 0)
+
+#define TGL_DPLL0_CFGCR1				0x164288
+#define TGL_DPLL1_CFGCR1				0x164290
+#define TGL_TBTPLL_CFGCR1				0x1642A0
+#define TGL_DPLL4_CFGCR1				0x164298
+#define TGL_DPLL_QDIV_RATIO				(0xFF << 10)
+#define TGL_DPLL_QDIV_RATIO_SHIFT		10
+#define TGL_DPLL_QDIV_ENABLE			(1 << 9)
+#define TGL_DPLL_KDIV					(7 << 6)
+#define TGL_DPLL_KDIV_1					(1 << 6)
+#define TGL_DPLL_KDIV_2					(2 << 6)
+#define TGL_DPLL_KDIV_3					(4 << 6)
+#define TGL_DPLL_PDIV					(0xF << 2)
+#define TGL_DPLL_PDIV_2					(1 << 2)
+#define TGL_DPLL_PDIV_3					(2 << 2)
+#define TGL_DPLL_PDIV_5					(4 << 2)
+#define TGL_DPLL_PDIV_7					(8 << 2)
+#define TGL_DPLL_CFSELOVRD				(3 << 0)
+
+#define TGL_DPLL0_DIV0					0x164B00
+#define TGL_DPLL1_DIV0					0x164C00
+#define TGL_DPLL4_DIV0					0x164E00
+#define TGL_DPLL_I_TRUELOCK_CRITERIA	(3 << 30)
+#define TGL_DPLL_I_EARLYLOCK_CRITERIA	(3 << 28)
+#define TGL_DPLL_I_AFC_STARTUP			(7 << 25)
+#define TGL_DPLL_I_DIV_RETIMER_EN		(1 << 24)
+#define TGL_DPLL_I_GAIN_CTRL			(7 << 21)
+#define TGL_DPLL_I_INTEGRAL_COEFF		(0xF << 16)
+#define TGL_DPLL_I_PROPORTIONAL_COEFF	(0xF << 12)
+#define TGL_DPLL_I_FB_PREDIVIDER		(0xF << 8)
+#define TGL_DPLL_I_FB_DIVIDER_M2		(0xFF << 0)
+
+#define TGL_DPLL0_ENABLE				0x46010
+#define TGL_DPLL1_ENABLE				0x46014
+#define TGL_DPLL4_ENABLE				0x46018
+#define TGL_DPLL_ENABLE					(1 << 31)
+#define TGL_DPLL_LOCK					(1 << 30)
+#define TGL_DPLL_POWER_ENABLE			(1 << 27)
+#define TGL_DPLL_POWER_STATE			(1 << 26)
+
+#define TGL_DPLL0_SPREAD_SPECTRUM		0x164B10
+#define TGL_DPLL1_SPREAD_SPECTRUM		0x164C10
+#define TGL_DPLL4_SPREAD_SPECTRUM		0x164E10
+#define TGL_DPLL_IREF_NDIVRATIO			(3 << 29)
+#define TGL_DPLL_SSC_STEP_NUMBER_OFFSET	(3 << 26)
+#define TGL_DPLL_SSC_INJECTION_ADAPTIVE_GAIN_CHANGE_ENABLE		(1 << 25)
+#define TGL_DPLL_SSC_INJECTION_ENABLE	(1 << 24)
+#define TGL_DPLL_SSC_STEP_LENGTH		(0xFF << 16)
+#define TGL_DPLL_SSC_FLL_UPDATE			(3 << 14)
+#define TGL_DPLL_SSC_STEP_NUMBER		(7 << 11)
+#define TGL_DPLL_SSC_OPENLOOP			(1 << 10)
+#define TGL_DPLL_SSC_ENABLE				(1 << 9)
+#define TGL_DPLL_SSC_FLL_ENABLE			(1 << 8)
+#define TGL_DPLL_SSC_BIAS_GUARD_BAND	(3 << 6)
+#define TGL_DPLL_SSC_INIT_DCO_AMP		(0x3F << 0)
+
 #define FUSE_STRAP						0x42014
 #define		HSW_CDCLK_LIMIT				(1 << 24)