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some coldstart finetuning and yet another script command. mods not yet checked (so not yet run).

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8745 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-08-31 12:16:18 +00:00
parent 4826cc5f6a
commit 595ca96f05
1 changed files with 48 additions and 6 deletions
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src/add-ons/accelerants/nvidia/engine/nv_info.c
+48 -6
View File
@@ -177,11 +177,19 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; NV_REG8(NV8_MISCW) = 0xcb;
/* unknown.. */
NV_REG8(NV8_VSE2) = 0x01;
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
/* unlock head's registers for R/W access */ /* unlock head's registers for R/W access */
CRTCW(LOCK, 0x57); CRTCW(LOCK, 0x57);
CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
/* disable RMA as it's not used */
/* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers
* and framebuffer via legacy ISA I/O space.) */
CRTCW(RMA, 0x00);
if (si->ps.secondary_head) if (si->ps.secondary_head)
{ {
/* enable access to secondary head */ /* enable access to secondary head */
@@ -309,6 +317,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size)
/* execute */ /* execute */
adress += 1; adress += 1;
LOG(8,("cmd 'setup RAM config'\n")); LOG(8,("cmd 'setup RAM config'\n"));
//fixme: setup_ram_config is also used on NV11 (at least), which means the
// routine should function differently there!
if (exec) setup_ram_config(rom); if (exec) setup_ram_config(rom);
break; break;
case 0x65: case 0x65:
@@ -383,6 +393,36 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size)
adress += 1; adress += 1;
break; break;
case 0x69:
*size -= 5;
if (*size < 0)
{
LOG(8,("script size error, aborting!\n\n"));
end = true;
result = B_ERROR;
break;
}
/* execute */
adress += 1;
reg = *((uint16*)(&(rom[adress])));
adress += 2;
and_out = *((uint8*)(&(rom[adress])));
adress += 1;
or_in = *((uint8*)(&(rom[adress])));
adress += 1;
LOG(8,("cmd 'RD 8bit ISA I/O REG $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n",
reg, and_out, or_in));
//fixme? this is for ISA I/O registers. Looks like they are in mapped range
// as well (confirm or update code!)
if (exec)
{
byte = NV_REG8(/*0x00601000 + */reg);
byte &= (uint8)and_out;
byte |= (uint8)or_in;
NV_REG8(/*0x00601000 + */reg) = byte;
}
break;
case 0x6e: case 0x6e:
*size -= 13; *size -= 13;
if (*size < 0) if (*size < 0)
@@ -479,17 +519,19 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size)
adress += 1; adress += 1;
or_in = *((uint8*)(&(rom[adress]))); or_in = *((uint8*)(&(rom[adress])));
adress += 1; adress += 1;
LOG(8,("cmd 'RD 8bit indexed REG $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", LOG(8,("cmd 'RD 8bit indexed ISA I/O REG $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n",
index, reg, and_out, or_in)); index, reg, and_out, or_in));
//fixme? this is for ISA I/O registers. Looks like they are in mapped range
// as well (confirm or update code!)
if (exec) if (exec)
{ {
safe = NV_REG8(0x00601000 + reg); safe = NV_REG8(/*0x00601000 + */reg);
NV_REG8(0x00601000 + reg) = index; NV_REG8(/*0x00601000 + */reg) = index;
byte = NV_REG8(0x00601000 + reg + 1); byte = NV_REG8(/*0x00601000 + */reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte |= (uint8)or_in; byte |= (uint8)or_in;
NV_REG8(0x00601000 + reg + 1) = byte; NV_REG8(/*0x00601000 + */reg + 1) = byte;
NV_REG8(0x00601000 + reg) = safe; NV_REG8(/*0x00601000 + */reg) = safe;
} }
break; break;
case 0x79: case 0x79: