From 5b0b486be48ffa1163e846cb00652654067b62ae Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Sun, 3 Jan 2016 15:22:38 -0600 Subject: [PATCH] intel_extreme: Correct LVDS DPLL mode on gen 3 --- src/add-ons/accelerants/intel_extreme/Ports.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp index 427f9f8c6b..e0d1bc72ef 100644 --- a/src/add-ons/accelerants/intel_extreme/Ports.cpp +++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp @@ -556,7 +556,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode) uint32 extraPLLFlags = 0; // DPLL mode LVDS for i915+ - if (gInfo->shared_info->device_type.Generation() >= 4) + if (gInfo->shared_info->device_type.Generation() >= 3) extraPLLFlags |= DISPLAY_PLL_MODE_LVDS; // Program pipe PLL's (pixel_clock is *always* the hardware pixel clock)