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Rename B_MTR_* constants to "something more meaningful".

Browse Source 
The names chosen (e.g. "B_UNCACHED_MEMORY") follow the existing naming
conventions for memory-related constants, of putting the type at the end
of the name: B_KERNEL_BLOCK_ADDRESS, B_FULL_LOCK, B_READ_AREA, etc.

Resolves a very old TODO. No functional change intended.

Change-Id: I31491f6b3abc1e95f915aa302b9f2fb2af14774c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8316
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Augustin Cavalier
2024-09-19 16:43:24 +00:00
committed by waddlesplash
parent e323bc248c
commit 5c1f231967
33 changed files with 108 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/os/drivers/KernelExport.h
+8 -9
View File
@@ -114,21 +114,20 @@ typedef struct {
/* address specifications for mapping physical memory */
#define B_ANY_KERNEL_BLOCK_ADDRESS (B_ANY_KERNEL_ADDRESS + 1)
/* memory types for physical memory */
#define B_UNCACHED_MEMORY (1 << 28)
#define B_WRITE_COMBINING_MEMORY (2 << 28)
#define B_WRITE_THROUGH_MEMORY (3 << 28)
#define B_WRITE_PROTECTED_MEMORY (4 << 28)
#define B_WRITE_BACK_MEMORY (5 << 28)
#define B_MEMORY_TYPE_MASK (0xf0000000)
/* area protection flags for the kernel */
#define B_KERNEL_READ_AREA (1 << 4)
#define B_KERNEL_WRITE_AREA (1 << 5)
#define B_KERNEL_EXECUTE_AREA (1 << 6)
#define B_KERNEL_STACK_AREA (1 << 7)
/* MTR attributes for mapping physical memory (Intel Architecture only) */
// TODO: rename those to something more meaningful
#define B_MTR_UC 0x10000000
#define B_MTR_WC 0x20000000
#define B_MTR_WT 0x30000000
#define B_MTR_WP 0x40000000
#define B_MTR_WB 0x50000000
#define B_MTR_MASK 0xf0000000
/* kernel daemon service */
src/add-ons/kernel/bus_managers/acpi/ACPICAHaiku.cpp
+2 -1
View File
@@ -500,7 +500,8 @@ AcpiOsMapMemory(ACPI_PHYSICAL_ADDRESS where, ACPI_SIZE length)
// unaligned accesses. Hence we specify "writeback" to avoid the default.
void *there;
area_id area = map_physical_memory("acpi_physical_mem_area", (phys_addr_t)where, length,
B_ANY_KERNEL_ADDRESS | B_MTR_WB, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, &there);
B_ANY_KERNEL_ADDRESS | B_WRITE_BACK_MEMORY, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
&there);
DEBUG_FUNCTION_F("addr: 0x%08lx; length: %lu; mapped: %p; area: %" B_PRId32,
(addr_t)where, (size_t)length, there, area);
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+1 -1
View File
@@ -770,7 +770,7 @@ intel_map(intel_info &info)
AreaKeeper apertureMapper;
info.aperture_area = apertureMapper.Map("intel graphics aperture",
info.aperture_physical_base, info.aperture_size,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base);
if (apertureMapper.InitCheck() < B_OK) {
// try again without write combining
src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
+3 -3
View File
@@ -601,7 +601,7 @@ init_corb_rirb_pos(hda_controller* controller, uint32 quirks)
if (!controller->dma_snooping) {
vm_set_area_memory_type(controller->corb_rirb_pos_area,
pe.address, B_MTR_UC);
pe.address, B_UNCACHED_MEMORY);
}
// Program CORB/RIRB for these locations
@@ -908,7 +908,7 @@ hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream,
if (!stream->controller->dma_snooping) {
vm_set_area_memory_type(stream->buffer_area,
bufferPhysicalAddress, B_MTR_UC);
bufferPhysicalAddress, B_UNCACHED_MEMORY);
}
dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32
@@ -948,7 +948,7 @@ hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream,
if (!stream->controller->dma_snooping) {
vm_set_area_memory_type(stream->buffer_descriptors_area,
stream->physical_buffer_descriptors, B_MTR_UC);
stream->physical_buffer_descriptors, B_UNCACHED_MEMORY);
}
dprintf("hda: %s(%s): Allocated %" B_PRIu32 " bytes for %" B_PRIu32
src/add-ons/kernel/drivers/disk/nvme/compat/libnvme_haiku.cpp
+1 -1
View File
@@ -168,7 +168,7 @@ nvme_pcicfg_map_bar_write_combine(void* devhandle, unsigned int bar,
// Turn on write combining for the area
status = vm_set_area_memory_type(area_for(*mapped_addr),
nvme_mem_vtophys(*mapped_addr), B_MTR_WC);
nvme_mem_vtophys(*mapped_addr), B_WRITE_COMBINING_MEMORY);
if (status != 0)
nvme_pcicfg_unmap_bar(devhandle, bar, *mapped_addr);
return status;
src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp
+1 -1
View File
@@ -143,7 +143,7 @@ MapDevice(DeviceInfo& di)
frameBufferAreaName,
videoRamAddr,
videoRamSize,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA + B_WRITE_AREA,
(void**)&si.videoMemAddr);
src/add-ons/kernel/drivers/graphics/ati/driver.cpp
+1 -1
View File
@@ -617,7 +617,7 @@ MapDevice(DeviceInfo& di)
frameBufferAreaName,
videoRamAddr,
videoRamSize,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA + B_WRITE_AREA,
(void**)&(si.videoMemAddr));
src/add-ons/kernel/drivers/graphics/et6x00/driver.c
+3 -3
View File
@@ -390,14 +390,14 @@ pci_info *pcii = &(di->pcii);
/*
* We map the whole graphics card memory area (which consist of RAM memory
* and memory mapped registers) at once. Memory mapped registers must not
* be cacheble, so the whole area is mapped with B_MTR_UC (unable caching).
* be cacheble, so the whole area is mapped with B_UNCACHED_MEMORY.
* We certainly could map separately the RAM memory with write combining
* (B_MTR_WC) and the memory mapped registers with B_MTR_UC.
* and the memory mapped registers with B_UNCACHED_MEMORY.
*/
si->memoryArea = map_physical_memory(buffer,
di->pcii.u.h0.base_registers[0],
di->pcii.u.h0.base_register_sizes[0],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_UC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_UNCACHED_MEMORY,
B_READ_AREA + B_WRITE_AREA,
&(si->memory));
src/add-ons/kernel/drivers/graphics/framebuffer/framebuffer.cpp
+1 -1
View File
@@ -134,7 +134,7 @@ remap_frame_buffer(framebuffer_info& info, addr_t physicalBase, uint32 width,
sharedInfo.frame_buffer_area = area;
// Turn on write combining for the area
vm_set_area_memory_type(area, base, B_MTR_WC);
vm_set_area_memory_type(area, base, B_WRITE_COMBINING_MEMORY);
if (info.physical_frame_buffer_size != 0)
info.complete_frame_buffer_mapped = true;
src/add-ons/kernel/drivers/graphics/matrox/driver.c
+1 -1
View File
@@ -498,7 +498,7 @@ static status_t map_device(device_info *di)
buffer,
di->pcii.u.h0.base_registers[frame_buffer],
di->pcii.u.h0.base_register_sizes[frame_buffer],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
&(si->framebuffer));
src/add-ons/kernel/drivers/graphics/neomagic/driver.c
+1 -1
View File
@@ -494,7 +494,7 @@ static status_t map_device(device_info *di)
buffer,
di->pcii.u.h0.base_registers[frame_buffer],
di->pcii.u.h0.base_register_sizes[frame_buffer],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
&(si->framebuffer));
src/add-ons/kernel/drivers/graphics/nvidia/driver.c
+2 -2
View File
@@ -685,7 +685,7 @@ map_device(device_info *di)
/* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
physicalAddress,
di->pcii.u.h0.base_register_sizes[frame_buffer],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
&(si->framebuffer));
@@ -960,7 +960,7 @@ open_hook(const char* name, uint32 flags, void** cookie)
/* map the net DMA command buffer into vmem, using Write Combining */
si->dma_area = map_physical_memory(
"NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));
/* if failed with write combining try again without */
if (si->dma_area < 0) {
src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c
+1 -1
View File
@@ -102,7 +102,7 @@ static status_t createGARTBuffer( GART_info *gart, size_t size )
gart->buffer.area = map_physical_memory( "Radeon aligned PCI GART buffer",
(addr_t)aligned_phys,
size, B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
size, B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA, &gart->buffer.ptr );
if( gart->buffer.area < 0 ) {
src/add-ons/kernel/drivers/graphics/radeon/init.c
+1 -1
View File
@@ -133,7 +133,7 @@ status_t Radeon_MapDevice( device_info *di, bool mmio_only )
buffer,
di->pcii.u.h0.base_registers[fb],
di->pcii.u.h0.base_register_sizes[fb],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
(void **)&(si->local_mem));
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
+1 -1
View File
@@ -806,7 +806,7 @@ radeon_hd_init(radeon_info &info)
(size_t)info.shared_info->frame_buffer_size * 1024);
// Turn on write combining for the frame buffer area
vm_set_area_memory_type(info.framebuffer_area, fbAddr, B_MTR_WC);
vm_set_area_memory_type(info.framebuffer_area, fbAddr, B_WRITE_COMBINING_MEMORY);
frambufferMapper.Detach();
src/add-ons/kernel/drivers/graphics/s3/driver.cpp
+1 -1
View File
@@ -261,7 +261,7 @@ MapDevice(DeviceInfo& di)
areaName,
videoRamAddr,
videoRamSize,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA + B_WRITE_AREA,
&(si.videoMemAddr));
src/add-ons/kernel/drivers/graphics/skeleton/driver.c
+1 -1
View File
@@ -470,7 +470,7 @@ static status_t map_device(device_info *di)
/* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
di->pcii.u.h0.base_registers_pci[frame_buffer],
di->pcii.u.h0.base_register_sizes[frame_buffer],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
&(si->framebuffer));
src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp
+1 -1
View File
@@ -332,7 +332,7 @@ remap_frame_buffer(vesa_info& info, addr_t physicalBase, uint32 width,
sharedInfo.frame_buffer_area = area;
// Turn on write combining for the area
vm_set_area_memory_type(area, base, B_MTR_WC);
vm_set_area_memory_type(area, base, B_WRITE_COMBINING_MEMORY);
if (info.physical_frame_buffer_size != 0)
info.complete_frame_buffer_mapped = true;
src/add-ons/kernel/drivers/graphics/via/driver.c
+1 -1
View File
@@ -479,7 +479,7 @@ static status_t map_device(device_info *di)
/* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
di->pcii.u.h0.base_registers_pci[frame_buffer],
di->pcii.u.h0.base_register_sizes[frame_buffer],
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_ANY_KERNEL_BLOCK_ADDRESS | B_WRITE_COMBINING_MEMORY,
B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA,
&(si->framebuffer));
src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.h
+5 -5
View File
@@ -238,17 +238,17 @@ ARMPagingMethod32Bit::PageTableEntryFlagsToAttributes(uint32 pageTableEntry)
ARMPagingMethod32Bit::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
{
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
// Strongly Ordered
return 0;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
// Shareable Device Memory
return ARM_MMU_L2_FLAG_B;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
// Outer and Inner Write-Through, no Write-Allocate
return ARM_MMU_L2_FLAG_C;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
// Outer and Inner Write-Back, no Write-Allocate
return ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C;
src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp
+6 -6
View File
@@ -508,22 +508,22 @@ VMSAv8TranslationMap::GetMemoryAttr(uint32 attributes, uint32 memoryType, bool i
uint8_t type = MAIR_NORMAL_WB;
switch (memoryType & B_MTR_MASK) {
case B_MTR_UC:
switch (memoryType & B_MEMORY_TYPE_MASK) {
case B_UNCACHED_MEMORY:
// TODO: This probably should be nGnRE for PCI
type = MAIR_DEVICE_nGnRnE;
break;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
type = MAIR_NORMAL_NC;
break;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
type = MAIR_NORMAL_WT;
break;
case B_MTR_WP:
case B_WRITE_PROTECTED_MEMORY:
type = MAIR_NORMAL_WT;
break;
default:
case B_MTR_WB:
case B_WRITE_BACK_MEMORY:
type = MAIR_NORMAL_WB;
break;
}
src/system/kernel/arch/m68k/paging/040/M68KPagingMethod040.h
+5 -5
View File
@@ -169,17 +169,17 @@ M68KPagingMethod040::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
// (usually only write-combining for the frame buffer).
#warning M68K: Check this
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return CM_DISABLED_SERIALIZED | CM_CACHABLE_WRITETHROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
return 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return CM_CACHABLE_WRITETHROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/arch/ppc/paging/460/PPCPagingMethod460.cpp
+2 -2
View File
@@ -308,8 +308,8 @@ PPCPagingMethod460::FillPageTableEntry(page_table_entry *entry,
entry->_reserved0 = 0;
entry->referenced = false;
entry->changed = false;
entry->write_through = (memoryType == B_MTR_UC) || (memoryType == B_MTR_WT);
entry->caching_inhibited = (memoryType == B_MTR_UC);
entry->write_through = (memoryType == B_UNCACHED_MEMORY) || (memoryType == B_WRITE_THROUGH_MEMORY);
entry->caching_inhibited = (memoryType == B_UNCACHED_MEMORY);
entry->memory_coherent = false;
entry->guarded = false;
entry->_reserved1 = 0;
src/system/kernel/arch/ppc/paging/460/PPCPagingMethod460.h
+5 -5
View File
@@ -185,19 +185,19 @@ PPCPagingMethod460::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
// actually *have* to do with the MTRRs to setting the remaining types
// (usually only write-combining for the frame buffer).
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return PPC_PTE_CACHING_DISABLED | PPC_PTE_WRITE_THROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
// PPC_PTE_WRITE_THROUGH would be closer, but the combination with
// MTRR WC is "implementation defined" for Pentium Pro/II.
return 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return PPC_PTE_WRITE_THROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/arch/ppc/paging/classic/PPCPagingMethodClassic.cpp
+2 -2
View File
@@ -308,8 +308,8 @@ PPCPagingMethodClassic::FillPageTableEntry(page_table_entry *entry,
entry->_reserved0 = 0;
entry->referenced = false;
entry->changed = false;
entry->write_through = (memoryType == B_MTR_UC) || (memoryType == B_MTR_WT);
entry->caching_inhibited = (memoryType == B_MTR_UC);
entry->write_through = (memoryType == B_UNCACHED_MEMORY) || (memoryType == B_WRITE_THROUGH_MEMORY);
entry->caching_inhibited = (memoryType == B_UNCACHED_MEMORY);
entry->memory_coherent = false;
entry->guarded = false;
entry->_reserved1 = 0;
src/system/kernel/arch/ppc/paging/classic/PPCPagingMethodClassic.h
+5 -5
View File
@@ -185,19 +185,19 @@ PPCPagingMethodClassic::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
// actually *have* to do with the MTRRs to setting the remaining types
// (usually only write-combining for the frame buffer).
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return PPC_PTE_CACHING_DISABLED | PPC_PTE_WRITE_THROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
// PPC_PTE_WRITE_THROUGH would be closer, but the combination with
// MTRR WC is "implementation defined" for Pentium Pro/II.
return 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return PPC_PTE_WRITE_THROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/arch/x86/32/bios.cpp
+1 -1
View File
@@ -121,7 +121,7 @@ bios_init(void)
{
// map BIOS area 0xe0000 - 0xfffff
area_id biosArea = map_physical_memory("pc bios", 0xe0000, 0x20000,
B_ANY_KERNEL_ADDRESS | B_MTR_WB,
B_ANY_KERNEL_ADDRESS | B_WRITE_BACK_MEMORY,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&gBiosBase);
if (biosArea < 0)
return biosArea;
src/system/kernel/arch/x86/arch_vm.cpp
+21 -22
View File
@@ -131,19 +131,19 @@ static bool
add_used_mtrr(uint64 base, uint64 size, uint32 type)
{
switch (type) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
type = IA32_MTR_UNCACHED;
break;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
type = IA32_MTR_WRITE_COMBINING;
break;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
type = IA32_MTR_WRITE_THROUGH;
break;
case B_MTR_WP:
case B_WRITE_PROTECTED_MEMORY:
type = IA32_MTR_WRITE_PROTECTED;
break;
case B_MTR_WB:
case B_WRITE_BACK_MEMORY:
type = IA32_MTR_WRITE_BACK;
break;
default:
@@ -340,7 +340,7 @@ update_mtrrs(update_mtrr_info& updateInfo)
int32 pointCount = 0;
for (MemoryTypeRangeList::Iterator it = sMemoryTypeRanges.GetIterator();
memory_type_range* range = it.Next();) {
if (range->type == B_MTR_UC) {
if (range->type == B_UNCACHED_MEMORY) {
// Ignore uncacheable ranges below a certain size, if requested.
// Since we always enforce uncacheability via the PTE attributes,
// this is no problem (though not recommended for performance
@@ -457,14 +457,13 @@ update_mtrrs(update_mtrr_info& updateInfo)
rangeList.Add(&ranges[i]);
static const uint32 kMemoryTypes[] = {
B_MTR_UC,
B_MTR_WC,
B_MTR_WP,
B_MTR_WT,
B_MTR_WB
B_UNCACHED_MEMORY,
B_WRITE_COMBINING_MEMORY,
B_WRITE_PROTECTED_MEMORY,
B_WRITE_THROUGH_MEMORY,
B_WRITE_BACK_MEMORY
};
static const int32 kMemoryTypeCount = sizeof(kMemoryTypes)
/ sizeof(*kMemoryTypes);
static const int32 kMemoryTypeCount = B_COUNT_OF(kMemoryTypes);
for (int32 i = 0; i < kMemoryTypeCount; i++) {
uint32 type = kMemoryTypes[i];
@@ -472,7 +471,7 @@ update_mtrrs(update_mtrr_info& updateInfo)
// Remove uncached and write-through ranges after processing them. This
// let's us leverage their intersection property with any other
// respectively write-back ranges.
bool removeRanges = type == B_MTR_UC || type == B_MTR_WT;
bool removeRanges = type == B_UNCACHED_MEMORY || type == B_WRITE_THROUGH_MEMORY;
optimize_memory_ranges(rangeList, type, removeRanges);
}
@@ -494,7 +493,7 @@ update_mtrrs(update_mtrr_info& updateInfo)
uint32 type = kMemoryTypes[i];
// skip write-back ranges -- that'll be the default type anyway
if (type == B_MTR_WB)
if (type == B_WRITE_BACK_MEMORY)
continue;
for (int32 i = 0; i < rangeCount; i++) {
@@ -661,15 +660,15 @@ static const char *
memory_type_to_string(uint32 type)
{
switch (type) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return "uncacheable";
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
return "write combining";
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return "write-through";
case B_MTR_WP:
case B_WRITE_PROTECTED_MEMORY:
return "write-protected";
case B_MTR_WB:
case B_WRITE_BACK_MEMORY:
return "write-back";
default:
return "unknown";
@@ -720,7 +719,7 @@ arch_vm_init_post_area(kernel_args *args)
// map 0 - 0xa0000 directly
id = map_physical_memory("dma_region", 0x0, 0xa0000,
B_ANY_KERNEL_ADDRESS | B_MTR_WB,
B_ANY_KERNEL_ADDRESS | B_WRITE_BACK_MEMORY,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, &gDmaAddress);
if (id < 0) {
panic("arch_vm_init_post_area: unable to map dma region\n");
@@ -770,7 +769,7 @@ arch_vm_init_post_modules(kernel_args *args)
// set the physical memory ranges to write-back mode
for (uint32 i = 0; i < args->num_physical_memory_ranges; i++) {
add_memory_type_range(-1, args->physical_memory_range[i].start,
args->physical_memory_range[i].size, B_MTR_WB, NULL);
args->physical_memory_range[i].size, B_WRITE_BACK_MEMORY, NULL);
}
return B_OK;
src/system/kernel/arch/x86/paging/32bit/X86PagingMethod32Bit.h
+5 -5
View File
@@ -148,10 +148,10 @@ X86PagingMethod32Bit::ClearPageTableEntryFlags(page_table_entry* entry, uint32 f
X86PagingMethod32Bit::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
{
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return X86_PTE_CACHING_DISABLED | X86_PTE_WRITE_THROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
if (x86_use_pat())
return X86_PTE_PAT;
@@ -159,11 +159,11 @@ X86PagingMethod32Bit::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
// MTRR WC is "implementation defined" for Pentium Pro/II.
return 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return X86_PTE_WRITE_THROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/arch/x86/paging/64bit/X86PagingMethod64Bit.h
+5 -5
View File
@@ -168,17 +168,17 @@ X86PagingMethod64Bit::ClearTableEntryFlags(uint64_t* entryPointer,
X86PagingMethod64Bit::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
{
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return X86_64_PTE_CACHING_DISABLED | X86_64_PTE_WRITE_THROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
return x86_use_pat() ? X86_64_PTE_PAT : 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return X86_64_PTE_WRITE_THROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.h
+5 -5
View File
@@ -193,10 +193,10 @@ X86PagingMethodPAE::ClearTableEntryFlags(uint64_t* entry, uint64_t flags)
X86PagingMethodPAE::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
{
switch (memoryType) {
case B_MTR_UC:
case B_UNCACHED_MEMORY:
return X86_PAE_PTE_CACHING_DISABLED | X86_PAE_PTE_WRITE_THROUGH;
case B_MTR_WC:
case B_WRITE_COMBINING_MEMORY:
if (x86_use_pat())
return X86_PAE_PTE_PAT;
@@ -204,11 +204,11 @@ X86PagingMethodPAE::MemoryTypeToPageTableEntryFlags(uint32 memoryType)
// MTRR WC is "implementation defined" for Pentium Pro/II.
return 0;
case B_MTR_WT:
case B_WRITE_THROUGH_MEMORY:
return X86_PAE_PTE_WRITE_THROUGH;
case B_MTR_WP:
case B_MTR_WB:
case B_WRITE_PROTECTED_MEMORY:
case B_WRITE_BACK_MEMORY:
default:
return 0;
}
src/system/kernel/debug/frame_buffer_console.cpp
+1 -1
View File
@@ -507,7 +507,7 @@ frame_buffer_console_init_post_modules(kernel_args* args)
// try to set frame buffer memory to write combined
return vm_set_area_memory_type(sConsole.area,
args->frame_buffer.physical_buffer.start, B_MTR_WC);
args->frame_buffer.physical_buffer.start, B_WRITE_COMBINING_MEMORY);
}
src/system/kernel/vm/vm.cpp
+8 -8
View File
@@ -1937,7 +1937,7 @@ vm_map_physical_memory(team_id team, const char* name, void** _address,
virtual_address_restrictions addressRestrictions = {};
addressRestrictions.address = *_address;
addressRestrictions.address_specification = addressSpec & ~B_MTR_MASK;
addressRestrictions.address_specification = addressSpec & ~B_MEMORY_TYPE_MASK;
status = map_backing_store(locker.AddressSpace(), cache, 0, name, size,
B_FULL_LOCK, protection, 0, REGION_NO_PRIVATE_MAP, 0, &addressRestrictions,
true, &area, _address);
@@ -1948,12 +1948,12 @@ vm_map_physical_memory(team_id team, const char* name, void** _address,
cache->Unlock();
if (status == B_OK) {
// Set requested memory type -- use uncached if not given but allow it
// to be overridden by ranges that may already exist
uint32 memoryType = addressSpec & B_MTR_MASK;
bool weak = memoryType == 0;
// Set requested memory type -- default to uncached, but allow
// that to be overridden by ranges that may already exist.
uint32 memoryType = addressSpec & B_MEMORY_TYPE_MASK;
const bool weak = (memoryType == 0);
if (weak)
memoryType = B_MTR_UC;
memoryType = B_UNCACHED_MEMORY;
status = arch_vm_set_memory_type(area, physicalAddress, memoryType,
weak ? &memoryType : NULL);
@@ -2023,7 +2023,7 @@ vm_map_physical_memory_vecs(team_id team, const char* name, void** _address,
addressSpec, _size, protection, vecs, vecCount));
if (!arch_vm_supports_protection(protection)
|| (addressSpec & B_MTR_MASK) != 0) {
|| (addressSpec & B_MEMORY_TYPE_MASK) != 0) {
return B_NOT_SUPPORTED;
}
@@ -2057,7 +2057,7 @@ vm_map_physical_memory_vecs(team_id team, const char* name, void** _address,
VMArea* area;
virtual_address_restrictions addressRestrictions = {};
addressRestrictions.address = *_address;
addressRestrictions.address_specification = addressSpec & ~B_MTR_MASK;
addressRestrictions.address_specification = addressSpec & ~B_MEMORY_TYPE_MASK;
result = map_backing_store(locker.AddressSpace(), cache, 0, name,
size, B_FULL_LOCK, protection, 0, REGION_NO_PRIVATE_MAP, 0,
&addressRestrictions, true, &area, _address);