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agp now fully works with the agp busmanager module: still some finetuning needed though..

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8385 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-07-12 19:06:06 +00:00
parent 927754fb6a
commit 5c742e1422
1 changed files with 39 additions and 173 deletions
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src/add-ons/accelerants/nvidia/engine/nv_agp.c
+39 -173
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@@ -8,12 +8,15 @@
#include "nv_std.h" #include "nv_std.h"
static void nv_agp_list_info(agp_info ai); static void nv_agp_list_info(agp_info ai);
static bool zooi(void); static void nv_agp_list_active(uint32 cmd);
status_t nv_agp_setup(void) status_t nv_agp_setup(void)
{ {
nv_nth_agp_info nai; nv_nth_agp_info nai;
nv_cmd_agp nca;
uint8 index; uint8 index;
uint8 nv_index = 0xff;
agp_info ai[8];
bool agp = false; bool agp = false;
/* first try to enable FW support on our card if user requested this /* first try to enable FW support on our card if user requested this
@@ -35,7 +38,7 @@ status_t nv_agp_setup(void)
} }
/* set the magic number so the nvidia kerneldriver knows we're for real */ /* set the magic number so the nvidia kerneldriver knows we're for real */
nai.magic = NV_PRIVATE_DATA_MAGIC; nca.magic = nai.magic = NV_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */ /* contact driver and get a pointer to the registers and shared data */
for (index = 0; index < 8; index++) for (index = 0; index < 8; index++)
@@ -55,11 +58,16 @@ status_t nv_agp_setup(void)
LOG(4,("AGP: AGP capable device #%d:\n", (index + 1))); LOG(4,("AGP: AGP capable device #%d:\n", (index + 1)));
/* remember the info we got */
ai[index] = nai.agpi;
/* see if we are this one */ /* see if we are this one */
if (((((uint32)(nai.agpi.device_id)) << 16) | nai.agpi.vendor_id) == CFGR(DEVID)) if (((((uint32)(nai.agpi.device_id)) << 16) | nai.agpi.vendor_id) == CFGR(DEVID))
{ {
LOG(4,("AGP: (this is the device this accelerant controls)\n")); LOG(4,("AGP: (this is the device this accelerant controls)\n"));
agp = true; agp = true;
/* remember where we are */
nv_index = index;
} }
/* log capabilities */ /* log capabilities */
@@ -83,178 +91,31 @@ status_t nv_agp_setup(void)
return B_ERROR; return B_ERROR;
} }
}
static bool zooi(void)
{
/* get host bridge info */
// ioctl(agp_fd, GET_CONFIG, &ai_bridge);
// LOG(4,("AGP: AGP host bridge found, vendorID $%04x, deviceID $%04x\n",
// ai_bridge.dev.vendor_id, ai_bridge.dev.device_id));
// if (ai_bridge.status != B_OK)
{
LOG(4,("AGP: host bridge failed to respond correctly, aborting AGP setup!\n"));
/* close host bridge driver */
// close(agp_fd);
/* program card for PCI access */
// PCI_CFGW((adress + 8), 0x00000000);
return B_ERROR;
}
/* list host bridge capabilities */
// LOG(4,("AGP: host bridge supports specification %d.%d;\n",
// ((ai_bridge.config.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
// ((ai_bridge.config.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift)));
// nv_agp_list_caps(ai_bridge);
/* abort if specified by user in nv.settings */ /* abort if specified by user in nv.settings */
if (si->settings.force_pci) if (si->settings.force_pci)
{ {
/* user specified not to use AGP */ /* user specified not to use AGP */
LOG(4,("AGP: forcing PCI mode (specified in nv.settings).\n")); LOG(4,("AGP: forcing PCI mode (specified in nv.settings).\n"));
/* close host bridge driver */
// close(agp_fd);
/* program card for PCI access */ /* program card for PCI access */
// PCI_CFGW((adress + 8), 0x00000000); CFGW(AGPCMD, 0x00000000);
return B_ERROR; return B_ERROR;
} }
/* find out if AGP modes are supported: devices exist that have the AGP style /* activate AGP mode */
* connector with AGP style registers, but not the features! LOG(4,("AGP: activating AGP mode...\n"));
* (confirmed Matrox Millenium II AGP for instance) */
// if (!(ai_card.config.agp_stat & AGP_rates) ||
// !(ai_bridge.config.agp_stat & AGP_rates))
{
LOG(4,("AGP: no AGP modes possible, aborting AGP setup!\n"));
/* close host bridge driver */
// close(agp_fd);
/* program card for PCI access */
// PCI_CFGW((adress + 8), 0x00000000);
return B_ERROR; /* let the AGP busmanager worry about what mode to set.. */
} nca.cmd = (0xfffffff7);
/* ..but we do need to select the right speed scheme fetched from our card */
if (ai[nv_index].interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev;
ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca));
/* find out shared AGP capabilities of card and host bridge */ /* list mode now activated */
// if ((ai_card.config.agp_stat & AGP_rate_rev) != nv_agp_list_active(nca.cmd);
// (ai_bridge.config.agp_stat & AGP_rate_rev))
{
LOG(4,("AGP: compatibility problem detected, aborting AGP setup!\n"));
/* close host bridge driver */
// close(agp_fd);
/* program card for PCI access */
// PCI_CFGW((adress + 8), 0x00000000);
return B_ERROR;
}
/* both card and bridge are set to the same standard */
/* (which is as it should be!) */
LOG(4,("AGP: enabling AGP\n"));
/* select highest AGP mode */
// if (!(ai_bridge.config.agp_stat & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
// if ((ai_card.config.agp_stat & AGP_2_4x) &&
// (ai_bridge.config.agp_stat & AGP_2_4x))
{
LOG(4,("AGP: using AGP 2.0 4x mode\n"));
// ai_card.config.agp_cmd = AGP_2_4x;
// ai_bridge.config.agp_cmd = AGP_2_4x;
}
// else
{
// if ((ai_card.config.agp_stat & AGP_2_2x) &&
// (ai_bridge.config.agp_stat & AGP_2_2x))
{
LOG(4,("AGP: using AGP 2.0 2x mode\n"));
// ai_card.config.agp_cmd = AGP_2_2x;
// ai_bridge.config.agp_cmd = AGP_2_2x;
}
// else
{
LOG(4,("AGP: using AGP 2.0 1x mode\n"));
// ai_card.config.agp_cmd = AGP_2_1x;
// ai_bridge.config.agp_cmd = AGP_2_1x;
}
}
}
// else
{
/* AGP 3.0 scheme applies */
// if ((ai_card.config.agp_stat & AGP_3_8x) &&
// (ai_bridge.config.agp_stat & AGP_3_8x))
{
LOG(4,("AGP: using AGP 3.0 8x mode\n"));
// ai_card.config.agp_cmd = AGP_3_8x;
// ai_bridge.config.agp_cmd = AGP_3_8x;
}
// else
{
LOG(4,("AGP: using AGP 3.0 4x mode\n"));
// ai_card.config.agp_cmd = AGP_3_4x;
// ai_bridge.config.agp_cmd = AGP_3_4x;
}
}
/* activate sideband adressing if possible */
// if ((ai_card.config.agp_stat & AGP_SBA) &&
// (ai_bridge.config.agp_stat & AGP_SBA))
{
LOG(4,("AGP: enabling sideband adressing (SBA)\n"));
// ai_card.config.agp_cmd |= AGP_SBA;
// ai_bridge.config.agp_cmd |= AGP_SBA;
}
/* activate fast writes if possible */
// if ((ai_card.config.agp_stat & AGP_FW) &&
// (ai_bridge.config.agp_stat & AGP_FW))
{
LOG(4,("AGP: enabling fast writes (FW)\n"));
// ai_card.config.agp_cmd |= AGP_FW;
// ai_bridge.config.agp_cmd |= AGP_FW;
}
/* setup maximum request depth supported */
/* note:
* this is writable only in the graphics card */
// rq_depth_card = ((ai_card.config.agp_stat & AGP_RQ) >> AGP_RQ_shift);
// rq_depth_bridge = ((ai_bridge.config.agp_stat & AGP_RQ) >> AGP_RQ_shift);
// if (rq_depth_card < rq_depth_bridge)
{
// ai_card.config.agp_cmd |= (rq_depth_card << AGP_RQ_shift);
// LOG(4,("AGP: max. AGP queued request depth will be set to %d\n",
// (rq_depth_card + 1)));
}
// else
{
// ai_card.config.agp_cmd |= (rq_depth_bridge << AGP_RQ_shift);
// LOG(4,("AGP: max. AGP queued request depth will be set to %d\n",
// (rq_depth_bridge + 1)));
}
/* set the enable AGP bits */
/* note:
* the AGP standard defines that this bit may be written to the AGPCMD
* registers simultanously with the other bits if a single 32bit write
* to each register is used. */
// ai_card.config.agp_cmd |= AGP_enable;
// ai_bridge.config.agp_cmd |= AGP_enable;
/* finally program both the host bridge and the graphics card! */
/* note:
* the AGP standard defines that the host bridge should be enabled first. */
// ioctl(agp_fd, SET_CONFIG, &ai_bridge);
// PCI_CFGW((adress + 8), ai_card.config.agp_cmd);
/* extra check */
LOG(4,("AGP: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD))); LOG(4,("AGP: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD)));
/* close host bridge driver */
// close(agp_fd);
return B_OK; return B_OK;
} }
@@ -305,31 +166,36 @@ static void nv_agp_list_info(agp_info ai)
/* /*
list current settings list current settings
*/ */
LOG(4,("AGP: listing current active settings:\n")); nv_agp_list_active(ai.interface.agp_cmd);
if (!(ai.interface.agp_stat & AGP_rate_rev)) }
static void nv_agp_list_active(uint32 cmd)
{
LOG(4,("AGP: listing settings now in use:\n"));
if (!(cmd & AGP_rate_rev))
{ {
/* AGP 2.0 scheme applies */ /* AGP 2.0 scheme applies */
if (ai.interface.agp_cmd & AGP_2_1x) if (cmd & AGP_2_1x)
LOG(4,("AGP: AGP 2.0 1x mode is set\n")); LOG(4,("AGP: AGP 2.0 1x mode is set\n"));
if (ai.interface.agp_cmd & AGP_2_2x) if (cmd & AGP_2_2x)
LOG(4,("AGP: AGP 2.0 2x mode is set\n")); LOG(4,("AGP: AGP 2.0 2x mode is set\n"));
if (ai.interface.agp_cmd & AGP_2_4x) if (cmd & AGP_2_4x)
LOG(4,("AGP: AGP 2.0 4x mode is set\n")); LOG(4,("AGP: AGP 2.0 4x mode is set\n"));
} }
else else
{ {
/* AGP 3.0 scheme applies */ /* AGP 3.0 scheme applies */
if (ai.interface.agp_cmd & AGP_3_4x) if (cmd & AGP_3_4x)
LOG(4,("AGP: AGP 3.0 4x mode is set\n")); LOG(4,("AGP: AGP 3.0 4x mode is set\n"));
if (ai.interface.agp_cmd & AGP_3_8x) if (cmd & AGP_3_8x)
LOG(4,("AGP: AGP 3.0 8x mode is set\n")); LOG(4,("AGP: AGP 3.0 8x mode is set\n"));
} }
if (ai.interface.agp_cmd & AGP_FW) LOG(4,("AGP: fastwrite transfers are enabled\n")); if (cmd & AGP_FW) LOG(4,("AGP: fastwrite transfers are enabled\n"));
if (ai.interface.agp_cmd & AGP_SBA) LOG(4,("AGP: sideband adressing is enabled\n")); if (cmd & AGP_SBA) LOG(4,("AGP: sideband adressing is enabled\n"));
LOG(4,("AGP: max. AGP queued request depth is set to %d\n", LOG(4,("AGP: max. AGP queued request depth is set to %d\n",
(((ai.interface.agp_cmd & AGP_RQ) >> AGP_RQ_shift) + 1))); (((cmd & AGP_RQ) >> AGP_RQ_shift) + 1)));
if (ai.interface.agp_cmd & AGP_enable) if (cmd & AGP_enable)
LOG(4,("AGP: this AGP interface is currently enabled.\n")); LOG(4,("AGP: the AGP interface is enabled.\n"));
else else
LOG(4,("AGP: this AGP interface is currently disabled.\n")); LOG(4,("AGP: the AGP interface is disabled.\n"));
} }