From 5de64e32fdbf2ec19e9fdd91499d0220748eb2f3 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Mon, 11 Jul 2005 15:29:50 +0000 Subject: [PATCH] setup hardware cursor. bitmap not yet correct, colors neither. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13633 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../accelerants/via/GetAccelerantHook.c | 2 +- src/add-ons/accelerants/via/InitAccelerant.c | 7 +- src/add-ons/accelerants/via/engine/agp.c | 8 +- src/add-ons/accelerants/via/engine/bes.c | 8 +- src/add-ons/accelerants/via/engine/crtc.c | 126 ++++++------------ src/add-ons/accelerants/via/engine/crtc2.c | 12 +- src/add-ons/accelerants/via/engine/general.c | 12 +- src/add-ons/accelerants/via/engine/info.c | 124 ++++++++--------- 8 files changed, 131 insertions(+), 168 deletions(-) diff --git a/src/add-ons/accelerants/via/GetAccelerantHook.c b/src/add-ons/accelerants/via/GetAccelerantHook.c index 3c85f1278f..e19ad43861 100644 --- a/src/add-ons/accelerants/via/GetAccelerantHook.c +++ b/src/add-ons/accelerants/via/GetAccelerantHook.c @@ -4,7 +4,7 @@ Other authors: Mark Watson, - Rudolf Cornelissen 10/2002-4/2004 + Rudolf Cornelissen 10/2002-7/2005 */ #define MODULE_BIT 0x08000000 diff --git a/src/add-ons/accelerants/via/InitAccelerant.c b/src/add-ons/accelerants/via/InitAccelerant.c index 6c87b83931..93dc9bf1af 100644 --- a/src/add-ons/accelerants/via/InitAccelerant.c +++ b/src/add-ons/accelerants/via/InitAccelerant.c @@ -4,7 +4,7 @@ Other authors: Mark Watson, - Rudolf Cornelissen 10/2002-7/2004. + Rudolf Cornelissen 10/2002-7/2005. */ #define MODULE_BIT 0x00800000 @@ -153,8 +153,9 @@ status_t INIT_ACCELERANT(int the_fd) { to the app_server later. */ pointer_reservation = 0; - /* Nvidia hardcursor needs 2kB space */ - if (si->settings.hardcursor) pointer_reservation = 2048; + /* VIA hardcursor needs 4kB space */ +//rud: shutoff until adress of FB is programmed! <<<<<<<<<< +// if (si->settings.hardcursor) pointer_reservation = 4096; si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation); si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation); diff --git a/src/add-ons/accelerants/via/engine/agp.c b/src/add-ons/accelerants/via/engine/agp.c index ec45a59725..4e71559302 100644 --- a/src/add-ons/accelerants/via/engine/agp.c +++ b/src/add-ons/accelerants/via/engine/agp.c @@ -25,15 +25,15 @@ status_t eng_agp_setup(void) // { // uint32 reg; -// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); +// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2))); // LOG(4, ("AGP: attempting to enable fastwrite support..\n")); /* 'force' FW support */ -// reg = (ENG_RG32(RG32_NVSTRAPINFO2) & ~0x00000800); +// reg = (ENG_REG32(RG32_NVSTRAPINFO2) & ~0x00000800); /* enable strapinfo overwrite */ -// ENG_RG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000); +// ENG_REG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000); -// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); +// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2))); // } /* set the magic number so the skeleton kerneldriver knows we're for real */ diff --git a/src/add-ons/accelerants/via/engine/bes.c b/src/add-ons/accelerants/via/engine/bes.c index 22a0a5e5f5..b0fe8cf442 100644 --- a/src/add-ons/accelerants/via/engine/bes.c +++ b/src/add-ons/accelerants/via/engine/bes.c @@ -357,16 +357,16 @@ status_t eng_bes_to_crtc(bool crtc) { LOG(4,("Overlay: switching overlay to CRTC2\n")); /* switch overlay engine to CRTC2 */ - ENG_RG32(RG32_FUNCSEL) &= ~0x00001000; - ENG_RG32(RG32_2FUNCSEL) |= 0x00001000; + ENG_REG32(RG32_FUNCSEL) &= ~0x00001000; + ENG_REG32(RG32_2FUNCSEL) |= 0x00001000; si->overlay.crtc = !si->crtc_switch_mode; } else { LOG(4,("Overlay: switching overlay to CRTC1\n")); /* switch overlay engine to CRTC1 */ - ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; - ENG_RG32(RG32_FUNCSEL) |= 0x00001000; + ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000; + ENG_REG32(RG32_FUNCSEL) |= 0x00001000; si->overlay.crtc = si->crtc_switch_mode; } return B_OK; diff --git a/src/add-ons/accelerants/via/engine/crtc.c b/src/add-ons/accelerants/via/engine/crtc.c index 70bb632ac8..dd02ea0f6d 100644 --- a/src/add-ons/accelerants/via/engine/crtc.c +++ b/src/add-ons/accelerants/via/engine/crtc.c @@ -1,6 +1,6 @@ /* CTRC functionality */ /* Author: - Rudolf Cornelissen 11/2002-9/2004 + Rudolf Cornelissen 11/2002-7/2005 */ #define MODULE_BIT 0x00040000 @@ -610,7 +610,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) /* we might have no retraces during setmode! */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && + while (((ENG_REG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && (timeout < (25000/10))) { /* don't snooze much longer or retrace might get missed! */ @@ -646,7 +646,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) * wrap-around at 16Mb boundaries!! */ /* 30bit adress in 32bit words */ - ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc); + ENG_REG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc); } /* set NV4/NV10 byte adress: (b0 - 1) */ @@ -662,11 +662,8 @@ status_t eng_crtc_cursor_init() /* cursor bitmap will be stored at the start of the framebuffer */ const uint32 curadd = 0; - /* enable access to primary head */ - set_crtc_owner(0); - /* set cursor bitmap adress ... */ - if ((si->ps.card_arch == NV04A) || (si->ps.laptop)) + if (0)//(si->ps.card_arch == NV04A) || (si->ps.laptop)) { /* must be used this way on pre-NV10 and on all 'Go' cards! */ @@ -686,20 +683,24 @@ status_t eng_crtc_cursor_init() * This register does not exist on pre-NV10 and 'Go' cards. */ /* cursorbitmap must still start on 2Kbyte boundary: */ - ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800); +//via + /* background is black */ + CRTCDW(CURSOR_BG, 0x00000000); + /* foreground is white */ + CRTCDW(CURSOR_FG, 0x00ffffff); + /* set cursor bitmap adress */ + CRTCDW(CURSOR_MODE, (curadd & 0xfffffffc)); } - /* set cursor colour: not needed because of direct nature of cursor bitmap. */ - - /*clear cursor*/ + /* clear cursor (via cursor uses 4kb) */ fb = (uint32 *) si->framebuffer + curadd; - for (i=0;i<(2048/4);i++) + for (i=0;i<(4096/4);i++) { fb[i]=0; } /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - ENG_RG32(RG32_CURCONF) = 0x02000100; +// ENG_REG32(RG32_CURCONF) = 0x02000100; /* activate hardware cursor */ eng_crtc_cursor_show(); @@ -710,12 +711,7 @@ status_t eng_crtc_cursor_init() status_t eng_crtc_cursor_show() { LOG(4,("CRTC: enabling cursor\n")); - - /* enable access to CRTC1 on dualhead cards */ - set_crtc_owner(0); - - /* b0 = 1 enables cursor */ - CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); + CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) | 0x00000003)); return B_OK; } @@ -723,12 +719,7 @@ status_t eng_crtc_cursor_show() status_t eng_crtc_cursor_hide() { LOG(4,("CRTC: disabling cursor\n")); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* b0 = 0 disables cursor */ - CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); + CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) & 0xfffffffc)); return B_OK; } @@ -736,50 +727,50 @@ status_t eng_crtc_cursor_hide() /*set up cursor shape*/ status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask) { - int x, y; - uint8 b; + int y; + uint8 b,s; uint16 *cursor; - uint16 pixel; + uint16 data; /* get a pointer to the cursor */ cursor = (uint16*) si->framebuffer; /* draw the cursor */ - /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ for (y = 0; y < 16; y++) { - b = 0x80; - for (x = 0; x < 8; x++) + b = 0x01; + /* preset transparant */ + data = 0x0000; + for (s = 0; s < 15; s += 2) { - /* preset transparant */ - pixel = 0x0000; /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; + if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s); /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; + if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s); /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; + if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s); + b <<= 1; } + /* place the 8 pixels in the bitmap */ + cursor[0 + (y * 4)] = data; xorMask++; andMask++; - b = 0x80; - for (; x < 16; x++) + + b = 0x01; + /* preset transparant */ + data = 0x0000; + for (s = 0; s < 15; s += 2) { - /* preset transparant */ - pixel = 0x0000; /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; + if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s); /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; + if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s); /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; + if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s); + b <<= 1; } + /* place the 8 pixels in the bitmap */ + cursor[1 + (y * 4)] = data; xorMask++; andMask++; } @@ -790,40 +781,11 @@ status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask) /* position the cursor */ status_t eng_crtc_cursor_position(uint16 x, uint16 y) { - uint16 yhigh; - - /* make sure we are beyond the first line of the cursorbitmap being drawn during - * updating the position to prevent distortions: no double buffering feature */ - /* Note: - * we need to return as quick as possible or some apps will exhibit lagging.. */ - - /* read the old cursor Y position */ - yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16); - /* make sure we will wait until we are below both the old and new Y position: - * visible cursorbitmap drawing needs to be done at least... */ - if (y > yhigh) yhigh = y; - - if (yhigh < (si->dm.timing.v_display - 16)) - { - /* we have vertical lines below old and new cursorposition to spare. So we - * update the cursor postion 'mid-screen', but below that area. */ - while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16)) - { - snooze(10); - } - } - else - { - /* no room to spare, just wait for retrace (is relatively slow) */ - while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) - { - /* don't snooze much longer or retrace might get missed! */ - snooze(10); - } - } - + /* set cursor origin, b1-7 = Y offset; b17-23 = X offset + * (? linux seems non-consistent) */ + CRTCDW(CURSOR_ORG, 0x00000000); /* update cursorposition */ - DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); + CRTCDW(CURSOR_POS, (((x & 0x07ff) << 16) | (y & 0x07ff))); return B_OK; } diff --git a/src/add-ons/accelerants/via/engine/crtc2.c b/src/add-ons/accelerants/via/engine/crtc2.c index fa1c181259..bd8f91241f 100644 --- a/src/add-ons/accelerants/via/engine/crtc2.c +++ b/src/add-ons/accelerants/via/engine/crtc2.c @@ -592,7 +592,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) /* we might have no retraces during setmode! */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && + while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && (timeout < (25000/10))) { /* don't snooze much longer or retrace might get missed! */ @@ -609,7 +609,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) * wrap-around at 16Mb boundaries!! */ /* 30bit adress in 32bit words */ - ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); + ENG_REG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); /* set byte adress: (b0 - 1) */ ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); @@ -648,7 +648,7 @@ status_t eng_crtc2_cursor_init() * This register does not exist on pre-NV10 and 'Go' cards. */ /* cursorbitmap must still start on 2Kbyte boundary: */ - ENG_RG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800); + ENG_REG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800); } /* set cursor colour: not needed because of direct nature of cursor bitmap. */ @@ -661,7 +661,7 @@ status_t eng_crtc2_cursor_init() } /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - ENG_RG32(RG32_2CURCONF) = 0x02000100; + ENG_REG32(RG32_2CURCONF) = 0x02000100; /* activate hardware cursor */ eng_crtc2_cursor_show(); @@ -769,7 +769,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y) { /* we have vertical lines below old and new cursorposition to spare. So we * update the cursor postion 'mid-screen', but below that area. */ - while (((uint16)(ENG_RG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16)) + while (((uint16)(ENG_REG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16)) { snooze(10); } @@ -777,7 +777,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y) else { /* no room to spare, just wait for retrace (is relatively slow) */ - while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) + while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) { /* don't snooze much longer or retrace might get missed! */ snooze(10); diff --git a/src/add-ons/accelerants/via/engine/general.c b/src/add-ons/accelerants/via/engine/general.c index bf597d3eef..d9a33874b7 100644 --- a/src/add-ons/accelerants/via/engine/general.c +++ b/src/add-ons/accelerants/via/engine/general.c @@ -90,7 +90,7 @@ status_t eng_general_powerup() { status_t status; - LOG(1,("POWERUP: Haiku skeleton Accelerant 0.01 running.\n")); + LOG(1,("POWERUP: Haiku VIA Accelerant 0.01 running.\n")); /* preset no laptop */ si->ps.laptop = false; @@ -102,7 +102,7 @@ status_t eng_general_powerup() case 0x31221106: /* */ si->ps.card_type = NV04; si->ps.card_arch = NV04A; - LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n")); + LOG(4,("POWERUP: Detected VIA CLE266 Unichrome\n")); status = engxx_general_powerup(); break; default: @@ -416,7 +416,7 @@ status_t eng_general_head_select(bool cross) static status_t eng_general_bios_to_powergraphics() { /* let acc engine make power off/power on cycle to start 'fresh' */ -// ENG_RG32(RG32_PWRUPCTRL) = 0x13110011; +// ENG_REG32(RG32_PWRUPCTRL) = 0x13110011; snooze(1000); /* power-up all hardware function blocks */ @@ -429,7 +429,7 @@ static status_t eng_general_bios_to_powergraphics() * bit 8: PFIFO, * bit 4: PMEDIA, * bit 0: TVOUT. (> NV04A) */ -// ENG_RG32(RG32_PWRUPCTRL) = 0x13111111; +// ENG_REG32(RG32_PWRUPCTRL) = 0x13111111; /* select colormode CRTC registers base adresses */ // ENG_REG8(RG8_MISCW) = 0xcb; @@ -469,8 +469,8 @@ static status_t eng_general_bios_to_powergraphics() * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), * bit 8: TVout chip #1 (all cards), * bit 4: both I2C busses (all cards) */ - ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; - ENG_RG32(RG32_FUNCSEL) |= 0x00001000; + ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000; + ENG_REG32(RG32_FUNCSEL) |= 0x00001000; } si->overlay.crtc = false; diff --git a/src/add-ons/accelerants/via/engine/info.c b/src/add-ons/accelerants/via/engine/info.c index fe34991feb..e6549f5fce 100644 --- a/src/add-ons/accelerants/via/engine/info.c +++ b/src/add-ons/accelerants/via/engine/info.c @@ -311,8 +311,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta //fixme?: works on at least one NV28... how about other cards? if (si->ps.card_type == NV28) { - fb_mrs2 = ENG_RG32(RG32_FB_MRS2); - fb_mrs1 = ENG_RG32(RG32_FB_MRS1); + fb_mrs2 = ENG_REG32(RG32_FB_MRS2); + fb_mrs1 = ENG_REG32(RG32_FB_MRS1); } /* select colormode CRTC registers base adresses */ @@ -381,8 +381,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta /* get NV28 RAM access up and running */ //fixme?: works on at least one NV28... how about other cards? - ENG_RG32(RG32_FB_MRS2) = fb_mrs2; - ENG_RG32(RG32_FB_MRS1) = fb_mrs1; + ENG_REG32(RG32_FB_MRS2) = fb_mrs2; + ENG_REG32(RG32_FB_MRS1) = fb_mrs1; } /* now enable ROM shadow or the card will remain shut-off! */ @@ -448,7 +448,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 float calced_clk; uint8 m, n, p; eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); - ENG_RG32(reg) = ((p << 16) | (n << 8) | m); + ENG_REG32(reg) = ((p << 16) | (n << 8) | m); } log_pll(reg, data2); break; @@ -470,7 +470,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 adress += 2; data2 = *((uint32*)(&(rom[data]))); LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); - if (exec) ENG_RG32(reg) = data2; + if (exec) ENG_REG32(reg) = data2; break; case 0x63: *size -= 1; @@ -509,8 +509,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", reg, data, data2)); /* always done */ - ENG_RG32(reg) = data; - ENG_RG32(reg) = data2; + ENG_REG32(reg) = data; + ENG_REG32(reg) = data2; CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); break; case 0x69: @@ -554,7 +554,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 /* execute */ adress += 1; - data = ENG_RG32(RG32_NV4STRAPINFO); + data = ENG_REG32(RG32_NV4STRAPINFO); and_out = *((uint8*)(&(rom[adress]))); adress += 1; byte = *((uint8*)(&(rom[adress]))); @@ -594,10 +594,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 reg, and_out, or_in)); if (exec) { - data = ENG_RG32(reg); + data = ENG_REG32(reg); data &= and_out; data |= or_in; - ENG_RG32(reg) = data; + ENG_REG32(reg) = data; } break; case 0x71: @@ -637,7 +637,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 /* execute */ adress += 1; - data = ENG_RG32(RG32_NVSTRAPINFO2); + data = ENG_REG32(RG32_NVSTRAPINFO2); and_out = *((uint32*)(&(rom[adress]))); adress += 4; data2 = *((uint32*)(&(rom[adress]))); @@ -691,7 +691,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 adress += 2; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", reg, data)); - if (exec) ENG_RG32(reg) = data; + if (exec) ENG_REG32(reg) = data; break; case 0x78: *size -= 6; @@ -747,7 +747,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 float calced_clk; uint8 m, n, p; eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); - ENG_RG32(reg) = ((p << 16) | (n << 8) | m); + ENG_REG32(reg) = ((p << 16) | (n << 8) | m); } log_pll(reg, (data / 100)); break; @@ -768,7 +768,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 data = *((uint32*)(&(rom[adress]))); adress += 4; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (exec) ENG_RG32(reg) = data; + if (exec) ENG_REG32(reg) = data; break; default: LOG(8,("unknown cmd, aborting!\n\n")); @@ -828,9 +828,9 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) uint8 cnt; /* set MRS = 256 */ - ENG_RG32(RG32_PFB_DEBUG_0) &= 0xffffffef; + ENG_REG32(RG32_PFB_DEBUG_0) &= 0xffffffef; /* read RAM config hardware(?) strap */ - ram_cfg = ((ENG_RG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f); + ram_cfg = ((ENG_REG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f); LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); /* use it as a pointer in a BIOS table for prerecorded RAM configurations */ ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); @@ -876,15 +876,15 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) break; } /* set RAM amount, width and type */ - data = (ENG_RG32(RG32_NV4STRAPINFO) & 0xffffffc0); - ENG_RG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); + data = (ENG_REG32(RG32_NV4STRAPINFO) & 0xffffffc0); + ENG_REG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); /* setup write to read delay (?) */ - data = (ENG_RG32(RG32_PFB_CONFIG_1) & 0xff8ffffe); + data = (ENG_REG32(RG32_PFB_CONFIG_1) & 0xff8ffffe); data |= ((ram_cfg & 0x00000700) << 12); /* force update via b0 = 0... */ - ENG_RG32(RG32_PFB_CONFIG_1) = data; + ENG_REG32(RG32_PFB_CONFIG_1) = data; /* ... followed by b0 = 1(?) */ - ENG_RG32(RG32_PFB_CONFIG_1) = (data | 0x00000001); + ENG_REG32(RG32_PFB_CONFIG_1) = (data | 0x00000001); /* do RAM width test to confirm RAM width set to be correct */ /* write testpattern to first 128 bits of graphics memory... */ @@ -896,7 +896,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) if (((uint32 *)si->framebuffer)[3] != data) { LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); - ENG_RG32(RG32_NV4STRAPINFO) &= ~0x00000004; + ENG_REG32(RG32_NV4STRAPINFO) &= ~0x00000004; } else { @@ -963,11 +963,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); if (*exec && reg2) { - data = ENG_RG32(reg); + data = ENG_REG32(reg); data &= and_out; data >>= shift; data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); - ENG_RG32(reg2) = data2; + ENG_REG32(reg2) = data2; } *adress += size32; break; @@ -1009,7 +1009,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, byte >>= byte2; offset32 = (byte << 2); data = *((uint32*)(&(rom[(*adress + offset32)]))); - ENG_RG32(reg2) = data; + ENG_REG32(reg2) = data; } *adress += size32; break; @@ -1102,10 +1102,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, uint8 m, n, p; eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data = ENG_RG32(reg2); - ENG_RG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); - data = ENG_RG32(reg2); - ENG_RG32(reg2) = ((p << 16) | (n << 8) | m); + data = ENG_REG32(reg2); + ENG_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); + data = ENG_REG32(reg2); + ENG_REG32(reg2) = ((p << 16) | (n << 8) | m); //fixme? /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) @@ -1178,7 +1178,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, index, reg2, and_out2)); if (*exec) { - data = ENG_RG32(reg); + data = ENG_REG32(reg); if (byte2 < 0x80) { data >>= byte2; @@ -1274,12 +1274,12 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, *adress += 1; data2 = *((uint8*)(&(rom[*adress]))); *adress += 1; - ENG_RG32(reg2) = data2; - data = ENG_RG32(reg); + ENG_REG32(reg2) = data2; + data = ENG_REG32(reg); data &= and_out; data |= or_in; data |= or_in2; - ENG_RG32(reg) = data; + ENG_REG32(reg) = data; } } else @@ -1380,8 +1380,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", reg, data, data2)); /* always done */ - ENG_RG32(reg) = data; - ENG_RG32(reg) = data2; + ENG_REG32(reg) = data; + ENG_REG32(reg) = data2; CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); break; case 0x69: /* identical to type1 */ @@ -1479,10 +1479,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, reg, and_out, or_in)); if (*exec) { - data = ENG_RG32(reg); + data = ENG_REG32(reg); data &= and_out; data |= or_in; - ENG_RG32(reg) = data; + ENG_REG32(reg) = data; } break; case 0x6f: /* new */ @@ -1522,7 +1522,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, { reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); - ENG_RG32(reg2) = data2; + ENG_REG32(reg2) = data2; safe32++; } } @@ -1598,7 +1598,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, reg = *((uint32*)(&(rom[data]))); and_out = *((uint32*)(&(rom[(data + 4)]))); data2 = *((uint32*)(&(rom[(data + 8)]))); - data = ENG_RG32(reg); + data = ENG_REG32(reg); data &= and_out; LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", and_out, reg, data2)); @@ -1701,10 +1701,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, uint8 m, n, p; eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data2 = ENG_RG32(reg); - ENG_RG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); - data2 = ENG_RG32(reg); - ENG_RG32(reg) = ((p << 16) | (n << 8) | m); + data2 = ENG_REG32(reg); + ENG_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); + data2 = ENG_REG32(reg); + ENG_REG32(reg) = ((p << 16) | (n << 8) | m); //fixme? /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) @@ -1729,7 +1729,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, data = *((uint32*)(&(rom[*adress]))); *adress += 4; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (*exec) ENG_RG32(reg) = data; + if (*exec) ENG_REG32(reg) = data; break; default: LOG(8,("unknown cmd, aborting!\n\n")); @@ -1787,7 +1787,7 @@ static void setup_ram_config_nv10_up(uint8* rom) status_t stat = B_ERROR; /* set 'refctrl is valid' */ - ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; + ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000; /* check RAM for 256bits buswidth(?) */ while ((cnt < 4) && (stat != B_OK)) @@ -1810,7 +1810,7 @@ static void setup_ram_config_nv10_up(uint8* rom) if (stat != B_OK) { LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); - data = ENG_RG32(RG32_PFB_CONFIG_0); + data = ENG_REG32(RG32_PFB_CONFIG_0); if (data & 0x00000010) { data &= 0xffffffcf; @@ -1820,7 +1820,7 @@ static void setup_ram_config_nv10_up(uint8* rom) data &= 0xffffffcf; data |= 0x00000020; } - ENG_RG32(RG32_PFB_CONFIG_0) = data; + ENG_REG32(RG32_PFB_CONFIG_0) = data; } else { @@ -1833,7 +1833,7 @@ static void setup_ram_config_nv10_up(uint8* rom) while ((cnt < 4) && (stat != B_OK)) { /* read RAM size */ - data = ENG_RG32(RG32_NV10STRAPINFO); + data = ENG_REG32(RG32_NV10STRAPINFO); /* subtract 1MB */ data -= 0x00100000; /* write testpattern at generated RAM adress */ @@ -1854,7 +1854,7 @@ static void setup_ram_config_nv10_up(uint8* rom) if (stat != B_OK) { LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); - ENG_RG32(RG32_PFB_CONFIG_0) &= 0xffffefff; + ENG_REG32(RG32_PFB_CONFIG_0) &= 0xffffefff; } else { @@ -1871,13 +1871,13 @@ static void setup_ram_config_nv28(uint8* rom) status_t stat = B_ERROR; /* set 'refctrl is valid' */ - ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; + ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000; /* check RAM */ while ((cnt < 4) && (stat != B_OK)) { /* set bit 11: 'pulse' something into a new setting? */ - ENG_RG32(RG32_PFB_CONFIG_0) |= 0x00000800; + ENG_REG32(RG32_PFB_CONFIG_0) |= 0x00000800; /* write testpattern to RAM adress 127Mb */ ((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; /* reset first RAM adress */ @@ -1897,7 +1897,7 @@ static void setup_ram_config_nv28(uint8* rom) } /* clear bit 11: set normal mode */ - ENG_RG32(RG32_PFB_CONFIG_0) &= ~0x00000800; + ENG_REG32(RG32_PFB_CONFIG_0) &= ~0x00000800; if (stat == B_OK) LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); @@ -2334,7 +2334,7 @@ static void detect_panels() /* dump some panel configuration registers... */ LOG(2,("INFO: Dumping flatpanel registers:\n")); - LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_RG32(RG32_DUALHEAD_CTRL))); + LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_REG32(RG32_DUALHEAD_CTRL))); LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); @@ -2359,8 +2359,8 @@ static void detect_panels() LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); - LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_RG32(RG32_FUNCSEL))); - LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_RG32(RG32_PANEL_PWR))); + LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_REG32(RG32_FUNCSEL))); + LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_REG32(RG32_PANEL_PWR))); if(si->ps.secondary_head) { @@ -2388,8 +2388,8 @@ static void detect_panels() LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); - LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_RG32(RG32_2FUNCSEL))); - LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_RG32(RG32_2PANEL_PWR))); + LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_REG32(RG32_2FUNCSEL))); + LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_REG32(RG32_2PANEL_PWR))); } LOG(2,("INFO: End flatpanel registers dump.\n")); } @@ -2850,7 +2850,7 @@ static void pinsnv30_arch_fake(void) static void getRAMsize_arch_nv4(void) { - uint32 strapinfo = ENG_RG32(RG32_NV4STRAPINFO); + uint32 strapinfo = ENG_REG32(RG32_NV4STRAPINFO); if (strapinfo & 0x00000100) { @@ -2883,7 +2883,7 @@ static void getRAMsize_arch_nv4(void) static void getstrap_arch_nv4(void) { - uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); + uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2); /* determine PLL reference crystal frequency */ if (strapinfo & 0x00000040) @@ -2898,7 +2898,7 @@ static void getstrap_arch_nv4(void) static void getRAMsize_arch_nv10_20_30_40(void) { uint32 dev_manID = CFGR(DEVID); - uint32 strapinfo = ENG_RG32(RG32_NV10STRAPINFO); + uint32 strapinfo = ENG_REG32(RG32_NV10STRAPINFO); switch (dev_manID) { @@ -2950,7 +2950,7 @@ static void getRAMsize_arch_nv10_20_30_40(void) static void getstrap_arch_nv10_20_30_40(void) { uint32 dev_manID = CFGR(DEVID); - uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); + uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2); /* determine PLL reference crystal frequency: three types are used... */ if (strapinfo & 0x00000040)