From 5e87e39562345d1e654b92540a63cb50a0e59c0b Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Sat, 24 Mar 2012 21:08:28 -0500 Subject: [PATCH] radeon_hd: Don't pass old pixel clock to encoder * pll_set can make pixel clock adjustments. * Anything after pll_set should use encoder pll to ensure adjustments are picked up. --- src/add-ons/accelerants/radeon_hd/encoder.cpp | 10 +++++++--- src/add-ons/accelerants/radeon_hd/encoder.h | 2 +- src/add-ons/accelerants/radeon_hd/mode.cpp | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp b/src/add-ons/accelerants/radeon_hd/encoder.cpp index da10cffbbe..d4fe6ea736 100644 --- a/src/add-ons/accelerants/radeon_hd/encoder.cpp +++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp @@ -282,12 +282,16 @@ encoder_apply_quirks(uint8 crtcID) void -encoder_mode_set(uint8 id, uint32 pixelClock) +encoder_mode_set(uint8 crtcID) { TRACE("%s\n", __func__); radeon_shared_info &info = *gInfo->shared_info; - uint32 connectorIndex = gDisplay[id]->connectorIndex; + uint32 connectorIndex = gDisplay[crtcID]->connectorIndex; uint16 encoderFlags = gConnector[connectorIndex]->encoder.flags; + pll_info* pll = &gConnector[connectorIndex]->encoder.pll; + + // Adjusted pixel clock (*NOT* original mode pixel clock) + uint32 pixelClock = pll->pixelClock; switch (gConnector[connectorIndex]->encoder.objectID) { case ENCODER_OBJECT_ID_INTERNAL_DAC1: @@ -367,7 +371,7 @@ encoder_mode_set(uint8 id, uint32 pixelClock) } } - encoder_apply_quirks(id); + encoder_apply_quirks(crtcID); } diff --git a/src/add-ons/accelerants/radeon_hd/encoder.h b/src/add-ons/accelerants/radeon_hd/encoder.h index 2451c625f0..6d3a03bc73 100644 --- a/src/add-ons/accelerants/radeon_hd/encoder.h +++ b/src/add-ons/accelerants/radeon_hd/encoder.h @@ -17,7 +17,7 @@ void encoder_assign_crtc(uint8 crtcID); uint32 encoder_pick_dig(uint32 connectorIndex); void encoder_apply_quirks(uint8 crtcID); -void encoder_mode_set(uint8 id, uint32 pixelClock); +void encoder_mode_set(uint8 crtcID); status_t encoder_analog_setup(uint32 connectorIndex, uint32 pixelClock, int command); status_t encoder_digital_setup(uint32 connectorIndex, diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index 30db993dc9..e79d3a4826 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -193,7 +193,7 @@ radeon_set_display_mode(display_mode* mode) display_crtc_scale(id, mode); // *** encoder mode set - encoder_mode_set(id, mode->timing.pixel_clock); + encoder_mode_set(id); // *** CRT controler commit display_crtc_dpms(id, B_DPMS_ON);