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fixed PLL locking trouble on NV36 (confirmed) and problably more cards (NV31, NV40 and higher): those with extended PLL's.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11404 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-02-17 13:47:54 +00:00
parent cb9c0a693e
commit 6072aa9f44
1 changed files with 14 additions and 4 deletions
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src/add-ons/accelerants/nvidia/engine/nv_info.c
+14 -4
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@@ -2838,10 +2838,20 @@ static void pinsnv30_arch_fake(void)
/* carefull not to take to high limits, and high should be >= 2x low. */ /* carefull not to take to high limits, and high should be >= 2x low. */
si->ps.max_system_vco = 350; si->ps.max_system_vco = 350;
si->ps.min_system_vco = 128; si->ps.min_system_vco = 128;
si->ps.max_pixel_vco = 350; if (si->ps.ext_pll)
si->ps.min_pixel_vco = 128; {
si->ps.max_video_vco = 350; si->ps.max_pixel_vco = 600;
si->ps.min_video_vco = 128; si->ps.min_pixel_vco = 220;
si->ps.max_video_vco = 600;
si->ps.min_video_vco = 220;
}
else
{
si->ps.max_pixel_vco = 350;
si->ps.min_pixel_vco = 128;
si->ps.max_video_vco = 350;
si->ps.min_video_vco = 128;
}
si->ps.max_dac1_clock = 350; si->ps.max_dac1_clock = 350;
si->ps.max_dac1_clock_8 = 350; si->ps.max_dac1_clock_8 = 350;
si->ps.max_dac1_clock_16 = 350; si->ps.max_dac1_clock_16 = 350;