From 61291964c3e6cc275ece67168ea4b9631338f861 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Axel=20D=C3=B6rfler?= Date: Wed, 31 Oct 2007 19:23:59 +0000 Subject: [PATCH] The intel_extreme driver now finally works with the i965 chipset; acceleration works fine, but overlay doesn't - that's next on my list. Turns out the i965 differentiates between RGB-32 and RGB-32-alpha, and didn't like trying to use the latter as display mode (the i865 didn't care at all)... finding that took me *way* too long, though. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22780 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../private/graphics/intel_extreme/intel_extreme.h | 2 +- src/add-ons/accelerants/intel_extreme/mode.cpp | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index dcd6c37790..9bee7131bc 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -204,7 +204,7 @@ struct intel_free_graphics_memory { #define DISPLAY_CONTROL_CMAP8 (2UL << 26) #define DISPLAY_CONTROL_RGB15 (4UL << 26) #define DISPLAY_CONTROL_RGB16 (5UL << 26) -#define DISPLAY_CONTROL_RGB32 (7UL << 26) +#define DISPLAY_CONTROL_RGB32 (6UL << 26) #define INTEL_VGA_DISPLAY_CONTROL 0x71400 #define VGA_DISPLAY_DISABLED (1UL << 31) diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index 8d671d7537..08e5d3c4b4 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -483,12 +483,7 @@ if (first) { write32(INTEL_DISPLAY_A_PLL, pll); read32(INTEL_DISPLAY_A_PLL); spin(150); -#if 0 - write32(INTEL_DISPLAY_A_PLL, DISPLAY_PLL_ENABLED | DISPLAY_PLL_2X_CLOCK - | DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_DIVIDE_4X - | (((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) & DISPLAY_PLL_POST1_DIVISOR_MASK) - | (divisorRegister == INTEL_DISPLAY_A_PLL_DIVISOR_1 ? DISPLAY_PLL_DIVISOR_1 : 0)); -#endif + // update timing parameters write32(INTEL_DISPLAY_A_HTOTAL, ((uint32)(target.timing.h_total - 1) << 16) | ((uint32)target.timing.h_display - 1)); @@ -513,6 +508,9 @@ if (first) { | ((target.timing.flags & B_POSITIVE_VSYNC) != 0 ? DISPLAY_MONITOR_POSITIVE_VSYNC : 0)); } + // TODO: verify the two comments below: the X driver doesn't seem to + // care about both of them! + // These two have to be set for display B, too - this obviously means // that the second head always must adopt the color space of the first // head. @@ -650,6 +648,8 @@ intel_get_display_mode(display_mode *_currentMode) status_t intel_get_edid_info(void* info, size_t size, uint32* _version) { + TRACE(("intel_get_edid_info()\n")); + if (!gInfo->has_edid) return B_ERROR; if (size < sizeof(struct edid1_info))