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* No longer switch between divisor register set 0 and 1; it doesn't really

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make any sense.
* "pll" might have been set incorrectly on i8xx chips.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22253 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2007-09-19 15:07:58 +00:00
parent 46189f70a9
commit 61dad86a02
2 changed files with 16 additions and 17 deletions
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src/add-ons/accelerants/intel_extreme/dpms.cpp
+4 -1
View File
@@ -1,5 +1,5 @@
/* /*
* Copyright 2006, Haiku, Inc. All Rights Reserved. * Copyright 2006-2007, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License. * Distributed under the terms of the MIT License.
* *
* Authors: * Authors:
@@ -109,6 +109,9 @@ set_display_power_mode(uint32 mode)
enable_display_plane(false); enable_display_plane(false);
enable_display_pipe(false); enable_display_pipe(false);
} }
read32(INTEL_DISPLAY_A_BASE);
// flush the eventually cached PCI bus writes
} }
src/add-ons/accelerants/intel_extreme/mode.cpp
+12 -16
View File
@@ -432,24 +432,17 @@ if (first) {
pll_divisors divisors; pll_divisors divisors;
compute_pll_divisors(target, divisors); compute_pll_divisors(target, divisors);
// switch divisor register with every mode change (not required) write32(INTEL_DISPLAY_A_PLL_DIVISOR_0,
uint32 divisorRegister;
if (gInfo->shared_info->pll_info.divisor_register == INTEL_DISPLAY_A_PLL_DIVISOR_0)
divisorRegister = INTEL_DISPLAY_A_PLL_DIVISOR_1;
else
divisorRegister = INTEL_DISPLAY_A_PLL_DIVISOR_0;
write32(divisorRegister,
(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK) (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK)
| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK) | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK));
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL; uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
// pll |= ((1 << (divisors.post1 - 1)) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) pll |= ((1 << (divisors.post1 - 1)) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
// pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
if (divisors.post2_high) if (divisors.post2_high)
pll |= DISPLAY_PLL_DIVIDE_HIGH; pll |= DISPLAY_PLL_DIVIDE_HIGH;
@@ -460,12 +453,15 @@ if (first) {
} else { } else {
if (divisors.post2_high) if (divisors.post2_high)
pll |= DISPLAY_PLL_DIVIDE_4X; pll |= DISPLAY_PLL_DIVIDE_4X;
pll |= DISPLAY_PLL_2X_CLOCK;
pll |= (((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_POST1_DIVISOR_MASK);
}
pll |= (divisorRegister == INTEL_DISPLAY_A_PLL_DIVISOR_1 ? DISPLAY_PLL_DIVISOR_1 : 0); pll |= DISPLAY_PLL_2X_CLOCK;
if (divisors.post1 > 2) {
pll |= (((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_POST1_DIVISOR_MASK);
} else
pll |= DISPLAY_PLL_POST1_DIVIDE_2;
}
debug_printf("PLL is %#lx, write: %#lx\n", read32(INTEL_DISPLAY_A_PLL), pll); debug_printf("PLL is %#lx, write: %#lx\n", read32(INTEL_DISPLAY_A_PLL), pll);
write32(INTEL_DISPLAY_A_PLL, pll); write32(INTEL_DISPLAY_A_PLL, pll);