updated head sel code for NV11 special treatment

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@7314 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

@@ -144,8 +144,8 @@ status_t nv_crtc_set_timing(display_mode target)
 	/* prevent memory adress counter from being reset (linecomp may not occur) */
 	linecomp = target.timing.v_display;
 
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* Note for laptop and DVI flatpanels:
 	 * CRTC timing has a seperate set of registers from flatpanel timing.
@@ -413,8 +413,8 @@ status_t nv_crtc_depth(int mode)
 		genctrl = 0x00101130;
 		break;
 	}
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay));
 	DACW(GENCTRL, genctrl);
@@ -428,8 +428,8 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
 
 	LOG(4,("CRTC: setting DPMS: "));
 
-	/* enable access to CRTC1 (and SEQUENCER1) on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* start synchronous reset: required before turning screen off! */
 	SEQW(RESET, 0x01);
@@ -484,8 +484,8 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
 
 status_t nv_crtc_dpms_fetch(bool *display, bool *h, bool *v)
 {
-	/* enable access to CRTC1 (and SEQUENCER1) on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	*display = !(SEQR(CLKMODE) & 0x20);
 	*h = !(CRTCR(REPAINT1) & 0x80);
@@ -513,8 +513,8 @@ status_t nv_crtc_set_display_pitch()
 
 	LOG(2,("CRTC: offset register set to: $%04x\n", offset));
 
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* program the card */
 	CRTCW(PITCHL, (offset & 0x00ff));
@@ -544,8 +544,8 @@ status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp)
 		timeout++;
 	}
 
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	if (si->ps.card_arch == NV04A)
 	{
@@ -588,8 +588,8 @@ status_t nv_crtc_cursor_init()
 	/* cursor bitmap will be stored at the start of the framebuffer */
 	const uint32 curadd = 0;
 
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* set cursor bitmap adress ... */
 	if ((si->ps.card_arch == NV04A) || (si->ps.laptop))
@@ -638,7 +638,7 @@ status_t nv_crtc_cursor_show()
 	LOG(4,("CRTC: enabling cursor\n"));
 
 	/* enable access to CRTC1 on dualhead cards */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* b0 = 1 enables cursor */
 	CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01));
@@ -650,8 +650,8 @@ status_t nv_crtc_cursor_hide()
 {
 	LOG(4,("CRTC: disabling cursor\n"));
 
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
 	/* b0 = 0 disables cursor */
 	CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

@@ -130,8 +130,8 @@ status_t nv_crtc2_set_timing(display_mode target)
 	/* prevent memory adress counter from being reset (linecomp may not occur) */
 	linecomp = target.timing.v_display;
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* Note for laptop and DVI flatpanels:
 	 * CRTC timing has a seperate set of registers from flatpanel timing.
@@ -396,8 +396,8 @@ status_t nv_crtc2_depth(int mode)
 		genctrl = 0x00101130;
 		break;
 	}
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay));
 	DAC2W(GENCTRL, genctrl);
@@ -411,8 +411,8 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
 
 	LOG(4,("CRTC2: setting DPMS: "));
 
-	/* enable access to CRTC2 (and SEQUENCER2) */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* start synchronous reset: required before turning screen off! */
 	SEQW(RESET, 0x01);
@@ -467,8 +467,8 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
 
 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
 {
-	/* enable access to CRTC2 (and SEQUENCER2) */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	*display = !(SEQR(CLKMODE) & 0x20);
 	*h = !(CRTC2R(REPAINT1) & 0x80);
@@ -496,8 +496,8 @@ status_t nv_crtc2_set_display_pitch()
 
 	LOG(2,("CRTC2: offset register set to: $%04x\n", offset));
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* program the card */
 	CRTC2W(PITCHL, (offset & 0x00ff));
@@ -526,8 +526,8 @@ status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)
 		timeout++;
 	}
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* upto 4Gb RAM adressing: must be used on NV10 and later! */
 	/* NOTE:
@@ -550,8 +550,8 @@ status_t nv_crtc2_cursor_init()
 	/* cursor bitmap will be stored at the start of the framebuffer */
 	const uint32 curadd = 0;
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* set cursor bitmap adress ... */
 	if (si->ps.laptop)
@@ -599,8 +599,8 @@ status_t nv_crtc2_cursor_show()
 {
 	LOG(4,("CRTC2: enabling cursor\n"));
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* b0 = 1 enables cursor */
 	CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01));
@@ -612,8 +612,8 @@ status_t nv_crtc2_cursor_hide()
 {
 	LOG(4,("CRTC2: disabling cursor\n"));
 
-	/* enable access to CRTC2 */
+	/* enable access to secondary head */
-	CRTC2W(OWNER, 0x03);
+	set_crtc_owner(1);
 
 	/* b0 = 0 disables cursor */
 	CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe));

src/add-ons/accelerants/nvidia/engine/nv_general.c

@@ -80,7 +80,7 @@ status_t nv_general_powerup()
 {
 	status_t status;
 
-	LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.10-15 running.\n"));
+	LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.10-16 running.\n"));
 
 	/* preset no laptop */
 	si->ps.laptop = false;
@@ -770,6 +770,35 @@ void setup_virtualized_heads(bool cross)
 	}
 }
 
+void set_crtc_owner(bool head)
+{
+	if (si->ps.secondary_head)
+	{
+		if (!head)
+		{
+			/* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's,
+			 * while non-NV11 cards behave normally.
+			 *
+			 * Double-write action needed on those strange NV11 cards: */
+			/* RESET: needed on NV11 */
+			CRTCW(OWNER, 0xff);
+			/* enable access to CRTC1, SEQ1, GRPH1, ATB1, ??? */
+			CRTCW(OWNER, 0x00);
+		}
+		else
+		{
+			/* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's,
+			 * while non-NV11 cards behave normally.
+			 *
+			 * Double-write action needed on those strange NV11 cards: */
+			/* RESET: needed on NV11 */
+			CRTC2W(OWNER, 0xff);
+			/* enable access to CRTC2, SEQ2, GRPH2, ATB2, ??? */
+			CRTC2W(OWNER, 0x03);
+		}
+	}
+}
+
 static status_t nvxx_general_powerup()
 {
 	status_t result;
@@ -973,13 +1002,16 @@ static status_t nv_general_bios_to_powergraphics()
 	/* select colormode CRTC registers base adresses */
 	NV_REG8(NV8_MISCW) = 0xcb;
 
-	/* unlock card registers for R/W access */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
+	/* unlock head's registers for R/W access */
 	CRTCW(LOCK, 0x57);
 	CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
 	if (si->ps.secondary_head)
 	{
-		CRTC2W(OWNER, 0x03);
+		/* enable access to secondary head */
+		set_crtc_owner(1);
+		/* unlock head's registers for R/W access */
 		CRTC2W(LOCK, 0x57);
 		CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
 	}
@@ -1006,7 +1038,7 @@ static status_t nv_general_bios_to_powergraphics()
 
 	/* enable 'enhanced' mode on primary head: */
 	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 	/* note: 'BUFFER' is a non-standard register in behaviour(!) on most
 	 * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards
 	 * behave normally.
@@ -1036,8 +1068,8 @@ static status_t nv_general_bios_to_powergraphics()
 	/* enable 'enhanced' mode on secondary head: */
 	if (si->ps.secondary_head)
 	{
-		/* enable access to secondary head (is SEQ2, GRPH2, CRTC2, ATB2, etc!!) */
+		/* enable access to secondary head */
-		CRTC2W(OWNER, 0x03);
+		set_crtc_owner(1);
 		/* select colormode CRTC2 registers base adresses */
 		NV_REG8(NV8_MISCW) = 0xcb;
 		/* note: 'BUFFER' is a non-standard register in behaviour(!) on most

src/add-ons/accelerants/nvidia/engine/nv_info.c

@@ -270,10 +270,10 @@ static void detect_panels()
 	bool tvout1 = false, tvout2 = false;
 
 	/* check primary head: */
-	/* enable access to CRTC1 on dualhead cards */
+	/* enable access to primary head */
-	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
+	set_crtc_owner(0);
 
-	/* unlock CRTC1 */
+	/* unlock head's registers for R/W access */
 	CRTCW(LOCK, 0x57);
 	CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
 
@@ -293,9 +293,9 @@ static void detect_panels()
 	if (si->ps.secondary_head)
 	{
 		/* check secondary head: */
-		/* enable access to CRTC2 */
+		/* enable access to secondary head */
-		CRTC2W(OWNER, 0x03);
+		set_crtc_owner(1);
-		/* unlock CRTC2 */
+		/* unlock head's registers for R/W access */
 		CRTC2W(LOCK, 0x57);
 		CRTC2W(VSYNCE ,(CRTC2R(VSYNCE) & 0x7f));
 

src/add-ons/accelerants/nvidia/engine/nv_proto.h

@@ -2,6 +2,7 @@
 status_t nv_general_powerup(void);
 status_t nv_set_cas_latency(void);
 void setup_virtualized_heads(bool);
+void set_crtc_owner(bool);
 status_t nv_general_output_select(bool);
 status_t nv_general_head_select(bool);
 status_t nv_general_wait_retrace(void);

src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html

@@ -4,7 +4,7 @@
 </head>
 <body>
 <p><h2>Changes done for each driverversion:</h2></p>
-<p><h1>head (0.10-15), (Rudolf)</h1></p>
+<p><h1>head (0.10-16), (Rudolf)</h1></p>
 <ul>
 	<li>Implemented laptop internal flatpanel presence and native resolution detection;
 	<li>Implemented external DVI flatpanel(s) presence and native resolution detection;
@@ -27,7 +27,8 @@
 	<li>Added dualhead switch mode for NV11 (works via virtualized head access implemented now);
 	<li>Modified dualhead switch mode for all other cards to work via the virtualized head access also;
 	<li>Modified overlay to work correctly with the virtualized setup;
-	<li>Added output-devices/heads matrix setup: the driver now selects the right head for primary output and dualhead should work for all cards with all monitor-types now (fixme: NV11 setup is yet incomplete).
+	<li>Added output-devices/heads matrix setup: the driver now selects the right head for primary output and dualhead should work for all cards with all monitor-types now;
+	<li>Updated head selection code for register programming: NV11 needs a special treatment (again); NV11 dualhead modes are finally OK now, including switch mode.
 </ul>
 <p><h1>nv_driver 0.09, (Rudolf)</h1></p>
 <ul>