diff --git a/src/add-ons/kernel/drivers/graphics/radeon/vip.c b/src/add-ons/kernel/drivers/graphics/radeon/vip.c
index 9c5c2b7e27..e4fcef35bf 100644
--- a/src/add-ons/kernel/drivers/graphics/radeon/vip.c
+++ b/src/add-ons/kernel/drivers/graphics/radeon/vip.c
@@ -226,38 +226,43 @@ bool Radeon_VIPWrite(device_info *di, uint8 channel, uint address, uint32 data,
 static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
 {
 	vuint8 *regs = di->regs;
-    
-    uint32 status;
+
+	uint32 status;
 	uint32 i;
-	
+
 	SHOW_FLOW( 2, "address=%lx, count=%ld, ", address, count );
 
-    Radeon_WaitForFifo( di, 2 );
-    OUTREG( regs, RADEON_VIPH_REG_ADDR, ((channel << 14) | address | 0x1000) & ~0x2000 );
-   	SHOW_FLOW0( 2, "1");
-    while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
-	
-    
-    if(B_OK != status){
+	Radeon_WaitForFifo( di, 2 );
+	OUTREG( regs, RADEON_VIPH_REG_ADDR, ((channel << 14) | address | 0x1000) & ~0x2000 );
+	SHOW_FLOW0( 2, "1");
+	do {
+		status = RADEON_VIPFifoIdle(di, 0x0f);
+	} while (status == B_BUSY);
+
+	if(B_OK != status){
 		SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
 		return false;
 	}
-    
-    SHOW_FLOW0( 2, "2");
+
+	SHOW_FLOW0( 2, "2");
 	for (i = 0; i < count; i+=4)
 	{
 		Radeon_WaitForFifo( di, 2);
 		SHOW_FLOW( 2, "count %ld", count);
 		OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));
-		while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
+
+		do {
+			status = RADEON_VIPFifoIdle(di, 0x0f);
+		} while (status == B_BUSY);
+
     	if(B_OK != status)
 		{
     		SHOW_FLOW0( 2 , "cannot write to VIPH_REG_DATA\n");
 			return false;
-	 	}
+		}
 	}
 				
-    return true;
+	return true;
 }
 
 bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)