radeon_hd: Add DP link_train_ce
* First attempts at DisplayPort link training clock equalization. * Add DP define to detect equalization state * Working towards resolving #8626
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@@ -168,6 +168,12 @@
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#define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool
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#define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool
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#define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool
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#define DP_LANE_STATUS_EQUALIZED_A DP_LANE_STATUS_CR_DONE_A \
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|| DP_LANE_STATUS_CHEQ_DONE_A \
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|| DP_LANE_STATUS_SYMB_LOCK_A
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#define DP_LANE_STATUS_EQUALIZED_B DP_LANE_STATUS_CR_DONE_B \
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|| DP_LANE_STATUS_CHEQ_DONE_B \
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|| DP_LANE_STATUS_SYMB_LOCK_B
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// DP Lane Align Status (0x0204)
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#define DP_LANE_ALIGN 0x0204 // Reg
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#define DP_LANE_ALIGN_DONE (1 << 0) // Bool
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