diff --git a/build/jam/HaikuImage b/build/jam/HaikuImage index 3f60443324..603b845a35 100644 --- a/build/jam/HaikuImage +++ b/build/jam/HaikuImage @@ -169,7 +169,7 @@ SYSTEM_ADD_ONS_DRIVERS_GRAPHICS = $(X86_ONLY)radeon $(X86_ONLY)nvidia SYSTEM_ADD_ONS_DRIVERS_MIDI = emuxki usb_midi ; SYSTEM_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com $(X86_ONLY)atheros813x $(X86_ONLY)ar81xx $(X86_ONLY)attansic_l1 $(X86_ONLY)attansic_l2 - $(X86_ONLY)broadcom440x $(X86_ONLY)broadcom570x etherpci + $(X86_ONLY)broadcom440x $(X86_ONLY)broadcom570x $(X86_ONLY)dec21xxx etherpci $(X86_ONLY)ipro100 $(X86_ONLY)ipro1000 $(X86_ONLY)jmicron2x0 $(X86_ONLY)marvell_yukon $(X86_ONLY)nforce $(X86_ONLY)pcnet pegasus $(X86_ONLY)rtl8139 $(X86_ONLY)rtl81xx sis900 diff --git a/src/add-ons/kernel/drivers/network/3com/Jamfile b/src/add-ons/kernel/drivers/network/3com/Jamfile index 6b888756c2..1ce0f507de 100644 --- a/src/add-ons/kernel/drivers/network/3com/Jamfile +++ b/src/add-ons/kernel/drivers/network/3com/Jamfile @@ -1,4 +1,3 @@ SubDir HAIKU_TOP src add-ons kernel drivers network 3com ; SubInclude HAIKU_TOP src add-ons kernel drivers network 3com dev ; -SubInclude HAIKU_TOP src add-ons kernel drivers network 3com pci ; diff --git a/src/add-ons/kernel/drivers/network/3com/dev/Jamfile b/src/add-ons/kernel/drivers/network/3com/dev/Jamfile index b9ccb440e2..0a072bc397 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/Jamfile +++ b/src/add-ons/kernel/drivers/network/3com/dev/Jamfile @@ -1,3 +1,4 @@ SubDir HAIKU_TOP src add-ons kernel drivers network 3com dev ; SubInclude HAIKU_TOP src add-ons kernel drivers network 3com dev mii ; +SubInclude HAIKU_TOP src add-ons kernel drivers network 3com dev xl ; diff --git a/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphy.c b/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphy.c index e98b33bc87..01d0c80608 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphy.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphy.c @@ -14,13 +14,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED @@ -46,11 +39,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Manuel Bouyer. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -68,7 +56,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/bmtphy.c,v 1.9.2.1 2006/08/08 04:37:18 yongari Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/bmtphy.c,v 1.12.10.8.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * Driver for the Broadcom BCM5201/BCM5202 "Mini-Theta" PHYs. This also @@ -97,6 +85,11 @@ __FBSDID("$FreeBSD: src/sys/dev/mii/bmtphy.c,v 1.9.2.1 2006/08/08 04:37:18 yonga static int bmtphy_probe(device_t); static int bmtphy_attach(device_t); +struct bmtphy_softc { + struct mii_softc mii_sc; + int mii_model; +}; + static device_method_t bmtphy_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bmtphy_probe), @@ -112,81 +105,73 @@ static devclass_t bmtphy_devclass; static driver_t bmtphy_driver = { "bmtphy", bmtphy_methods, - sizeof(struct mii_softc) + sizeof(struct bmtphy_softc) }; DRIVER_MODULE(bmtphy, miibus, bmtphy_driver, bmtphy_devclass, 0, 0); static int bmtphy_service(struct mii_softc *, struct mii_data *, int); static void bmtphy_status(struct mii_softc *); +static void bmtphy_reset(struct mii_softc *); + +static const struct mii_phydesc bmtphys_dp[] = { + MII_PHY_DESC(BROADCOM, BCM4401), + MII_PHY_DESC(BROADCOM, BCM5201), + MII_PHY_DESC(BROADCOM, BCM5214), + MII_PHY_DESC(BROADCOM, BCM5221), + MII_PHY_DESC(BROADCOM, BCM5222), + MII_PHY_END +}; + +static const struct mii_phydesc bmtphys_lp[] = { + MII_PHY_DESC(BROADCOM, 3C905B), + MII_PHY_DESC(BROADCOM, 3C905C), + MII_PHY_END +}; static int bmtphy_probe(device_t dev) { - struct mii_attach_args *ma; int rval; - ma = device_get_ivars(dev); - rval = BUS_PROBE_DEFAULT; + /* Let exphy(4) take precedence for these. */ + rval = mii_phy_dev_probe(dev, bmtphys_lp, BUS_PROBE_LOW_PRIORITY); + if (rval <= 0) + return (rval); - if (MII_OUI(ma->mii_id1, ma->mii_id2) != MII_OUI_BROADCOM) - return (ENXIO); - - switch (MII_MODEL(ma->mii_id2)) { - case MII_MODEL_BROADCOM_3C905B: - device_set_desc(dev, MII_STR_BROADCOM_3C905B); - rval = BUS_PROBE_LOW_PRIORITY; /* Let exphy take precedence. */ - break; - case MII_MODEL_BROADCOM_3C905C: - device_set_desc(dev, MII_STR_BROADCOM_3C905C); - rval = BUS_PROBE_LOW_PRIORITY; /* Let exphy take precedence. */ - break; - case MII_MODEL_BROADCOM_BCM5201: - device_set_desc(dev, MII_STR_BROADCOM_BCM5201); - break; - case MII_MODEL_BROADCOM_BCM5221: - device_set_desc(dev, MII_STR_BROADCOM_BCM5221); - break; - case MII_MODEL_BROADCOM_BCM4401: - device_set_desc(dev, MII_STR_BROADCOM_BCM4401); - break; - default: - return (ENXIO); - } - - return (rval); + return (mii_phy_dev_probe(dev, bmtphys_dp, BUS_PROBE_DEFAULT)); } static int bmtphy_attach(device_t dev) { - struct mii_softc *sc; - struct mii_attach_args *ma; - struct mii_data *mii; + struct bmtphy_softc *bsc; + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; - sc = device_get_softc(dev); + bsc = device_get_softc(dev); + sc = &bsc->mii_sc; ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); - mii = device_get_softc(sc->mii_dev); + mii = ma->mii_data; LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); - sc->mii_inst = mii->mii_instance; + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = bmtphy_service; sc->mii_pdata = mii; - mii_phy_reset(sc); + sc->mii_flags |= MIIF_NOMANPAUSE; - mii->mii_instance++; + bsc->mii_model = MII_MODEL(ma->mii_id2); - sc->mii_capabilities = - PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + bmtphy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; device_printf(dev, " "); - if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0) - printf("no media present"); - else - mii_phy_add_media(sc); - + mii_phy_add_media(sc); printf("\n"); MIIBUS_MEDIAINIT(sc->mii_dev); @@ -197,31 +182,12 @@ bmtphy_attach(device_t dev) static int bmtphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { - struct ifmedia_entry *ife; - int reg; - - ife = mii->mii_media.ifm_cur; switch (cmd) { case MII_POLLSTAT: - /* - * If we're not polling our PHY instance, just return. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); break; case MII_MEDIACHG: - /* - * If the media indicates a different PHY instance, - * isolate ourselves. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) { - reg = PHY_READ(sc, MII_BMCR); - PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); - return (0); - } - /* * If the interface is not up, don't do anything. */ @@ -232,11 +198,6 @@ bmtphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) break; case MII_TICK: - /* - * If we're not currently selected, just return. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); if (mii_phy_tick(sc) == EJUSTRETURN) return (0); break; @@ -247,16 +208,15 @@ bmtphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) /* Callback if something changed. */ mii_phy_update(sc, cmd); - return (0); } static void bmtphy_status(struct mii_softc *sc) { - struct mii_data *mii; - struct ifmedia_entry *ife; - int bmsr, bmcr, aux_csr; + struct mii_data *mii; + struct ifmedia_entry *ife; + int bmsr, bmcr, aux_csr; mii = sc->mii_pdata; ife = mii->mii_media.ifm_cur; @@ -265,7 +225,6 @@ bmtphy_status(struct mii_softc *sc) mii->mii_media_active = IFM_ETHER; bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); - aux_csr = PHY_READ(sc, MII_BMTPHY_AUX_CSR); if (bmsr & BMSR_LINK) mii->mii_media_status |= IFM_ACTIVE; @@ -291,12 +250,45 @@ bmtphy_status(struct mii_softc *sc) return; } + aux_csr = PHY_READ(sc, MII_BMTPHY_AUX_CSR); if (aux_csr & AUX_CSR_SPEED) mii->mii_media_active |= IFM_100_TX; else mii->mii_media_active |= IFM_10_T; if (aux_csr & AUX_CSR_FDX) - mii->mii_media_active |= IFM_FDX; + mii->mii_media_active |= + IFM_FDX | mii_phy_flowstatus(sc); + else + mii->mii_media_active |= IFM_HDX; } else mii->mii_media_active = ife->ifm_media; } + +static void +bmtphy_reset(struct mii_softc *sc) +{ + struct bmtphy_softc *bsc; + u_int16_t data; + + bsc = (struct bmtphy_softc *)sc; + + mii_phy_reset(sc); + + if (bsc->mii_model == MII_MODEL_BROADCOM_BCM5221) { + /* Enable shadow register mode. */ + data = PHY_READ(sc, 0x1f); + PHY_WRITE(sc, 0x1f, data | 0x0080); + + /* Enable APD (Auto PowerDetect). */ + data = PHY_READ(sc, MII_BMTPHY_AUX2); + PHY_WRITE(sc, MII_BMTPHY_AUX2, data | 0x0020); + + /* Enable clocks across APD for Auto-MDIX functionality. */ + data = PHY_READ(sc, MII_BMTPHY_INTR); + PHY_WRITE(sc, MII_BMTPHY_INTR, data | 0x0004); + + /* Disable shadow register mode. */ + data = PHY_READ(sc, 0x1f); + PHY_WRITE(sc, 0x1f, data & ~0x0080); + } +} diff --git a/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphyreg.h b/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphyreg.h index 7b8abe1625..45ad8e75ef 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphyreg.h +++ b/src/add-ons/kernel/drivers/network/3com/dev/mii/bmtphyreg.h @@ -13,13 +13,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED @@ -35,7 +28,7 @@ * * from NetBSD: bmtphyreg.h,v 1.1 2001/06/02 21:42:10 thorpej Exp * - * $FreeBSD: src/sys/dev/mii/bmtphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp $ + * $FreeBSD: src/sys/dev/mii/bmtphyreg.h,v 1.2.22.2.2.1 2010/12/21 17:09:25 kensmith Exp $ */ #ifndef _DEV_MII_BMTPHYREG_H_ diff --git a/src/add-ons/kernel/drivers/network/3com/dev/mii/exphy.c b/src/add-ons/kernel/drivers/network/3com/dev/mii/exphy.c index bbcddf7038..8ddc8c8896 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/mii/exphy.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/mii/exphy.c @@ -16,13 +16,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED @@ -48,11 +41,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Manuel Bouyer. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -67,7 +55,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/exphy.c,v 1.19.2.1 2006/08/08 04:37:18 yongari Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/exphy.c,v 1.23.10.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * driver for 3Com internal PHYs @@ -114,42 +102,31 @@ DRIVER_MODULE(xlphy, miibus, exphy_driver, exphy_devclass, 0, 0); static int exphy_service(struct mii_softc *, struct mii_data *, int); static void exphy_reset(struct mii_softc *); +/* + * Some 3Com internal PHYs report zero for OUI and model, others use + * actual values. + * Note that the 3Com internal PHYs having OUI 0x105a and model 0 are + * handled fine by ukphy(4); they can be isolated and don't require + * special treatment after reset. + */ +static const struct mii_phydesc exphys[] = { + { 0, 0, "3Com internal media interface" }, + MII_PHY_DESC(BROADCOM, 3C905C), + MII_PHY_END +}; + static int -exphy_probe(dev) - device_t dev; +exphy_probe(device_t dev) { - struct mii_attach_args *ma; - device_t parent; - ma = device_get_ivars(dev); - parent = device_get_parent(device_get_parent(dev)); - - /* - * Argh, 3Com PHY reports oui == 0 model == 0! - */ - if ((MII_OUI(ma->mii_id1, ma->mii_id2) != 0 || - MII_MODEL(ma->mii_id2) != 0) && - (MII_OUI(ma->mii_id1, ma->mii_id2) != MII_OUI_BROADCOM || - MII_MODEL(ma->mii_id2) != MII_MODEL_BROADCOM_3C905C)) - return (ENXIO); - - /* - * Make sure the parent is an `ex'. - */ - if (strcmp(device_get_name(parent), "xl") != 0) - return (ENXIO); - - if (MII_OUI(ma->mii_id1, ma->mii_id2) == 0) - device_set_desc(dev, "3Com internal media interface"); - else - device_set_desc(dev, MII_STR_BROADCOM_3C905C); - - return (BUS_PROBE_DEFAULT); + if (strcmp(device_get_name(device_get_parent(device_get_parent(dev))), + "xl") == 0) + return (mii_phy_dev_probe(dev, exphys, BUS_PROBE_DEFAULT)); + return (ENXIO); } static int -exphy_attach(dev) - device_t dev; +exphy_attach(device_t dev) { struct mii_softc *sc; struct mii_attach_args *ma; @@ -158,62 +135,39 @@ exphy_attach(dev) sc = device_get_softc(dev); ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); - mii = device_get_softc(sc->mii_dev); - - /* - * The 3Com PHY can never be isolated, so never allow non-zero - * instances! - */ - if (mii->mii_instance != 0) { - device_printf(dev, "ignoring this PHY, non-zero instance\n"); - return(ENXIO); - } - + mii = ma->mii_data; LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); - sc->mii_inst = mii->mii_instance; + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = exphy_service; sc->mii_pdata = mii; - mii->mii_instance++; + /* + * The 3Com PHY can never be isolated. + */ sc->mii_flags |= MIIF_NOISOLATE; #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) -#if 0 /* See above. */ - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), - BMCR_ISO); -#endif - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), - BMCR_LOOP|BMCR_S100); + MII_MEDIA_100_TX); exphy_reset(sc); - sc->mii_capabilities = - PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); #undef ADD MIIBUS_MEDIAINIT(sc->mii_dev); - return(0); + return (0); } static int -exphy_service(sc, mii, cmd) - struct mii_softc *sc; - struct mii_data *mii; - int cmd; +exphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { - struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - - /* - * We can't isolate the 3Com PHY, so it has to be the only one! - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - panic("exphy_service: can't isolate 3Com PHY"); switch (cmd) { case MII_POLLSTAT: @@ -236,12 +190,6 @@ exphy_service(sc, mii, cmd) if ((mii->mii_ifp->if_flags & IFF_UP) == 0) return (0); - /* - * Only used for autonegotiation. - */ - if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) - break; - /* * The 3Com PHY's autonegotiation doesn't need to be * kicked; it continues in the background. diff --git a/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy.c b/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy.c index 10347825bf..ad59059aad 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy.c @@ -16,13 +16,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED @@ -48,11 +41,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Manuel Bouyer. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -67,7 +55,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20.10.6.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * driver for generic unknown PHYs @@ -134,7 +122,7 @@ ukphy_attach(device_t dev) sc = device_get_softc(dev); ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); - mii = device_get_softc(sc->mii_dev); + mii = ma->mii_data; LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); if (bootverbose) @@ -142,17 +130,17 @@ ukphy_attach(device_t dev) MII_OUI(ma->mii_id1, ma->mii_id2), MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2)); - sc->mii_inst = mii->mii_instance; + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = ukphy_service; sc->mii_pdata = mii; - mii->mii_instance++; + sc->mii_flags |= MIIF_NOMANPAUSE; mii_phy_reset(sc); - sc->mii_capabilities = - PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; if (sc->mii_capabilities & BMSR_EXTSTAT) sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); device_printf(dev, " "); @@ -168,29 +156,12 @@ ukphy_attach(device_t dev) static int ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { - struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - int reg; switch (cmd) { case MII_POLLSTAT: - /* - * If we're not polling our PHY instance, just return. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); break; case MII_MEDIACHG: - /* - * If the media indicates a different PHY instance, - * isolate ourselves. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) { - reg = PHY_READ(sc, MII_BMCR); - PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); - return (0); - } - /* * If the interface is not up, don't do anything. */ @@ -201,11 +172,6 @@ ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) break; case MII_TICK: - /* - * If we're not currently selected, just return. - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); if (mii_phy_tick(sc) == EJUSTRETURN) return (0); break; diff --git a/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy_subr.c b/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy_subr.c index fb40b75c1d..73007e197b 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy_subr.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/mii/ukphy_subr.c @@ -16,13 +16,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED @@ -38,7 +31,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.10.2.4.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * Subroutines shared by the ukphy driver and other PHY drivers. @@ -111,19 +104,26 @@ ukphy_status(struct mii_softc *phy) mii->mii_media_active |= IFM_1000_T|IFM_FDX; else if ((gtcr & GTCR_ADV_1000THDX) && (gtsr & GTSR_LP_1000THDX)) - mii->mii_media_active |= IFM_1000_T; - else if (anlpar & ANLPAR_T4) - mii->mii_media_active |= IFM_100_T4; + mii->mii_media_active |= IFM_1000_T|IFM_HDX; else if (anlpar & ANLPAR_TX_FD) mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4|IFM_HDX; else if (anlpar & ANLPAR_TX) - mii->mii_media_active |= IFM_100_TX; + mii->mii_media_active |= IFM_100_TX|IFM_HDX; else if (anlpar & ANLPAR_10_FD) mii->mii_media_active |= IFM_10_T|IFM_FDX; else if (anlpar & ANLPAR_10) - mii->mii_media_active |= IFM_10_T; + mii->mii_media_active |= IFM_10_T|IFM_HDX; else mii->mii_media_active |= IFM_NONE; + + if ((mii->mii_media_active & IFM_1000_T) != 0 && + (gtsr & GTSR_MS_RES) != 0) + mii->mii_media_active |= IFM_ETH_MASTER; + + if ((mii->mii_media_active & IFM_FDX) != 0) + mii->mii_media_active |= mii_phy_flowstatus(phy); } else mii->mii_media_active = ife->ifm_media; } diff --git a/src/add-ons/kernel/drivers/network/3com/pci/Jamfile b/src/add-ons/kernel/drivers/network/3com/dev/xl/Jamfile similarity index 70% rename from src/add-ons/kernel/drivers/network/3com/pci/Jamfile rename to src/add-ons/kernel/drivers/network/3com/dev/xl/Jamfile index aa8ef75a18..3658f24140 100644 --- a/src/add-ons/kernel/drivers/network/3com/pci/Jamfile +++ b/src/add-ons/kernel/drivers/network/3com/dev/xl/Jamfile @@ -1,6 +1,6 @@ -SubDir HAIKU_TOP src add-ons kernel drivers network 3com pci ; +SubDir HAIKU_TOP src add-ons kernel drivers network 3com dev xl ; -UseHeaders [ FDirName $(SUBDIR) .. ] : true ; +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; UsePrivateHeaders net system ; diff --git a/src/add-ons/kernel/drivers/network/3com/pci/glue.c b/src/add-ons/kernel/drivers/network/3com/dev/xl/glue.c similarity index 100% rename from src/add-ons/kernel/drivers/network/3com/pci/glue.c rename to src/add-ons/kernel/drivers/network/3com/dev/xl/glue.c diff --git a/src/add-ons/kernel/drivers/network/3com/pci/if_xl.c b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c similarity index 91% rename from src/add-ons/kernel/drivers/network/3com/pci/if_xl.c rename to src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c index 04da8f9be9..629dd1237b 100644 --- a/src/add-ons/kernel/drivers/network/3com/pci/if_xl.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c @@ -31,7 +31,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/pci/if_xl.c,v 1.210 2007/08/06 14:26:03 rwatson Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/xl/if_xl.c,v 1.8.2.7.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * 3Com 3c90x Etherlink XL PCI NIC driver @@ -96,9 +96,6 @@ __FBSDID("$FreeBSD: src/sys/pci/if_xl.c,v 1.210 2007/08/06 14:26:03 rwatson Exp * Since using bus master DMA is a big win, we use this driver to * support the PCI "boomerang" chips even though they work with the * "vortex" driver in order to obtain better performance. - * - * This driver is in the /sys/pci directory because it only supports - * PCI-based NICs. */ #ifdef HAVE_KERNEL_OPTION_HEADERS @@ -142,7 +139,7 @@ MODULE_DEPEND(xl, miibus, 1, 1, 1); /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" -#include +#include /* * TX Checksumming is disabled by default for two reasons: @@ -163,7 +160,7 @@ MODULE_DEPEND(xl, miibus, 1, 1, 1); /* * Various supported device vendors/types and their names. */ -static struct xl_type xl_devs[] = { +static const struct xl_type xl_devs[] = { { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, "3Com 3c900-TPO Etherlink XL" }, { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, @@ -230,8 +227,8 @@ static int xl_detach(device_t); static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); static void xl_stats_update(void *); static void xl_stats_update_locked(struct xl_softc *); -static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *); -static void xl_rxeof(struct xl_softc *); +static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); +static int xl_rxeof(struct xl_softc *); static void xl_rxeof_task(void *, int); static int xl_rx_resync(struct xl_softc *); static void xl_txeof(struct xl_softc *); @@ -246,13 +243,14 @@ static void xl_init(void *); static void xl_init_locked(struct xl_softc *); static void xl_stop(struct xl_softc *); static int xl_watchdog(struct xl_softc *); -static void xl_shutdown(device_t); +static int xl_shutdown(device_t); static int xl_suspend(device_t); static int xl_resume(device_t); +static void xl_setwol(struct xl_softc *); #ifdef DEVICE_POLLING -static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); -static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); +static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); +static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); #endif static int xl_ifmedia_upd(struct ifnet *); @@ -278,8 +276,6 @@ static void xl_mediacheck(struct xl_softc *); static void xl_choose_media(struct xl_softc *sc, int *media); static void xl_choose_xcvr(struct xl_softc *, int); static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); -static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); -static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); #ifdef notdef static void xl_testpacket(struct xl_softc *); #endif @@ -319,7 +315,6 @@ static driver_t xl_driver = { static devclass_t xl_devclass; -DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0); DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); @@ -332,46 +327,6 @@ xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) *paddr = segs->ds_addr; } -static void -xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, - bus_size_t mapsize, int error) -{ - u_int32_t *paddr; - - if (error) - return; - - KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); - paddr = arg; - *paddr = segs->ds_addr; -} - -static void -xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, - bus_size_t mapsize, int error) -{ - struct xl_list *l; - int i, total_len; - - if (error) - return; - - KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); - - total_len = 0; - l = arg; - for (i = 0; i < nseg; i++) { - KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); - l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); - l->xl_frag[i].xl_len = htole32(segs[i].ds_len); - total_len += segs[i].ds_len; - } - l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | - XL_LAST_FRAG); - l->xl_status = htole32(total_len); - l->xl_next = 0; -} - /* * Murphy's law says that it's possible the chip can wedge and * the 'command in progress' bit may never clear. Hence, we wait @@ -568,16 +523,6 @@ xl_miibus_readreg(device_t dev, int phy, int reg) sc = device_get_softc(dev); - /* - * Pretend that PHYs are only available at MII address 24. - * This is to guard against problems with certain 3Com ASIC - * revisions that incorrectly map the internal transceiver - * control registers at all MII addresses. This can cause - * the miibus code to attach the same PHY several times over. - */ - if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) - return (0); - bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; @@ -595,9 +540,6 @@ xl_miibus_writereg(device_t dev, int phy, int reg, int data) sc = device_get_softc(dev); - if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) - return (0); - bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; @@ -613,6 +555,7 @@ xl_miibus_statchg(device_t dev) { struct xl_softc *sc; struct mii_data *mii; + uint8_t macctl; sc = device_get_softc(dev); mii = device_get_softc(sc->xl_miibus); @@ -621,11 +564,22 @@ xl_miibus_statchg(device_t dev) /* Set ASIC's duplex mode to match the PHY. */ XL_SEL_WIN(3); - if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) - CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); - else - CSR_WRITE_1(sc, XL_W3_MAC_CTRL, - (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); + macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + macctl |= XL_MACCTRL_DUPLEX; + if (sc->xl_type == XL_TYPE_905B) { + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) + macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; + else + macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; + } + } else { + macctl &= ~XL_MACCTRL_DUPLEX; + if (sc->xl_type == XL_TYPE_905B) + macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; + } + CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); } /* @@ -770,10 +724,10 @@ xl_setmulti(struct xl_softc *sc) return; } - IF_ADDR_LOCK(ifp); + if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) mcnt++; - IF_ADDR_UNLOCK(ifp); + if_maddr_runlock(ifp); if (mcnt) rxfilt |= XL_RXFILTER_ALLMULTI; @@ -812,7 +766,7 @@ xl_setmulti_hash(struct xl_softc *sc) CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); /* now program new ones */ - IF_ADDR_LOCK(ifp); + if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; @@ -834,7 +788,7 @@ xl_setmulti_hash(struct xl_softc *sc) h | XL_CMD_RX_SET_HASH | XL_HASH_SET); mcnt++; } - IF_ADDR_UNLOCK(ifp); + if_maddr_runlock(ifp); if (mcnt) rxfilt |= XL_RXFILTER_MULTIHASH; @@ -844,32 +798,6 @@ xl_setmulti_hash(struct xl_softc *sc) CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); } -#ifdef notdef -static void -xl_testpacket(struct xl_softc *sc) -{ - struct mbuf *m; - struct ifnet *ifp = sc->xl_ifp; - - MGETHDR(m, M_DONTWAIT, MT_DATA); - - if (m == NULL) - return; - - bcopy(IF_LLADDR(sc->xl_ifp), - mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); - bcopy(IF_LLADDR(sc->xl_ifp), - mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); - mtod(m, struct ether_header *)->ether_type = htons(3); - mtod(m, unsigned char *)[14] = 0; - mtod(m, unsigned char *)[15] = 0; - mtod(m, unsigned char *)[16] = 0xE3; - m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; - IFQ_ENQUEUE(&ifp->if_snd, m); - xl_start(ifp); -} -#endif - static void xl_setcfg(struct xl_softc *sc) { @@ -1052,7 +980,7 @@ xl_reset(struct xl_softc *sc) static int xl_probe(device_t dev) { - struct xl_type *t; + const struct xl_type *t; t = xl_devs; @@ -1217,16 +1145,16 @@ static int xl_attach(device_t dev) { u_char eaddr[ETHER_ADDR_LEN]; - u_int16_t xcvr[2]; + u_int16_t sinfo2, xcvr[2]; struct xl_softc *sc; struct ifnet *ifp; - int media; - int unit, error = 0, rid, res; + int media, pmcap; + int error = 0, phy, rid, res, unit; uint16_t did; sc = device_get_softc(dev); sc->xl_dev = dev; - + unit = device_get_unit(dev); mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, @@ -1369,7 +1297,6 @@ xl_attach(device_t dev) goto fail; } - sc->xl_unit = unit; callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); @@ -1478,6 +1405,18 @@ xl_attach(device_t dev) else sc->xl_type = XL_TYPE_90X; + /* Check availability of WOL. */ + if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && + pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) { + sc->xl_pmcap = pmcap; + sc->xl_flags |= XL_FLAG_WOL; + sinfo2 = 0; + xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); + if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) + device_printf(dev, + "No auxiliary remote wakeup connector!\n"); + } + /* Set the TX start threshold for best performance. */ sc->xl_tx_thresh = XL_MIN_FRAMELEN; @@ -1492,6 +1431,8 @@ xl_attach(device_t dev) ifp->if_capabilities |= IFCAP_HWCSUM; #endif } + if ((sc->xl_flags & XL_FLAG_WOL) != 0) + ifp->if_capabilities |= IFCAP_WOL_MAGIC; ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; @@ -1525,10 +1466,20 @@ xl_attach(device_t dev) if (bootverbose) device_printf(dev, "found MII/AUTO\n"); xl_setcfg(sc); - if (mii_phy_probe(dev, &sc->xl_miibus, - xl_ifmedia_upd, xl_ifmedia_sts)) { - device_printf(dev, "no PHY found!\n"); - error = ENXIO; + /* + * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. + * This is to guard against problems with certain 3Com ASIC + * revisions that incorrectly map the internal transceiver + * control registers at all MII addresses. + */ + phy = MII_PHY_ANY; + if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) + phy = 24; + error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, + xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, + sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); + if (error != 0) { + device_printf(dev, "attaching PHYs failed\n"); goto fail; } goto done; @@ -1708,7 +1659,6 @@ xl_detach(device_t dev) /* These should only be active if attach succeeded */ if (device_is_attached(dev)) { XL_LOCK(sc); - xl_reset(sc); xl_stop(sc); XL_UNLOCK(sc); taskqueue_drain(taskqueue_swi, &sc->xl_task); @@ -1890,8 +1840,8 @@ xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) { struct mbuf *m_new = NULL; bus_dmamap_t map; - int error; - u_int32_t baddr; + bus_dma_segment_t segs[1]; + int error, nseg; XL_LOCK_ASSERT(sc); @@ -1904,14 +1854,16 @@ xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) /* Force longword alignment for packet payload. */ m_adj(m_new, ETHER_ALIGN); - error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, - xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); + error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, + segs, &nseg, BUS_DMA_NOWAIT); if (error) { m_freem(m_new); device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", error); return (error); } + KASSERT(nseg == 1, + ("%s: too many DMA segments (%d)", __func__, nseg)); bus_dmamap_unload(sc->xl_mtag, c->xl_map); map = c->xl_map; @@ -1920,7 +1872,7 @@ xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) c->xl_mbuf = m_new; c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); c->xl_ptr->xl_status = 0; - c->xl_ptr->xl_frag.xl_addr = htole32(baddr); + c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); return (0); } @@ -1953,13 +1905,14 @@ xl_rx_resync(struct xl_softc *sc) * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. */ -static void +static int xl_rxeof(struct xl_softc *sc) { struct mbuf *m; struct ifnet *ifp = sc->xl_ifp; struct xl_chain_onefrag *cur_rx; int total_len = 0; + int rx_npkts = 0; u_int32_t rxstat; XL_LOCK_ASSERT(sc); @@ -2061,6 +2014,7 @@ again: XL_UNLOCK(sc); (*ifp->if_input)(ifp, m); XL_LOCK(sc); + rx_npkts++; /* * If we are running from the taskqueue, the interface @@ -2068,7 +2022,7 @@ again: * packet up the network stack. */ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) - return; + return (rx_npkts); } /* @@ -2092,6 +2046,7 @@ again: CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); goto again; } + return (rx_npkts); } /* @@ -2142,13 +2097,13 @@ xl_txeof(struct xl_softc *sc) m_freem(cur_tx->xl_mbuf); cur_tx->xl_mbuf = NULL; ifp->if_opackets++; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; cur_tx->xl_next = sc->xl_cdata.xl_tx_free; sc->xl_cdata.xl_tx_free = cur_tx; } if (sc->xl_cdata.xl_tx_head == NULL) { - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; sc->xl_wdog_timer = 0; sc->xl_cdata.xl_tx_tail = NULL; } else { @@ -2174,7 +2129,6 @@ xl_txeof_90xB(struct xl_softc *sc) BUS_DMASYNC_POSTREAD); idx = sc->xl_cdata.xl_tx_cons; while (idx != sc->xl_cdata.xl_tx_prod) { - cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; if (!(le32toh(cur_tx->xl_ptr->xl_status) & @@ -2286,6 +2240,7 @@ xl_intr(void *arg) } #endif + #ifndef __HAIKU__ while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { @@ -2293,6 +2248,9 @@ xl_intr(void *arg) status = atomic_get((int32 *)&sc->xl_intr_status); while (true) { #endif + CSR_WRITE_2(sc, XL_COMMAND, + XL_CMD_INTR_ACK|(status & XL_INTRS)); + if (status & XL_STAT_UP_COMPLETE) { int curpkts; @@ -2317,7 +2275,7 @@ xl_intr(void *arg) } if (status & XL_STAT_ADFAIL) { - xl_reset(sc); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; xl_init_locked(sc); } @@ -2347,26 +2305,29 @@ xl_intr(void *arg) } #ifdef DEVICE_POLLING -static void +static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct xl_softc *sc = ifp->if_softc; + int rx_npkts = 0; XL_LOCK(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) - xl_poll_locked(ifp, cmd, count); + rx_npkts = xl_poll_locked(ifp, cmd, count); XL_UNLOCK(sc); + return (rx_npkts); } -static void +static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct xl_softc *sc = ifp->if_softc; + int rx_npkts; XL_LOCK_ASSERT(sc); sc->rxcycles = count; - xl_rxeof(sc); + rx_npkts = xl_rxeof(sc); if (sc->xl_type == XL_TYPE_905B) xl_txeof_90xB(sc); else @@ -2393,7 +2354,7 @@ xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) } if (status & XL_STAT_ADFAIL) { - xl_reset(sc); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; xl_init_locked(sc); } @@ -2404,6 +2365,7 @@ xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) } } } + return (rx_npkts); } #endif /* DEVICE_POLLING */ @@ -2475,26 +2437,21 @@ xl_stats_update_locked(struct xl_softc *sc) * pointers to the fragment pointers. */ static int -xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) +xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) { - int error; - u_int32_t status; + struct mbuf *m_new; struct ifnet *ifp = sc->xl_ifp; + int error, i, nseg, total_len; + u_int32_t status; XL_LOCK_ASSERT(sc); - /* - * Start packing the mbufs in this chain into - * the fragment pointers. Stop when we run out - * of fragments or hit the end of the mbuf chain. - */ - error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, - xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); + error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, + sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); if (error && error != EFBIG) { - m_freem(m_head); if_printf(ifp, "can't map mbuf (error %d)\n", error); - return (1); + return (error); } /* @@ -2506,42 +2463,64 @@ xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) * and would waste cycles. */ if (error) { - struct mbuf *m_new; - - m_new = m_defrag(m_head, M_DONTWAIT); + m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); if (m_new == NULL) { - m_freem(m_head); - return (1); - } else { - m_head = m_new; + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); } + *m_head = m_new; - error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, - m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); + error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, + *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); if (error) { - m_freem(m_head); + m_freem(*m_head); + *m_head = NULL; if_printf(ifp, "can't map mbuf (error %d)\n", error); - return (1); + return (error); } } + KASSERT(nseg <= XL_MAXFRAGS, + ("%s: too many DMA segments (%d)", __func__, nseg)); + if (nseg == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + total_len = 0; + for (i = 0; i < nseg; i++) { + KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, + ("segment size too large")); + c->xl_ptr->xl_frag[i].xl_addr = + htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); + c->xl_ptr->xl_frag[i].xl_len = + htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); + total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; + } + c->xl_ptr->xl_frag[nseg - 1].xl_len = + htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); + c->xl_ptr->xl_status = htole32(total_len); + c->xl_ptr->xl_next = 0; + if (sc->xl_type == XL_TYPE_905B) { status = XL_TXSTAT_RND_DEFEAT; #ifndef XL905B_TXCSUM_BROKEN - if (m_head->m_pkthdr.csum_flags) { - if (m_head->m_pkthdr.csum_flags & CSUM_IP) + if ((*m_head)->m_pkthdr.csum_flags) { + if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) status |= XL_TXSTAT_IPCKSUM; - if (m_head->m_pkthdr.csum_flags & CSUM_TCP) + if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) status |= XL_TXSTAT_TCPCKSUM; - if (m_head->m_pkthdr.csum_flags & CSUM_UDP) + if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) status |= XL_TXSTAT_UDPCKSUM; } #endif c->xl_ptr->xl_status = htole32(status); } - c->xl_mbuf = m_head; + c->xl_mbuf = *m_head; bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); return (0); } @@ -2574,12 +2553,14 @@ xl_start_locked(struct ifnet *ifp) struct xl_softc *sc = ifp->if_softc; struct mbuf *m_head = NULL; struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; - struct xl_chain *prev_tx; u_int32_t status; int error; XL_LOCK_ASSERT(sc); + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING) + return; /* * Check for an available queue slot. If there are none, * punt. @@ -2595,20 +2576,23 @@ xl_start_locked(struct ifnet *ifp) start_tx = sc->xl_cdata.xl_tx_free; - while (sc->xl_cdata.xl_tx_free != NULL) { + for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && + sc->xl_cdata.xl_tx_free != NULL;) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; /* Pick a descriptor off the free list. */ - prev_tx = cur_tx; cur_tx = sc->xl_cdata.xl_tx_free; /* Pack the data into the descriptor. */ - error = xl_encap(sc, cur_tx, m_head); + error = xl_encap(sc, cur_tx, &m_head); if (error) { - cur_tx = prev_tx; - continue; + if (m_head == NULL) + break; + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + break; } sc->xl_cdata.xl_tx_free = cur_tx->xl_next; @@ -2638,7 +2622,7 @@ xl_start_locked(struct ifnet *ifp) * Place the request for the upload interrupt * in the last descriptor in the chain. This way, if * we're chaining several packets at once, we'll only - * get an interupt once for the whole chain rather than + * get an interrupt once for the whole chain rather than * once for each packet. */ cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | @@ -2701,19 +2685,19 @@ xl_start_90xB_locked(struct ifnet *ifp) struct xl_softc *sc = ifp->if_softc; struct mbuf *m_head = NULL; struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; - struct xl_chain *prev_tx; int error, idx; XL_LOCK_ASSERT(sc); - if (ifp->if_drv_flags & IFF_DRV_OACTIVE) + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING) return; idx = sc->xl_cdata.xl_tx_prod; start_tx = &sc->xl_cdata.xl_tx_chain[idx]; - while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { - + for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && + sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; @@ -2723,14 +2707,16 @@ xl_start_90xB_locked(struct ifnet *ifp) if (m_head == NULL) break; - prev_tx = cur_tx; cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; /* Pack the data into the descriptor. */ - error = xl_encap(sc, cur_tx, m_head); + error = xl_encap(sc, cur_tx, &m_head); if (error) { - cur_tx = prev_tx; - continue; + if (m_head == NULL) + break; + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + break; } /* Chain it together. */ @@ -2758,7 +2744,7 @@ xl_start_90xB_locked(struct ifnet *ifp) * Place the request for the upload interrupt * in the last descriptor in the chain. This way, if * we're chaining several packets at once, we'll only - * get an interupt once for the whole chain rather than + * get an interrupt once for the whole chain rather than * once for each packet. */ cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | @@ -2796,11 +2782,16 @@ xl_init_locked(struct xl_softc *sc) XL_LOCK_ASSERT(sc); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + return; /* * Cancel pending I/O and free all RX/TX buffers. */ xl_stop(sc); + /* Reset the chip to a known state. */ + xl_reset(sc); + if (sc->xl_miibus == NULL) { CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); xl_wait(sc); @@ -2812,6 +2803,15 @@ xl_init_locked(struct xl_softc *sc) if (sc->xl_miibus != NULL) mii = device_get_softc(sc->xl_miibus); + /* + * Clear WOL status and disable all WOL feature as WOL + * would interfere Rx operation under normal environments. + */ + if ((sc->xl_flags & XL_FLAG_WOL) != 0) { + XL_SEL_WIN(7); + CSR_READ_2(sc, XL_W7_BM_PME); + CSR_WRITE_2(sc, XL_W7_BM_PME, 0); + } /* Init our MAC address */ XL_SEL_WIN(2); for (i = 0; i < ETHER_ADDR_LEN; i++) { @@ -3037,15 +3037,14 @@ xl_ifmedia_upd(struct ifnet *ifp) case IFM_10_2: case IFM_10_5: xl_setmode(sc, ifm->ifm_media); + XL_UNLOCK(sc); return (0); - break; - default: - break; } if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX || sc->xl_media & XL_MEDIAOPT_BT4) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; xl_init_locked(sc); } else { xl_setmode(sc, ifm->ifm_media); @@ -3136,7 +3135,7 @@ xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct xl_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; - int error = 0; + int error = 0, mask; struct mii_data *mii = NULL; u_int8_t rxfilt; @@ -3161,10 +3160,8 @@ xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); XL_SEL_WIN(7); - } else { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) - xl_init_locked(sc); - } + } else + xl_init_locked(sc); } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) xl_stop(sc); @@ -3196,41 +3193,50 @@ xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) &mii->mii_media, command); break; case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; #ifdef DEVICE_POLLING - if (ifr->ifr_reqcap & IFCAP_POLLING && - !(ifp->if_capenable & IFCAP_POLLING)) { - error = ether_poll_register(xl_poll, ifp); - if (error) - return(error); - XL_LOCK(sc); - /* Disable interrupts */ - CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); - ifp->if_capenable |= IFCAP_POLLING; - XL_UNLOCK(sc); - return (error); - - } - if (!(ifr->ifr_reqcap & IFCAP_POLLING) && - ifp->if_capenable & IFCAP_POLLING) { - error = ether_poll_deregister(ifp); - /* Enable interrupts. */ - XL_LOCK(sc); - CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); - CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); - if (sc->xl_flags & XL_FLAG_FUNCREG) - bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, - 4, 0x8000); - ifp->if_capenable &= ~IFCAP_POLLING; - XL_UNLOCK(sc); - return (error); + if ((mask & IFCAP_POLLING) != 0 && + (ifp->if_capabilities & IFCAP_POLLING) != 0) { + ifp->if_capenable ^= IFCAP_POLLING; + if ((ifp->if_capenable & IFCAP_POLLING) != 0) { + error = ether_poll_register(xl_poll, ifp); + if (error) + break; + XL_LOCK(sc); + /* Disable interrupts */ + CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); + ifp->if_capenable |= IFCAP_POLLING; + XL_UNLOCK(sc); + } else { + error = ether_poll_deregister(ifp); + /* Enable interrupts. */ + XL_LOCK(sc); + CSR_WRITE_2(sc, XL_COMMAND, + XL_CMD_INTR_ACK | 0xFF); + CSR_WRITE_2(sc, XL_COMMAND, + XL_CMD_INTR_ENB | XL_INTRS); + if (sc->xl_flags & XL_FLAG_FUNCREG) + bus_space_write_4(sc->xl_ftag, + sc->xl_fhandle, 4, 0x8000); + XL_UNLOCK(sc); + } } #endif /* DEVICE_POLLING */ XL_LOCK(sc); - ifp->if_capenable = ifr->ifr_reqcap; - if (ifp->if_capenable & IFCAP_TXCSUM) - ifp->if_hwassist = XL905B_CSUM_FEATURES; - else - ifp->if_hwassist = 0; + if ((mask & IFCAP_TXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { + ifp->if_capenable ^= IFCAP_TXCSUM; + if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) + ifp->if_hwassist |= XL905B_CSUM_FEATURES; + else + ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; + } + if ((mask & IFCAP_RXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_RXCSUM) != 0) + ifp->if_capenable ^= IFCAP_RXCSUM; + if ((mask & IFCAP_WOL_MAGIC) != 0 && + (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) + ifp->if_capenable ^= IFCAP_WOL_MAGIC; XL_UNLOCK(sc); break; default: @@ -3246,12 +3252,31 @@ xl_watchdog(struct xl_softc *sc) { struct ifnet *ifp = sc->xl_ifp; u_int16_t status = 0; + int misintr; XL_LOCK_ASSERT(sc); if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) return (0); + xl_rxeof(sc); + xl_txeoc(sc); + misintr = 0; + if (sc->xl_type == XL_TYPE_905B) { + xl_txeof_90xB(sc); + if (sc->xl_cdata.xl_tx_cnt == 0) + misintr++; + } else { + xl_txeof(sc); + if (sc->xl_cdata.xl_tx_head == NULL) + misintr++; + } + if (misintr != 0) { + device_printf(sc->xl_dev, + "watchdog timeout (missed Tx interrupts) -- recovering\n"); + return (0); + } + ifp->if_oerrors++; XL_SEL_WIN(4); status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); @@ -3261,10 +3286,7 @@ xl_watchdog(struct xl_softc *sc) device_printf(sc->xl_dev, "no carrier - transceiver cable problem?\n"); - xl_txeoc(sc); - xl_txeof(sc); - xl_rxeof(sc); - xl_reset(sc); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; xl_init_locked(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { @@ -3354,17 +3376,11 @@ xl_stop(struct xl_softc *sc) * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ -static void +static int xl_shutdown(device_t dev) { - struct xl_softc *sc; - sc = device_get_softc(dev); - - XL_LOCK(sc); - xl_reset(sc); - xl_stop(sc); - XL_UNLOCK(sc); + return (xl_suspend(dev)); } static int @@ -3376,6 +3392,7 @@ xl_suspend(device_t dev) XL_LOCK(sc); xl_stop(sc); + xl_setwol(sc); XL_UNLOCK(sc); return (0); @@ -3392,11 +3409,43 @@ xl_resume(device_t dev) XL_LOCK(sc); - xl_reset(sc); - if (ifp->if_flags & IFF_UP) + if (ifp->if_flags & IFF_UP) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; xl_init_locked(sc); + } XL_UNLOCK(sc); return (0); } + +static void +xl_setwol(struct xl_softc *sc) +{ + struct ifnet *ifp; + u_int16_t cfg, pmstat; + + if ((sc->xl_flags & XL_FLAG_WOL) == 0) + return; + + ifp = sc->xl_ifp; + XL_SEL_WIN(7); + /* Clear any pending PME events. */ + CSR_READ_2(sc, XL_W7_BM_PME); + cfg = 0; + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + cfg |= XL_BM_PME_MAGIC; + CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); + /* Enable RX. */ + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); + /* Request PME. */ + pmstat = pci_read_config(sc->xl_dev, + sc->xl_pmcap + PCIR_POWER_STATUS, 2); + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + pmstat |= PCIM_PSTAT_PMEENABLE; + else + pmstat &= ~PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->xl_dev, + sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); +} diff --git a/src/add-ons/kernel/drivers/network/3com/pci/if_xlreg.h b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xlreg.h similarity index 96% rename from src/add-ons/kernel/drivers/network/3com/pci/if_xlreg.h rename to src/add-ons/kernel/drivers/network/3com/dev/xl/if_xlreg.h index 1251d3e4c8..0dca3fd19b 100644 --- a/src/add-ons/kernel/drivers/network/3com/pci/if_xlreg.h +++ b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xlreg.h @@ -29,7 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - * $FreeBSD: src/sys/pci/if_xlreg.h,v 1.59 2006/12/06 02:18:41 marius Exp $ + * $FreeBSD: src/sys/dev/xl/if_xlreg.h,v 1.1.2.2.2.1 2010/12/21 17:09:25 kensmith Exp $ */ #define XL_EE_READ 0x0080 /* read, 5 bit address */ @@ -81,6 +81,17 @@ #define XL_CAPS_100MBPS 0x1000 #define XL_CAPS_PWRMGMT 0x2000 +/* + * Bits in the software information 2 word + */ +#define XL_SINFO2_FIXED_BCAST_RX_BUG 0x0002 +#define XL_SINFO2_FIXED_ENDEC_LOOP_BUG 0x0004 +#define XL_SINFO2_AUX_WOL_CON 0x0008 +#define XL_SINFO2_PME_PULSED 0x0010 +#define XL_SINFO2_FIXED_MWI_BUG 0x0020 +#define XL_SINFO2_WOL_AFTER_PWR_LOSS 0x0040 +#define XL_SINFO2_AUTO_RST_TO_D0 0x0080 + #define XL_PACKET_SIZE 1540 #define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) @@ -408,7 +419,12 @@ #define XL_W7_BM_LEN 0x06 #define XL_W7_BM_STATUS 0x0B #define XL_W7_BM_TIMEr 0x0A +#define XL_W7_BM_PME 0x0C +#define XL_BM_PME_WAKE 0x0001 +#define XL_BM_PME_MAGIC 0x0002 +#define XL_BM_PME_LINKCHG 0x0004 +#define XL_BM_PME_WAKETIMER 0x0008 /* * bus master control registers */ @@ -486,6 +502,7 @@ struct xl_chain_onefrag { struct xl_chain_data { struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; + bus_dma_segment_t xl_tx_segs[XL_MAXFRAGS]; struct xl_chain_onefrag *xl_rx_head; @@ -576,6 +593,7 @@ struct xl_mii_frame { #define XL_FLAG_NO_XCVR_PWR 0x0080 #define XL_FLAG_USE_MMIO 0x0100 #define XL_FLAG_NO_MMIO 0x0200 +#define XL_FLAG_WOL 0x0400 #define XL_NO_XCVR_PWR_MAGICBITS 0x0900 @@ -589,16 +607,16 @@ struct xl_softc { struct resource *xl_irq; struct resource *xl_res; device_t xl_miibus; - struct xl_type *xl_info; /* 3Com adapter info */ + const struct xl_type *xl_info; /* 3Com adapter info */ bus_dma_tag_t xl_mtag; bus_dmamap_t xl_tmpmap; /* spare DMA map */ - u_int8_t xl_unit; /* interface number */ u_int8_t xl_type; u_int32_t xl_xcvr; u_int16_t xl_media; u_int16_t xl_caps; u_int8_t xl_stats_no_timeout; u_int16_t xl_tx_thresh; + int xl_pmcap; int xl_if_flags; struct xl_list_data xl_ldata; struct xl_chain_data xl_cdata; diff --git a/src/add-ons/kernel/drivers/network/Jamfile b/src/add-ons/kernel/drivers/network/Jamfile index b03a8e80a3..c8a3a1d181 100644 --- a/src/add-ons/kernel/drivers/network/Jamfile +++ b/src/add-ons/kernel/drivers/network/Jamfile @@ -3,7 +3,6 @@ SubDir HAIKU_TOP src add-ons kernel drivers network ; SubInclude HAIKU_TOP src add-ons kernel drivers network etherpci ; SubInclude HAIKU_TOP src add-ons kernel drivers network ipro1000 ; SubInclude HAIKU_TOP src add-ons kernel drivers network pegasus ; -SubInclude HAIKU_TOP src add-ons kernel drivers network rtl8139 ; SubInclude HAIKU_TOP src add-ons kernel drivers network rtl8169 ; SubInclude HAIKU_TOP src add-ons kernel drivers network sis900 ; SubInclude HAIKU_TOP src add-ons kernel drivers network usb_asix ; @@ -14,10 +13,8 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network vlance ; SubInclude HAIKU_TOP src add-ons kernel drivers network wb840 ; # FreeBSD 7 drivers -SubInclude HAIKU_TOP src add-ons kernel drivers network 3com ; SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom440x ; SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom570x ; -SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ; SubInclude HAIKU_TOP src add-ons kernel drivers network jmicron2x0 ; SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ; SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ; @@ -33,7 +30,11 @@ SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ; SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ; # FreeBSD 8 drivers +SubInclude HAIKU_TOP src add-ons kernel drivers network 3com ; SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x ; +SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ; +SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx ; +SubInclude HAIKU_TOP src add-ons kernel drivers network rtl8139 ; SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/Jamfile b/src/add-ons/kernel/drivers/network/dec21xxx/Jamfile new file mode 100644 index 0000000000..5859fbd629 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/Jamfile @@ -0,0 +1,3 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network dec21xxx ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx dev ; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/Jamfile b/src/add-ons/kernel/drivers/network/dec21xxx/dev/Jamfile new file mode 100644 index 0000000000..155a4cdccb --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/Jamfile @@ -0,0 +1,4 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network dec21xxx dev ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx dev mii ; +SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx dev dc ; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/Jamfile b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/Jamfile new file mode 100644 index 0000000000..c4da39c098 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/Jamfile @@ -0,0 +1,15 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network dec21xxx dev dc ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; + +UsePrivateHeaders net ; +UsePrivateKernelHeaders ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelAddon dec21xxx : + if_dc.c + glue.c + : libfreebsd_network.a dec21xxx_mii.a + ; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/glue.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/glue.c new file mode 100644 index 0000000000..60160c0e7e --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/glue.c @@ -0,0 +1,82 @@ +/* + * Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved. + * Distributed under the terms of the MIT License. + */ + + +#include +#include +#include +#include + +#include "if_dcreg.h" + +HAIKU_FBSD_DRIVER_GLUE(dec21xxx, dc, pci) + +HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE | FBSD_SWI_TASKQUEUE); + +extern driver_t *DRIVER_MODULE_NAME(acphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(amphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(dcphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(pnphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus); + + +driver_t * +__haiku_select_miibus_driver(device_t dev) +{ + driver_t *drivers[] = { + DRIVER_MODULE_NAME(acphy, miibus), + DRIVER_MODULE_NAME(amphy, miibus), + DRIVER_MODULE_NAME(dcphy, miibus), + DRIVER_MODULE_NAME(pnphy, miibus), + DRIVER_MODULE_NAME(ukphy, miibus), + NULL + }; + + return __haiku_probe_miibus(dev, drivers); +} + + +int +HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) +{ + struct dc_softc *sc = device_get_softc(dev); + uint16_t status; + HAIKU_INTR_REGISTER_STATE; + + HAIKU_INTR_REGISTER_ENTER(); + + status = CSR_READ_4(sc, DC_ISR); + if (status == 0xffff) { + HAIKU_INTR_REGISTER_LEAVE(); + return 0; + } + + if (status != 0 && (status & DC_INTRS) == 0) { + CSR_WRITE_4(sc, DC_ISR, status); + HAIKU_INTR_REGISTER_LEAVE(); + return 0; + } + + if ((status & DC_INTRS) == 0) { + HAIKU_INTR_REGISTER_LEAVE(); + return 0; + } + + CSR_WRITE_4(sc, DC_IMR, 0); + + HAIKU_INTR_REGISTER_LEAVE(); + + return 1; +} + + +void +HAIKU_REENABLE_INTERRUPTS(device_t dev) +{ + struct dc_softc *sc = device_get_softc(dev); + DC_LOCK(sc); + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + DC_UNLOCK(sc); +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c new file mode 100644 index 0000000000..6f26484995 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c @@ -0,0 +1,3804 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/dc/if_dc.c,v 1.201.2.3.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 + * series chips and several workalikes including the following: + * + * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) + * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) + * Lite-On 82c168/82c169 PNIC (www.litecom.com) + * ASIX Electronics AX88140A (www.asix.com.tw) + * ASIX Electronics AX88141 (www.asix.com.tw) + * ADMtek AL981 (www.admtek.com.tw) + * ADMtek AN983 (www.admtek.com.tw) + * ADMtek cardbus AN985 (www.admtek.com.tw) + * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek cardbus AN985 + * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) + * Accton EN1217 (www.accton.com) + * Xircom X3201 (www.xircom.com) + * Abocom FE2500 + * Conexant LANfinity (www.conexant.com) + * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) + * + * Datasheets for the 21143 are available at developer.intel.com. + * Datasheets for the clone parts can be found at their respective sites. + * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) + * The PNIC II is essentially a Macronix 98715A chip; the only difference + * worth noting is that its multicast hash table is only 128 bits wide + * instead of 512. + * + * Written by Bill Paul + * Electrical Engineering Department + * Columbia University, New York City + */ +/* + * The Intel 21143 is the successor to the DEC 21140. It is basically + * the same as the 21140 but with a few new features. The 21143 supports + * three kinds of media attachments: + * + * o MII port, for 10Mbps and 100Mbps support and NWAY + * autonegotiation provided by an external PHY. + * o SYM port, for symbol mode 100Mbps support. + * o 10baseT port. + * o AUI/BNC port. + * + * The 100Mbps SYM port and 10baseT port can be used together in + * combination with the internal NWAY support to create a 10/100 + * autosensing configuration. + * + * Note that not all tulip workalikes are handled in this driver: we only + * deal with those which are relatively well behaved. The Winbond is + * handled separately due to its different register offsets and the + * special handling needed for its various bugs. The PNIC is handled + * here, but I'm not thrilled about it. + * + * All of the workalike chips use some form of MII transceiver support + * with the exception of the Macronix chips, which also have a SYM port. + * The ASIX AX88140A is also documented to have a SYM port, but all + * the cards I've seen use an MII transceiver, probably because the + * AX88140A doesn't support internal NWAY. + */ + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define DC_USEIOSPACE + +#include + +#ifdef __sparc64__ +#include +#include +#endif + +MODULE_DEPEND(dc, pci, 1, 1, 1); +MODULE_DEPEND(dc, ether, 1, 1, 1); +MODULE_DEPEND(dc, miibus, 1, 1, 1); + +/* + * "device miibus" is required in kernel config. See GENERIC if you get + * errors here. + */ +#include "miibus_if.h" + +/* + * Various supported device vendors/types and their names. + */ +static const struct dc_type dc_devs[] = { + { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, + "Intel 21143 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, + "Davicom DM9009 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, + "Davicom DM9100 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, + "Davicom DM9102A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, + "Davicom DM9102 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, + "ADMtek AL981 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, + "ADMtek AN983 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, + "ADMtek AN985 cardBus 10/100BaseTX or clone" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, + "ADMtek ADM9511 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, + "ADMtek ADM9513 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, + "ASIX AX88141 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, + "ASIX AX88140A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, + "Macronix 98713A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, + "Macronix 98713 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, + "Compex RL100-TX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, + "Compex RL100-TX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, + "Macronix 98725 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, + "Macronix 98715AEC-C 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, + "Macronix 98715/98715A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, + "Macronix 98727/98732 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, + "LC82C115 PNIC II 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, + "82c169 PNIC 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, + "82c168 PNIC 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, + "Accton EN1217 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, + "Accton EN2242 MiniPCI 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, + "Xircom X3201 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, + "Neteasy DRP-32TXD Cardbus 10/100" }, + { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, + "Abocom FE2500 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, + "Abocom FE2500MX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, + "Conexant LANfinity MiniPCI 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, + "Hawking CB102 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, + "PlaneX FNW-3602-T CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, + "3Com OfficeConnect 10/100B" }, + { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, + "Microsoft MN-120 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, + "Microsoft MN-130 10/100" }, + { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, + "Linksys PCMPC200 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, + "Linksys PCMPC200 CardBus 10/100" }, + { 0, 0, NULL } +}; + +static int dc_probe(device_t); +static int dc_attach(device_t); +static int dc_detach(device_t); +static int dc_suspend(device_t); +static int dc_resume(device_t); +static const struct dc_type *dc_devtype(device_t); +static int dc_newbuf(struct dc_softc *, int, int); +static int dc_encap(struct dc_softc *, struct mbuf **); +static void dc_pnic_rx_bug_war(struct dc_softc *, int); +static int dc_rx_resync(struct dc_softc *); +static int dc_rxeof(struct dc_softc *); +static void dc_txeof(struct dc_softc *); +static void dc_tick(void *); +static void dc_tx_underrun(struct dc_softc *); +static void dc_intr(void *); +static void dc_start(struct ifnet *); +static void dc_start_locked(struct ifnet *); +static int dc_ioctl(struct ifnet *, u_long, caddr_t); +static void dc_init(void *); +static void dc_init_locked(struct dc_softc *); +static void dc_stop(struct dc_softc *); +static void dc_watchdog(void *); +static int dc_shutdown(device_t); +static int dc_ifmedia_upd(struct ifnet *); +static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); + +static void dc_delay(struct dc_softc *); +static void dc_eeprom_idle(struct dc_softc *); +static void dc_eeprom_putbyte(struct dc_softc *, int); +static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_width(struct dc_softc *); +static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); + +static void dc_mii_writebit(struct dc_softc *, int); +static int dc_mii_readbit(struct dc_softc *); +static void dc_mii_sync(struct dc_softc *); +static void dc_mii_send(struct dc_softc *, u_int32_t, int); +static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); +static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); +static int dc_miibus_readreg(device_t, int, int); +static int dc_miibus_writereg(device_t, int, int, int); +static void dc_miibus_statchg(device_t); +static void dc_miibus_mediainit(device_t); + +static void dc_setcfg(struct dc_softc *, int); +static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); +static uint32_t dc_mchash_be(const uint8_t *); +static void dc_setfilt_21143(struct dc_softc *); +static void dc_setfilt_asix(struct dc_softc *); +static void dc_setfilt_admtek(struct dc_softc *); +static void dc_setfilt_xircom(struct dc_softc *); + +static void dc_setfilt(struct dc_softc *); + +static void dc_reset(struct dc_softc *); +static int dc_list_rx_init(struct dc_softc *); +static int dc_list_tx_init(struct dc_softc *); + +static void dc_read_srom(struct dc_softc *, int); +static void dc_parse_21143_srom(struct dc_softc *); +static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); +static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); +static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); +static void dc_apply_fixup(struct dc_softc *, int); + +#ifdef DC_USEIOSPACE +#define DC_RES SYS_RES_IOPORT +#define DC_RID DC_PCI_CFBIO +#else +#define DC_RES SYS_RES_MEMORY +#define DC_RID DC_PCI_CFBMA +#endif + +static device_method_t dc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, dc_probe), + DEVMETHOD(device_attach, dc_attach), + DEVMETHOD(device_detach, dc_detach), + DEVMETHOD(device_suspend, dc_suspend), + DEVMETHOD(device_resume, dc_resume), + DEVMETHOD(device_shutdown, dc_shutdown), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, dc_miibus_readreg), + DEVMETHOD(miibus_writereg, dc_miibus_writereg), + DEVMETHOD(miibus_statchg, dc_miibus_statchg), + DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), + + { 0, 0 } +}; + +static driver_t dc_driver = { + "dc", + dc_methods, + sizeof(struct dc_softc) +}; + +static devclass_t dc_devclass; + +DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); +DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) + +#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) +#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) + +static void +dc_delay(struct dc_softc *sc) +{ + int idx; + + for (idx = (300 / 33) + 1; idx > 0; idx--) + CSR_READ_4(sc, DC_BUSCTL); +} + +static void +dc_eeprom_width(struct dc_softc *sc) +{ + int i; + + /* Force EEPROM to idle state. */ + dc_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + for (i = 3; i--;) { + if (6 & (1 << i)) + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + else + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + for (i = 1; i <= 12; i++) { + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + break; + } + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); + + if (i < 4 || i > 12) + sc->dc_romwidth = 6; + else + sc->dc_romwidth = i; + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); +} + +static void +dc_eeprom_idle(struct dc_softc *sc) +{ + int i; + + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + for (i = 0; i < 25; i++) { + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + CSR_WRITE_4(sc, DC_SIO, 0x00000000); +} + +/* + * Send a read command and address to the EEPROM, check for ACK. + */ +static void +dc_eeprom_putbyte(struct dc_softc *sc, int addr) +{ + int d, i; + + d = DC_EECMD_READ >> 6; + for (i = 3; i--; ) { + if (d & (1 << i)) + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + else + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* + * Feed in each bit and strobe the clock. + */ + for (i = sc->dc_romwidth; i--;) { + if (addr & (1 << i)) { + SIO_SET(DC_SIO_EE_DATAIN); + } else { + SIO_CLR(DC_SIO_EE_DATAIN); + } + dc_delay(sc); + SIO_SET(DC_SIO_EE_CLK); + dc_delay(sc); + SIO_CLR(DC_SIO_EE_CLK); + dc_delay(sc); + } +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + * The PNIC 82c168/82c169 has its own non-standard way to read + * the EEPROM. + */ +static void +dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + int i; + u_int32_t r; + + CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); + + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(1); + r = CSR_READ_4(sc, DC_SIO); + if (!(r & DC_PN_SIOCTL_BUSY)) { + *dest = (u_int16_t)(r & 0xFFFF); + return; + } + } +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + * The Xircom X3201 has its own non-standard way to read + * the EEPROM, too. + */ +static void +dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + + SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); + + addr *= 2; + CSR_WRITE_4(sc, DC_ROM, addr | 0x160); + *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; + addr += 1; + CSR_WRITE_4(sc, DC_ROM, addr | 0x160); + *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; + + SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +static void +dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + int i; + u_int16_t word = 0; + + /* Force EEPROM to idle state. */ + dc_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + /* + * Send address of word we want to read. + */ + dc_eeprom_putbyte(sc, addr); + + /* + * Start reading bits from EEPROM. + */ + for (i = 0x8000; i; i >>= 1) { + SIO_SET(DC_SIO_EE_CLK); + dc_delay(sc); + if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) + word |= i; + dc_delay(sc); + SIO_CLR(DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); + + *dest = word; +} + +/* + * Read a sequence of words from the EEPROM. + */ +static void +dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + if (DC_IS_PNIC(sc)) + dc_eeprom_getword_pnic(sc, off + i, &word); + else if (DC_IS_XIRCOM(sc)) + dc_eeprom_getword_xircom(sc, off + i, &word); + else + dc_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (be) + *ptr = be16toh(word); + else + *ptr = le16toh(word); + } +} + +/* + * The following two routines are taken from the Macronix 98713 + * Application Notes pp.19-21. + */ +/* + * Write a bit to the MII bus. + */ +static void +dc_mii_writebit(struct dc_softc *sc, int bit) +{ + uint32_t reg; + + reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + + CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); +} + +/* + * Read a bit from the MII bus. + */ +static int +dc_mii_readbit(struct dc_softc *sc) +{ + uint32_t reg; + + reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + (void)CSR_READ_4(sc, DC_SIO); + CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) + return (1); + + return (0); +} + +/* + * Sync the PHYs by setting data bit and strobing the clock 32 times. + */ +static void +dc_mii_sync(struct dc_softc *sc) +{ + int i; + + CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + + for (i = 0; i < 32; i++) + dc_mii_writebit(sc, 1); +} + +/* + * Clock a series of bits through the MII. + */ +static void +dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) +{ + int i; + + for (i = (0x1 << (cnt - 1)); i; i >>= 1) + dc_mii_writebit(sc, bits & i); +} + +/* + * Read an PHY register through the MII. + */ +static int +dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) +{ + int i; + + /* + * Set up frame for RX. + */ + frame->mii_stdelim = DC_MII_STARTDELIM; + frame->mii_opcode = DC_MII_READOP; + + /* + * Sync the PHYs. + */ + dc_mii_sync(sc); + + /* + * Send command/address info. + */ + dc_mii_send(sc, frame->mii_stdelim, 2); + dc_mii_send(sc, frame->mii_opcode, 2); + dc_mii_send(sc, frame->mii_phyaddr, 5); + dc_mii_send(sc, frame->mii_regaddr, 5); + + /* + * Now try reading data bits. If the turnaround failed, we still + * need to clock through 16 cycles to keep the PHY(s) in sync. + */ + frame->mii_turnaround = dc_mii_readbit(sc); + if (frame->mii_turnaround != 0) { + for (i = 0; i < 16; i++) + dc_mii_readbit(sc); + goto fail; + } + for (i = 0x8000; i; i >>= 1) { + if (dc_mii_readbit(sc)) + frame->mii_data |= i; + } + +fail: + + /* Clock the idle bits. */ + dc_mii_writebit(sc, 0); + dc_mii_writebit(sc, 0); + + if (frame->mii_turnaround != 0) + return (1); + return (0); +} + +/* + * Write to a PHY register through the MII. + */ +static int +dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) +{ + + /* + * Set up frame for TX. + */ + frame->mii_stdelim = DC_MII_STARTDELIM; + frame->mii_opcode = DC_MII_WRITEOP; + frame->mii_turnaround = DC_MII_TURNAROUND; + + /* + * Sync the PHYs. + */ + dc_mii_sync(sc); + + dc_mii_send(sc, frame->mii_stdelim, 2); + dc_mii_send(sc, frame->mii_opcode, 2); + dc_mii_send(sc, frame->mii_phyaddr, 5); + dc_mii_send(sc, frame->mii_regaddr, 5); + dc_mii_send(sc, frame->mii_turnaround, 2); + dc_mii_send(sc, frame->mii_data, 16); + + /* Clock the idle bits. */ + dc_mii_writebit(sc, 0); + dc_mii_writebit(sc, 0); + + return (0); +} + +static int +dc_miibus_readreg(device_t dev, int phy, int reg) +{ + struct dc_mii_frame frame; + struct dc_softc *sc; + int i, rval, phy_reg = 0; + + sc = device_get_softc(dev); + bzero(&frame, sizeof(frame)); + + if (sc->dc_pmode != DC_PMODE_MII) { + if (phy == (MII_NPHY - 1)) { + switch (reg) { + case MII_BMSR: + /* + * Fake something to make the probe + * code think there's a PHY here. + */ + return (BMSR_MEDIAMASK); + break; + case MII_PHYIDR1: + if (DC_IS_PNIC(sc)) + return (DC_VENDORID_LO); + return (DC_VENDORID_DEC); + break; + case MII_PHYIDR2: + if (DC_IS_PNIC(sc)) + return (DC_DEVICEID_82C168); + return (DC_DEVICEID_21143); + break; + default: + return (0); + break; + } + } else + return (0); + } + + if (DC_IS_PNIC(sc)) { + CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | + (phy << 23) | (reg << 18)); + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(1); + rval = CSR_READ_4(sc, DC_PN_MII); + if (!(rval & DC_PN_MII_BUSY)) { + rval &= 0xFFFF; + return (rval == 0xFFFF ? 0 : rval); + } + } + return (0); + } + + if (DC_IS_COMET(sc)) { + switch (reg) { + case MII_BMCR: + phy_reg = DC_AL_BMCR; + break; + case MII_BMSR: + phy_reg = DC_AL_BMSR; + break; + case MII_PHYIDR1: + phy_reg = DC_AL_VENID; + break; + case MII_PHYIDR2: + phy_reg = DC_AL_DEVID; + break; + case MII_ANAR: + phy_reg = DC_AL_ANAR; + break; + case MII_ANLPAR: + phy_reg = DC_AL_LPAR; + break; + case MII_ANER: + phy_reg = DC_AL_ANER; + break; + default: + device_printf(dev, "phy_read: bad phy register %x\n", + reg); + return (0); + break; + } + + rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; + + if (rval == 0xFFFF) + return (0); + return (rval); + } + + frame.mii_phyaddr = phy; + frame.mii_regaddr = reg; + if (sc->dc_type == DC_TYPE_98713) { + phy_reg = CSR_READ_4(sc, DC_NETCFG); + CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); + } + dc_mii_readreg(sc, &frame); + if (sc->dc_type == DC_TYPE_98713) + CSR_WRITE_4(sc, DC_NETCFG, phy_reg); + + return (frame.mii_data); +} + +static int +dc_miibus_writereg(device_t dev, int phy, int reg, int data) +{ + struct dc_softc *sc; + struct dc_mii_frame frame; + int i, phy_reg = 0; + + sc = device_get_softc(dev); + bzero(&frame, sizeof(frame)); + + if (DC_IS_PNIC(sc)) { + CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | + (phy << 23) | (reg << 10) | data); + for (i = 0; i < DC_TIMEOUT; i++) { + if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) + break; + } + return (0); + } + + if (DC_IS_COMET(sc)) { + switch (reg) { + case MII_BMCR: + phy_reg = DC_AL_BMCR; + break; + case MII_BMSR: + phy_reg = DC_AL_BMSR; + break; + case MII_PHYIDR1: + phy_reg = DC_AL_VENID; + break; + case MII_PHYIDR2: + phy_reg = DC_AL_DEVID; + break; + case MII_ANAR: + phy_reg = DC_AL_ANAR; + break; + case MII_ANLPAR: + phy_reg = DC_AL_LPAR; + break; + case MII_ANER: + phy_reg = DC_AL_ANER; + break; + default: + device_printf(dev, "phy_write: bad phy register %x\n", + reg); + return (0); + break; + } + + CSR_WRITE_4(sc, phy_reg, data); + return (0); + } + + frame.mii_phyaddr = phy; + frame.mii_regaddr = reg; + frame.mii_data = data; + + if (sc->dc_type == DC_TYPE_98713) { + phy_reg = CSR_READ_4(sc, DC_NETCFG); + CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); + } + dc_mii_writereg(sc, &frame); + if (sc->dc_type == DC_TYPE_98713) + CSR_WRITE_4(sc, DC_NETCFG, phy_reg); + + return (0); +} + +static void +dc_miibus_statchg(device_t dev) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = device_get_softc(dev); + if (DC_IS_ADMTEK(sc)) + return; + + mii = device_get_softc(sc->dc_miibus); + ifm = &mii->mii_media; + if (DC_IS_DAVICOM(sc) && + IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { + dc_setcfg(sc, ifm->ifm_media); + sc->dc_if_media = ifm->ifm_media; + } else { + dc_setcfg(sc, mii->mii_media_active); + sc->dc_if_media = mii->mii_media_active; + } +} + +/* + * Special support for DM9102A cards with HomePNA PHYs. Note: + * with the Davicom DM9102A/DM9801 eval board that I have, it seems + * to be impossible to talk to the management interface of the DM9801 + * PHY (its MDIO pin is not connected to anything). Consequently, + * the driver has to just 'know' about the additional mode and deal + * with it itself. *sigh* + */ +static void +dc_miibus_mediainit(device_t dev) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + int rev; + + rev = pci_get_revid(dev); + + sc = device_get_softc(dev); + mii = device_get_softc(sc->dc_miibus); + ifm = &mii->mii_media; + + if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) + ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); +} + +#define DC_BITS_512 9 +#define DC_BITS_128 7 +#define DC_BITS_64 6 + +static uint32_t +dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) +{ + uint32_t crc; + + /* Compute CRC for the address value. */ + crc = ether_crc32_le(addr, ETHER_ADDR_LEN); + + /* + * The hash table on the PNIC II and the MX98715AEC-C/D/E + * chips is only 128 bits wide. + */ + if (sc->dc_flags & DC_128BIT_HASH) + return (crc & ((1 << DC_BITS_128) - 1)); + + /* The hash table on the MX98715BEC is only 64 bits wide. */ + if (sc->dc_flags & DC_64BIT_HASH) + return (crc & ((1 << DC_BITS_64) - 1)); + + /* Xircom's hash filtering table is different (read: weird) */ + /* Xircom uses the LEAST significant bits */ + if (DC_IS_XIRCOM(sc)) { + if ((crc & 0x180) == 0x180) + return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); + else + return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + + (12 << 4)); + } + + return (crc & ((1 << DC_BITS_512) - 1)); +} + +/* + * Calculate CRC of a multicast group address, return the lower 6 bits. + */ +static uint32_t +dc_mchash_be(const uint8_t *addr) +{ + uint32_t crc; + + /* Compute CRC for the address value. */ + crc = ether_crc32_be(addr, ETHER_ADDR_LEN); + + /* Return the filter bit position. */ + return ((crc >> 26) & 0x0000003F); +} + +/* + * 21143-style RX filter setup routine. Filter programming is done by + * downloading a special setup frame into the TX engine. 21143, Macronix, + * PNIC, PNIC II and Davicom chips are programmed this way. + * + * We always program the chip using 'hash perfect' mode, i.e. one perfect + * address (our node address) and a 512-bit hash filter for multicast + * frames. We also sneak the broadcast address into the hash filter since + * we need that too. + */ +static void +dc_setfilt_21143(struct dc_softc *sc) +{ + uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; + struct dc_desc *sframe; + u_int32_t h, *sp; + struct ifmultiaddr *ifma; + struct ifnet *ifp; + int i; + + ifp = sc->dc_ifp; + + i = sc->dc_cdata.dc_tx_prod; + DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); + sc->dc_cdata.dc_tx_cnt++; + sframe = &sc->dc_ldata->dc_tx_list[i]; + sp = sc->dc_cdata.dc_sbuf; + bzero(sp, DC_SFRAME_LEN); + + sframe->dc_data = htole32(sc->dc_saddr); + sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | + DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); + + sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + if_maddr_runlock(ifp); + + if (ifp->if_flags & IFF_BROADCAST) { + h = dc_mchash_le(sc, ifp->if_broadcastaddr); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + + /* Set our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + sp[39] = DC_SP_MAC(eaddr[0]); + sp[40] = DC_SP_MAC(eaddr[1]); + sp[41] = DC_SP_MAC(eaddr[2]); + + sframe->dc_status = htole32(DC_TXSTAT_OWN); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * The PNIC takes an exceedingly long time to process its + * setup frame; wait 10ms after posting the setup frame + * before proceeding, just so it has time to swallow its + * medicine. + */ + DELAY(10000); + + sc->dc_wdog_timer = 5; +} + +static void +dc_setfilt_admtek(struct dc_softc *sc) +{ + uint8_t eaddr[ETHER_ADDR_LEN]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + + ifp = sc->dc_ifp; + + /* Init our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | + eaddr[1] << 8 | eaddr[0]); + CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + /* First, zot all the existing hash bits. */ + CSR_WRITE_4(sc, DC_AL_MAR0, 0); + CSR_WRITE_4(sc, DC_AL_MAR1, 0); + + /* + * If we're already in promisc or allmulti mode, we + * don't have to bother programming the multicast filter. + */ + if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) + return; + + /* Now program new ones. */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + if (DC_IS_CENTAUR(sc)) + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + else + h = dc_mchash_be( + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + if_maddr_runlock(ifp); + + CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); + CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); +} + +static void +dc_setfilt_asix(struct dc_softc *sc) +{ + uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + + ifp = sc->dc_ifp; + + /* Init our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + /* + * The ASIX chip has a special bit to enable reception + * of broadcast frames. + */ + if (ifp->if_flags & IFF_BROADCAST) + DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); + else + DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); + + /* first, zot all the existing hash bits */ + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); + + /* + * If we're already in promisc or allmulti mode, we + * don't have to bother programming the multicast filter. + */ + if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) + return; + + /* now program new ones */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + if_maddr_runlock(ifp); + + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); +} + +static void +dc_setfilt_xircom(struct dc_softc *sc) +{ + uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + struct dc_desc *sframe; + u_int32_t h, *sp; + int i; + + ifp = sc->dc_ifp; + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); + + i = sc->dc_cdata.dc_tx_prod; + DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); + sc->dc_cdata.dc_tx_cnt++; + sframe = &sc->dc_ldata->dc_tx_list[i]; + sp = sc->dc_cdata.dc_sbuf; + bzero(sp, DC_SFRAME_LEN); + + sframe->dc_data = htole32(sc->dc_saddr); + sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | + DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); + + sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + if_maddr_runlock(ifp); + + if (ifp->if_flags & IFF_BROADCAST) { + h = dc_mchash_le(sc, ifp->if_broadcastaddr); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + + /* Set our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + sp[0] = DC_SP_MAC(eaddr[0]); + sp[1] = DC_SP_MAC(eaddr[1]); + sp[2] = DC_SP_MAC(eaddr[2]); + + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); + ifp->if_drv_flags |= IFF_DRV_RUNNING; + sframe->dc_status = htole32(DC_TXSTAT_OWN); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * Wait some time... + */ + DELAY(1000); + + sc->dc_wdog_timer = 5; +} + +static void +dc_setfilt(struct dc_softc *sc) +{ + + if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || + DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) + dc_setfilt_21143(sc); + + if (DC_IS_ASIX(sc)) + dc_setfilt_asix(sc); + + if (DC_IS_ADMTEK(sc)) + dc_setfilt_admtek(sc); + + if (DC_IS_XIRCOM(sc)) + dc_setfilt_xircom(sc); +} + +/* + * In order to fiddle with the 'full-duplex' and '100Mbps' bits in + * the netconfig register, we first have to put the transmit and/or + * receive logic in the idle state. + */ +static void +dc_setcfg(struct dc_softc *sc, int media) +{ + int i, restart = 0, watchdogreg; + u_int32_t isr; + + if (IFM_SUBTYPE(media) == IFM_NONE) + return; + + if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { + restart = 1; + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); + + for (i = 0; i < DC_TIMEOUT; i++) { + isr = CSR_READ_4(sc, DC_ISR); + if (isr & DC_ISR_TX_IDLE && + ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || + (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) + break; + DELAY(10); + } + + if (i == DC_TIMEOUT) { + if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) + device_printf(sc->dc_dev, + "%s: failed to force tx to idle state\n", + __func__); + if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || + (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && + !DC_HAS_BROKEN_RXSTATE(sc)) + device_printf(sc->dc_dev, + "%s: failed to force rx to idle state\n", + __func__); + } + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); + if (sc->dc_pmode == DC_PMODE_MII) { + if (DC_IS_INTEL(sc)) { + /* There's a write enable bit here that reads as 1. */ + watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); + watchdogreg &= ~DC_WDOG_CTLWREN; + watchdogreg |= DC_WDOG_JABBERDIS; + CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); + } else { + DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); + } + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_SCRAMBLER)); + if (!DC_IS_DAVICOM(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, IFM_AUTO); + } else { + if (DC_IS_PNIC(sc)) { + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); + DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); + } + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, + (media & IFM_GMASK) == IFM_FDX ? + IFM_100_TX | IFM_FDX : IFM_100_TX); + } + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); + if (sc->dc_pmode == DC_PMODE_MII) { + /* There's a write enable bit here that reads as 1. */ + if (DC_IS_INTEL(sc)) { + watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); + watchdogreg &= ~DC_WDOG_CTLWREN; + watchdogreg |= DC_WDOG_JABBERDIS; + CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); + } else { + DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); + } + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + if (!DC_IS_DAVICOM(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, IFM_AUTO); + } else { + if (DC_IS_PNIC(sc)) { + DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); + DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); + } + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); + if (DC_IS_INTEL(sc)) { + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if ((media & IFM_GMASK) == IFM_FDX) + DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); + else + DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(sc, DC_10BTCTRL, + DC_TCTL_AUTONEGENBL); + dc_apply_fixup(sc, + (media & IFM_GMASK) == IFM_FDX ? + IFM_10_T | IFM_FDX : IFM_10_T); + DELAY(20000); + } + } + } + + /* + * If this is a Davicom DM9102A card with a DM9801 HomePNA + * PHY and we want HomePNA mode, set the portsel bit to turn + * on the external MII port. + */ + if (DC_IS_DAVICOM(sc)) { + if (IFM_SUBTYPE(media) == IFM_HPNA_1) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + sc->dc_link = 1; + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + } + } + + if ((media & IFM_GMASK) == IFM_FDX) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) + DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) + DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); + } + + if (restart) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); +} + +static void +dc_reset(struct dc_softc *sc) +{ + int i; + + DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); + + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) + break; + } + + if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || + DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { + DELAY(10000); + DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); + i = 0; + } + + if (i == DC_TIMEOUT) + device_printf(sc->dc_dev, "reset never completed!\n"); + + /* Wait a little while for the chip to get its brains in order. */ + DELAY(1000); + + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); + CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); + + /* + * Bring the SIA out of reset. In some cases, it looks + * like failing to unreset the SIA soon enough gets it + * into a state where it will never come out of reset + * until we reset the whole chip again. + */ + if (DC_IS_INTEL(sc)) { + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + CSR_WRITE_4(sc, DC_10BTCTRL, 0); + CSR_WRITE_4(sc, DC_WATCHDOG, 0); + } +} + +static const struct dc_type * +dc_devtype(device_t dev) +{ + const struct dc_type *t; + u_int32_t devid; + u_int8_t rev; + + t = dc_devs; + devid = pci_get_devid(dev); + rev = pci_get_revid(dev); + + while (t->dc_name != NULL) { + if (devid == t->dc_devid && rev >= t->dc_minrev) + return (t); + t++; + } + + return (NULL); +} + +/* + * Probe for a 21143 or clone chip. Check the PCI vendor and device + * IDs against our list and return a device name if we find a match. + * We do a little bit of extra work to identify the exact type of + * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, + * but different revision IDs. The same is true for 98715/98715A + * chips and the 98725, as well as the ASIX and ADMtek chips. In some + * cases, the exact chip revision affects driver behavior. + */ +static int +dc_probe(device_t dev) +{ + const struct dc_type *t; + + t = dc_devtype(dev); + + if (t != NULL) { + device_set_desc(dev, t->dc_name); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static void +dc_apply_fixup(struct dc_softc *sc, int media) +{ + struct dc_mediainfo *m; + u_int8_t *p; + int i; + u_int32_t reg; + + m = sc->dc_mi; + + while (m != NULL) { + if (m->dc_media == media) + break; + m = m->dc_next; + } + + if (m == NULL) + return; + + for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { + reg = (p[0] | (p[1] << 8)) << 16; + CSR_WRITE_4(sc, DC_WATCHDOG, reg); + } + + for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { + reg = (p[0] | (p[1] << 8)) << 16; + CSR_WRITE_4(sc, DC_WATCHDOG, reg); + } +} + +static void +dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) +{ + struct dc_mediainfo *m; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { + case DC_SIA_CODE_10BT: + m->dc_media = IFM_10_T; + break; + case DC_SIA_CODE_10BT_FDX: + m->dc_media = IFM_10_T | IFM_FDX; + break; + case DC_SIA_CODE_10B2: + m->dc_media = IFM_10_2; + break; + case DC_SIA_CODE_10B5: + m->dc_media = IFM_10_5; + break; + default: + break; + } + + /* + * We need to ignore CSR13, CSR14, CSR15 for SIA mode. + * Things apparently already work for cards that do + * supply Media Specific Data. + */ + if (l->dc_sia_code & DC_SIA_CODE_EXT) { + m->dc_gp_len = 2; + m->dc_gp_ptr = + (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; + } else { + m->dc_gp_len = 2; + m->dc_gp_ptr = + (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; + } + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; + + sc->dc_pmode = DC_PMODE_SIA; +} + +static void +dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) +{ + struct dc_mediainfo *m; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + if (l->dc_sym_code == DC_SYM_CODE_100BT) + m->dc_media = IFM_100_TX; + + if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) + m->dc_media = IFM_100_TX | IFM_FDX; + + m->dc_gp_len = 2; + m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; + + sc->dc_pmode = DC_PMODE_SYM; +} + +static void +dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) +{ + struct dc_mediainfo *m; + u_int8_t *p; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + /* We abuse IFM_AUTO to represent MII. */ + m->dc_media = IFM_AUTO; + m->dc_gp_len = l->dc_gpr_len; + + p = (u_int8_t *)l; + p += sizeof(struct dc_eblock_mii); + m->dc_gp_ptr = p; + p += 2 * l->dc_gpr_len; + m->dc_reset_len = *p; + p++; + m->dc_reset_ptr = p; + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; +} + +static void +dc_read_srom(struct dc_softc *sc, int bits) +{ + int size; + + size = 2 << bits; + sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); + dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); +} + +static void +dc_parse_21143_srom(struct dc_softc *sc) +{ + struct dc_leaf_hdr *lhdr; + struct dc_eblock_hdr *hdr; + int have_mii, i, loff; + char *ptr; + + have_mii = 0; + loff = sc->dc_srom[27]; + lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); + + ptr = (char *)lhdr; + ptr += sizeof(struct dc_leaf_hdr) - 1; + /* + * Look if we got a MII media block. + */ + for (i = 0; i < lhdr->dc_mcnt; i++) { + hdr = (struct dc_eblock_hdr *)ptr; + if (hdr->dc_type == DC_EBLOCK_MII) + have_mii++; + + ptr += (hdr->dc_len & 0x7F); + ptr++; + } + + /* + * Do the same thing again. Only use SIA and SYM media + * blocks if no MII media block is available. + */ + ptr = (char *)lhdr; + ptr += sizeof(struct dc_leaf_hdr) - 1; + for (i = 0; i < lhdr->dc_mcnt; i++) { + hdr = (struct dc_eblock_hdr *)ptr; + switch (hdr->dc_type) { + case DC_EBLOCK_MII: + dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); + break; + case DC_EBLOCK_SIA: + if (! have_mii) + dc_decode_leaf_sia(sc, + (struct dc_eblock_sia *)hdr); + break; + case DC_EBLOCK_SYM: + if (! have_mii) + dc_decode_leaf_sym(sc, + (struct dc_eblock_sym *)hdr); + break; + default: + /* Don't care. Yet. */ + break; + } + ptr += (hdr->dc_len & 0x7F); + ptr++; + } +} + +static void +dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + u_int32_t *paddr; + + KASSERT(nseg == 1, + ("%s: wrong number of segments (%d)", __func__, nseg)); + paddr = arg; + *paddr = segs->ds_addr; +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +static int +dc_attach(device_t dev) +{ + uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; + u_int32_t command; + struct dc_softc *sc; + struct ifnet *ifp; + u_int32_t reg, revision; + int error, i, mac_offset, phy, rid, tmp; + u_int8_t *mac; + + sc = device_get_softc(dev); + sc->dc_dev = dev; + + mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + + rid = DC_RID; + sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); + + if (sc->dc_res == NULL) { + device_printf(dev, "couldn't map ports/memory\n"); + error = ENXIO; + goto fail; + } + + sc->dc_btag = rman_get_bustag(sc->dc_res); + sc->dc_bhandle = rman_get_bushandle(sc->dc_res); + + /* Allocate interrupt. */ + rid = 0; + sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + + if (sc->dc_irq == NULL) { + device_printf(dev, "couldn't map interrupt\n"); + error = ENXIO; + goto fail; + } + + /* Need this info to decide on a chip type. */ + sc->dc_info = dc_devtype(dev); + revision = pci_get_revid(dev); + + /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ + if (sc->dc_info->dc_devid != + DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && + sc->dc_info->dc_devid != + DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) + dc_eeprom_width(sc); + + switch (sc->dc_info->dc_devid) { + case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): + sc->dc_type = DC_TYPE_21143; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL; + /* Save EEPROM contents so we can parse them later. */ + dc_read_srom(sc, sc->dc_romwidth); + break; + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): + sc->dc_type = DC_TYPE_DM9102; + sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; + sc->dc_flags |= DC_TX_ALIGN; + sc->dc_pmode = DC_PMODE_MII; + + /* Increase the latency timer value. */ + pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); + break; + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): + sc->dc_type = DC_TYPE_AL981; + sc->dc_flags |= DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_TX_ADMTEK_WAR; + sc->dc_pmode = DC_PMODE_MII; + dc_read_srom(sc, sc->dc_romwidth); + break; + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): + case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): + case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): + case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): + case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): + case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): + case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): + case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): + case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): + case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): + case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): + case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): + sc->dc_type = DC_TYPE_AN983; + sc->dc_flags |= DC_64BIT_HASH; + sc->dc_flags |= DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_TX_ADMTEK_WAR; + sc->dc_pmode = DC_PMODE_MII; + /* Don't read SROM for - auto-loaded on reset */ + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): + case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): + if (revision < DC_REVISION_98713A) { + sc->dc_type = DC_TYPE_98713; + } + if (revision >= DC_REVISION_98713A) { + sc->dc_type = DC_TYPE_98713A; + sc->dc_flags |= DC_21143_NWAY; + } + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): + case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): + /* + * Macronix MX98715AEC-C/D/E parts have only a + * 128-bit hash table. We need to deal with these + * in the same manner as the PNIC II so that we + * get the right number of bits out of the + * CRC routine. + */ + if (revision >= DC_REVISION_98715AEC_C && + revision < DC_REVISION_98725) + sc->dc_flags |= DC_128BIT_HASH; + sc->dc_type = DC_TYPE_987x5; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): + sc->dc_type = DC_TYPE_987x5; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): + sc->dc_type = DC_TYPE_PNICII; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): + sc->dc_type = DC_TYPE_PNIC; + sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_PNIC_RX_BUG_WAR; + sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); + if (revision < DC_REVISION_82C169) + sc->dc_pmode = DC_PMODE_SYM; + break; + case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): + sc->dc_type = DC_TYPE_ASIX; + sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_pmode = DC_PMODE_MII; + break; + case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): + sc->dc_type = DC_TYPE_XIRCOM; + sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | + DC_TX_ALIGN; + /* + * We don't actually need to coalesce, but we're doing + * it to obtain a double word aligned buffer. + * The DC_TX_COALESCE flag is required. + */ + sc->dc_pmode = DC_PMODE_MII; + break; + case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): + sc->dc_type = DC_TYPE_CONEXANT; + sc->dc_flags |= DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_pmode = DC_PMODE_MII; + dc_read_srom(sc, sc->dc_romwidth); + break; + default: + device_printf(dev, "unknown device: %x\n", + sc->dc_info->dc_devid); + break; + } + + /* Save the cache line size. */ + if (DC_IS_DAVICOM(sc)) + sc->dc_cachesize = 0; + else + sc->dc_cachesize = pci_get_cachelnsz(dev); + + /* Reset the adapter. */ + dc_reset(sc); + + /* Take 21143 out of snooze mode */ + if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { + command = pci_read_config(dev, DC_PCI_CFDD, 4); + command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); + pci_write_config(dev, DC_PCI_CFDD, command, 4); + } + + /* + * Try to learn something about the supported media. + * We know that ASIX and ADMtek and Davicom devices + * will *always* be using MII media, so that's a no-brainer. + * The tricky ones are the Macronix/PNIC II and the + * Intel 21143. + */ + if (DC_IS_INTEL(sc)) + dc_parse_21143_srom(sc); + else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { + if (sc->dc_type == DC_TYPE_98713) + sc->dc_pmode = DC_PMODE_MII; + else + sc->dc_pmode = DC_PMODE_SYM; + } else if (!sc->dc_pmode) + sc->dc_pmode = DC_PMODE_MII; + + /* + * Get station address from the EEPROM. + */ + switch(sc->dc_type) { + case DC_TYPE_98713: + case DC_TYPE_98713A: + case DC_TYPE_987x5: + case DC_TYPE_PNICII: + dc_read_eeprom(sc, (caddr_t)&mac_offset, + (DC_EE_NODEADDR_OFFSET / 2), 1, 0); + dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); + break; + case DC_TYPE_PNIC: + dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); + break; + case DC_TYPE_DM9102: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); +#ifdef __sparc64__ + /* + * If this is an onboard dc(4) the station address read from + * the EEPROM is all zero and we have to get it from the FCode. + */ + if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) + OF_getetheraddr(dev, (caddr_t)&eaddr); +#endif + break; + case DC_TYPE_21143: + case DC_TYPE_ASIX: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); + break; + case DC_TYPE_AL981: + case DC_TYPE_AN983: + reg = CSR_READ_4(sc, DC_AL_PAR0); + mac = (uint8_t *)&eaddr[0]; + mac[0] = (reg >> 0) & 0xff; + mac[1] = (reg >> 8) & 0xff; + mac[2] = (reg >> 16) & 0xff; + mac[3] = (reg >> 24) & 0xff; + reg = CSR_READ_4(sc, DC_AL_PAR1); + mac[4] = (reg >> 0) & 0xff; + mac[5] = (reg >> 8) & 0xff; + break; + case DC_TYPE_CONEXANT: + bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, + ETHER_ADDR_LEN); + break; + case DC_TYPE_XIRCOM: + /* The MAC comes from the CIS. */ + mac = pci_get_ether(dev); + if (!mac) { + device_printf(dev, "No station address in CIS!\n"); + error = ENXIO; + goto fail; + } + bcopy(mac, eaddr, ETHER_ADDR_LEN); + break; + default: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); + break; + } + + /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), + 0, NULL, NULL, &sc->dc_ltag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); + if (error) { + device_printf(dev, "failed to allocate DMA safe memory\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, + sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, + BUS_DMA_NOWAIT); + if (error) { + device_printf(dev, "cannot get address of the descriptors\n"); + error = ENXIO; + goto fail; + } + + /* + * Allocate a busdma tag and DMA safe memory for the multicast + * setup frame. + */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, + 0, NULL, NULL, &sc->dc_stag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, + BUS_DMA_NOWAIT, &sc->dc_smap); + if (error) { + device_printf(dev, "failed to allocate DMA safe memory\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, + DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); + if (error) { + device_printf(dev, "cannot get address of the descriptors\n"); + error = ENXIO; + goto fail; + } + + /* Allocate a busdma tag for mbufs. */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, + 0, NULL, NULL, &sc->dc_mtag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + + /* Create the TX/RX busdma maps. */ + for (i = 0; i < DC_TX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->dc_mtag, 0, + &sc->dc_cdata.dc_tx_map[i]); + if (error) { + device_printf(dev, "failed to init TX ring\n"); + error = ENXIO; + goto fail; + } + } + for (i = 0; i < DC_RX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->dc_mtag, 0, + &sc->dc_cdata.dc_rx_map[i]); + if (error) { + device_printf(dev, "failed to init RX ring\n"); + error = ENXIO; + goto fail; + } + } + error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); + if (error) { + device_printf(dev, "failed to init RX ring\n"); + error = ENXIO; + goto fail; + } + + ifp = sc->dc_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "can not if_alloc()\n"); + error = ENOSPC; + goto fail; + } + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = dc_ioctl; + ifp->if_start = dc_start; + ifp->if_init = dc_init; + IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); + ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; + IFQ_SET_READY(&ifp->if_snd); + + /* + * Do MII setup. If this is a 21143, check for a PHY on the + * MII bus after applying any necessary fixups to twiddle the + * GPIO bits. If we don't end up finding a PHY, restore the + * old selection (SIA only or SIA/SYM) and attach the dcphy + * driver instead. + */ + tmp = 0; + if (DC_IS_INTEL(sc)) { + dc_apply_fixup(sc, IFM_AUTO); + tmp = sc->dc_pmode; + sc->dc_pmode = DC_PMODE_MII; + } + + /* + * Setup General Purpose port mode and data so the tulip can talk + * to the MII. This needs to be done before mii_attach so that + * we can actually see them. + */ + if (DC_IS_XIRCOM(sc)) { + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + } + + phy = MII_PHY_ANY; + /* + * Note: both the AL981 and AN983 have internal PHYs, however the + * AL981 provides direct access to the PHY registers while the AN983 + * uses a serial MII interface. The AN983's MII interface is also + * buggy in that you can read from any MII address (0 to 31), but + * only address 1 behaves normally. To deal with both cases, we + * pretend that the PHY is at MII address 1. + */ + if (DC_IS_ADMTEK(sc)) + phy = DC_ADMTEK_PHYADDR; + + /* + * Note: the ukphy probes of the RS7112 report a PHY at MII address + * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the + * correct one. + */ + if (DC_IS_CONEXANT(sc)) + phy = DC_CONEXANT_PHYADDR; + + error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, + dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); + + if (error && DC_IS_INTEL(sc)) { + sc->dc_pmode = tmp; + if (sc->dc_pmode != DC_PMODE_SIA) + sc->dc_pmode = DC_PMODE_SYM; + sc->dc_flags |= DC_21143_NWAY; + mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, + dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, + MII_OFFSET_ANY, 0); + /* + * For non-MII cards, we need to have the 21143 + * drive the LEDs. Except there are some systems + * like the NEC VersaPro NoteBook PC which have no + * LEDs, and twiddling these bits has adverse effects + * on them. (I.e. you suddenly can't get a link.) + */ + if (!(pci_get_subvendor(dev) == 0x1033 && + pci_get_subdevice(dev) == 0x8028)) + sc->dc_flags |= DC_TULIP_LEDS; + error = 0; + } + + if (error) { + device_printf(dev, "attaching PHYs failed\n"); + goto fail; + } + + if (DC_IS_ADMTEK(sc)) { + /* + * Set automatic TX underrun recovery for the ADMtek chips + */ + DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); + } + + /* + * Tell the upper layer(s) we support long frames. + */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + ifp->if_capabilities |= IFCAP_VLAN_MTU; + ifp->if_capenable = ifp->if_capabilities; +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); + callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); + + /* + * Call MI attach routine. + */ + ether_ifattach(ifp, (caddr_t)eaddr); + + /* Hook interrupt last to avoid having to lock softc */ + error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, dc_intr, sc, &sc->dc_intrhand); + + if (error) { + device_printf(dev, "couldn't set up irq\n"); + ether_ifdetach(ifp); + goto fail; + } + +fail: + if (error) + dc_detach(dev); + return (error); +} + +/* + * Shutdown hardware and free up resources. This can be called any + * time after the mutex has been initialized. It is called in both + * the error case in attach and the normal detach case so it needs + * to be careful about only freeing resources that have actually been + * allocated. + */ +static int +dc_detach(device_t dev) +{ + struct dc_softc *sc; + struct ifnet *ifp; + struct dc_mediainfo *m; + int i; + + sc = device_get_softc(dev); + KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); + + ifp = sc->dc_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(ifp); +#endif + + /* These should only be active if attach succeeded */ + if (device_is_attached(dev)) { + DC_LOCK(sc); + dc_stop(sc); + DC_UNLOCK(sc); + callout_drain(&sc->dc_stat_ch); + callout_drain(&sc->dc_wdog_ch); + ether_ifdetach(ifp); + } + if (sc->dc_miibus) + device_delete_child(dev, sc->dc_miibus); + bus_generic_detach(dev); + + if (sc->dc_intrhand) + bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); + if (sc->dc_irq) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); + if (sc->dc_res) + bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); + + if (ifp) + if_free(ifp); + + if (sc->dc_cdata.dc_sbuf != NULL) + bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); + if (sc->dc_ldata != NULL) + bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); + if (sc->dc_mtag) { + for (i = 0; i < DC_TX_LIST_CNT; i++) + if (sc->dc_cdata.dc_tx_map[i] != NULL) + bus_dmamap_destroy(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[i]); + for (i = 0; i < DC_RX_LIST_CNT; i++) + if (sc->dc_cdata.dc_rx_map[i] != NULL) + bus_dmamap_destroy(sc->dc_mtag, + sc->dc_cdata.dc_rx_map[i]); + bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); + } + if (sc->dc_stag) + bus_dma_tag_destroy(sc->dc_stag); + if (sc->dc_mtag) + bus_dma_tag_destroy(sc->dc_mtag); + if (sc->dc_ltag) + bus_dma_tag_destroy(sc->dc_ltag); + + free(sc->dc_pnic_rx_buf, M_DEVBUF); + + while (sc->dc_mi != NULL) { + m = sc->dc_mi->dc_next; + free(sc->dc_mi, M_DEVBUF); + sc->dc_mi = m; + } + free(sc->dc_srom, M_DEVBUF); + + mtx_destroy(&sc->dc_mtx); + + return (0); +} + +/* + * Initialize the transmit descriptors. + */ +static int +dc_list_tx_init(struct dc_softc *sc) +{ + struct dc_chain_data *cd; + struct dc_list_data *ld; + int i, nexti; + + cd = &sc->dc_cdata; + ld = sc->dc_ldata; + for (i = 0; i < DC_TX_LIST_CNT; i++) { + if (i == DC_TX_LIST_CNT - 1) + nexti = 0; + else + nexti = i + 1; + ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); + cd->dc_tx_chain[i] = NULL; + ld->dc_tx_list[i].dc_data = 0; + ld->dc_tx_list[i].dc_ctl = 0; + } + + cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + + +/* + * Initialize the RX descriptors and allocate mbufs for them. Note that + * we arrange the descriptors in a closed ring, so that the last descriptor + * points back to the first. + */ +static int +dc_list_rx_init(struct dc_softc *sc) +{ + struct dc_chain_data *cd; + struct dc_list_data *ld; + int i, nexti; + + cd = &sc->dc_cdata; + ld = sc->dc_ldata; + + for (i = 0; i < DC_RX_LIST_CNT; i++) { + if (dc_newbuf(sc, i, 1) != 0) + return (ENOBUFS); + if (i == DC_RX_LIST_CNT - 1) + nexti = 0; + else + nexti = i + 1; + ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); + } + + cd->dc_rx_prod = 0; + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +/* + * Initialize an RX descriptor and attach an MBUF cluster. + */ +static int +dc_newbuf(struct dc_softc *sc, int i, int alloc) +{ + struct mbuf *m_new; + bus_dmamap_t tmp; + bus_dma_segment_t segs[1]; + int error, nseg; + + if (alloc) { + m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m_new == NULL) + return (ENOBUFS); + } else { + m_new = sc->dc_cdata.dc_rx_chain[i]; + m_new->m_data = m_new->m_ext.ext_buf; + } + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + m_adj(m_new, sizeof(u_int64_t)); + + /* + * If this is a PNIC chip, zero the buffer. This is part + * of the workaround for the receive bug in the 82c168 and + * 82c169 chips. + */ + if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) + bzero(mtod(m_new, char *), m_new->m_len); + + /* No need to remap the mbuf if we're reusing it. */ + if (alloc) { + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, + m_new, segs, &nseg, 0); + if (error) { + m_freem(m_new); + return (error); + } + KASSERT(nseg == 1, + ("%s: wrong number of segments (%d)", __func__, nseg)); + sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); + bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); + tmp = sc->dc_cdata.dc_rx_map[i]; + sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; + sc->dc_sparemap = tmp; + sc->dc_cdata.dc_rx_chain[i] = m_new; + } + + sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); + sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], + BUS_DMASYNC_PREREAD); + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +/* + * Grrrrr. + * The PNIC chip has a terrible bug in it that manifests itself during + * periods of heavy activity. The exact mode of failure if difficult to + * pinpoint: sometimes it only happens in promiscuous mode, sometimes it + * will happen on slow machines. The bug is that sometimes instead of + * uploading one complete frame during reception, it uploads what looks + * like the entire contents of its FIFO memory. The frame we want is at + * the end of the whole mess, but we never know exactly how much data has + * been uploaded, so salvaging the frame is hard. + * + * There is only one way to do it reliably, and it's disgusting. + * Here's what we know: + * + * - We know there will always be somewhere between one and three extra + * descriptors uploaded. + * + * - We know the desired received frame will always be at the end of the + * total data upload. + * + * - We know the size of the desired received frame because it will be + * provided in the length field of the status word in the last descriptor. + * + * Here's what we do: + * + * - When we allocate buffers for the receive ring, we bzero() them. + * This means that we know that the buffer contents should be all + * zeros, except for data uploaded by the chip. + * + * - We also force the PNIC chip to upload frames that include the + * ethernet CRC at the end. + * + * - We gather all of the bogus frame data into a single buffer. + * + * - We then position a pointer at the end of this buffer and scan + * backwards until we encounter the first non-zero byte of data. + * This is the end of the received frame. We know we will encounter + * some data at the end of the frame because the CRC will always be + * there, so even if the sender transmits a packet of all zeros, + * we won't be fooled. + * + * - We know the size of the actual received frame, so we subtract + * that value from the current pointer location. This brings us + * to the start of the actual received packet. + * + * - We copy this into an mbuf and pass it on, along with the actual + * frame length. + * + * The performance hit is tremendous, but it beats dropping frames all + * the time. + */ + +#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) +static void +dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) +{ + struct dc_desc *cur_rx; + struct dc_desc *c = NULL; + struct mbuf *m = NULL; + unsigned char *ptr; + int i, total_len; + u_int32_t rxstat = 0; + + i = sc->dc_pnic_rx_bug_save; + cur_rx = &sc->dc_ldata->dc_rx_list[idx]; + ptr = sc->dc_pnic_rx_buf; + bzero(ptr, DC_RXLEN * 5); + + /* Copy all the bytes from the bogus buffers. */ + while (1) { + c = &sc->dc_ldata->dc_rx_list[i]; + rxstat = le32toh(c->dc_status); + m = sc->dc_cdata.dc_rx_chain[i]; + bcopy(mtod(m, char *), ptr, DC_RXLEN); + ptr += DC_RXLEN; + /* If this is the last buffer, break out. */ + if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) + break; + dc_newbuf(sc, i, 0); + DC_INC(i, DC_RX_LIST_CNT); + } + + /* Find the length of the actual receive frame. */ + total_len = DC_RXBYTES(rxstat); + + /* Scan backwards until we hit a non-zero byte. */ + while (*ptr == 0x00) + ptr--; + + /* Round off. */ + if ((uintptr_t)(ptr) & 0x3) + ptr -= 1; + + /* Now find the start of the frame. */ + ptr -= total_len; + if (ptr < sc->dc_pnic_rx_buf) + ptr = sc->dc_pnic_rx_buf; + + /* + * Now copy the salvaged frame to the last mbuf and fake up + * the status word to make it look like a successful + * frame reception. + */ + dc_newbuf(sc, i, 0); + bcopy(ptr, mtod(m, char *), total_len); + cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); +} + +/* + * This routine searches the RX ring for dirty descriptors in the + * event that the rxeof routine falls out of sync with the chip's + * current descriptor pointer. This may happen sometimes as a result + * of a "no RX buffer available" condition that happens when the chip + * consumes all of the RX buffers before the driver has a chance to + * process the RX ring. This routine may need to be called more than + * once to bring the driver back in sync with the chip, however we + * should still be getting RX DONE interrupts to drive the search + * for new packets in the RX ring, so we should catch up eventually. + */ +static int +dc_rx_resync(struct dc_softc *sc) +{ + struct dc_desc *cur_rx; + int i, pos; + + pos = sc->dc_cdata.dc_rx_prod; + + for (i = 0; i < DC_RX_LIST_CNT; i++) { + cur_rx = &sc->dc_ldata->dc_rx_list[pos]; + if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) + break; + DC_INC(pos, DC_RX_LIST_CNT); + } + + /* If the ring really is empty, then just return. */ + if (i == DC_RX_LIST_CNT) + return (0); + + /* We've fallen behing the chip: catch it. */ + sc->dc_cdata.dc_rx_prod = pos; + + return (EAGAIN); +} + +/* + * A frame has been uploaded: pass the resulting mbuf chain up to + * the higher level protocols. + */ +static int +dc_rxeof(struct dc_softc *sc) +{ + struct mbuf *m, *m0; + struct ifnet *ifp; + struct dc_desc *cur_rx; + int i, total_len, rx_npkts; + u_int32_t rxstat; + + DC_LOCK_ASSERT(sc); + + ifp = sc->dc_ifp; + i = sc->dc_cdata.dc_rx_prod; + total_len = 0; + rx_npkts = 0; + + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); + while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & + DC_RXSTAT_OWN)) { +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + if (sc->rxcycles <= 0) + break; + sc->rxcycles--; + } +#endif + cur_rx = &sc->dc_ldata->dc_rx_list[i]; + rxstat = le32toh(cur_rx->dc_status); + m = sc->dc_cdata.dc_rx_chain[i]; + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], + BUS_DMASYNC_POSTREAD); + total_len = DC_RXBYTES(rxstat); + + if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { + if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { + if (rxstat & DC_RXSTAT_FIRSTFRAG) + sc->dc_pnic_rx_bug_save = i; + if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { + DC_INC(i, DC_RX_LIST_CNT); + continue; + } + dc_pnic_rx_bug_war(sc, i); + rxstat = le32toh(cur_rx->dc_status); + total_len = DC_RXBYTES(rxstat); + } + } + + /* + * If an error occurs, update stats, clear the + * status word and leave the mbuf cluster in place: + * it should simply get re-used next time this descriptor + * comes up in the ring. However, don't report long + * frames as errors since they could be vlans. + */ + if ((rxstat & DC_RXSTAT_RXERR)) { + if (!(rxstat & DC_RXSTAT_GIANT) || + (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | + DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | + DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { + ifp->if_ierrors++; + if (rxstat & DC_RXSTAT_COLLSEEN) + ifp->if_collisions++; + dc_newbuf(sc, i, 0); + if (rxstat & DC_RXSTAT_CRCERR) { + DC_INC(i, DC_RX_LIST_CNT); + continue; + } else { + dc_init_locked(sc); + return (rx_npkts); + } + } + } + + /* No errors; receive the packet. */ + total_len -= ETHER_CRC_LEN; +#ifdef __NO_STRICT_ALIGNMENT + /* + * On architectures without alignment problems we try to + * allocate a new buffer for the receive ring, and pass up + * the one where the packet is already, saving the expensive + * copy done in m_devget(). + * If we are on an architecture with alignment problems, or + * if the allocation fails, then use m_devget and leave the + * existing buffer in the receive ring. + */ + if (dc_newbuf(sc, i, 1) == 0) { + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = total_len; + DC_INC(i, DC_RX_LIST_CNT); + } else +#endif + { + m0 = m_devget(mtod(m, char *), total_len, + ETHER_ALIGN, ifp, NULL); + dc_newbuf(sc, i, 0); + DC_INC(i, DC_RX_LIST_CNT); + if (m0 == NULL) { + ifp->if_ierrors++; + continue; + } + m = m0; + } + + ifp->if_ipackets++; + DC_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + DC_LOCK(sc); + rx_npkts++; + } + + sc->dc_cdata.dc_rx_prod = i; + return (rx_npkts); +} + +/* + * A frame was downloaded to the chip. It's safe for us to clean up + * the list buffers. + */ +static void +dc_txeof(struct dc_softc *sc) +{ + struct dc_desc *cur_tx = NULL; + struct ifnet *ifp; + int idx; + u_int32_t ctl, txstat; + + ifp = sc->dc_ifp; + + /* + * Go through our tx list and free mbufs for those + * frames that have been transmitted. + */ + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); + idx = sc->dc_cdata.dc_tx_cons; + while (idx != sc->dc_cdata.dc_tx_prod) { + + cur_tx = &sc->dc_ldata->dc_tx_list[idx]; + txstat = le32toh(cur_tx->dc_status); + ctl = le32toh(cur_tx->dc_ctl); + + if (txstat & DC_TXSTAT_OWN) + break; + + if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { + if (ctl & DC_TXCTL_SETUP) { + /* + * Yes, the PNIC is so brain damaged + * that it will sometimes generate a TX + * underrun error while DMAing the RX + * filter setup frame. If we detect this, + * we have to send the setup frame again, + * or else the filter won't be programmed + * correctly. + */ + if (DC_IS_PNIC(sc)) { + if (txstat & DC_TXSTAT_ERRSUM) + dc_setfilt(sc); + } + sc->dc_cdata.dc_tx_chain[idx] = NULL; + } + sc->dc_cdata.dc_tx_cnt--; + DC_INC(idx, DC_TX_LIST_CNT); + continue; + } + + if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { + /* + * XXX: Why does my Xircom taunt me so? + * For some reason it likes setting the CARRLOST flag + * even when the carrier is there. wtf?!? + * Who knows, but Conexant chips have the + * same problem. Maybe they took lessons + * from Xircom. + */ + if (/*sc->dc_type == DC_TYPE_21143 &&*/ + sc->dc_pmode == DC_PMODE_MII && + ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | + DC_TXSTAT_NOCARRIER))) + txstat &= ~DC_TXSTAT_ERRSUM; + } else { + if (/*sc->dc_type == DC_TYPE_21143 &&*/ + sc->dc_pmode == DC_PMODE_MII && + ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | + DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) + txstat &= ~DC_TXSTAT_ERRSUM; + } + + if (txstat & DC_TXSTAT_ERRSUM) { + ifp->if_oerrors++; + if (txstat & DC_TXSTAT_EXCESSCOLL) + ifp->if_collisions++; + if (txstat & DC_TXSTAT_LATECOLL) + ifp->if_collisions++; + if (!(txstat & DC_TXSTAT_UNDERRUN)) { + dc_init_locked(sc); + return; + } + } + + ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; + + ifp->if_opackets++; + if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { + bus_dmamap_sync(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx]); + m_freem(sc->dc_cdata.dc_tx_chain[idx]); + sc->dc_cdata.dc_tx_chain[idx] = NULL; + } + + sc->dc_cdata.dc_tx_cnt--; + DC_INC(idx, DC_TX_LIST_CNT); + } + sc->dc_cdata.dc_tx_cons = idx; + + if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + if (sc->dc_cdata.dc_tx_cnt == 0) + sc->dc_wdog_timer = 0; +} + +static void +dc_tick(void *xsc) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + u_int32_t r; + + sc = xsc; + DC_LOCK_ASSERT(sc); + ifp = sc->dc_ifp; + mii = device_get_softc(sc->dc_miibus); + + if (sc->dc_flags & DC_REDUCED_MII_POLL) { + if (sc->dc_flags & DC_21143_NWAY) { + r = CSR_READ_4(sc, DC_10BTSTAT); + if (IFM_SUBTYPE(mii->mii_media_active) == + IFM_100_TX && (r & DC_TSTAT_LS100)) { + sc->dc_link = 0; + mii_mediachg(mii); + } + if (IFM_SUBTYPE(mii->mii_media_active) == + IFM_10_T && (r & DC_TSTAT_LS10)) { + sc->dc_link = 0; + mii_mediachg(mii); + } + if (sc->dc_link == 0) + mii_tick(mii); + } else { + /* + * For NICs which never report DC_RXSTATE_WAIT, we + * have to bite the bullet... + */ + if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, + DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && + sc->dc_cdata.dc_tx_cnt == 0) { + mii_tick(mii); + if (!(mii->mii_media_status & IFM_ACTIVE)) + sc->dc_link = 0; + } + } + } else + mii_tick(mii); + + /* + * When the init routine completes, we expect to be able to send + * packets right away, and in fact the network code will send a + * gratuitous ARP the moment the init routine marks the interface + * as running. However, even though the MAC may have been initialized, + * there may be a delay of a few seconds before the PHY completes + * autonegotiation and the link is brought up. Any transmissions + * made during that delay will be lost. Dealing with this is tricky: + * we can't just pause in the init routine while waiting for the + * PHY to come ready since that would bring the whole system to + * a screeching halt for several seconds. + * + * What we do here is prevent the TX start routine from sending + * any packets until a link has been established. After the + * interface has been initialized, the tick routine will poll + * the state of the PHY until the IFM_ACTIVE flag is set. Until + * that time, packets will stay in the send queue, and once the + * link comes up, they will be flushed out to the wire. + */ + if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->dc_link++; + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); + } + + if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) + callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); + else + callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); +} + +/* + * A transmit underrun has occurred. Back off the transmit threshold, + * or switch to store and forward mode if we have to. + */ +static void +dc_tx_underrun(struct dc_softc *sc) +{ + u_int32_t isr; + int i; + + if (DC_IS_DAVICOM(sc)) + dc_init_locked(sc); + + if (DC_IS_INTEL(sc)) { + /* + * The real 21143 requires that the transmitter be idle + * in order to change the transmit threshold or store + * and forward state. + */ + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + + for (i = 0; i < DC_TIMEOUT; i++) { + isr = CSR_READ_4(sc, DC_ISR); + if (isr & DC_ISR_TX_IDLE) + break; + DELAY(10); + } + if (i == DC_TIMEOUT) { + device_printf(sc->dc_dev, + "%s: failed to force tx to idle state\n", + __func__); + dc_init_locked(sc); + } + } + + device_printf(sc->dc_dev, "TX underrun -- "); + sc->dc_txthresh += DC_TXTHRESH_INC; + if (sc->dc_txthresh > DC_TXTHRESH_MAX) { + printf("using store and forward mode\n"); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + } else { + printf("increasing TX threshold\n"); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); + DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); + } + + if (DC_IS_INTEL(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); +} + +#ifdef DEVICE_POLLING +static poll_handler_t dc_poll; + +static int +dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct dc_softc *sc = ifp->if_softc; + int rx_npkts = 0; + + DC_LOCK(sc); + + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + DC_UNLOCK(sc); + return (rx_npkts); + } + + sc->rxcycles = count; + rx_npkts = dc_rxeof(sc); + dc_txeof(sc); + if (!IFQ_IS_EMPTY(&ifp->if_snd) && + !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) + dc_start_locked(ifp); + + if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ + u_int32_t status; + + status = CSR_READ_4(sc, DC_ISR); + status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | + DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | + DC_ISR_BUS_ERR); + if (!status) { + DC_UNLOCK(sc); + return (rx_npkts); + } + /* ack what we have */ + CSR_WRITE_4(sc, DC_ISR, status); + + if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { + u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); + ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); + + if (dc_rx_resync(sc)) + dc_rxeof(sc); + } + /* restart transmit unit if necessary */ + if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + if (status & DC_ISR_TX_UNDERRUN) + dc_tx_underrun(sc); + + if (status & DC_ISR_BUS_ERR) { + if_printf(ifp, "%s: bus error\n", __func__); + dc_reset(sc); + dc_init_locked(sc); + } + } + DC_UNLOCK(sc); + return (rx_npkts); +} +#endif /* DEVICE_POLLING */ + +static void +dc_intr(void *arg) +{ + struct dc_softc *sc; + struct ifnet *ifp; + u_int32_t status; + + sc = arg; + + if (sc->suspended) + return; + + if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) + return; + + DC_LOCK(sc); + ifp = sc->dc_ifp; +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + DC_UNLOCK(sc); + return; + } +#endif + + /* Suppress unwanted interrupts */ + if (!(ifp->if_flags & IFF_UP)) { + if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) + dc_stop(sc); + DC_UNLOCK(sc); + return; + } + + /* Disable interrupts. */ + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + + while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && + status != 0xFFFFFFFF && + (ifp->if_drv_flags & IFF_DRV_RUNNING)) { + + CSR_WRITE_4(sc, DC_ISR, status); + + if (status & DC_ISR_RX_OK) { + int curpkts; + curpkts = ifp->if_ipackets; + dc_rxeof(sc); + if (curpkts == ifp->if_ipackets) { + while (dc_rx_resync(sc)) + dc_rxeof(sc); + } + } + + if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) + dc_txeof(sc); + + if (status & DC_ISR_TX_IDLE) { + dc_txeof(sc); + if (sc->dc_cdata.dc_tx_cnt) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + } + } + + if (status & DC_ISR_TX_UNDERRUN) + dc_tx_underrun(sc); + + if ((status & DC_ISR_RX_WATDOGTIMEO) + || (status & DC_ISR_RX_NOBUF)) { + int curpkts; + curpkts = ifp->if_ipackets; + dc_rxeof(sc); + if (curpkts == ifp->if_ipackets) { + while (dc_rx_resync(sc)) + dc_rxeof(sc); + } + } + + if (status & DC_ISR_BUS_ERR) { + dc_reset(sc); + dc_init_locked(sc); + } + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); + + DC_UNLOCK(sc); +} + +/* + * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data + * pointers to the fragment pointers. + */ +static int +dc_encap(struct dc_softc *sc, struct mbuf **m_head) +{ + bus_dma_segment_t segs[DC_MAXFRAGS]; + struct dc_desc *f; + struct mbuf *m; + int cur, defragged, error, first, frag, i, idx, nseg; + + /* + * If there's no way we can send any packets, return now. + */ + if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) + return (ENOBUFS); + + m = NULL; + defragged = 0; + if (sc->dc_flags & DC_TX_COALESCE && + ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { + m = m_defrag(*m_head, M_DONTWAIT); + defragged = 1; + } else { + /* + * Count the number of frags in this chain to see if we + * need to m_collapse. Since the descriptor list is shared + * by all packets, we'll m_collapse long chains so that they + * do not use up the entire list, even if they would fit. + */ + i = 0; + for (m = *m_head; m != NULL; m = m->m_next) + i++; + if (i > DC_TX_LIST_CNT / 4 || + DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= + DC_TX_LIST_RSVD) { + m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); + defragged = 1; + } + } + if (defragged != 0) { + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + } + + idx = sc->dc_cdata.dc_tx_prod; + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); + if (error == EFBIG) { + if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, + DC_MAXFRAGS)) == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (defragged != 0 ? error : ENOBUFS); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + KASSERT(nseg <= DC_MAXFRAGS, + ("%s: wrong number of segments (%d)", __func__, nseg)); + if (nseg == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + first = cur = frag = sc->dc_cdata.dc_tx_prod; + for (i = 0; i < nseg; i++) { + if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && + (frag == (DC_TX_LIST_CNT - 1)) && + (first != sc->dc_cdata.dc_tx_first)) { + bus_dmamap_unload(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[first]); + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + + f = &sc->dc_ldata->dc_tx_list[frag]; + f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); + if (i == 0) { + f->dc_status = 0; + f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); + } else + f->dc_status = htole32(DC_TXSTAT_OWN); + f->dc_data = htole32(segs[i].ds_addr); + cur = frag; + DC_INC(frag, DC_TX_LIST_CNT); + } + + sc->dc_cdata.dc_tx_prod = frag; + sc->dc_cdata.dc_tx_cnt += nseg; + sc->dc_cdata.dc_tx_chain[cur] = *m_head; + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); + if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) + sc->dc_ldata->dc_tx_list[first].dc_ctl |= + htole32(DC_TXCTL_FINT); + if (sc->dc_flags & DC_TX_INTR_ALWAYS) + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); + if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); + sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); + + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +static void +dc_start(struct ifnet *ifp) +{ + struct dc_softc *sc; + + sc = ifp->if_softc; + DC_LOCK(sc); + dc_start_locked(ifp); + DC_UNLOCK(sc); +} + +/* + * Main transmit routine + * To avoid having to do mbuf copies, we put pointers to the mbuf data + * regions directly in the transmit lists. We also save a copy of the + * pointers since the transmit list fragment pointers are physical + * addresses. + */ +static void +dc_start_locked(struct ifnet *ifp) +{ + struct dc_softc *sc; + struct mbuf *m_head = NULL; + unsigned int queued = 0; + int idx; + + sc = ifp->if_softc; + + DC_LOCK_ASSERT(sc); + + if (!sc->dc_link && ifp->if_snd.ifq_len < 10) + return; + + if (ifp->if_drv_flags & IFF_DRV_OACTIVE) + return; + + idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; + + while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + if (dc_encap(sc, &m_head)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + idx = sc->dc_cdata.dc_tx_prod; + + queued++; + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + BPF_MTAP(ifp, m_head); + + if (sc->dc_flags & DC_TX_ONE) { + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + } + + if (queued > 0) { + /* Transmit */ + if (!(sc->dc_flags & DC_TX_POLL)) + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->dc_wdog_timer = 5; + } +} + +static void +dc_init(void *xsc) +{ + struct dc_softc *sc = xsc; + + DC_LOCK(sc); + dc_init_locked(sc); + DC_UNLOCK(sc); +} + +static void +dc_init_locked(struct dc_softc *sc) +{ + struct ifnet *ifp = sc->dc_ifp; + struct mii_data *mii; + + DC_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->dc_miibus); + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + dc_stop(sc); + dc_reset(sc); + + /* + * Set cache alignment and burst length. + */ + if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) + CSR_WRITE_4(sc, DC_BUSCTL, 0); + else + CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); + /* + * Evenly share the bus between receive and transmit process. + */ + if (DC_IS_INTEL(sc)) + DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); + if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { + DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); + } else { + DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); + } + if (sc->dc_flags & DC_TX_POLL) + DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); + switch(sc->dc_cachesize) { + case 32: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); + break; + case 16: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); + break; + case 8: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); + break; + case 0: + default: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); + break; + } + + if (sc->dc_flags & DC_TX_STORENFWD) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + else { + if (sc->dc_txthresh > DC_TXTHRESH_MAX) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); + } + } + + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); + + if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { + /* + * The app notes for the 98713 and 98715A say that + * in order to have the chips operate properly, a magic + * number must be written to CSR16. Macronix does not + * document the meaning of these bits so there's no way + * to know exactly what they do. The 98713 has a magic + * number all its own; the rest all use a different one. + */ + DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); + else + DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); + } + + if (DC_IS_XIRCOM(sc)) { + /* + * setup General Purpose Port mode and data so the tulip + * can talk to the MII. + */ + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + } + + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); + DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); + + /* Init circular RX list. */ + if (dc_list_rx_init(sc) == ENOBUFS) { + device_printf(sc->dc_dev, + "initialization failed: no memory for rx buffers\n"); + dc_stop(sc); + return; + } + + /* + * Init TX descriptors. + */ + dc_list_tx_init(sc); + + /* + * Load the address of the RX list. + */ + CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); + CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); + + /* + * Enable interrupts. + */ +#ifdef DEVICE_POLLING + /* + * ... but only if we are not polling, and make sure they are off in + * the case of polling. Some cards (e.g. fxp) turn interrupts on + * after a reset. + */ + if (ifp->if_capenable & IFCAP_POLLING) + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + else +#endif + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); + + /* Enable transmitter. */ + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + + /* + * If this is an Intel 21143 and we're not using the + * MII port, program the LED control pins so we get + * link and activity indications. + */ + if (sc->dc_flags & DC_TULIP_LEDS) { + CSR_WRITE_4(sc, DC_WATCHDOG, + DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); + CSR_WRITE_4(sc, DC_WATCHDOG, 0); + } + + /* + * Load the RX/multicast filter. We do this sort of late + * because the filter programming scheme on the 21143 and + * some clones requires DMAing a setup frame via the TX + * engine, and we need the transmitter enabled for that. + */ + dc_setfilt(sc); + + /* Enable receiver. */ + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); + CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); + + mii_mediachg(mii); + dc_setcfg(sc, sc->dc_if_media); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + /* Don't start the ticker if this is a homePNA link. */ + if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) + sc->dc_link = 1; + else { + if (sc->dc_flags & DC_21143_NWAY) + callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); + else + callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); + } + + sc->dc_wdog_timer = 0; + callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); +} + +/* + * Set media options. + */ +static int +dc_ifmedia_upd(struct ifnet *ifp) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = ifp->if_softc; + mii = device_get_softc(sc->dc_miibus); + DC_LOCK(sc); + mii_mediachg(mii); + ifm = &mii->mii_media; + + if (DC_IS_DAVICOM(sc) && + IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) + dc_setcfg(sc, ifm->ifm_media); + else + sc->dc_link = 0; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Report current media status. + */ +static void +dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = ifp->if_softc; + mii = device_get_softc(sc->dc_miibus); + DC_LOCK(sc); + mii_pollstat(mii); + ifm = &mii->mii_media; + if (DC_IS_DAVICOM(sc)) { + if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { + ifmr->ifm_active = ifm->ifm_media; + ifmr->ifm_status = 0; + DC_UNLOCK(sc); + return; + } + } + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + DC_UNLOCK(sc); +} + +static int +dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct dc_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + struct mii_data *mii; + int error = 0; + + switch (command) { + case SIOCSIFFLAGS: + DC_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & + (IFF_PROMISC | IFF_ALLMULTI); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + if (need_setfilt) + dc_setfilt(sc); + } else { + sc->dc_txthresh = 0; + dc_init_locked(sc); + } + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + dc_stop(sc); + } + sc->dc_if_flags = ifp->if_flags; + DC_UNLOCK(sc); + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + DC_LOCK(sc); + dc_setfilt(sc); + DC_UNLOCK(sc); + error = 0; + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + mii = device_get_softc(sc->dc_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); + break; + case SIOCSIFCAP: +#ifdef DEVICE_POLLING + if (ifr->ifr_reqcap & IFCAP_POLLING && + !(ifp->if_capenable & IFCAP_POLLING)) { + error = ether_poll_register(dc_poll, ifp); + if (error) + return(error); + DC_LOCK(sc); + /* Disable interrupts */ + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + ifp->if_capenable |= IFCAP_POLLING; + DC_UNLOCK(sc); + return (error); + } + if (!(ifr->ifr_reqcap & IFCAP_POLLING) && + ifp->if_capenable & IFCAP_POLLING) { + error = ether_poll_deregister(ifp); + /* Enable interrupts. */ + DC_LOCK(sc); + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + ifp->if_capenable &= ~IFCAP_POLLING; + DC_UNLOCK(sc); + return (error); + } +#endif /* DEVICE_POLLING */ + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +dc_watchdog(void *xsc) +{ + struct dc_softc *sc = xsc; + struct ifnet *ifp; + + DC_LOCK_ASSERT(sc); + + if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { + callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); + return; + } + + ifp = sc->dc_ifp; + ifp->if_oerrors++; + device_printf(sc->dc_dev, "watchdog timeout\n"); + + dc_stop(sc); + dc_reset(sc); + dc_init_locked(sc); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +dc_stop(struct dc_softc *sc) +{ + struct ifnet *ifp; + struct dc_list_data *ld; + struct dc_chain_data *cd; + int i; + u_int32_t ctl; + + DC_LOCK_ASSERT(sc); + + ifp = sc->dc_ifp; + ld = sc->dc_ldata; + cd = &sc->dc_cdata; + + callout_stop(&sc->dc_stat_ch); + callout_stop(&sc->dc_wdog_ch); + sc->dc_wdog_timer = 0; + + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); + CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); + sc->dc_link = 0; + + /* + * Free data in the RX lists. + */ + for (i = 0; i < DC_RX_LIST_CNT; i++) { + if (cd->dc_rx_chain[i] != NULL) { + m_freem(cd->dc_rx_chain[i]); + cd->dc_rx_chain[i] = NULL; + } + } + bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); + + /* + * Free the TX list buffers. + */ + for (i = 0; i < DC_TX_LIST_CNT; i++) { + if (cd->dc_tx_chain[i] != NULL) { + ctl = le32toh(ld->dc_tx_list[i].dc_ctl); + if ((ctl & DC_TXCTL_SETUP) || + !(ctl & DC_TXCTL_LASTFRAG)) { + cd->dc_tx_chain[i] = NULL; + continue; + } + bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); + m_freem(cd->dc_tx_chain[i]); + cd->dc_tx_chain[i] = NULL; + } + } + bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); +} + +/* + * Device suspend routine. Stop the interface and save some PCI + * settings in case the BIOS doesn't restore them properly on + * resume. + */ +static int +dc_suspend(device_t dev) +{ + struct dc_softc *sc; + + sc = device_get_softc(dev); + DC_LOCK(sc); + dc_stop(sc); + sc->suspended = 1; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Device resume routine. Restore some PCI settings in case the BIOS + * doesn't, re-enable busmastering, and restart the interface if + * appropriate. + */ +static int +dc_resume(device_t dev) +{ + struct dc_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + ifp = sc->dc_ifp; + + /* reinitialize interface if necessary */ + DC_LOCK(sc); + if (ifp->if_flags & IFF_UP) + dc_init_locked(sc); + + sc->suspended = 0; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static int +dc_shutdown(device_t dev) +{ + struct dc_softc *sc; + + sc = device_get_softc(dev); + + DC_LOCK(sc); + dc_stop(sc); + DC_UNLOCK(sc); + + return (0); +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dcreg.h b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dcreg.h new file mode 100644 index 0000000000..e77e4b917b --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dcreg.h @@ -0,0 +1,1172 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/dc/if_dcreg.h,v 1.57.2.2.2.1 2010/12/21 17:09:25 kensmith Exp $ + */ + +/* + * 21143 and clone common register definitions. + */ + +#define DC_BUSCTL 0x00 /* bus control */ +#define DC_TXSTART 0x08 /* tx start demand */ +#define DC_RXSTART 0x10 /* rx start demand */ +#define DC_RXADDR 0x18 /* rx descriptor list start addr */ +#define DC_TXADDR 0x20 /* tx descriptor list start addr */ +#define DC_ISR 0x28 /* interrupt status register */ +#define DC_NETCFG 0x30 /* network config register */ +#define DC_IMR 0x38 /* interrupt mask */ +#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ +#define DC_ROM 0x50 /* ROM programming address */ +#define DC_TIMER 0x58 /* general timer */ +#define DC_10BTSTAT 0x60 /* SIA status */ +#define DC_SIARESET 0x68 /* SIA connectivity */ +#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ +#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ +#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ + +/* + * There are two general 'types' of MX chips that we need to be + * concerned with. One is the original 98713, which has its internal + * NWAY support controlled via the MDIO bits in the serial I/O + * register. The other is everything else (from the 98713A on up), + * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, + * just like the 21143. This type setting also governs which of the + * 'magic' numbers we write to CSR16. The PNIC II falls into the + * 98713A/98715/98715A/98725 category. + */ +#define DC_TYPE_98713 0x1 +#define DC_TYPE_98713A 0x2 +#define DC_TYPE_987x5 0x3 + +/* Other type of supported chips. */ +#define DC_TYPE_21143 0x4 /* Intel 21143 */ +#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ +#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ +#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ +#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ +#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ +#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ +#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ +#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ + +#define DC_IS_MACRONIX(x) \ + (x->dc_type == DC_TYPE_98713 || \ + x->dc_type == DC_TYPE_98713A || \ + x->dc_type == DC_TYPE_987x5) + +#define DC_IS_ADMTEK(x) \ + (x->dc_type == DC_TYPE_AL981 || \ + x->dc_type == DC_TYPE_AN983) + +#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) +#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) +#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) +#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) +#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) +#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) +#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) +#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) +#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) + +/* MII/symbol mode port types */ +#define DC_PMODE_MII 0x1 +#define DC_PMODE_SYM 0x2 +#define DC_PMODE_SIA 0x3 + +/* + * Bus control bits. + */ +#define DC_BUSCTL_RESET 0x00000001 +#define DC_BUSCTL_ARBITRATION 0x00000002 +#define DC_BUSCTL_SKIPLEN 0x0000007C +#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 +#define DC_BUSCTL_BURSTLEN 0x00003F00 +#define DC_BUSCTL_CACHEALIGN 0x0000C000 +#define DC_BUSCTL_TXPOLL 0x000E0000 +#define DC_BUSCTL_DBO 0x00100000 +#define DC_BUSCTL_MRME 0x00200000 +#define DC_BUSCTL_MRLE 0x00800000 +#define DC_BUSCTL_MWIE 0x01000000 +#define DC_BUSCTL_ONNOW_ENB 0x04000000 + +#define DC_SKIPLEN_1LONG 0x00000004 +#define DC_SKIPLEN_2LONG 0x00000008 +#define DC_SKIPLEN_3LONG 0x00000010 +#define DC_SKIPLEN_4LONG 0x00000020 +#define DC_SKIPLEN_5LONG 0x00000040 + +#define DC_CACHEALIGN_NONE 0x00000000 +#define DC_CACHEALIGN_8LONG 0x00004000 +#define DC_CACHEALIGN_16LONG 0x00008000 +#define DC_CACHEALIGN_32LONG 0x0000C000 + +#define DC_BURSTLEN_USECA 0x00000000 +#define DC_BURSTLEN_1LONG 0x00000100 +#define DC_BURSTLEN_2LONG 0x00000200 +#define DC_BURSTLEN_4LONG 0x00000400 +#define DC_BURSTLEN_8LONG 0x00000800 +#define DC_BURSTLEN_16LONG 0x00001000 +#define DC_BURSTLEN_32LONG 0x00002000 + +#define DC_TXPOLL_OFF 0x00000000 +#define DC_TXPOLL_1 0x00020000 +#define DC_TXPOLL_2 0x00040000 +#define DC_TXPOLL_3 0x00060000 +#define DC_TXPOLL_4 0x00080000 +#define DC_TXPOLL_5 0x000A0000 +#define DC_TXPOLL_6 0x000C0000 +#define DC_TXPOLL_7 0x000E0000 + +/* + * Interrupt status bits. + */ +#define DC_ISR_TX_OK 0x00000001 +#define DC_ISR_TX_IDLE 0x00000002 +#define DC_ISR_TX_NOBUF 0x00000004 +#define DC_ISR_TX_JABBERTIMEO 0x00000008 +#define DC_ISR_LINKGOOD 0x00000010 +#define DC_ISR_TX_UNDERRUN 0x00000020 +#define DC_ISR_RX_OK 0x00000040 +#define DC_ISR_RX_NOBUF 0x00000080 +#define DC_ISR_RX_READ 0x00000100 +#define DC_ISR_RX_WATDOGTIMEO 0x00000200 +#define DC_ISR_TX_EARLY 0x00000400 +#define DC_ISR_TIMER_EXPIRED 0x00000800 +#define DC_ISR_LINKFAIL 0x00001000 +#define DC_ISR_BUS_ERR 0x00002000 +#define DC_ISR_RX_EARLY 0x00004000 +#define DC_ISR_ABNORMAL 0x00008000 +#define DC_ISR_NORMAL 0x00010000 +#define DC_ISR_RX_STATE 0x000E0000 +#define DC_ISR_TX_STATE 0x00700000 +#define DC_ISR_BUSERRTYPE 0x03800000 +#define DC_ISR_100MBPSLINK 0x08000000 +#define DC_ISR_MAGICKPACK 0x10000000 + +#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define DC_HAS_BROKEN_RXSTATE(x) \ + (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ + pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A)) + +#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define DC_NETCFG_RX_HASHPERF 0x00000001 +#define DC_NETCFG_RX_ON 0x00000002 +#define DC_NETCFG_RX_HASHONLY 0x00000004 +#define DC_NETCFG_RX_BADFRAMES 0x00000008 +#define DC_NETCFG_RX_INVFILT 0x00000010 +#define DC_NETCFG_BACKOFFCNT 0x00000020 +#define DC_NETCFG_RX_PROMISC 0x00000040 +#define DC_NETCFG_RX_ALLMULTI 0x00000080 +#define DC_NETCFG_FULLDUPLEX 0x00000200 +#define DC_NETCFG_LOOPBACK 0x00000C00 +#define DC_NETCFG_FORCECOLL 0x00001000 +#define DC_NETCFG_TX_ON 0x00002000 +#define DC_NETCFG_TX_THRESH 0x0000C000 +#define DC_NETCFG_TX_BACKOFF 0x00020000 +#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ +#define DC_NETCFG_HEARTBEAT 0x00080000 +#define DC_NETCFG_STORENFWD 0x00200000 +#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define DC_NETCFG_PCS 0x00800000 +#define DC_NETCFG_SCRAMBLER 0x01000000 +#define DC_NETCFG_NO_RXCRC 0x02000000 +#define DC_NETCFG_RX_ALL 0x40000000 +#define DC_NETCFG_CAPEFFECT 0x80000000 + +#define DC_OPMODE_NORM 0x00000000 +#define DC_OPMODE_INTLOOP 0x00000400 +#define DC_OPMODE_EXTLOOP 0x00000800 + +#if 0 +#define DC_TXTHRESH_72BYTES 0x00000000 +#define DC_TXTHRESH_96BYTES 0x00004000 +#define DC_TXTHRESH_128BYTES 0x00008000 +#define DC_TXTHRESH_160BYTES 0x0000C000 +#endif + +#define DC_TXTHRESH_MIN 0x00000000 +#define DC_TXTHRESH_INC 0x00004000 +#define DC_TXTHRESH_MAX 0x0000C000 + + +/* + * Interrupt mask bits. + */ +#define DC_IMR_TX_OK 0x00000001 +#define DC_IMR_TX_IDLE 0x00000002 +#define DC_IMR_TX_NOBUF 0x00000004 +#define DC_IMR_TX_JABBERTIMEO 0x00000008 +#define DC_IMR_LINKGOOD 0x00000010 +#define DC_IMR_TX_UNDERRUN 0x00000020 +#define DC_IMR_RX_OK 0x00000040 +#define DC_IMR_RX_NOBUF 0x00000080 +#define DC_IMR_RX_READ 0x00000100 +#define DC_IMR_RX_WATDOGTIMEO 0x00000200 +#define DC_IMR_TX_EARLY 0x00000400 +#define DC_IMR_TIMER_EXPIRED 0x00000800 +#define DC_IMR_LINKFAIL 0x00001000 +#define DC_IMR_BUS_ERR 0x00002000 +#define DC_IMR_RX_EARLY 0x00004000 +#define DC_IMR_ABNORMAL 0x00008000 +#define DC_IMR_NORMAL 0x00010000 +#define DC_IMR_100MBPSLINK 0x08000000 +#define DC_IMR_MAGICKPACK 0x10000000 + +#define DC_INTRS \ + (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ + DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ + DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define DC_SIO_ROMDATA4 0x00000010 +#define DC_SIO_ROMDATA5 0x00000020 +#define DC_SIO_ROMDATA6 0x00000040 +#define DC_SIO_ROMDATA7 0x00000080 +#define DC_SIO_EESEL 0x00000800 +#define DC_SIO_ROMSEL 0x00001000 +#define DC_SIO_ROMCTL_WRITE 0x00002000 +#define DC_SIO_ROMCTL_READ 0x00004000 +#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define DC_EECMD_WRITE 0x140 +#define DC_EECMD_READ 0x180 +#define DC_EECMD_ERASE 0x1c0 + +#define DC_EE_NODEADDR_OFFSET 0x70 +#define DC_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define DC_TIMER_VALUE 0x0000FFFF +#define DC_TIMER_CONTINUOUS 0x00010000 + +/* + * 10baseT status register + */ +#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ +#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ +#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ +#define DC_TSTAT_AUTOPOLARITY 0x00000008 +#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ +#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ +#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ +#define DC_TSTAT_REMFAULT 0x00000800 +#define DC_TSTAT_ANEGSTAT 0x00007000 +#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ +#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ + +#define DC_ASTAT_DISABLE 0x00000000 +#define DC_ASTAT_TXDISABLE 0x00001000 +#define DC_ASTAT_ABDETECT 0x00002000 +#define DC_ASTAT_ACKDETECT 0x00003000 +#define DC_ASTAT_CMPACKDETECT 0x00004000 +#define DC_ASTAT_AUTONEGCMP 0x00005000 +#define DC_ASTAT_LINKCHECK 0x00006000 + +/* + * PHY reset register + */ +#define DC_SIA_RESET 0x00000001 +#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ + +/* + * 10baseT control register + */ +#define DC_TCTL_ENCODER_ENB 0x00000001 +#define DC_TCTL_LOOPBACK 0x00000002 +#define DC_TCTL_DRIVER_ENB 0x00000004 +#define DC_TCTL_LNKPULSE_ENB 0x00000008 +#define DC_TCTL_HALFDUPLEX 0x00000040 +#define DC_TCTL_AUTONEGENBL 0x00000080 +#define DC_TCTL_RX_SQUELCH 0x00000100 +#define DC_TCTL_COLL_SQUELCH 0x00000200 +#define DC_TCTL_COLL_DETECT 0x00000400 +#define DC_TCTL_SQE_ENB 0x00000800 +#define DC_TCTL_LINKTEST 0x00001000 +#define DC_TCTL_AUTOPOLARITY 0x00002000 +#define DC_TCTL_SET_POL_PLUS 0x00004000 +#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ +#define DC_TCTL_100BTXHALF 0x00010000 +#define DC_TCTL_100BTXFULL 0x00020000 +#define DC_TCTL_100BT4 0x00040000 + +/* + * Watchdog timer register + */ +#define DC_WDOG_JABBERDIS 0x00000001 +#define DC_WDOG_HOSTUNJAB 0x00000002 +#define DC_WDOG_JABBERCLK 0x00000004 +#define DC_WDOG_RXWDOGDIS 0x00000010 +#define DC_WDOG_RXWDOGCLK 0x00000020 +#define DC_WDOG_MUSTBEZERO 0x00000100 +#define DC_WDOG_AUIBNC 0x00100000 +#define DC_WDOG_ACTIVITY 0x00200000 +#define DC_WDOG_RX_MATCH 0x00400000 +#define DC_WDOG_LINK 0x00800000 +#define DC_WDOG_CTLWREN 0x08000000 + +/* + * SIA and General Purpose Port register (X3201) + */ +#define DC_SIAGP_RXMATCH 0x40000000 +#define DC_SIAGP_INT1 0x20000000 +#define DC_SIAGP_INT0 0x10000000 +#define DC_SIAGP_WRITE_EN 0x08000000 +#define DC_SIAGP_RXMATCH_EN 0x04000000 +#define DC_SIAGP_INT1_EN 0x02000000 +#define DC_SIAGP_INT0_EN 0x01000000 +#define DC_SIAGP_LED3 0x00800000 +#define DC_SIAGP_LED2 0x00400000 +#define DC_SIAGP_LED1 0x00200000 +#define DC_SIAGP_LED0 0x00100000 +#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 +#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 +#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 +#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 + +/* + * Size of a setup frame. + */ +#define DC_SFRAME_LEN 192 + +/* + * 21x4x TX/RX list structure. + */ + +struct dc_desc { + u_int32_t dc_status; + u_int32_t dc_ctl; + u_int32_t dc_ptr1; + u_int32_t dc_ptr2; +}; + +#define dc_data dc_ptr1 +#define dc_next dc_ptr2 + +#define DC_RXSTAT_FIFOOFLOW 0x00000001 +#define DC_RXSTAT_CRCERR 0x00000002 +#define DC_RXSTAT_DRIBBLE 0x00000004 +#define DC_RXSTAT_MIIERE 0x00000008 +#define DC_RXSTAT_WATCHDOG 0x00000010 +#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define DC_RXSTAT_COLLSEEN 0x00000040 +#define DC_RXSTAT_GIANT 0x00000080 +#define DC_RXSTAT_LASTFRAG 0x00000100 +#define DC_RXSTAT_FIRSTFRAG 0x00000200 +#define DC_RXSTAT_MULTICAST 0x00000400 +#define DC_RXSTAT_RUNT 0x00000800 +#define DC_RXSTAT_RXTYPE 0x00003000 +#define DC_RXSTAT_DE 0x00004000 +#define DC_RXSTAT_RXERR 0x00008000 +#define DC_RXSTAT_RXLEN 0x3FFF0000 +#define DC_RXSTAT_OWN 0x80000000 + +#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) +#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) + +#define DC_RXCTL_BUFLEN1 0x00000FFF +#define DC_RXCTL_BUFLEN2 0x00FFF000 +#define DC_RXCTL_RLINK 0x01000000 +#define DC_RXCTL_RLAST 0x02000000 + +#define DC_TXSTAT_DEFER 0x00000001 +#define DC_TXSTAT_UNDERRUN 0x00000002 +#define DC_TXSTAT_LINKFAIL 0x00000003 +#define DC_TXSTAT_COLLCNT 0x00000078 +#define DC_TXSTAT_SQE 0x00000080 +#define DC_TXSTAT_EXCESSCOLL 0x00000100 +#define DC_TXSTAT_LATECOLL 0x00000200 +#define DC_TXSTAT_NOCARRIER 0x00000400 +#define DC_TXSTAT_CARRLOST 0x00000800 +#define DC_TXSTAT_JABTIMEO 0x00004000 +#define DC_TXSTAT_ERRSUM 0x00008000 +#define DC_TXSTAT_OWN 0x80000000 + +#define DC_TXCTL_BUFLEN1 0x000007FF +#define DC_TXCTL_BUFLEN2 0x003FF800 +#define DC_TXCTL_FILTTYPE0 0x00400000 +#define DC_TXCTL_PAD 0x00800000 +#define DC_TXCTL_TLINK 0x01000000 +#define DC_TXCTL_TLAST 0x02000000 +#define DC_TXCTL_NOCRC 0x04000000 +#define DC_TXCTL_SETUP 0x08000000 +#define DC_TXCTL_FILTTYPE1 0x10000000 +#define DC_TXCTL_FIRSTFRAG 0x20000000 +#define DC_TXCTL_LASTFRAG 0x40000000 +#define DC_TXCTL_FINT 0x80000000 + +#define DC_FILTER_PERFECT 0x00000000 +#define DC_FILTER_HASHPERF 0x00400000 +#define DC_FILTER_INVERSE 0x10000000 +#define DC_FILTER_HASHONLY 0x10400000 + +#define DC_MAXFRAGS 16 +#ifdef DEVICE_POLLING +#define DC_RX_LIST_CNT 192 +#else +#define DC_RX_LIST_CNT 64 +#endif +#define DC_TX_LIST_CNT 256 +#define DC_TX_LIST_RSVD 5 +#define DC_MIN_FRAMELEN 60 +#define DC_RXLEN 1536 + +#define DC_INC(x, y) (x) = (x + 1) % y + +/* Macros to easily get the DMA address of a descriptor. */ +#define DC_RXDESC(sc, i) (sc->dc_laddr + \ + (uintptr_t)(sc->dc_ldata->dc_rx_list + i) - (uintptr_t)sc->dc_ldata) +#define DC_TXDESC(sc, i) (sc->dc_laddr + \ + (uintptr_t)(sc->dc_ldata->dc_tx_list + i) - (uintptr_t)sc->dc_ldata) + +#if BYTE_ORDER == BIG_ENDIAN +#define DC_SP_MAC(x) ((x) << 16) +#else +#define DC_SP_MAC(x) (x) +#endif + +struct dc_list_data { + struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; + struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; +}; + +struct dc_chain_data { + struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; + struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; + bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT]; + bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT]; + u_int32_t *dc_sbuf; + u_int8_t dc_pad[DC_MIN_FRAMELEN]; + int dc_tx_first; + int dc_tx_prod; + int dc_tx_cons; + int dc_tx_cnt; + int dc_rx_prod; +}; + +struct dc_mediainfo { + int dc_media; + u_int8_t *dc_gp_ptr; + u_int8_t dc_gp_len; + u_int8_t *dc_reset_ptr; + u_int8_t dc_reset_len; + struct dc_mediainfo *dc_next; +}; + + +struct dc_type { + u_int32_t dc_devid; + u_int8_t dc_minrev; + char *dc_name; +}; + +struct dc_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define DC_MII_STARTDELIM 0x01 +#define DC_MII_READOP 0x02 +#define DC_MII_WRITEOP 0x01 +#define DC_MII_TURNAROUND 0x02 + + +/* + * Registers specific to clone devices. + * This mainly relates to RX filter programming: not all 21x4x clones + * use the standard DEC filter programming mechanism. + */ + +/* + * ADMtek specific registers and constants for the AL981 and AN983. + * The AN983 doesn't use the magic PHY registers. + */ +#define DC_AL_CR 0x88 /* command register */ +#define DC_AL_PAR0 0xA4 /* station address */ +#define DC_AL_PAR1 0xA8 /* station address */ +#define DC_AL_MAR0 0xAC /* multicast hash filter */ +#define DC_AL_MAR1 0xB0 /* multicast hash filter */ +#define DC_AL_BMCR 0xB4 /* built in PHY control */ +#define DC_AL_BMSR 0xB8 /* built in PHY status */ +#define DC_AL_VENID 0xBC /* built in PHY ID0 */ +#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ +#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ +#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ +#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ + +#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ +#define DC_ADMTEK_PHYADDR 0x1 +#define DC_AL_EE_NODEADDR 4 +/* End of ADMtek specific registers */ + +/* + * ASIX specific registers. + */ +#define DC_AX_FILTIDX 0x68 /* RX filter index */ +#define DC_AX_FILTDATA 0x70 /* RX filter data */ + +/* + * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). + */ +#define DC_AX_NETCFG_RX_BROAD 0x00000100 + +/* + * RX Filter Index Register values + */ +#define DC_AX_FILTIDX_PAR0 0x00000000 +#define DC_AX_FILTIDX_PAR1 0x00000001 +#define DC_AX_FILTIDX_MAR0 0x00000002 +#define DC_AX_FILTIDX_MAR1 0x00000003 +/* End of ASIX specific registers */ + +/* + * Macronix specific registers. The Macronix chips have a special + * register for reading the NWAY status, which we don't use, plus + * a magic packet register, which we need to tweak a bit per the + * Macronix application notes. + */ +#define DC_MX_MAGICPACKET 0x80 +#define DC_MX_NWAYSTAT 0xA0 + +/* + * Magic packet register + */ +#define DC_MX_MPACK_DISABLE 0x00400000 + +/* + * NWAY status register. + */ +#define DC_MX_NWAY_10BTHALF 0x08000000 +#define DC_MX_NWAY_10BTFULL 0x10000000 +#define DC_MX_NWAY_100BTHALF 0x20000000 +#define DC_MX_NWAY_100BTFULL 0x40000000 +#define DC_MX_NWAY_100BT4 0x80000000 + +/* + * These are magic values that must be written into CSR16 + * (DC_MX_MAGICPACKET) in order to put the chip into proper + * operating mode. The magic numbers are documented in the + * Macronix 98715 application notes. + */ +#define DC_MX_MAGIC_98713 0x0F370000 +#define DC_MX_MAGIC_98713A 0x0B3C0000 +#define DC_MX_MAGIC_98715 0x0B3C0000 +#define DC_MX_MAGIC_98725 0x0B3C0000 +/* End of Macronix specific registers */ + +/* + * PNIC 82c168/82c169 specific registers. + * The PNIC has its own special NWAY support, which doesn't work, + * and shortcut ways of reading the EEPROM and MII bus. + */ +#define DC_PN_GPIO 0x60 /* general purpose pins control */ +#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ +#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ +#define DC_PN_MII 0xA0 /* MII access register */ +#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ + +/* Serial I/O EEPROM register */ +#define DC_PN_SIOCTL_DATA 0x0000003F +#define DC_PN_SIOCTL_OPCODE 0x00000300 +#define DC_PN_SIOCTL_BUSY 0x80000000 + +#define DC_PN_EEOPCODE_ERASE 0x00000300 +#define DC_PN_EEOPCODE_READ 0x00000600 +#define DC_PN_EEOPCODE_WRITE 0x00000100 + +/* + * The first two general purpose pins control speed selection and + * 100Mbps loopback on the 82c168 chip. The control bits should always + * be set (to make the data pins outputs) and the speed selction and + * loopback bits set accordingly when changing media. Physically, this + * will set the state of a relay mounted on the card. + */ +#define DC_PN_GPIO_DATA0 0x000000001 +#define DC_PN_GPIO_DATA1 0x000000002 +#define DC_PN_GPIO_DATA2 0x000000004 +#define DC_PN_GPIO_DATA3 0x000000008 +#define DC_PN_GPIO_CTL0 0x000000010 +#define DC_PN_GPIO_CTL1 0x000000020 +#define DC_PN_GPIO_CTL2 0x000000040 +#define DC_PN_GPIO_CTL3 0x000000080 +#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ +#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ +#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 +#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 +#define DC_PN_GPIO_SETBIT(sc, r) \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) +#define DC_PN_GPIO_CLRBIT(sc, r) \ + { \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ + DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ + } + +/* shortcut MII access register */ +#define DC_PN_MII_DATA 0x0000FFFF +#define DC_PN_MII_RESERVER 0x00020000 +#define DC_PN_MII_REGADDR 0x007C0000 +#define DC_PN_MII_PHYADDR 0x0F800000 +#define DC_PN_MII_OPCODE 0x30000000 +#define DC_PN_MII_BUSY 0x80000000 + +#define DC_PN_MIIOPCODE_READ 0x60020000 +#define DC_PN_MIIOPCODE_WRITE 0x50020000 + +/* Internal NWAY bits */ +#define DC_PN_NWAY_RESET 0x00000001 /* reset */ +#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ +#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ +#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ +#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ +#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ +#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ +#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ +#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ +#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ +#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ +#define DC_PN_NWAY_CAP10HDX 0x00002000 +#define DC_PN_NWAY_CAP10FDX 0x00004000 +#define DC_PN_NWAY_CAP100FDX 0x00008000 +#define DC_PN_NWAY_CAP100HDX 0x00010000 +#define DC_PN_NWAY_CAP100T4 0x00020000 +#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ +#define DC_PN_NWAY_REMFAULT 0x04000000 +#define DC_PN_NWAY_LPAR10HDX 0x08000000 +#define DC_PN_NWAY_LPAR10FDX 0x10000000 +#define DC_PN_NWAY_LPAR100FDX 0x20000000 +#define DC_PN_NWAY_LPAR100HDX 0x40000000 +#define DC_PN_NWAY_LPAR100T4 0x80000000 + +/* End of PNIC specific registers */ + +/* + * CONEXANT specific registers. + */ + +#define DC_CONEXANT_PHYADDR 0x1 +#define DC_CONEXANT_EE_NODEADDR 0x19A + +/* End of CONEXANT specific registers */ + + +struct dc_softc { + struct ifnet *dc_ifp; /* interface info */ + device_t dc_dev; /* device info */ + bus_space_handle_t dc_bhandle; /* bus space handle */ + bus_space_tag_t dc_btag; /* bus space tag */ + bus_dma_tag_t dc_ltag; /* tag for descriptor ring */ + bus_dmamap_t dc_lmap; /* map for descriptor ring */ + u_int32_t dc_laddr; /* DMA address of dc_ldata */ + bus_dma_tag_t dc_mtag; /* tag for mbufs */ + bus_dmamap_t dc_sparemap; + bus_dma_tag_t dc_stag; /* tag for the setup frame */ + bus_dmamap_t dc_smap; /* map for the setup frame */ + u_int32_t dc_saddr; /* DMA address of setup frame */ + void *dc_intrhand; + struct resource *dc_irq; + struct resource *dc_res; + const struct dc_type *dc_info; /* adapter info */ + device_t dc_miibus; + u_int8_t dc_type; + u_int8_t dc_pmode; + u_int8_t dc_link; + u_int8_t dc_cachesize; + int dc_romwidth; + int dc_pnic_rx_bug_save; + unsigned char *dc_pnic_rx_buf; + int dc_if_flags; + int dc_if_media; + u_int32_t dc_flags; + u_int32_t dc_txthresh; + u_int8_t *dc_srom; + struct dc_mediainfo *dc_mi; + struct dc_list_data *dc_ldata; + struct dc_chain_data dc_cdata; + struct callout dc_stat_ch; + struct callout dc_wdog_ch; + int dc_wdog_timer; + struct mtx dc_mtx; +#ifdef DEVICE_POLLING + int rxcycles; /* ... when polling */ +#endif + int suspended; /* 0 = normal 1 = suspended */ +}; + + +#define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) +#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) +#define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED) + +#define DC_TX_POLL 0x00000001 +#define DC_TX_COALESCE 0x00000002 +#define DC_TX_ADMTEK_WAR 0x00000004 +#define DC_TX_USE_TX_INTR 0x00000008 +#define DC_RX_FILTER_TULIP 0x00000010 +#define DC_TX_INTR_FIRSTFRAG 0x00000020 +#define DC_PNIC_RX_BUG_WAR 0x00000040 +#define DC_TX_FIXED_RING 0x00000080 +#define DC_TX_STORENFWD 0x00000100 +#define DC_REDUCED_MII_POLL 0x00000200 +#define DC_TX_INTR_ALWAYS 0x00000400 +#define DC_21143_NWAY 0x00000800 +#define DC_128BIT_HASH 0x00001000 +#define DC_64BIT_HASH 0x00002000 +#define DC_TULIP_LEDS 0x00004000 +#define DC_TX_ONE 0x00008000 +#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) + +#define CSR_BARRIER_4(sc, reg, flags) \ + bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) + +#define DC_TIMEOUT 1000 +#define ETHER_ALIGN 2 + +/* + * General constants that are fun to know. + */ + +/* + * DEC PCI vendor ID + */ +#define DC_VENDORID_DEC 0x1011 + +/* + * DEC/Intel 21143 PCI device ID + */ +#define DC_DEVICEID_21143 0x0019 + +/* + * Macronix PCI vendor ID + */ +#define DC_VENDORID_MX 0x10D9 + +/* + * Macronix PMAC device IDs. + */ +#define DC_DEVICEID_98713 0x0512 +#define DC_DEVICEID_987x5 0x0531 +#define DC_DEVICEID_98727 0x0532 +#define DC_DEVICEID_98732 0x0532 + +/* Macronix PCI revision codes. */ +#define DC_REVISION_98713 0x00 +#define DC_REVISION_98713A 0x10 +#define DC_REVISION_98715 0x20 +#define DC_REVISION_98715AEC_C 0x25 +#define DC_REVISION_98725 0x30 + +/* + * Compex PCI vendor ID. + */ +#define DC_VENDORID_CP 0x11F6 + +/* + * Compex PMAC PCI device IDs. + */ +#define DC_DEVICEID_98713_CP 0x9881 + +/* + * Lite-On PNIC PCI vendor ID + */ +#define DC_VENDORID_LO 0x11AD + +/* + * 82c168/82c169 PNIC device IDs. Both chips have the same device + * ID but different revisions. Revision 0x10 is the 82c168, and + * 0x20 is the 82c169. + */ +#define DC_DEVICEID_82C168 0x0002 + +#define DC_REVISION_82C168 0x10 +#define DC_REVISION_82C169 0x20 + +/* + * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A + * with wake on lan/magic packet support. + */ +#define DC_DEVICEID_82C115 0xc115 + +/* + * Davicom vendor ID. + */ +#define DC_VENDORID_DAVICOM 0x1282 + +/* + * Davicom device IDs. + */ +#define DC_DEVICEID_DM9009 0x9009 +#define DC_DEVICEID_DM9100 0x9100 +#define DC_DEVICEID_DM9102 0x9102 + +/* + * The DM9102A has the same PCI device ID as the DM9102, + * but a higher revision code. + */ +#define DC_REVISION_DM9102 0x10 +#define DC_REVISION_DM9102A 0x30 + +/* + * ADMtek vendor ID. + */ +#define DC_VENDORID_ADMTEK 0x1317 + +/* + * ADMtek device IDs. + */ +#define DC_DEVICEID_AL981 0x0981 +#define DC_DEVICEID_AN983 0x0985 +#define DC_DEVICEID_AN985 0x1985 +#define DC_DEVICEID_ADM9511 0x9511 +#define DC_DEVICEID_ADM9513 0x9513 + +/* + * 3COM PCI vendor ID + */ +#define DC_VENDORID_3COM 0x10b7 + +/* + * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) + */ +#define DC_DEVICEID_3CSOHOB 0x9300 + +/* + * ASIX vendor ID. + */ +#define DC_VENDORID_ASIX 0x125B + +/* + * ASIX device IDs. + */ +#define DC_DEVICEID_AX88140A 0x1400 + +/* + * The ASIX AX88140 and ASIX AX88141 have the same vendor and + * device IDs but different revision values. + */ +#define DC_REVISION_88140 0x00 +#define DC_REVISION_88141 0x10 + +/* + * Accton vendor ID. + */ +#define DC_VENDORID_ACCTON 0x1113 + +/* + * Accton device IDs. + */ +#define DC_DEVICEID_EN1217 0x1217 +#define DC_DEVICEID_EN2242 0x1216 + +/* + * Xircom vendor ID + */ +#define DC_VENDORID_XIRCOM 0x115d + +/* + * Xircom device IDs. + */ +#define DC_DEVICEID_X3201 0x0003 + +/* + * D-Link vendor ID + */ +#define DC_VENDORID_DLINK 0x1186 + +/* + * D-Link device IDs. + */ +#define DC_DEVICEID_DRP32TXD 0x1561 + +/* + * Abocom vendor ID + */ +#define DC_VENDORID_ABOCOM 0x13d1 + +/* + * Abocom device IDs. + */ +#define DC_DEVICEID_FE2500 0xAB02 +#define DC_DEVICEID_FE2500MX 0xab08 + +/* + * Conexant vendor ID. + */ +#define DC_VENDORID_CONEXANT 0x14f1 + +/* + * Conexant device IDs. + */ +#define DC_DEVICEID_RS7112 0x1803 + +/* + * Planex vendor ID + */ +#define DC_VENDORID_PLANEX 0x14ea + +/* + * Planex device IDs. + */ +#define DC_DEVICEID_FNW3602T 0xab08 + +/* + * Not sure who this vendor should be, so we'll go with HAWKING until + * I can locate the right one. + */ +#define DC_VENDORID_HAWKING 0x17b3 + +/* + * Sure looks like an abocom device ID, but it found on my hawking PN672TX + * card. Use that for now, and upgrade later. + */ +#define DC_DEVICEID_HAWKING_PN672TX 0xab08 + +/* + * Microsoft device ID. + */ +#define DC_VENDORID_MICROSOFT 0x1414 + +/* + * Supported Microsoft PCI and cardbus NICs. These are really + * ADMtek parts in disguise. + */ + +#define DC_DEVICEID_MSMN120 0x0001 +#define DC_DEVICEID_MSMN130 0x0002 + +/* + * Linksys vendor ID. + */ +#define DC_VENDORID_LINKSYS 0x1737 + +/* + * Linksys device IDs. + */ +#define DC_DEVICEID_PCMPC200_AB08 0xab08 +#define DC_DEVICEID_PCMPC200_AB09 0xab09 + +#define DC_DEVID(vendor, device) ((device) << 16 | (vendor)) + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */ +#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */ +#define DC_PCI_CFDD 0x40 /* Device and driver area */ +#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ +#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ +#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ +#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ +#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ + +#define DC_21143_PB_REV 0x00000030 +#define DC_21143_TB_REV 0x00000030 +#define DC_21143_PC_REV 0x00000030 +#define DC_21143_TC_REV 0x00000030 +#define DC_21143_PD_REV 0x00000041 +#define DC_21143_TD_REV 0x00000041 + +/* Configuration and driver area */ +#define DC_CFDD_DRVUSE 0x0000FFFF +#define DC_CFDD_SNOOZE_MODE 0x40000000 +#define DC_CFDD_SLEEP_MODE 0x80000000 + +/* Configuration wake-up command register */ +#define DC_CWUC_MUST_BE_ZERO 0x00000001 +#define DC_CWUC_SECUREON_ENB 0x00000002 +#define DC_CWUC_FORCE_WUL 0x00000004 +#define DC_CWUC_BNC_ABILITY 0x00000008 +#define DC_CWUC_AUI_ABILITY 0x00000010 +#define DC_CWUC_TP10_ABILITY 0x00000020 +#define DC_CWUC_MII_ABILITY 0x00000040 +#define DC_CWUC_SYM_ABILITY 0x00000080 +#define DC_CWUC_LOCK 0x00000100 + +/* + * SROM nonsense. + */ + +#define DC_IB_CTLRCNT 0x13 +#define DC_IB_LEAF0_CNUM 0x1A +#define DC_IB_LEAF0_OFFSET 0x1B + +struct dc_info_leaf { + u_int16_t dc_conntype; + u_int8_t dc_blkcnt; + u_int8_t dc_rsvd; + u_int16_t dc_infoblk; +}; + +#define DC_CTYPE_10BT 0x0000 +#define DC_CTYPE_10BT_NWAY 0x0100 +#define DC_CTYPE_10BT_FDX 0x0204 +#define DC_CTYPE_10B2 0x0001 +#define DC_CTYPE_10B5 0x0002 +#define DC_CTYPE_100BT 0x0003 +#define DC_CTYPE_100BT_FDX 0x0205 +#define DC_CTYPE_100T4 0x0006 +#define DC_CTYPE_100FX 0x0007 +#define DC_CTYPE_100FX_FDX 0x0208 +#define DC_CTYPE_MII_10BT 0x0009 +#define DC_CTYPE_MII_10BT_FDX 0x020A +#define DC_CTYPE_MII_100BT 0x000D +#define DC_CTYPE_MII_100BT_FDX 0x020E +#define DC_CTYPE_MII_100T4 0x000F +#define DC_CTYPE_MII_100FX 0x0010 +#define DC_CTYPE_MII_100FX_FDX 0x0211 +#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 +#define DC_CTYPE_PUP_AUTOSENSE 0x8800 +#define DC_CTYPE_NOMEDIA 0xFFFF + +#define DC_EBLOCK_SIA 0x0002 +#define DC_EBLOCK_MII 0x0003 +#define DC_EBLOCK_SYM 0x0004 +#define DC_EBLOCK_RESET 0x0005 +#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 + +struct dc_leaf_hdr { + u_int16_t dc_mtype; + u_int8_t dc_mcnt; + u_int8_t dc_rsvd; +}; + +struct dc_eblock_hdr { + u_int8_t dc_len; + u_int8_t dc_type; +}; + +struct dc_eblock_sia { + struct dc_eblock_hdr dc_sia_hdr; + u_int8_t dc_sia_code; + union { + struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ + u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; + } dc_sia_ext; + struct dc_sia_noext { + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; + } dc_sia_noext; + } dc_un; +}; + +#define DC_SIA_CODE_10BT 0x00 +#define DC_SIA_CODE_10B2 0x01 +#define DC_SIA_CODE_10B5 0x02 +#define DC_SIA_CODE_10BT_FDX 0x04 +#define DC_SIA_CODE_EXT 0x40 + +/* + * Note that the first word in the gpr and reset + * sequences is always a control word. + */ +struct dc_eblock_mii { + struct dc_eblock_hdr dc_mii_hdr; + u_int8_t dc_mii_phynum; + u_int8_t dc_gpr_len; +/* u_int16_t dc_gpr_dat[n]; */ +/* u_int8_t dc_reset_len; */ +/* u_int16_t dc_reset_dat[n]; */ +/* There are other fields after these, but we don't + * care about them since they can be determined by looking + * at the PHY. + */ +}; + +struct dc_eblock_sym { + struct dc_eblock_hdr dc_sym_hdr; + u_int8_t dc_sym_code; + u_int8_t dc_sym_gpio_ctl[2]; + u_int8_t dc_sym_gpio_dat[2]; + u_int8_t dc_sym_cmd[2]; +}; + +#define DC_SYM_CODE_100BT 0x03 +#define DC_SYM_CODE_100BT_FDX 0x05 +#define DC_SYM_CODE_100T4 0x06 +#define DC_SYM_CODE_100FX 0x07 +#define DC_SYM_CODE_100FX_FDX 0x08 + +struct dc_eblock_reset { + struct dc_eblock_hdr dc_reset_hdr; + u_int8_t dc_reset_len; +/* u_int16_t dc_reset_dat[n]; */ +}; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/Jamfile b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/Jamfile new file mode 100644 index 0000000000..fe60e270b7 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/Jamfile @@ -0,0 +1,26 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network dec21xxx dev mii ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] + : true ; + +UsePrivateHeaders net system ; +UsePrivateKernelHeaders ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelStaticLibrary dec21xxx_mii.a + : + acphy.c + amphy.c + dcphy.c + pnphy.c + ukphy.c + ukphy_subr.c + ; + +ObjectHdrs [ FGristFiles acphy$(SUFOBJ) amphy$(SUFOBJ) dcphy$(SUFOBJ) + pnphy$(SUFOBJ) ukphy$(SUFOBJ) ] + : [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR) libs compat freebsd_network ] ; +Includes [ FGristFiles dcphy.c pnphy.c ] + : miidevs.h ; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphy.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphy.c new file mode 100644 index 0000000000..ca83841f40 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphy.c @@ -0,0 +1,261 @@ +/*- + * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1997 Manuel Bouyer. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/acphy.c,v 1.21.10.6.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * Driver for Altima AC101 10/100 PHY + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "miidevs.h" + +#include + +#include "miibus_if.h" + +static int acphy_probe(device_t); +static int acphy_attach(device_t); + +static device_method_t acphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, acphy_probe), + DEVMETHOD(device_attach, acphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t acphy_devclass; + +static driver_t acphy_driver = { + "acphy", + acphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(acphy, miibus, acphy_driver, acphy_devclass, 0, 0); + +static int acphy_service(struct mii_softc *, struct mii_data *, int); +static void acphy_reset(struct mii_softc *); +static void acphy_status(struct mii_softc *); + +static const struct mii_phydesc acphys[] = { + MII_PHY_DESC(xxALTIMA, AC101), + MII_PHY_DESC(xxALTIMA, AC101L), + /* XXX This is reported to work, but it's not from any data sheet. */ + MII_PHY_DESC(xxALTIMA, ACXXX), + MII_PHY_END +}; + +static int +acphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, acphys, BUS_PROBE_DEFAULT)); +} + +static int +acphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = acphy_service; + sc->mii_pdata = mii; + + acphy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + device_printf(dev, " "); + +#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) + if ((PHY_READ(sc, MII_ACPHY_MCTL) & AC_MCTL_FX_SEL) != 0) { + sc->mii_flags |= MIIF_HAVEFIBER; + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, 0, sc->mii_inst), + MII_MEDIA_100_TX); + printf("100baseFX, "); + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, IFM_FDX, sc->mii_inst), + MII_MEDIA_100_TX_FDX); + printf("100baseFX-FDX, "); + } +#undef ADD + + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +acphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + int reg; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + /* Wake & deisolate up if necessary */ + reg = PHY_READ(sc, MII_BMCR); + if (reg & (BMCR_ISO | BMCR_PDOWN)) + PHY_WRITE(sc, MII_BMCR, reg & ~(BMCR_ISO | BMCR_PDOWN)); + + mii_phy_setmedia(sc); + break; + + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * This PHY's autonegotiation doesn't need to be kicked. + */ + break; + } + + /* Update the media status. */ + acphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +acphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr, diag; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, MII_BMSR) | + PHY_READ(sc, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + if ((bmsr & BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + diag = PHY_READ(sc, MII_ACPHY_DIAG); + if (diag & AC_DIAG_SPEED) + mii->mii_media_active |= IFM_100_TX; + else + mii->mii_media_active |= IFM_10_T; + + if (diag & AC_DIAG_DUPLEX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + } else + mii->mii_media_active = ife->ifm_media; +} + +static void +acphy_reset(struct mii_softc *sc) +{ + + mii_phy_reset(sc); + PHY_WRITE(sc, MII_ACPHY_INT, 0); +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphyreg.h b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphyreg.h new file mode 100644 index 0000000000..664671aa2e --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/acphyreg.h @@ -0,0 +1,77 @@ +/*- + * Copyright (c) 2001 Semen Ustimenko (semenu@FreeBSD.org) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/mii/acphyreg.h,v 1.2.10.1.6.1 2010/12/21 17:09:25 kensmith Exp $ + */ + +#ifndef _DEV_MII_ACPHYREG_H_ +#define _DEV_MII_ACPHYREG_H_ + +/* + * Register definitions for the Altima Communications AC101 + */ + +#define MII_ACPHY_POL 0x10 /* Polarity int level */ + +/* High byte is interrupt mask register */ +#define MII_ACPHY_INT 0x11 /* Interrupt control/status */ +#define AC_INT_ACOMP 0x0001 /* Autoneg complete */ +#define AC_INT_REM_FLT 0x0002 /* Remote fault */ +#define AC_INT_LINK_DOWN 0x0004 /* Link not OK */ +#define AC_INT_LP_ACK 0x0008 /* FLP ack recved */ +#define AC_INT_PD_FLT 0x0010 /* Parallel detect fault */ +#define AC_INT_PAGE_RECV 0x0020 /* New page recved */ +#define AC_INT_RX_ER 0x0040 /* RX_ER transitions high */ +#define AC_INT_JAB 0x0080 /* Jabber detected */ + +#define MII_ACPHY_DIAG 0x12 /* Diagnostic */ +#define AC_DIAG_RX_LOCK 0x0100 +#define AC_DIAG_RX_PASS 0x0200 +#define AC_DIAG_SPEED 0x0400 /* Aneg speed result */ +#define AC_DIAG_DUPLEX 0x0800 /* Aneg duplex result */ + +#define MII_ACPHY_PWRLOOP 0x13 /* Power/Loopback */ +#define MII_ACPHY_CBLMEAS 0x14 /* Cable meas. */ + +#define MII_ACPHY_MCTL 0x15 /* Mode control */ +#define AC_MCTL_FX_SEL 0x0001 /* FX mode */ +#define AC_MCTL_BYP_PCS 0x0002 /* Bypass PCS */ +#define AC_MCTL_SCRMBL 0x0004 /* Data scrambling */ +#define AC_MCTL_REM_LOOP 0x0008 /* Remote loopback */ +#define AC_MCTL_DIS_WDT 0x0010 /* Disable watchdog timer */ +#define AC_MCTL_DIS_REC 0x0020 /* Disable recv error counter */ +#define AC_MCTL_REC_FULL 0x0040 /* Recv error counter full */ +#define AC_MCTL_FRC_FEF 0x0080 /* Force Far End Fault Insert. */ +#define AC_MCTL_DIS_FEF 0x0100 /* Disable FEF Insertion */ +#define AC_MCTL_LED_SEL 0x0200 /* Compat LED config */ +#define AC_MCTL_ALED_SEL 0x0400 /* ActLED RX&TX - RX only */ +#define AC_MCTL_10BT_SEL 0x0800 /* Enable 7-wire interface */ +#define AC_MCTL_DIS_JAB 0x1000 /* Disable jabber */ +#define AC_MCTL_FRC_LINK 0x2000 /* Force TX link up */ +#define AC_MCTL_DIS_NLP 0x4000 /* Disable NLP check */ + +#define MII_ACPHY_REC 0x18 /* Recv error counter */ + +#endif /* _DEV_MII_ACPHYREG_H_ */ diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphy.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphy.c new file mode 100644 index 0000000000..551cfe6aa3 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphy.c @@ -0,0 +1,236 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/amphy.c,v 1.24.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * driver for AMD AM79c873 PHYs + * This driver also works for Davicom DM910{1,2} PHYs, which appear + * to be AM79c873 workalikes. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "miidevs.h" + +#include + +#include "miibus_if.h" + +static int amphy_probe(device_t); +static int amphy_attach(device_t); + +static device_method_t amphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, amphy_probe), + DEVMETHOD(device_attach, amphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t amphy_devclass; + +static driver_t amphy_driver = { + "amphy", + amphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(amphy, miibus, amphy_driver, amphy_devclass, 0, 0); + +static int amphy_service(struct mii_softc *, struct mii_data *, int); +static void amphy_status(struct mii_softc *); + +static const struct mii_phydesc amphys[] = { + MII_PHY_DESC(DAVICOM, DM9102), + MII_PHY_DESC(xxAMD, 79C873), + MII_PHY_DESC(xxDAVICOM, DM9101), + MII_PHY_END +}; + +static int +amphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, amphys, BUS_PROBE_DEFAULT)); +} + +static int +amphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = amphy_service; + sc->mii_pdata = mii; + +#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) + +#if 0 + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), + MII_MEDIA_100_TX); +#endif + + mii_phy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); +#undef ADD + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +amphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii_phy_setmedia(sc); + break; + + case MII_TICK: + if (mii_phy_tick(sc) == EJUSTRETURN) + return (0); + break; + } + + /* Update the media status. */ + amphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +amphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr, par, anlpar; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, MII_BMSR) | + PHY_READ(sc, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + /* + * The PAR status bits are only valid if autonegotiation + * has completed (or it's disabled). + */ + if ((bmsr & BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + if (PHY_READ(sc, MII_ANER) & ANER_LPAN) { + anlpar = PHY_READ(sc, MII_ANAR) & + PHY_READ(sc, MII_ANLPAR); + if (anlpar & ANLPAR_TX_FD) + mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4|IFM_HDX; + else if (anlpar & ANLPAR_TX) + mii->mii_media_active |= IFM_100_TX|IFM_HDX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T|IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T|IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + return; + } + + /* + * Link partner is not capable of autonegotiation. + */ + par = PHY_READ(sc, MII_AMPHY_DSCSR); + if (par & DSCSR_100FDX) + mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (par & DSCSR_100HDX) + mii->mii_media_active |= IFM_100_TX|IFM_HDX; + else if (par & DSCSR_10FDX) + mii->mii_media_active |= IFM_10_T|IFM_HDX; + else if (par & DSCSR_10HDX) + mii->mii_media_active |= IFM_10_T|IFM_HDX; + } else + mii->mii_media_active = ife->ifm_media; +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphyreg.h b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphyreg.h new file mode 100644 index 0000000000..6aa82e3934 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/amphyreg.h @@ -0,0 +1,84 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/mii/amphyreg.h,v 1.2.22.1.6.1 2010/12/21 17:09:25 kensmith Exp $ + */ + +#ifndef _DEV_MII_AMTPHYREG_H_ +#define _DEV_MII_AMTPHYREG_H_ + +/* + * AMD Am79C873 registers. + */ + + +#define MII_AMPHY_DSCR 0x10 /* Specified configuration register */a +#define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */ +#define DSCR_BPSCR 0x4000 /* Bypass scrambler */ +#define DSCR_BPALIGN 0x2000 /* Bypass symbol alignment */ +#define DSCR_REPEATER 0x0800 /* Repeater mode */ +#define DSCR_TX 0x0400 /* TX/FX mode control */ +#define DSCR_UTP 0x0200 /* UTP/STP mode control */ +#define DSCR_CLK25MDIS 0x0100 /* CLK25M disable */ +#define DSCR_FGLNKTX 0x0080 /* Force good link at 100baseTX */ +#define DSCR_LINKLEDCTL 0x0020 /* Link LED control */ +#define DSCR_FDXLEDCTL 0x0010 /* FDX LED control */ +#define DSCR_SMRTS 0x0008 /* Reset state machine */ +#define DSCR_MFPSC 0x0004 /* Preamble surpression control */ +#define DSCR_SLEEP 0x0002 /* Sleep mode */ +#define DSCR_RLOUT 0x0001 /* Remote loopout control */ + +#define MII_AMPHY_DSCSR 0x11 /* Specified configuration and status */ +#define DSCSR_100FDX 0x8000 /* 100MBps full duplex */ +#define DSCSR_100HDX 0x4000 /* 100Mbps half duplex */ +#define DSCSR_10FDX 0x2000 /* 10Mbps full duplex */ +#define DSCSR_10HDX 0x1000 /* 10Mbps half duplex */ +#define DSCSR_PADDR 0x01F0 /* PHY address */ +#define DSCSR_ASTAT 0x000F /* Autonegotiation status */ + +#define ASTAT_COMPLETE 0x8 +#define ASTAT_PDLINK_READY_FAIL 0x7 +#define ASTAT_PDLINK_READY 0x6 +#define ASTAT_CONSTMATCH_FAIL 0x5 +#define ASTAT_CONSTMATCH 0x4 +#define ASTAT_ACKMATCH_FAIL 0x3 +#define ASTAT_ACKMATCH 0x2 +#define ASTAT_ABILITYMATCH 0x1 +#define ASTAT_IDLE 0x0 + +#define MII_AMPHY_T10CSRSCR 0x12 /* 10baseT configuration/status */ +#define T10CSRSCR_LPEN 0x4000 /* Link pulse enable */ +#define T10CSRSCR_HBE 0x2000 /* Heartbeat enable */ +#define T10CSRSCR_JABEN 0x0800 /* Jabber enable */ +#define T10CSRSCR_SER 0x0400 /* Serial mode enable */ +#define T10CSRSCR_POLR 0x0001 /* Polarity reversed */ + +#endif /* _DEV_MII_AMTPHYREG_H_ */ diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/dcphy.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/dcphy.c new file mode 100644 index 0000000000..68ec00b662 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/dcphy.c @@ -0,0 +1,421 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/dc/dcphy.c,v 1.35.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * Pseudo-driver for internal NWAY support on DEC 21143 and workalike + * controllers. Technically we're abusing the miibus code to handle + * media selection and NWAY support here since there is no MII + * interface. However the logical operations are roughly the same, + * and the alternative is to create a fake MII interface in the driver, + * which is harder to do. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include "miidevs.h" + +#include +#include +#include + +#include + +#include + +#include "miibus_if.h" + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +#define MIIF_AUTOTIMEOUT 0x0004 + +/* + * This is the subsystem ID for the built-in 21143 ethernet + * in several Compaq Presario systems. Apparently these are + * 10Mbps only, so we need to treat them specially. + */ +#define COMPAQ_PRESARIO_ID 0xb0bb0e11 + +static int dcphy_probe(device_t); +static int dcphy_attach(device_t); + +static device_method_t dcphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, dcphy_probe), + DEVMETHOD(device_attach, dcphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t dcphy_devclass; + +static driver_t dcphy_driver = { + "dcphy", + dcphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0); + +static int dcphy_service(struct mii_softc *, struct mii_data *, int); +static void dcphy_status(struct mii_softc *); +static void dcphy_reset(struct mii_softc *); +static int dcphy_auto(struct mii_softc *); + +static int +dcphy_probe(device_t dev) +{ + struct mii_attach_args *ma; + + ma = device_get_ivars(dev); + + /* + * The dc driver will report the 21143 vendor and device + * ID to let us know that it wants us to attach. + */ + if (ma->mii_id1 != DC_VENDORID_DEC || + ma->mii_id2 != DC_DEVICEID_21143) + return (ENXIO); + + device_set_desc(dev, "Intel 21143 NWAY media interface"); + + return (BUS_PROBE_DEFAULT); +} + +static int +dcphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + struct dc_softc *dc_sc; + device_t brdev; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = dcphy_service; + sc->mii_pdata = mii; + + /* + * Apparently, we can neither isolate nor do loopback. + */ + sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; + + /*dcphy_reset(sc);*/ + dc_sc = mii->mii_ifp->if_softc; + CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); + CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); + + brdev = device_get_parent(sc->mii_dev); + switch (pci_get_subdevice(brdev) << 16 | pci_get_subvendor(brdev)) { + case COMPAQ_PRESARIO_ID: + /* Example of how to only allow 10Mbps modes. */ + sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; + break; + default: + if (dc_sc->dc_pmode == DC_PMODE_SIA) + sc->mii_capabilities = + BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; + else + sc->mii_capabilities = + BMSR_ANEG | BMSR_100TXFDX | BMSR_100TXHDX | + BMSR_10TFDX | BMSR_10THDX; + break; + } + + sc->mii_capabilities &= ma->mii_capmask; + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct dc_softc *dc_sc; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int reg; + u_int32_t mode; + + dc_sc = mii->mii_ifp->if_softc; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii->mii_media_active = IFM_NONE; + mode = CSR_READ_4(dc_sc, DC_NETCFG); + mode &= ~(DC_NETCFG_FULLDUPLEX | DC_NETCFG_PORTSEL | + DC_NETCFG_PCS | DC_NETCFG_SCRAMBLER | DC_NETCFG_SPEEDSEL); + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + /*dcphy_reset(sc);*/ + (void) dcphy_auto(sc); + break; + case IFM_100_T4: + /* + * XXX Not supported as a manual setting right now. + */ + return (EINVAL); + case IFM_100_TX: + dcphy_reset(sc); + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + mode |= DC_NETCFG_PORTSEL | DC_NETCFG_PCS | + DC_NETCFG_SCRAMBLER; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mode |= DC_NETCFG_FULLDUPLEX; + else + mode &= ~DC_NETCFG_FULLDUPLEX; + CSR_WRITE_4(dc_sc, DC_NETCFG, mode); + break; + case IFM_10_T: + DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF); + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D); + else + DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F); + DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + mode &= ~DC_NETCFG_PORTSEL; + mode |= DC_NETCFG_SPEEDSEL; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mode |= DC_NETCFG_FULLDUPLEX; + else + mode &= ~DC_NETCFG_FULLDUPLEX; + CSR_WRITE_4(dc_sc, DC_NETCFG, mode); + break; + default: + return (EINVAL); + } + break; + + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) + break; + + reg = CSR_READ_4(dc_sc, DC_10BTSTAT); + if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) + break; + + /* + * Only retry autonegotiation every 5 seconds. + * + * Otherwise, fall through to calling dcphy_status() + * since real Intel 21143 chips don't show valid link + * status until autonegotiation is switched off, and + * that only happens in dcphy_status(). Without this, + * successful autonegotiation is never recognised on + * these chips. + */ + if (++sc->mii_ticks <= 50) + break; + + sc->mii_ticks = 0; + dcphy_auto(sc); + + break; + } + + /* Update the media status. */ + dcphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +dcphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int reg, anlpar, tstat = 0; + struct dc_softc *dc_sc; + + dc_sc = mii->mii_ifp->if_softc; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return; + + reg = CSR_READ_4(dc_sc, DC_10BTSTAT); + if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) + mii->mii_media_status |= IFM_ACTIVE; + + if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { + /* Erg, still trying, I guess... */ + tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); + if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) { + if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) && + (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE) + goto skip; + mii->mii_media_active |= IFM_NONE; + return; + } + + if (tstat & DC_TSTAT_LP_CAN_NWAY) { + anlpar = tstat >> 16; + if (anlpar & ANLPAR_TX_FD && + sc->mii_capabilities & BMSR_100TXFDX) + mii->mii_media_active |= IFM_100_TX | IFM_FDX; + else if (anlpar & ANLPAR_T4 && + sc->mii_capabilities & BMSR_100T4) + mii->mii_media_active |= IFM_100_T4 | IFM_HDX; + else if (anlpar & ANLPAR_TX && + sc->mii_capabilities & BMSR_100TXHDX) + mii->mii_media_active |= IFM_100_TX | IFM_HDX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T | IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T | IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + if (DC_IS_INTEL(dc_sc)) + DC_CLRBIT(dc_sc, DC_10BTCTRL, + DC_TCTL_AUTONEGENBL); + return; + } + + /* + * If the other side doesn't support NWAY, then the + * best we can do is determine if we have a 10Mbps or + * 100Mbps link. There's no way to know if the link + * is full or half duplex, so we default to half duplex + * and hope that the user is clever enough to manually + * change the media settings if we're wrong. + */ + if (!(reg & DC_TSTAT_LS100)) + mii->mii_media_active |= IFM_100_TX | IFM_HDX; + else if (!(reg & DC_TSTAT_LS10)) + mii->mii_media_active |= IFM_10_T | IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + if (DC_IS_INTEL(dc_sc)) + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + return; + } + +skip: + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_100_TX; + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; +} + +static int +dcphy_auto(struct mii_softc *mii) +{ + struct dc_softc *sc; + + sc = mii->mii_pdata->mii_ifp->if_softc; + + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + if (mii->mii_capabilities & BMSR_100TXHDX) + CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); + else + CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE); + + return (EJUSTRETURN); +} + +static void +dcphy_reset(struct mii_softc *mii) +{ + struct dc_softc *sc; + + sc = mii->mii_pdata->mii_ifp->if_softc; + + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + DELAY(1000); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/pnphy.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/pnphy.c new file mode 100644 index 0000000000..6143a1d98a --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/pnphy.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/dc/pnphy.c,v 1.23.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * Pseudo-driver for media selection on the Lite-On PNIC 82c168 + * chip. The NWAY support on this chip is horribly broken, so we + * only support manual mode selection. This is lame, but getting + * NWAY to work right is amazingly difficult. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include "miidevs.h" + +#include +#include +#include + +#include + +#include "miibus_if.h" + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +static int pnphy_probe(device_t); +static int pnphy_attach(device_t); + +static device_method_t pnphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, pnphy_probe), + DEVMETHOD(device_attach, pnphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t pnphy_devclass; + +static driver_t pnphy_driver = { + "pnphy", + pnphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(pnphy, miibus, pnphy_driver, pnphy_devclass, 0, 0); + +static int pnphy_service(struct mii_softc *, struct mii_data *, int); +static void pnphy_status(struct mii_softc *); + +static int +pnphy_probe(device_t dev) +{ + struct mii_attach_args *ma; + + ma = device_get_ivars(dev); + + /* + * The dc driver will report the 82c168 vendor and device + * ID to let us know that it wants us to attach. + */ + if (ma->mii_id1 != DC_VENDORID_LO || + ma->mii_id2 != DC_DEVICEID_82C168) + return (ENXIO); + + device_set_desc(dev, "PNIC 82c168 media interface"); + + return (BUS_PROBE_DEFAULT); +} + +static int +pnphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = pnphy_service; + sc->mii_pdata = mii; + + /* + * Apparently, we can neither isolate nor do loopback. + */ + sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; + + sc->mii_capabilities = + BMSR_100TXFDX | BMSR_100TXHDX | BMSR_10TFDX | BMSR_10THDX; + sc->mii_capabilities &= ma->mii_capmask; + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +pnphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + /* NWAY is busted on this chip */ + case IFM_100_T4: + /* + * XXX Not supported as a manual setting right now. + */ + return (EINVAL); + case IFM_100_TX: + mii->mii_media_active = IFM_ETHER | IFM_100_TX; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mii->mii_media_active |= IFM_FDX; + MIIBUS_STATCHG(sc->mii_dev); + return (0); + case IFM_10_T: + mii->mii_media_active = IFM_ETHER | IFM_10_T; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mii->mii_media_active |= IFM_FDX; + MIIBUS_STATCHG(sc->mii_dev); + return (0); + default: + return (EINVAL); + } + break; + + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + break; + } + + /* Update the media status. */ + pnphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +pnphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int reg; + struct dc_softc *dc_sc; + + dc_sc = mii->mii_ifp->if_softc; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + reg = CSR_READ_4(dc_sc, DC_ISR); + + if (!(reg & DC_ISR_LINKFAIL)) + mii->mii_media_status |= IFM_ACTIVE; + + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_100_TX; + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy.c new file mode 100644 index 0000000000..ad59059aad --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy.c @@ -0,0 +1,186 @@ +/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */ + +/*- + * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1997 Manuel Bouyer. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20.10.6.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * driver for generic unknown PHYs + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +static int ukphy_probe(device_t); +static int ukphy_attach(device_t); + +static device_method_t ukphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, ukphy_probe), + DEVMETHOD(device_attach, ukphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t ukphy_devclass; + +static driver_t ukphy_driver = { + "ukphy", + ukphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0); + +static int ukphy_service(struct mii_softc *, struct mii_data *, int); + +static int +ukphy_probe(device_t dev) +{ + + /* + * We know something is here, so always match at a low priority. + */ + device_set_desc(dev, "Generic IEEE 802.3u media interface"); + return (BUS_PROBE_GENERIC); +} + +static int +ukphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + MII_OUI(ma->mii_id1, ma->mii_id2), + MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2)); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = ukphy_service; + sc->mii_pdata = mii; + + sc->mii_flags |= MIIF_NOMANPAUSE; + + mii_phy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + mii_phy_setmedia(sc); + + return (0); +} + +static int +ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii_phy_setmedia(sc); + break; + + case MII_TICK: + if (mii_phy_tick(sc) == EJUSTRETURN) + return (0); + break; + } + + /* Update the media status. */ + ukphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy_subr.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy_subr.c new file mode 100644 index 0000000000..73007e197b --- /dev/null +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/mii/ukphy_subr.c @@ -0,0 +1,129 @@ +/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.10.2.4.2.1 2010/12/21 17:09:25 kensmith Exp $"); + +/* + * Subroutines shared by the ukphy driver and other PHY drivers. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +/* + * Media status subroutine. If a PHY driver does media detection simply + * by decoding the NWay autonegotiation, use this routine. + */ +void +ukphy_status(struct mii_softc *phy) +{ + struct mii_data *mii = phy->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr, anlpar, gtcr, gtsr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(phy, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + /* + * NWay autonegotiation takes the highest-order common + * bit of the ANAR and ANLPAR (i.e. best media advertised + * both by us and our link partner). + */ + if ((bmsr & BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR); + if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 && + (phy->mii_extcapabilities & + (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) { + gtcr = PHY_READ(phy, MII_100T2CR); + gtsr = PHY_READ(phy, MII_100T2SR); + } else + gtcr = gtsr = 0; + + if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX)) + mii->mii_media_active |= IFM_1000_T|IFM_FDX; + else if ((gtcr & GTCR_ADV_1000THDX) && + (gtsr & GTSR_LP_1000THDX)) + mii->mii_media_active |= IFM_1000_T|IFM_HDX; + else if (anlpar & ANLPAR_TX_FD) + mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4|IFM_HDX; + else if (anlpar & ANLPAR_TX) + mii->mii_media_active |= IFM_100_TX|IFM_HDX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T|IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T|IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + + if ((mii->mii_media_active & IFM_1000_T) != 0 && + (gtsr & GTSR_MS_RES) != 0) + mii->mii_media_active |= IFM_ETH_MASTER; + + if ((mii->mii_media_active & IFM_FDX) != 0) + mii->mii_media_active |= mii_phy_flowstatus(phy); + } else + mii->mii_media_active = ife->ifm_media; +} diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c index 873939ea1a..5239246d84 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c @@ -28,7 +28,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.266 2007/05/30 03:46:04 kevlo Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.295.2.14.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * Intel EtherExpress Pro/100B PCI Fast Ethernet driver @@ -40,38 +40,36 @@ __FBSDID("$FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.266 2007/05/30 03:46:04 kevlo E #include #include +#include #include -#include - /* #include */ #include +#include +#include #include +#include +#include #include +#include #include +#include +#include #include +#include #include #include - -#include -#include -#include -#include -#include -#include - -#include -#include - - #include #include -#ifdef FXP_IP_CSUM_WAR #include #include #include +#include +#include + +#include #include -#endif +#include #include #include /* for PCIM_CMD_xxx */ @@ -108,13 +106,12 @@ static int tx_threshold = 64; /* * The configuration byte map has several undefined fields which - * must be one or must be zero. Set up a template for these bits - * only, (assuming a 82557 chip) leaving the actual configuration - * to fxp_init. + * must be one or must be zero. Set up a template for these bits. + * The actual configuration is performed in fxp_init_body. * * See struct fxp_cb_config for the bit definitions. */ -static u_char fxp_cb_config_template[] = { +static const u_char const fxp_cb_config_template[] = { 0x0, 0x0, /* cb_status */ 0x0, 0x0, /* cb_command */ 0x0, 0x0, 0x0, 0x0, /* link_addr */ @@ -139,13 +136,17 @@ static u_char fxp_cb_config_template[] = { 0xf0, /* 18 */ 0x0, /* 19 */ 0x3f, /* 20 */ - 0x5 /* 21 */ -}; - -struct fxp_ident { - uint16_t devid; - int16_t revid; /* -1 matches anything */ - char *name; + 0x5, /* 21 */ + 0x0, /* 22 */ + 0x0, /* 23 */ + 0x0, /* 24 */ + 0x0, /* 25 */ + 0x0, /* 26 */ + 0x0, /* 27 */ + 0x0, /* 28 */ + 0x0, /* 29 */ + 0x0, /* 30 */ + 0x0 /* 31 */ }; /* @@ -154,53 +155,53 @@ struct fxp_ident { * particular variants, but we don't currently differentiate between * them. */ -static struct fxp_ident fxp_ident_table[] = { - { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, - { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, - { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, - { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, - { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, - { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, - { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, - { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, - { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, - { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, - { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, - { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, - { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, - { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, - { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, - { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, - { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, - { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, - { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, - { 0x1064, -1, "Intel 82562EZ (ICH6)" }, - { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, - { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, - { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, - { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, - { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, - { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, - { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, - { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, - { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, - { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, - { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, - { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, - { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, - { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, - { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, - { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, - { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, - { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, - { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, - { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, - { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, - { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, - { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, - { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, - { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, - { 0, -1, NULL }, +static const struct fxp_ident const fxp_ident_table[] = { + { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, + { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, + { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, + { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, + { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, + { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, + { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, + { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, + { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, + { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, + { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, + { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, + { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, + { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, + { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, + { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, + { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, + { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, + { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, + { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, + { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, + { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, + { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, + { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, + { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, + { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, + { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, + { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, + { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, + { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, + { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, + { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, + { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, + { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, + { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, + { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, + { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, + { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, + { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" }, + { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, + { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, + { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, + { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, + { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, + { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, + { 0, -1, 0, NULL }, }; #ifdef FXP_IP_CSUM_WAR @@ -216,21 +217,29 @@ static int fxp_shutdown(device_t dev); static int fxp_suspend(device_t dev); static int fxp_resume(device_t dev); +static const struct fxp_ident *fxp_find_ident(device_t dev); static void fxp_intr(void *xsc); -static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, +static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, + struct mbuf *m, uint16_t status, int pos); +static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, int count); static void fxp_init(void *xsc); -static void fxp_init_body(struct fxp_softc *sc); +static void fxp_init_body(struct fxp_softc *sc, int); static void fxp_tick(void *xsc); static void fxp_start(struct ifnet *ifp); static void fxp_start_body(struct ifnet *ifp); -static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); +static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); +static void fxp_txeof(struct fxp_softc *sc); static void fxp_stop(struct fxp_softc *sc); static void fxp_release(struct fxp_softc *sc); static int fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data); static void fxp_watchdog(struct fxp_softc *sc); -static int fxp_add_rfabuf(struct fxp_softc *sc, +static void fxp_add_rfabuf(struct fxp_softc *sc, + struct fxp_rx *rxp); +static void fxp_discard_rfabuf(struct fxp_softc *sc, + struct fxp_rx *rxp); +static int fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp); static int fxp_mc_addrs(struct fxp_softc *sc); static void fxp_mc_setup(struct fxp_softc *sc); @@ -250,9 +259,12 @@ static int fxp_serial_ifmedia_upd(struct ifnet *ifp); static void fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); static int fxp_miibus_readreg(device_t dev, int phy, int reg); -static void fxp_miibus_writereg(device_t dev, int phy, int reg, +static int fxp_miibus_writereg(device_t dev, int phy, int reg, int value); +static void fxp_miibus_statchg(device_t dev); static void fxp_load_ucode(struct fxp_softc *sc); +static void fxp_update_stats(struct fxp_softc *sc); +static void fxp_sysctl_node(struct fxp_softc *sc); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); @@ -275,6 +287,7 @@ static device_method_t fxp_methods[] = { /* MII interface */ DEVMETHOD(miibus_readreg, fxp_miibus_readreg), DEVMETHOD(miibus_writereg, fxp_miibus_writereg), + DEVMETHOD(miibus_statchg, fxp_miibus_statchg), { 0, 0 } }; @@ -288,7 +301,6 @@ static driver_t fxp_driver = { static devclass_t fxp_devclass; DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); -DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); static struct resource_spec fxp_res_spec_mem[] = { @@ -319,8 +331,8 @@ fxp_scb_wait(struct fxp_softc *sc) while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) DELAY(2); if (i == 0) { - flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); - flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); + flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); + flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), CSR_READ_1(sc, FXP_CSR_SCB_STATACK), @@ -343,37 +355,51 @@ static void fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, bus_dma_tag_t dmat, bus_dmamap_t map) { - int i = 10000; + int i; - bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); - while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { + for (i = 10000; i > 0; i--) { DELAY(2); - bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(dmat, map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) + break; } if (i == 0) device_printf(sc->dev, "DMA timeout\n"); } +static const struct fxp_ident * +fxp_find_ident(device_t dev) +{ + uint16_t devid; + uint8_t revid; + const struct fxp_ident *ident; + + if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { + devid = pci_get_device(dev); + revid = pci_get_revid(dev); + for (ident = fxp_ident_table; ident->name != NULL; ident++) { + if (ident->devid == devid && + (ident->revid == revid || ident->revid == -1)) { + return (ident); + } + } + } + return (NULL); +} + /* * Return identification string if this device is ours. */ static int fxp_probe(device_t dev) { - uint16_t devid; - uint8_t revid; - struct fxp_ident *ident; + const struct fxp_ident *ident; - if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { - devid = pci_get_device(dev); - revid = pci_get_revid(dev); - for (ident = fxp_ident_table; ident->name != NULL; ident++) { - if (ident->devid == devid && - (ident->revid == revid || ident->revid == -1)) { - device_set_desc(dev, ident->name); - return (BUS_PROBE_DEFAULT); - } - } + ident = fxp_find_ident(dev); + if (ident != NULL) { + device_set_desc(dev, ident->name); + return (BUS_PROBE_DEFAULT); } return (ENXIO); } @@ -402,8 +428,7 @@ fxp_attach(device_t dev) uint32_t val; uint16_t data, myea[ETHER_ADDR_LEN / 2]; u_char eaddr[ETHER_ADDR_LEN]; - int i, prefer_iomap; - int error; + int error, flags, i, pmc, prefer_iomap; error = 0; sc = device_get_softc(dev); @@ -460,10 +485,14 @@ fxp_attach(device_t dev) } /* - * Reset to a stable state. + * Put CU/RU idle state and prepare full reset. */ CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); DELAY(10); + /* Full reset and disable interrupts. */ + CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); + DELAY(10); + CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); /* * Find out how large of an SEEPROM we have. @@ -473,11 +502,37 @@ fxp_attach(device_t dev) /* * Find out the chip revision; lump all 82557 revs together. */ - fxp_read_eeprom(sc, &data, 5, 1); - if ((data >> 8) == 1) - sc->revision = FXP_REV_82557; - else - sc->revision = pci_get_revid(dev); + sc->ident = fxp_find_ident(dev); + if (sc->ident->ich > 0) { + /* Assume ICH controllers are 82559. */ + sc->revision = FXP_REV_82559_A0; + } else { + fxp_read_eeprom(sc, &data, 5, 1); + if ((data >> 8) == 1) + sc->revision = FXP_REV_82557; + else + sc->revision = pci_get_revid(dev); + } + + /* + * Check availability of WOL. 82559ER does not support WOL. + */ + if (sc->revision >= FXP_REV_82558_A4 && + sc->revision != FXP_REV_82559S_A) { + fxp_read_eeprom(sc, &data, 10, 1); + if ((data & 0x20) != 0 && + pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) + sc->flags |= FXP_FLAG_WOLCAP; + } + + /* Receiver lock-up workaround detection. */ + if (sc->revision < FXP_REV_82558_A4) { + fxp_read_eeprom(sc, &data, 3, 1); + if ((data & 0x03) != 0x03) { + sc->flags |= FXP_FLAG_RXBUG; + device_printf(dev, "Enabling Rx lock-up workaround\n"); + } + } /* * Determine whether we must use the 503 serial interface. @@ -487,54 +542,21 @@ fxp_attach(device_t dev) && (data & FXP_PHY_SERIAL_ONLY)) sc->flags |= FXP_FLAG_SERIAL_MEDIA; - SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), - SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), - OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, - &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", - "FXP driver receive interrupt microcode bundling delay"); - SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), - SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), - OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, - &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", - "FXP driver receive interrupt microcode bundle size limit"); - SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), - SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), - OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, - "FXP RNR events"); - SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), - SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), - OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, - "FXP flow control disabled"); - - /* - * Pull in device tunables. - */ - sc->tunable_int_delay = TUNABLE_INT_DELAY; - sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; - sc->tunable_noflow = 1; - (void) resource_int_value(device_get_name(dev), device_get_unit(dev), - "int_delay", &sc->tunable_int_delay); - (void) resource_int_value(device_get_name(dev), device_get_unit(dev), - "bundle_max", &sc->tunable_bundle_max); - (void) resource_int_value(device_get_name(dev), device_get_unit(dev), - "noflow", &sc->tunable_noflow); - sc->rnr = 0; - + fxp_sysctl_node(sc); /* * Enable workarounds for certain chip revision deficiencies. * * Systems based on the ICH2/ICH2-M chip from Intel, and possibly * some systems based a normal 82559 design, have a defect where * the chip can cause a PCI protocol violation if it receives - * a CU_RESUME command when it is entering the IDLE state. The + * a CU_RESUME command when it is entering the IDLE state. The * workaround is to disable Dynamic Standby Mode, so the chip never * deasserts CLKRUN#, and always remains in an active state. * * See Intel 82801BA/82801BAM Specification Update, Errata #30. */ - i = pci_get_device(dev); - if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || - sc->revision >= FXP_REV_82559_A0) { + if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || + (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { fxp_read_eeprom(sc, &data, 10, 1); if (data & 0x02) { /* STB enable */ uint16_t cksum; @@ -590,6 +612,12 @@ fxp_attach(device_t dev) sc->flags |= FXP_FLAG_SAVE_BAD; } + /* For 82559 or later chips, Rx checksum offload is supported. */ + if (sc->revision >= FXP_REV_82559_A0) { + /* 82559ER does not support Rx checksum offloading. */ + if (sc->ident->devid != 0x1209) + sc->flags |= FXP_FLAG_82559_RXCSUM; + } /* * Enable use of extended RFDs and TCBs for 82550 * and later chips. Note: we need extended TXCB support @@ -602,6 +630,8 @@ fxp_attach(device_t dev) sc->rfa_size = sizeof (struct fxp_rfa); sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; sc->flags |= FXP_FLAG_EXT_RFA; + /* Use extended RFA instead of 82559 checksum mode. */ + sc->flags &= ~FXP_FLAG_82559_RXCSUM; } else { sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; sc->tx_cmd = FXP_CB_COMMAND_XMIT; @@ -611,14 +641,27 @@ fxp_attach(device_t dev) * Allocate DMA tags and DMA safe memory. */ sc->maxtxseg = FXP_NTXSEG; - if (sc->flags & FXP_FLAG_EXT_RFA) + sc->maxsegsize = MCLBYTES; + if (sc->flags & FXP_FLAG_EXT_RFA) { sc->maxtxseg--; + sc->maxsegsize = FXP_TSO_SEGSIZE; + } error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - MCLBYTES * sc->maxtxseg, sc->maxtxseg, MCLBYTES, 0, - busdma_lock_mutex, &Giant, &sc->fxp_mtag); + sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), + sc->maxtxseg, sc->maxsegsize, 0, + busdma_lock_mutex, &Giant, &sc->fxp_txmtag); if (error) { - device_printf(dev, "could not allocate dma tag\n"); + device_printf(dev, "could not create TX DMA tag\n"); + goto fail; + } + + error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MCLBYTES, 1, MCLBYTES, 0, + busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); + if (error) { + device_printf(dev, "could not create RX DMA tag\n"); goto fail; } @@ -627,18 +670,20 @@ fxp_attach(device_t dev) sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, &sc->fxp_stag); if (error) { - device_printf(dev, "could not allocate dma tag\n"); + device_printf(dev, "could not create stats DMA tag\n"); goto fail; } error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); - if (error) + if (error) { + device_printf(dev, "could not allocate stats DMA memory\n"); goto fail; + } error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); if (error) { - device_printf(dev, "could not map the stats buffer\n"); + device_printf(dev, "could not load the stats DMA buffer\n"); goto fail; } @@ -647,20 +692,22 @@ fxp_attach(device_t dev) FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); if (error) { - device_printf(dev, "could not allocate dma tag\n"); + device_printf(dev, "could not create TxCB DMA tag\n"); goto fail; } error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); - if (error) + if (error) { + device_printf(dev, "could not allocate TxCB DMA memory\n"); goto fail; + } error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, &sc->fxp_desc.cbl_addr, 0); if (error) { - device_printf(dev, "could not map DMA memory\n"); + device_printf(dev, "could not load TxCB DMA buffer\n"); goto fail; } @@ -669,18 +716,23 @@ fxp_attach(device_t dev) sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, &sc->mcs_tag); if (error) { - device_printf(dev, "could not allocate dma tag\n"); + device_printf(dev, + "could not create multicast setup DMA tag\n"); goto fail; } error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, - BUS_DMA_NOWAIT, &sc->mcs_map); - if (error) + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->mcs_map); + if (error) { + device_printf(dev, + "could not allocate multicast setup DMA memory\n"); goto fail; + } error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); if (error) { - device_printf(dev, "can't map the multicast setup command\n"); + device_printf(dev, + "can't load the multicast setup DMA buffer\n"); goto fail; } @@ -692,13 +744,13 @@ fxp_attach(device_t dev) tcbp = sc->fxp_desc.cbl_list; for (i = 0; i < FXP_NTXCB; i++) { txp[i].tx_cb = tcbp + i; - error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); + error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); if (error) { device_printf(dev, "can't create DMA map for TX\n"); goto fail; } } - error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); + error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); if (error) { device_printf(dev, "can't create spare DMA map\n"); goto fail; @@ -710,15 +762,16 @@ fxp_attach(device_t dev) sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; for (i = 0; i < FXP_NRFABUFS; i++) { rxp = &sc->fxp_desc.rx_list[i]; - error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); + error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); if (error) { device_printf(dev, "can't create DMA map for RX\n"); goto fail; } - if (fxp_add_rfabuf(sc, rxp) != 0) { + if (fxp_new_rfabuf(sc, rxp) != 0) { error = ENOMEM; goto fail; } + fxp_add_rfabuf(sc, rxp); } /* @@ -754,10 +807,17 @@ fxp_attach(device_t dev) ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); } else { - if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, - fxp_ifmedia_sts)) { - device_printf(dev, "MII without any PHY!\n"); - error = ENXIO; + /* + * i82557 wedge when isolating all of their PHYs. + */ + flags = MIIF_NOISOLATE; + if (sc->revision >= FXP_REV_82558_A4) + flags |= MIIF_DOPAUSE; + error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd, + fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, + MII_OFFSET_ANY, flags); + if (error != 0) { + device_printf(dev, "attaching PHYs failed\n"); goto fail; } } @@ -771,11 +831,21 @@ fxp_attach(device_t dev) ifp->if_capabilities = ifp->if_capenable = 0; - /* Enable checksum offload for 82550 or better chips */ + /* Enable checksum offload/TSO for 82550 or better chips */ if (sc->flags & FXP_FLAG_EXT_RFA) { - ifp->if_hwassist = FXP_CSUM_FEATURES; - ifp->if_capabilities |= IFCAP_HWCSUM; - ifp->if_capenable |= IFCAP_HWCSUM; + ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; + ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; + ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; + } + + if (sc->flags & FXP_FLAG_82559_RXCSUM) { + ifp->if_capabilities |= IFCAP_RXCSUM; + ifp->if_capenable |= IFCAP_RXCSUM; + } + + if (sc->flags & FXP_FLAG_WOLCAP) { + ifp->if_capabilities |= IFCAP_WOL_MAGIC; + ifp->if_capenable |= IFCAP_WOL_MAGIC; } #ifdef DEVICE_POLLING @@ -796,6 +866,12 @@ fxp_attach(device_t dev) ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ + if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; + ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; + } /* * Let the system queue as many packets as we have available @@ -805,7 +881,7 @@ fxp_attach(device_t dev) ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; IFQ_SET_READY(&ifp->if_snd); - /* + /* * Hook our interrupt after all initialization is complete. */ error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, @@ -816,6 +892,19 @@ fxp_attach(device_t dev) goto fail; } + /* + * Configure hardware to reject magic frames otherwise + * system will hang on recipt of magic frames. + */ + if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { + FXP_LOCK(sc); + /* Clear wakeup events. */ + CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); + fxp_init_body(sc, 1); + fxp_stop(sc); + FXP_UNLOCK(sc); + } + fail: if (error) fxp_release(sc); @@ -854,29 +943,32 @@ fxp_release(struct fxp_softc *sc) bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); } bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); - if (sc->fxp_mtag) { + if (sc->fxp_rxmtag) { for (i = 0; i < FXP_NRFABUFS; i++) { rxp = &sc->fxp_desc.rx_list[i]; if (rxp->rx_mbuf != NULL) { - bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, + bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, BUS_DMASYNC_POSTREAD); - bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); + bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); m_freem(rxp->rx_mbuf); } - bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); + bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); } - bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); + bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); + bus_dma_tag_destroy(sc->fxp_rxmtag); + } + if (sc->fxp_txmtag) { for (i = 0; i < FXP_NTXCB; i++) { txp = &sc->fxp_desc.tx_list[i]; if (txp->tx_mbuf != NULL) { - bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, + bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); + bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); m_freem(txp->tx_mbuf); } - bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); + bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); } - bus_dma_tag_destroy(sc->fxp_mtag); + bus_dma_tag_destroy(sc->fxp_txmtag); } if (sc->fxp_stag) bus_dma_tag_destroy(sc->fxp_stag); @@ -899,12 +991,11 @@ fxp_detach(device_t dev) struct fxp_softc *sc = device_get_softc(dev); #ifdef DEVICE_POLLING - if (sc->ifp->if_capenable & IFCAP_POLLING) + if (sc->ifp->if_capenable & IFCAP_POLLING) ether_poll_deregister(sc->ifp); #endif FXP_LOCK(sc); - sc->suspended = 1; /* Do same thing as we do for suspend */ /* * Stop DMA and drop transmit queue, but disable interrupts first. */ @@ -938,17 +1029,13 @@ fxp_detach(device_t dev) static int fxp_shutdown(device_t dev) { - struct fxp_softc *sc = device_get_softc(dev); /* * Make sure that DMA is disabled prior to reboot. Not doing * do could allow DMA to corrupt kernel memory during the * reboot before the driver initializes. */ - FXP_LOCK(sc); - fxp_stop(sc); - FXP_UNLOCK(sc); - return (0); + return (fxp_suspend(dev)); } /* @@ -960,11 +1047,27 @@ static int fxp_suspend(device_t dev) { struct fxp_softc *sc = device_get_softc(dev); + struct ifnet *ifp; + int pmc; + uint16_t pmstat; FXP_LOCK(sc); + ifp = sc->ifp; + if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { + pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); + pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { + /* Request PME. */ + pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; + sc->flags |= FXP_FLAG_WOL; + /* Reconfigure hardware to accept magic frames. */ + fxp_init_body(sc, 1); + } + pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); + } fxp_stop(sc); - + sc->suspended = 1; FXP_UNLOCK(sc); @@ -980,15 +1083,28 @@ fxp_resume(device_t dev) { struct fxp_softc *sc = device_get_softc(dev); struct ifnet *ifp = sc->ifp; + int pmc; + uint16_t pmstat; FXP_LOCK(sc); + if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { + sc->flags &= ~FXP_FLAG_WOL; + pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); + /* Disable PME and clear PME status. */ + pmstat &= ~PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); + if ((sc->flags & FXP_FLAG_WOLCAP) != 0) + CSR_WRITE_1(sc, FXP_CSR_PMDR, + CSR_READ_1(sc, FXP_CSR_PMDR)); + } + CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); DELAY(10); /* reinitialize interface if necessary */ if (ifp->if_flags & IFF_UP) - fxp_init_body(sc); + fxp_init_body(sc, 1); sc->suspended = 0; @@ -996,7 +1112,7 @@ fxp_resume(device_t dev) return (0); } -static void +static void fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) { uint16_t reg; @@ -1185,7 +1301,7 @@ fxp_start(struct ifnet *ifp) } /* - * Start packet transmission on the interface. + * Start packet transmission on the interface. * This routine must be called with the softc lock held, and is an * internal entry point only. */ @@ -1194,18 +1310,16 @@ fxp_start_body(struct ifnet *ifp) { struct fxp_softc *sc = ifp->if_softc; struct mbuf *mb_head; - int error, txqueued; + int txqueued; FXP_LOCK_ASSERT(sc, MA_OWNED); - /* - * See if we need to suspend xmit until the multicast filter - * has been reprogrammed (which can only be done at the head - * of the command chain). - */ - if (sc->need_mcsetup) + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING) return; + if (sc->tx_queued > FXP_NTXCB_HIWAT) + fxp_txeof(sc); /* * We're finished if there is nothing more to add to the list or if * we're all filled up with buffers to transmit. @@ -1223,36 +1337,52 @@ fxp_start_body(struct ifnet *ifp) if (mb_head == NULL) break; - error = fxp_encap(sc, mb_head); - if (error) - break; - txqueued = 1; + if (fxp_encap(sc, &mb_head)) { + if (mb_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + } + txqueued++; + /* + * Pass packet to bpf if there is a listener. + */ + BPF_MTAP(ifp, mb_head); } - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); /* * We're finished. If we added to the list, issue a RESUME to get DMA * going again if suspended. */ - if (txqueued) { + if (txqueued > 0) { + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); fxp_scb_wait(sc); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); + /* + * Set a 5 second timer just in case we don't hear + * from the card again. + */ + sc->watchdog_timer = 5; } } static int -fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) +fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) { struct ifnet *ifp; struct mbuf *m; struct fxp_tx *txp; struct fxp_cb_tx *cbp; + struct tcphdr *tcp; bus_dma_segment_t segs[FXP_NTXSEG]; - int chainlen, error, i, nseg; + int error, i, nseg, tcp_payload; FXP_LOCK_ASSERT(sc, MA_OWNED); ifp = sc->ifp; + tcp_payload = 0; + tcp = NULL; /* * Get pointer to next available tx desc. */ @@ -1275,22 +1405,89 @@ fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) txp->tx_cb->ipcb_ip_activation_high = FXP_IPCB_HARDWAREPARSING_ENABLE; - /* - * Deal with TCP/IP checksum offload. Note that - * in order for TCP checksum offload to work, - * the pseudo header checksum must have already - * been computed and stored in the checksum field - * in the TCP header. The stack should have - * already done this for us. - */ - if (m_head->m_pkthdr.csum_flags) { - if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { - txp->tx_cb->ipcb_ip_schedule = - FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; - if (m_head->m_pkthdr.csum_flags & CSUM_TCP) - txp->tx_cb->ipcb_ip_schedule |= - FXP_IPCB_TCP_PACKET; + m = *m_head; + if (m->m_pkthdr.csum_flags & CSUM_TSO) { + /* + * 82550/82551 requires ethernet/IP/TCP headers must be + * contained in the first active transmit buffer. + */ + struct ether_header *eh; + struct ip *ip; + uint32_t ip_off, poff; + + if (M_WRITABLE(*m_head) == 0) { + /* Get a writable copy. */ + m = m_dup(*m_head, M_DONTWAIT); + m_freem(*m_head); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; } + ip_off = sizeof(struct ether_header); + m = m_pullup(*m_head, ip_off); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + eh = mtod(m, struct ether_header *); + /* Check the existence of VLAN tag. */ + if (eh->ether_type == htons(ETHERTYPE_VLAN)) { + ip_off = sizeof(struct ether_vlan_header); + m = m_pullup(m, ip_off); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + } + m = m_pullup(m, ip_off + sizeof(struct ip)); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + ip = (struct ip *)(mtod(m, char *) + ip_off); + poff = ip_off + (ip->ip_hl << 2); + m = m_pullup(m, poff + sizeof(struct tcphdr)); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + tcp = (struct tcphdr *)(mtod(m, char *) + poff); + m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + + /* + * Since 82550/82551 doesn't modify IP length and pseudo + * checksum in the first frame driver should compute it. + */ + ip = (struct ip *)(mtod(m, char *) + ip_off); + tcp = (struct tcphdr *)(mtod(m, char *) + poff); + ip->ip_sum = 0; + ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + + (tcp->th_off << 2)); + tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, + htons(IPPROTO_TCP + (tcp->th_off << 2) + + m->m_pkthdr.tso_segsz)); + /* Compute total TCP payload. */ + tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); + tcp_payload -= tcp->th_off << 2; + *m_head = m; + } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { + /* + * Deal with TCP/IP checksum offload. Note that + * in order for TCP checksum offload to work, + * the pseudo header checksum must have already + * been computed and stored in the checksum field + * in the TCP header. The stack should have + * already done this for us. + */ + txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; + if (m->m_pkthdr.csum_flags & CSUM_TCP) + txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; #ifdef FXP_IP_CSUM_WAR /* @@ -1315,13 +1512,14 @@ fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) * the header sizes/offsets vary. */ - if (m_head->m_pkthdr.csum_flags & CSUM_IP) { - if (m_head->m_pkthdr.len < 38) { + if (m->m_pkthdr.csum_flags & CSUM_IP) { + if (m->m_pkthdr.len < 38) { struct ip *ip; - m_head->m_data += ETHER_HDR_LEN; - ip = mtod(mb_head, struct ip *); - ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); - m_head->m_data -= ETHER_HDR_LEN; + m->m_data += ETHER_HDR_LEN; + ip = mtod(m, struct ip *); + ip->ip_sum = in_cksum(m, ip->ip_hl << 2); + m->m_data -= ETHER_HDR_LEN; + m->m_pkthdr.csum_flags &= ~CSUM_IP; } else { txp->tx_cb->ipcb_ip_activation_high = FXP_IPCB_HARDWAREPARSING_ENABLE; @@ -1332,44 +1530,36 @@ fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) #endif } - chainlen = 0; - for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) - chainlen++; - if (chainlen > sc->maxtxseg) { - struct mbuf *mn; - - /* - * We ran out of segments. We have to recopy this - * mbuf chain first. Bail out if we can't get the - * new buffers. - */ - mn = m_defrag(m_head, M_DONTWAIT); - if (mn == NULL) { - m_freem(m_head); - return (-1); - } else { - m_head = mn; + error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, + segs, &nseg, 0); + if (error == EFBIG) { + m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOMEM); } - } - - /* - * Go through each of the mbufs in the chain and initialize - * the transmit buffer descriptors with the physical address - * and size of the mbuf. - */ - error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, - m_head, segs, &nseg, 0); - if (error) { - device_printf(sc->dev, "can't map mbuf (error %d)\n", error); - m_freem(m_head); - return (-1); + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, + *m_head, segs, &nseg, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (ENOMEM); + } + } else if (error != 0) + return (error); + if (nseg == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); } KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); + bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); cbp = txp->tx_cb; for (i = 0; i < nseg; i++) { - KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); /* * If this is an 82550/82551, then we're using extended * TxCBs _and_ we're using checksum offload. This means @@ -1391,46 +1581,46 @@ fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) cbp->tbd[i].tb_size = htole32(segs[i].ds_len); } } - cbp->tbd_number = nseg; + if (sc->flags & FXP_FLAG_EXT_RFA) { + /* Configure dynamic TBD for 82550/82551. */ + cbp->tbd_number = 0xFF; + cbp->tbd[nseg].tb_size |= htole32(0x8000); + } else + cbp->tbd_number = nseg; + /* Configure TSO. */ + if (m->m_pkthdr.csum_flags & CSUM_TSO) { + cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); + cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); + cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | + FXP_IPCB_IP_CHECKSUM_ENABLE | + FXP_IPCB_TCP_PACKET | + FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; + } + /* Configure VLAN hardware tag insertion. */ + if ((m->m_flags & M_VLANTAG) != 0) { + cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); + txp->tx_cb->ipcb_ip_activation_high |= + FXP_IPCB_INSERTVLAN_ENABLE; + } - bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); - txp->tx_mbuf = m_head; + txp->tx_mbuf = m; txp->tx_cb->cb_status = 0; txp->tx_cb->byte_count = 0; - if (sc->tx_queued != FXP_CXINT_THRESH - 1) { + if (sc->tx_queued != FXP_CXINT_THRESH - 1) txp->tx_cb->cb_command = htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S); - } else { + else txp->tx_cb->cb_command = htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); - /* - * Set a 5 second timer just in case we don't hear - * from the card again. - */ - sc->watchdog_timer = 5; - } - txp->tx_cb->tx_threshold = tx_threshold; + if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) + txp->tx_cb->tx_threshold = tx_threshold; /* * Advance the end of list forward. */ - -#ifdef __alpha__ - /* - * On platforms which can't access memory in 16-bit - * granularities, we must prevent the card from DMA'ing - * up the status while we update the command field. - * This could cause us to overwrite the completion status. - * XXX This is probably bogus and we're _not_ looking - * for atomicity here. - */ - atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, - htole16(FXP_CB_COMMAND_S)); -#else sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); -#endif /*__alpha__*/ sc->fxp_desc.tx_last = txp; /* @@ -1443,26 +1633,23 @@ fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) sc->tx_queued++; - /* - * Pass packet to bpf if there is a listener. - */ - BPF_MTAP(ifp, m_head); return (0); } #ifdef DEVICE_POLLING static poll_handler_t fxp_poll; -static void +static int fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct fxp_softc *sc = ifp->if_softc; uint8_t statack; + int rx_npkts = 0; FXP_LOCK(sc); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { FXP_UNLOCK(sc); - return; + return (rx_npkts); } statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | @@ -1473,7 +1660,7 @@ fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); if (tmp == 0xff || tmp == 0) { FXP_UNLOCK(sc); - return; /* nothing to do */ + return (rx_npkts); /* nothing to do */ } tmp &= ~statack; /* ack what we can */ @@ -1481,8 +1668,9 @@ fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); statack |= tmp; } - fxp_intr_body(sc, ifp, statack, count); + rx_npkts = fxp_intr_body(sc, ifp, statack, count); FXP_UNLOCK(sc); + return (rx_npkts); } #endif /* DEVICE_POLLING */ @@ -1511,10 +1699,10 @@ fxp_intr(void *xsc) while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { /* * It should not be possible to have all bits set; the - * FXP_SCB_INTR_SWI bit always returns 0 on a read. If + * FXP_SCB_INTR_SWI bit always returns 0 on a read. If * all bits are set, this may indicate that the card has * been physically ejected, so ignore it. - */ + */ if (statack == 0xff) { FXP_UNLOCK(sc); return; @@ -1524,7 +1712,8 @@ fxp_intr(void *xsc) * First ACK all the interrupts in this pass. */ CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); - fxp_intr_body(sc, ifp, statack, -1); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + fxp_intr_body(sc, ifp, statack, -1); } FXP_UNLOCK(sc); } @@ -1532,28 +1721,113 @@ fxp_intr(void *xsc) static void fxp_txeof(struct fxp_softc *sc) { + struct ifnet *ifp; struct fxp_tx *txp; - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); + ifp = sc->ifp; + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); for (txp = sc->fxp_desc.tx_first; sc->tx_queued && (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; txp = txp->tx_next) { if (txp->tx_mbuf != NULL) { - bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, + bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); + bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); m_freem(txp->tx_mbuf); txp->tx_mbuf = NULL; /* clear this to reset csum offload bits */ txp->tx_cb->tbd[0].tb_addr = 0; } sc->tx_queued--; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; } sc->fxp_desc.tx_first = txp; - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + if (sc->tx_queued == 0) + sc->watchdog_timer = 0; } static void +fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, + uint16_t status, int pos) +{ + struct ether_header *eh; + struct ip *ip; + struct udphdr *uh; + int32_t hlen, len, pktlen, temp32; + uint16_t csum, *opts; + + if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { + if ((status & FXP_RFA_STATUS_PARSE) != 0) { + if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if (status & FXP_RFDX_CS_IP_CSUM_VALID) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && + (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | + CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + return; + } + + pktlen = m->m_pkthdr.len; + if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) + return; + eh = mtod(m, struct ether_header *); + if (eh->ether_type != htons(ETHERTYPE_IP)) + return; + ip = (struct ip *)(eh + 1); + if (ip->ip_v != IPVERSION) + return; + + hlen = ip->ip_hl << 2; + pktlen -= sizeof(struct ether_header); + if (hlen < sizeof(struct ip)) + return; + if (ntohs(ip->ip_len) < hlen) + return; + if (ntohs(ip->ip_len) != pktlen) + return; + if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) + return; /* can't handle fragmented packet */ + + switch (ip->ip_p) { + case IPPROTO_TCP: + if (pktlen < (hlen + sizeof(struct tcphdr))) + return; + break; + case IPPROTO_UDP: + if (pktlen < (hlen + sizeof(struct udphdr))) + return; + uh = (struct udphdr *)((caddr_t)ip + hlen); + if (uh->uh_sum == 0) + return; /* no checksum */ + break; + default: + return; + } + /* Extract computed checksum. */ + csum = be16dec(mtod(m, char *) + pos); + /* checksum fixup for IP options */ + len = hlen - sizeof(struct ip); + if (len > 0) { + opts = (uint16_t *)(ip + 1); + for (; len > 0; len -= sizeof(uint16_t), opts++) { + temp32 = csum - *opts; + temp32 = (temp32 >> 16) + (temp32 & 65535); + csum = temp32 & 65535; + } + } + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; + m->m_pkthdr.csum_data = csum; +} + +static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, int count) { @@ -1561,9 +1835,12 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, struct fxp_rx *rxp; struct fxp_rfa *rfa; int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; - int fxp_rc = 0; + int rx_npkts; + uint16_t status; + rx_npkts = 0; FXP_LOCK_ASSERT(sc, MA_OWNED); + if (rnr) sc->rnr++; #ifdef DEVICE_POLLING @@ -1587,26 +1864,20 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, * packets go out onto the wire for about 5 to 10 seconds * after the interface is ifconfig'ed for the first time. */ - if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { + if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) fxp_txeof(sc); - sc->watchdog_timer = 0; - if (sc->tx_queued == 0) { - if (sc->need_mcsetup) - fxp_mc_setup(sc); - } - /* - * Try to start more packets transmitting. - */ - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) - fxp_start_body(ifp); - } + /* + * Try to start more packets transmitting. + */ + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + fxp_start_body(ifp); /* * Just return if nothing happened on the receive side. */ if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) - return; + return (rx_npkts); /* * Process receiver interrupts. If a no-resource (RNR) @@ -1625,8 +1896,8 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, m = rxp->rx_mbuf; rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); - bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, - BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ if (count >= 0 && count-- == 0) { @@ -1639,9 +1910,12 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, } #endif /* DEVICE_POLLING */ - if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) + status = le16toh(rfa->rfa_status); + if ((status & FXP_RFA_STATUS_C) == 0) break; + if ((status & FXP_RFA_STATUS_RNR) != 0) + rnr++; /* * Advance head forward. */ @@ -1652,8 +1926,7 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, * If this fails, the old buffer is recycled * instead. */ - fxp_rc = fxp_add_rfabuf(sc, rxp); - if (fxp_rc == 0) { + if (fxp_new_rfabuf(sc, rxp) == 0) { int total_len; /* @@ -1663,37 +1936,33 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, * of bogus length or CRC errors. */ total_len = le16toh(rfa->actual_size) & 0x3fff; - if (total_len < sizeof(struct ether_header) || - total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - - sc->rfa_size || - le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { - m_freem(m); - continue; + if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && + (ifp->if_capenable & IFCAP_RXCSUM) != 0) { + /* Adjust for appended checksum bytes. */ + total_len -= 2; } - - /* Do IP checksum checking. */ - if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { - if (rfa->rfax_csum_sts & - FXP_RFDX_CS_IP_CSUM_BIT_VALID) - m->m_pkthdr.csum_flags |= - CSUM_IP_CHECKED; - if (rfa->rfax_csum_sts & - FXP_RFDX_CS_IP_CSUM_VALID) - m->m_pkthdr.csum_flags |= - CSUM_IP_VALID; - if ((rfa->rfax_csum_sts & - FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && - (rfa->rfax_csum_sts & - FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { - m->m_pkthdr.csum_flags |= - CSUM_DATA_VALID|CSUM_PSEUDO_HDR; - m->m_pkthdr.csum_data = 0xffff; - } + if (total_len < sizeof(struct ether_header) || + total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - + sc->rfa_size) || + status & (FXP_RFA_STATUS_CRC | + FXP_RFA_STATUS_ALIGN)) { + m_freem(m); + fxp_add_rfabuf(sc, rxp); + continue; } m->m_pkthdr.len = m->m_len = total_len; m->m_pkthdr.rcvif = ifp; + /* Do IP checksum checking. */ + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + fxp_rxcsum(sc, ifp, m, status, total_len); + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && + (status & FXP_RFA_STATUS_VLAN) != 0) { + m->m_pkthdr.ether_vtag = + ntohs(rfa->rfax_vlan_id); + m->m_flags |= M_VLANTAG; + } /* * Drop locks before calling if_input() since it * may re-enter fxp_start() in the netisr case. @@ -1705,10 +1974,15 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, FXP_UNLOCK(sc); (*ifp->if_input)(ifp, m); FXP_LOCK(sc); - } else if (fxp_rc == ENOBUFS) { - rnr = 0; - break; + rx_npkts++; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + return (rx_npkts); + } else { + /* Reuse RFA and loaded DMA map. */ + ifp->if_iqdrops++; + fxp_discard_rfabuf(sc, rxp); } + fxp_add_rfabuf(sc, rxp); } if (rnr) { fxp_scb_wait(sc); @@ -1716,6 +1990,82 @@ fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, sc->fxp_desc.rx_head->rx_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); } + return (rx_npkts); +} + +static void +fxp_update_stats(struct fxp_softc *sc) +{ + struct ifnet *ifp = sc->ifp; + struct fxp_stats *sp = sc->fxp_stats; + struct fxp_hwstats *hsp; + uint32_t *status; + + FXP_LOCK_ASSERT(sc, MA_OWNED); + + bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + /* Update statistical counters. */ + if (sc->revision >= FXP_REV_82559_A0) + status = &sp->completion_status; + else if (sc->revision >= FXP_REV_82558_A4) + status = (uint32_t *)&sp->tx_tco; + else + status = &sp->tx_pause; + if (*status == htole32(FXP_STATS_DR_COMPLETE)) { + hsp = &sc->fxp_hwstats; + hsp->tx_good += le32toh(sp->tx_good); + hsp->tx_maxcols += le32toh(sp->tx_maxcols); + hsp->tx_latecols += le32toh(sp->tx_latecols); + hsp->tx_underruns += le32toh(sp->tx_underruns); + hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); + hsp->tx_deffered += le32toh(sp->tx_deffered); + hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); + hsp->tx_multiple_collisions += + le32toh(sp->tx_multiple_collisions); + hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); + hsp->rx_good += le32toh(sp->rx_good); + hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); + hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); + hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); + hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); + hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); + hsp->rx_shortframes += le32toh(sp->rx_shortframes); + hsp->tx_pause += le32toh(sp->tx_pause); + hsp->rx_pause += le32toh(sp->rx_pause); + hsp->rx_controls += le32toh(sp->rx_controls); + hsp->tx_tco += le16toh(sp->tx_tco); + hsp->rx_tco += le16toh(sp->rx_tco); + + ifp->if_opackets += le32toh(sp->tx_good); + ifp->if_collisions += le32toh(sp->tx_total_collisions); + if (sp->rx_good) { + ifp->if_ipackets += le32toh(sp->rx_good); + sc->rx_idle_secs = 0; + } else if (sc->flags & FXP_FLAG_RXBUG) { + /* + * Receiver's been idle for another second. + */ + sc->rx_idle_secs++; + } + ifp->if_ierrors += + le32toh(sp->rx_crc_errors) + + le32toh(sp->rx_alignment_errors) + + le32toh(sp->rx_rnr_errors) + + le32toh(sp->rx_overrun_errors); + /* + * If any transmit underruns occured, bump up the transmit + * threshold by another 512 bytes (64 * 8). + */ + if (sp->tx_underruns) { + ifp->if_oerrors += le32toh(sp->tx_underruns); + if (tx_threshold < 192) + tx_threshold += 64; + } + *status = 0; + bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } } /* @@ -1734,35 +2084,11 @@ fxp_tick(void *xsc) { struct fxp_softc *sc = xsc; struct ifnet *ifp = sc->ifp; - struct fxp_stats *sp = sc->fxp_stats; FXP_LOCK_ASSERT(sc, MA_OWNED); - bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); - ifp->if_opackets += le32toh(sp->tx_good); - ifp->if_collisions += le32toh(sp->tx_total_collisions); - if (sp->rx_good) { - ifp->if_ipackets += le32toh(sp->rx_good); - sc->rx_idle_secs = 0; - } else { - /* - * Receiver's been idle for another second. - */ - sc->rx_idle_secs++; - } - ifp->if_ierrors += - le32toh(sp->rx_crc_errors) + - le32toh(sp->rx_alignment_errors) + - le32toh(sp->rx_rnr_errors) + - le32toh(sp->rx_overrun_errors); - /* - * If any transmit underruns occured, bump up the transmit - * threshold by another 512 bytes (64 * 8). - */ - if (sp->tx_underruns) { - ifp->if_oerrors += le32toh(sp->tx_underruns); - if (tx_threshold < 192) - tx_threshold += 64; - } + + /* Update statistical counters. */ + fxp_update_stats(sc); /* * Release any xmit buffers that have completed DMA. This isn't @@ -1770,7 +2096,7 @@ fxp_tick(void *xsc) * with external storage to be released in a timely manner rather * than being defered for a potentially long time. This limits * the delay to a maximum of one second. - */ + */ fxp_txeof(sc); /* @@ -1785,7 +2111,9 @@ fxp_tick(void *xsc) */ if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { sc->rx_idle_secs = 0; - fxp_mc_setup(sc); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + fxp_init_body(sc, 1); + return; } /* * If there is no pending command, start another stats @@ -1795,24 +2123,7 @@ fxp_tick(void *xsc) /* * Start another stats dump. */ - bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, - BUS_DMASYNC_PREREAD); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); - } else { - /* - * A previous command is still waiting to be accepted. - * Just zero our copy of the stats and wait for the - * next timer event to update them. - */ - sp->tx_good = 0; - sp->tx_underruns = 0; - sp->tx_total_collisions = 0; - - sp->rx_good = 0; - sp->rx_crc_errors = 0; - sp->rx_alignment_errors = 0; - sp->rx_rnr_errors = 0; - sp->rx_overrun_errors = 0; } if (sc->miibus != NULL) mii_tick(device_get_softc(sc->miibus)); @@ -1848,11 +2159,15 @@ fxp_stop(struct fxp_softc *sc) callout_stop(&sc->stat_ch); /* - * Issue software reset, which also unloads the microcode. + * Preserve PCI configuration, configure, IA/multicast + * setup and put RU and CU into idle state. */ - sc->flags &= ~FXP_FLAG_UCODE; - CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); + CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); DELAY(50); + /* Disable interrupts. */ + CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); + + fxp_update_stats(sc); /* * Release any xmit buffers. @@ -1861,9 +2176,10 @@ fxp_stop(struct fxp_softc *sc) if (txp != NULL) { for (i = 0; i < FXP_NTXCB; i++) { if (txp[i].tx_mbuf != NULL) { - bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, + bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); + bus_dmamap_unload(sc->fxp_txmtag, + txp[i].tx_map); m_freem(txp[i].tx_mbuf); txp[i].tx_mbuf = NULL; /* clear this to reset csum offload bits */ @@ -1871,7 +2187,8 @@ fxp_stop(struct fxp_softc *sc) } } } - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->tx_queued = 0; } @@ -1893,7 +2210,7 @@ fxp_watchdog(struct fxp_softc *sc) device_printf(sc->dev, "device timeout\n"); sc->ifp->if_oerrors++; - fxp_init_body(sc); + fxp_init_body(sc, 1); } /* @@ -1907,7 +2224,7 @@ fxp_init(void *xsc) struct fxp_softc *sc = xsc; FXP_LOCK(sc); - fxp_init_body(sc); + fxp_init_body(sc, 1); FXP_UNLOCK(sc); } @@ -1916,14 +2233,14 @@ fxp_init(void *xsc) * softc lock held. */ static void -fxp_init_body(struct fxp_softc *sc) +fxp_init_body(struct fxp_softc *sc, int setmedia) { struct ifnet *ifp = sc->ifp; + struct mii_data *mii; struct fxp_cb_config *cbp; struct fxp_cb_ias *cb_ias; struct fxp_cb_tx *tcbp; struct fxp_tx *txp; - struct fxp_cb_mcs *mcsp; int i, prm; FXP_LOCK_ASSERT(sc, MA_OWNED); @@ -1932,6 +2249,13 @@ fxp_init_body(struct fxp_softc *sc) */ fxp_stop(sc); + /* + * Issue software reset, which also unloads the microcode. + */ + sc->flags &= ~FXP_FLAG_UCODE; + CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); + DELAY(50); + prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; /* @@ -1948,37 +2272,27 @@ fxp_init_body(struct fxp_softc *sc) * Initialize base of dump-stats buffer. */ fxp_scb_wait(sc); - bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); + bzero(sc->fxp_stats, sizeof(struct fxp_stats)); + bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); /* * Attempt to load microcode if requested. + * For ICH based controllers do not load microcode. */ - if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) - fxp_load_ucode(sc); + if (sc->ident->ich == 0) { + if (ifp->if_flags & IFF_LINK0 && + (sc->flags & FXP_FLAG_UCODE) == 0) + fxp_load_ucode(sc); + } /* - * Initialize the multicast address list. + * Set IFF_ALLMULTI status. It's needed in configure action + * command. */ - if (fxp_mc_addrs(sc)) { - mcsp = sc->mcsp; - mcsp->cb_status = 0; - mcsp->cb_command = - htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); - mcsp->link_addr = 0xffffffff; - /* - * Start the multicast setup command. - */ - fxp_scb_wait(sc); - bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); - CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); - fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); - /* ...and wait for it to complete. */ - fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); - bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, - BUS_DMASYNC_POSTWRITE); - } + fxp_mc_addrs(sc); /* * We temporarily use memory that contains the TxCB list to @@ -2020,11 +2334,12 @@ fxp_init_body(struct fxp_softc *sc) cbp->disc_short_rx = !prm; /* discard short packets */ cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ - cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ + cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; cbp->csma_dis = 0; /* (don't) disable link */ - cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ + cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && + (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ @@ -2047,15 +2362,16 @@ fxp_init_body(struct fxp_softc *sc) cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; cbp->ia_wake_en = 0; /* (don't) wake up on address match */ - cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ - /* must set wake_en in PMCSR also */ + cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; cbp->force_fdx = 0; /* (don't) force full duplex */ cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ cbp->multi_ia = 0; /* (don't) accept multiple IAs */ - cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; + cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm; cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; + cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && + (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; - if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { + if (sc->revision == FXP_REV_82557) { /* * The 82557 has no hardware flow control, the values * below are the defaults for the chip. @@ -2069,26 +2385,60 @@ fxp_init_body(struct fxp_softc *sc) cbp->fc_filter = 0; cbp->pri_fc_loc = 1; } else { - cbp->fc_delay_lsb = 0x1f; - cbp->fc_delay_msb = 0x01; + /* Set pause RX FIFO threshold to 1KB. */ + CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); + /* Set pause time. */ + cbp->fc_delay_lsb = 0xff; + cbp->fc_delay_msb = 0xff; cbp->pri_fc_thresh = 3; - cbp->tx_fc_dis = 0; /* enable transmit FC */ - cbp->rx_fc_restop = 1; /* enable FC restop frames */ - cbp->rx_fc_restart = 1; /* enable FC restart frames */ + mii = device_get_softc(sc->miibus); + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_TXPAUSE) != 0) + /* enable transmit FC */ + cbp->tx_fc_dis = 0; + else + /* disable transmit FC */ + cbp->tx_fc_dis = 1; + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) { + /* enable FC restart/restop frames */ + cbp->rx_fc_restart = 1; + cbp->rx_fc_restop = 1; + } else { + /* disable FC restart/restop frames */ + cbp->rx_fc_restart = 0; + cbp->rx_fc_restop = 0; + } cbp->fc_filter = !prm; /* drop FC frames to host */ cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ } + /* Enable 82558 and 82559 extended statistics functionality. */ + if (sc->revision >= FXP_REV_82558_A4) { + if (sc->revision >= FXP_REV_82559_A0) { + /* + * Extend configuration table size to 32 + * to include TCO configuration. + */ + cbp->byte_count = 32; + cbp->ext_stats_dis = 1; + /* Enable TCO stats. */ + cbp->tno_int_or_tco_en = 1; + cbp->gamla_rx = 1; + } else + cbp->ext_stats_dis = 0; + } + /* * Start the config command/DMA. */ fxp_scb_wait(sc); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); /* * Now initialize the station address. Temporarily use the TxCB @@ -2104,11 +2454,17 @@ fxp_init_body(struct fxp_softc *sc) * Start the IAS (Individual Address Setup) command/DMA. */ fxp_scb_wait(sc); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); + + /* + * Initialize the multicast address list. + */ + fxp_mc_setup(sc); /* * Initialize transmit control block (TxCB) list. @@ -2135,11 +2491,13 @@ fxp_init_body(struct fxp_softc *sc) * unit. It will execute the NOP and then suspend. */ tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; sc->tx_queued = 1; fxp_scb_wait(sc); + CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* @@ -2149,10 +2507,7 @@ fxp_init_body(struct fxp_softc *sc) CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); - /* - * Set current media. - */ - if (sc->miibus != NULL) + if (sc->miibus != NULL && setmedia != 0) mii_mediachg(device_get_softc(sc->miibus)); ifp->if_drv_flags |= IFF_DRV_RUNNING; @@ -2203,11 +2558,11 @@ fxp_ifmedia_upd(struct ifnet *ifp) mii = device_get_softc(sc->miibus); FXP_LOCK(sc); - if (mii->mii_instance) { - struct mii_softc *miisc; - LIST_FOREACH(miisc, &mii->mii_phys, mii_list) - mii_phy_reset(miisc); - } + if (mii->mii_instance) { + struct mii_softc *miisc; + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + } mii_mediachg(mii); FXP_UNLOCK(sc); return (0); @@ -2239,17 +2594,15 @@ fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) /* * Add a buffer to the end of the RFA buffer list. * Return 0 if successful, 1 for failure. A failure results in - * adding the 'oldm' (if non-NULL) on to the end of the list - - * tossing out its old contents and recycling it. + * reusing the RFA buffer. * The RFA struct is stuck at the beginning of mbuf cluster and the * data pointer is fixed up to point just past it. */ static int -fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) +fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) { struct mbuf *m; - struct fxp_rfa *rfa, *p_rfa; - struct fxp_rx *p_rx; + struct fxp_rfa *rfa; bus_dmamap_t tmp_map; int error; @@ -2271,6 +2624,90 @@ fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) m->m_data += sc->rfa_size; rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); + rfa->rfa_status = 0; + rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); + rfa->actual_size = 0; + m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - + sc->rfa_size; + + /* + * Initialize the rest of the RFA. Note that since the RFA + * is misaligned, we cannot store values directly. We're thus + * using the le32enc() function which handles endianness and + * is also alignment-safe. + */ + le32enc(&rfa->link_addr, 0xffffffff); + le32enc(&rfa->rbd_addr, 0xffffffff); + + /* Map the RFA into DMA memory. */ + error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, + MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, + &rxp->rx_addr, BUS_DMA_NOWAIT); + if (error) { + m_freem(m); + return (error); + } + + if (rxp->rx_mbuf != NULL) + bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); + tmp_map = sc->spare_map; + sc->spare_map = rxp->rx_map; + rxp->rx_map = tmp_map; + rxp->rx_mbuf = m; + + bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + return (0); +} + +static void +fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) +{ + struct fxp_rfa *p_rfa; + struct fxp_rx *p_rx; + + /* + * If there are other buffers already on the list, attach this + * one to the end by fixing up the tail to point to this one. + */ + if (sc->fxp_desc.rx_head != NULL) { + p_rx = sc->fxp_desc.rx_tail; + p_rfa = (struct fxp_rfa *) + (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); + p_rx->rx_next = rxp; + le32enc(&p_rfa->link_addr, rxp->rx_addr); + p_rfa->rfa_control = 0; + bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } else { + rxp->rx_next = NULL; + sc->fxp_desc.rx_head = rxp; + } + sc->fxp_desc.rx_tail = rxp; +} + +static void +fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) +{ + struct mbuf *m; + struct fxp_rfa *rfa; + + m = rxp->rx_mbuf; + m->m_data = m->m_ext.ext_buf; + /* + * Move the data pointer up so that the incoming data packet + * will be 32-bit aligned. + */ + m->m_data += RFA_ALIGNMENT_FUDGE; + + /* + * Get a pointer to the base of the mbuf cluster and move + * data start past it. + */ + rfa = mtod(m, struct fxp_rfa *); + m->m_data += sc->rfa_size; + rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); + rfa->rfa_status = 0; rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); rfa->actual_size = 0; @@ -2284,43 +2721,8 @@ fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) le32enc(&rfa->link_addr, 0xffffffff); le32enc(&rfa->rbd_addr, 0xffffffff); - /* Map the RFA into DMA memory. */ - error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, - MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, - &rxp->rx_addr, 0); - if (error) { - m_freem(m); - return (error); - } - - bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); - tmp_map = sc->spare_map; - sc->spare_map = rxp->rx_map; - rxp->rx_map = tmp_map; - rxp->rx_mbuf = m; - - bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, + bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - /* - * If there are other buffers already on the list, attach this - * one to the end by fixing up the tail to point to this one. - */ - if (sc->fxp_desc.rx_head != NULL) { - p_rx = sc->fxp_desc.rx_tail; - p_rfa = (struct fxp_rfa *) - (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); - p_rx->rx_next = rxp; - le32enc(&p_rfa->link_addr, rxp->rx_addr); - p_rfa->rfa_control = 0; - bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, - BUS_DMASYNC_PREWRITE); - } else { - rxp->rx_next = NULL; - sc->fxp_desc.rx_head = rxp; - } - sc->fxp_desc.rx_tail = rxp; - return (0); } static int @@ -2343,7 +2745,7 @@ fxp_miibus_readreg(device_t dev, int phy, int reg) return (value & 0xffff); } -static void +static int fxp_miibus_writereg(device_t dev, int phy, int reg, int value) { struct fxp_softc *sc = device_get_softc(dev); @@ -2359,6 +2761,32 @@ fxp_miibus_writereg(device_t dev, int phy, int reg, int value) if (count <= 0) device_printf(dev, "fxp_miibus_writereg: timed out\n"); + return (0); +} + +static void +fxp_miibus_statchg(device_t dev) +{ + struct fxp_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + + sc = device_get_softc(dev); + mii = device_get_softc(sc->miibus); + ifp = sc->ifp; + if (mii == NULL || ifp == NULL || + (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || + (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != + (IFM_AVALID | IFM_ACTIVE)) + return; + + /* + * Call fxp_init_body in order to adjust the flow control settings. + * Note that the 82557 doesn't support hardware flow control. + */ + if (sc->revision == FXP_REV_82557) + return; + fxp_init_body(sc, 0); } static int @@ -2367,16 +2795,11 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) struct fxp_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *)data; struct mii_data *mii; - int flag, mask, error = 0; + int flag, mask, error = 0, reinit; switch (command) { case SIOCSIFFLAGS: FXP_LOCK(sc); - if (ifp->if_flags & IFF_ALLMULTI) - sc->flags |= FXP_FLAG_ALL_MCAST; - else - sc->flags &= ~FXP_FLAG_ALL_MCAST; - /* * If interface is marked up and not running, then start it. * If it is marked down and running, stop it. @@ -2384,35 +2807,24 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) * such as IFF_PROMISC are handled. */ if (ifp->if_flags & IFF_UP) { - fxp_init_body(sc); + if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) && + ((ifp->if_flags ^ sc->if_flags) & + (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) + fxp_init_body(sc, 1); + else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + fxp_init_body(sc, 1); } else { - if (ifp->if_drv_flags & IFF_DRV_RUNNING) + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) fxp_stop(sc); } + sc->if_flags = ifp->if_flags; FXP_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: - FXP_LOCK(sc); - if (ifp->if_flags & IFF_ALLMULTI) - sc->flags |= FXP_FLAG_ALL_MCAST; - else - sc->flags &= ~FXP_FLAG_ALL_MCAST; - /* - * Multicast list has changed; set the hardware filter - * accordingly. - */ - if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) - fxp_mc_setup(sc); - /* - * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it - * again rather than else {}. - */ - if (sc->flags & FXP_FLAG_ALL_MCAST) - fxp_init_body(sc); - FXP_UNLOCK(sc); - error = 0; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + fxp_init(sc); break; case SIOCSIFMEDIA: @@ -2427,6 +2839,7 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) break; case SIOCSIFCAP: + reinit = 0; mask = ifp->if_capenable ^ ifr->ifr_reqcap; #ifdef DEVICE_POLLING if (mask & IFCAP_POLLING) { @@ -2449,8 +2862,34 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) } } #endif - if (mask & IFCAP_VLAN_MTU) { - FXP_LOCK(sc); + FXP_LOCK(sc); + if ((mask & IFCAP_TXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { + ifp->if_capenable ^= IFCAP_TXCSUM; + if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) + ifp->if_hwassist |= FXP_CSUM_FEATURES; + else + ifp->if_hwassist &= ~FXP_CSUM_FEATURES; + } + if ((mask & IFCAP_RXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { + ifp->if_capenable ^= IFCAP_RXCSUM; + if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) + reinit++; + } + if ((mask & IFCAP_TSO4) != 0 && + (ifp->if_capabilities & IFCAP_TSO4) != 0) { + ifp->if_capenable ^= IFCAP_TSO4; + if ((ifp->if_capenable & IFCAP_TSO4) != 0) + ifp->if_hwassist |= CSUM_TSO; + else + ifp->if_hwassist &= ~CSUM_TSO; + } + if ((mask & IFCAP_WOL_MAGIC) != 0 && + (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) + ifp->if_capenable ^= IFCAP_WOL_MAGIC; + if ((mask & IFCAP_VLAN_MTU) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { ifp->if_capenable ^= IFCAP_VLAN_MTU; if (sc->revision != FXP_REV_82557) flag = FXP_FLAG_LONG_PKT_EN; @@ -2458,9 +2897,26 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) flag = FXP_FLAG_SAVE_BAD; sc->flags ^= flag; if (ifp->if_flags & IFF_UP) - fxp_init_body(sc); - FXP_UNLOCK(sc); + reinit++; } + if ((mask & IFCAP_VLAN_HWCSUM) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) + ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + if ((mask & IFCAP_VLAN_HWTSO) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) + ifp->if_capenable ^= IFCAP_VLAN_HWTSO; + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) + ifp->if_capenable &= + ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); + reinit++; + } + if (reinit > 0 && ifp->if_flags & IFF_UP) + fxp_init_body(sc, 1); + FXP_UNLOCK(sc); + VLAN_CAPABILITIES(ifp); break; default: @@ -2481,13 +2937,13 @@ fxp_mc_addrs(struct fxp_softc *sc) int nmcasts; nmcasts = 0; - if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { - IF_ADDR_LOCK(ifp); + if ((ifp->if_flags & IFF_ALLMULTI) == 0) { + if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (nmcasts >= MAXMCADDR) { - sc->flags |= FXP_FLAG_ALL_MCAST; + ifp->if_flags |= IFF_ALLMULTI; nmcasts = 0; break; } @@ -2495,7 +2951,7 @@ fxp_mc_addrs(struct fxp_softc *sc) &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); nmcasts++; } - IF_ADDR_UNLOCK(ifp); + if_maddr_runlock(ifp); } mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); return (nmcasts); @@ -2512,87 +2968,28 @@ fxp_mc_addrs(struct fxp_softc *sc) * points to the TxCB ring, but the mcsetup descriptor itself is not part * of it. We then can do 'CU_START' on the mcsetup descriptor and have it * lead into the regular TxCB ring when it completes. - * - * This function must be called at splimp. */ static void fxp_mc_setup(struct fxp_softc *sc) { - struct fxp_cb_mcs *mcsp = sc->mcsp; - struct fxp_tx *txp; + struct fxp_cb_mcs *mcsp; int count; FXP_LOCK_ASSERT(sc, MA_OWNED); - /* - * If there are queued commands, we must wait until they are all - * completed. If we are already waiting, then add a NOP command - * with interrupt option so that we're notified when all commands - * have been completed - fxp_start() ensures that no additional - * TX commands will be added when need_mcsetup is true. - */ - if (sc->tx_queued) { - /* - * need_mcsetup will be true if we are already waiting for the - * NOP command to be completed (see below). In this case, bail. - */ - if (sc->need_mcsetup) - return; - sc->need_mcsetup = 1; - /* - * Add a NOP command with interrupt so that we are notified - * when all TX commands have been processed. - */ - txp = sc->fxp_desc.tx_last->tx_next; - txp->tx_mbuf = NULL; - txp->tx_cb->cb_status = 0; - txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | - FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); - /* - * Advance the end of list forward. - */ - sc->fxp_desc.tx_last->tx_cb->cb_command &= - htole16(~FXP_CB_COMMAND_S); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); - sc->fxp_desc.tx_last = txp; - sc->tx_queued++; - /* - * Issue a resume in case the CU has just suspended. - */ - fxp_scb_wait(sc); - fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); - /* - * Set a 5 second timer just in case we don't hear from the - * card again. - */ - sc->watchdog_timer = 5; - - return; - } - sc->need_mcsetup = 0; - - /* - * Initialize multicast setup descriptor. - */ + mcsp = sc->mcsp; mcsp->cb_status = 0; - mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | - FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); - mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); - txp = &sc->fxp_desc.mcs_tx; - txp->tx_mbuf = NULL; - txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; - txp->tx_next = sc->fxp_desc.tx_list; - (void) fxp_mc_addrs(sc); - sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; - sc->tx_queued = 1; + mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); + mcsp->link_addr = 0xffffffff; + fxp_mc_addrs(sc); /* - * Wait until command unit is not active. This should never - * be the case when nothing is queued, but make sure anyway. + * Wait until command unit is idle. This should never be the + * case when nothing is queued, but make sure anyway. */ count = 100; - while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == - FXP_SCB_CUS_ACTIVE && --count) + while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != + FXP_SCB_CUS_IDLE && --count) DELAY(10); if (count == 0) { device_printf(sc->dev, "command queue timeout\n"); @@ -2603,12 +3000,12 @@ fxp_mc_setup(struct fxp_softc *sc) * Start the multicast setup command. */ fxp_scb_wait(sc); - bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); - - sc->watchdog_timer = 2; - return; + /* ...and wait for it to complete. */ + fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); } static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; @@ -2621,13 +3018,13 @@ static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) -struct ucode { +static const struct ucode { uint32_t revision; uint32_t *ucode; int length; u_short int_delay_offset; u_short bundle_max_offset; -} ucode_table[] = { +} const ucode_table[] = { { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), @@ -2646,7 +3043,7 @@ struct ucode { static void fxp_load_ucode(struct fxp_softc *sc) { - struct ucode *uc; + const struct ucode *uc; struct fxp_cb_ucode *cbp; int i; @@ -2671,19 +3068,120 @@ fxp_load_ucode(struct fxp_softc *sc) * Download the ucode to the chip. */ fxp_scb_wait(sc); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); - bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); device_printf(sc->dev, "Microcode loaded, int_delay: %d usec bundle_max: %d\n", - sc->tunable_int_delay, + sc->tunable_int_delay, uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); sc->flags |= FXP_FLAG_UCODE; } +#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ + SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) + +static void +fxp_sysctl_node(struct fxp_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *child, *parent; + struct sysctl_oid *tree; + struct fxp_hwstats *hsp; + + ctx = device_get_sysctl_ctx(sc->dev); + child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); + + SYSCTL_ADD_PROC(ctx, child, + OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, + &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", + "FXP driver receive interrupt microcode bundling delay"); + SYSCTL_ADD_PROC(ctx, child, + OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, + &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", + "FXP driver receive interrupt microcode bundle size limit"); + SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, + "FXP RNR events"); + + /* + * Pull in device tunables. + */ + sc->tunable_int_delay = TUNABLE_INT_DELAY; + sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; + (void) resource_int_value(device_get_name(sc->dev), + device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); + (void) resource_int_value(device_get_name(sc->dev), + device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); + sc->rnr = 0; + + hsp = &sc->fxp_hwstats; + tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, + NULL, "FXP statistics"); + parent = SYSCTL_CHILDREN(tree); + + /* Rx MAC statistics. */ + tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, + NULL, "Rx MAC statistics"); + child = SYSCTL_CHILDREN(tree); + FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", + &hsp->rx_good, "Good frames"); + FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", + &hsp->rx_crc_errors, "CRC errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", + &hsp->rx_alignment_errors, "Alignment errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", + &hsp->rx_rnr_errors, "RNR errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", + &hsp->rx_overrun_errors, "Overrun errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", + &hsp->rx_cdt_errors, "Collision detect errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", + &hsp->rx_shortframes, "Short frame errors"); + if (sc->revision >= FXP_REV_82558_A4) { + FXP_SYSCTL_STAT_ADD(ctx, child, "pause", + &hsp->rx_pause, "Pause frames"); + FXP_SYSCTL_STAT_ADD(ctx, child, "controls", + &hsp->rx_controls, "Unsupported control frames"); + } + if (sc->revision >= FXP_REV_82559_A0) + FXP_SYSCTL_STAT_ADD(ctx, child, "tco", + &hsp->rx_tco, "TCO frames"); + + /* Tx MAC statistics. */ + tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, + NULL, "Tx MAC statistics"); + child = SYSCTL_CHILDREN(tree); + FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", + &hsp->tx_good, "Good frames"); + FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", + &hsp->tx_maxcols, "Maximum collisions errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", + &hsp->tx_latecols, "Late collisions errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", + &hsp->tx_underruns, "Underrun errors"); + FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", + &hsp->tx_lostcrs, "Lost carrier sense"); + FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", + &hsp->tx_deffered, "Deferred"); + FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", + &hsp->tx_single_collisions, "Single collisions"); + FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", + &hsp->tx_multiple_collisions, "Multiple collisions"); + FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", + &hsp->tx_total_collisions, "Total collisions"); + if (sc->revision >= FXP_REV_82558_A4) + FXP_SYSCTL_STAT_ADD(ctx, child, "pause", + &hsp->tx_pause, "Pause frames"); + if (sc->revision >= FXP_REV_82559_A0) + FXP_SYSCTL_STAT_ADD(ctx, child, "tco", + &hsp->tx_tco, "TCO frames"); +} + +#undef FXP_SYSCTL_STAT_ADD + static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { @@ -2701,16 +3199,18 @@ sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) /* * Interrupt delay is expressed in microseconds, a multiplier is used - * to convert this to the appropriate clock ticks before using. + * to convert this to the appropriate clock ticks before using. */ static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) { + return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); } static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) { + return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); } diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h index 1bdb9bf281..e2b1e3f498 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h @@ -25,7 +25,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/fxp/if_fxpreg.h,v 1.39 2005/04/22 13:05:53 mux Exp $ + * $FreeBSD: src/sys/dev/fxp/if_fxpreg.h,v 1.43.2.3.2.1 2010/12/21 17:09:25 kensmith Exp $ */ #define FXP_VENDORID_INTEL 0x8086 @@ -45,7 +45,9 @@ #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ -#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ +#define FXP_CSR_FC_THRESH 0x19 /* flow control (1 byte) */ +#define FXP_CSR_FC_STATUS 0x1A /* flow control status (1 byte) */ +#define FXP_CSR_PMDR 0x1B /* power management driver (1 byte) */ #define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ /* @@ -223,7 +225,7 @@ struct fxp_cb_config { /* Bytes 22 - 31 -- i82550 only */ u_int __FXP_BITFIELD3(gamla_rx:1, - vlan_drop_en:1, + vlan_strip_en:1, :6); uint8_t pad[9]; }; @@ -287,12 +289,12 @@ struct fxp_cb_tx { /* * The following structure isn't actually part of the TxCB, * unless the extended TxCB feature is being used. In this - * case, the first two elements of the structure below are + * case, the first two elements of the structure below are * fetched along with the TxCB. */ union { struct fxp_ipcb ipcb; - struct fxp_tbd tbd[FXP_NTXSEG]; + struct fxp_tbd tbd[FXP_NTXSEG + 1]; } tx_cb_u; }; @@ -376,6 +378,7 @@ struct fxp_rfa { #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ +#define FXP_RFA_STATUS_VLAN 0x1000 /* VLAN tagged frame */ #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ @@ -416,11 +419,19 @@ struct fxp_stats { uint32_t rx_overrun_errors; uint32_t rx_cdt_errors; uint32_t rx_shortframes; + uint32_t tx_pause; + uint32_t rx_pause; + uint32_t rx_controls; + uint16_t tx_tco; + uint16_t rx_tco; uint32_t completion_status; + uint32_t reserved0; + uint32_t reserved1; + uint32_t reserved2; }; #define FXP_STATS_DUMP_COMPLETE 0xa005 #define FXP_STATS_DR_COMPLETE 0xa007 - + /* * Serial EEPROM control register bits */ diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpvar.h b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpvar.h index bccf3526f3..3d6ba30aad 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpvar.h +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpvar.h @@ -1,13 +1,13 @@ /*- * Copyright (c) 1995, David Greenman * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions - * are met: + * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following - * disclaimer. + * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. @@ -24,7 +24,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.40 2006/11/30 14:58:01 glebius Exp $ + * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.49.2.4.2.1 2010/12/21 17:09:25 kensmith Exp $ */ /* @@ -38,6 +38,12 @@ * This must be a power of two. */ #define FXP_NTXCB 128 +#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10) + +/* + * Maximum size of a DMA segment. + */ +#define FXP_TSO_SEGSIZE 4096 /* * Size of the TxCB list. @@ -86,16 +92,16 @@ /* * Default maximum time, in microseconds, that an interrupt may be delayed - * in an attempt to coalesce interrupts. This is only effective if the Intel + * in an attempt to coalesce interrupts. This is only effective if the Intel * microcode is loaded, and may be changed via either loader tunables or * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. */ #define TUNABLE_INT_DELAY 1000 /* - * Default number of packets that will be bundled, before an interrupt is + * Default number of packets that will be bundled, before an interrupt is * generated. This is only effective if the Intel microcode is loaded, and - * may be changed via either loader tunables or sysctl. This may not be + * may be changed via either loader tunables or sysctl. This may not be * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD * entry in rcvbundl.h. */ @@ -136,6 +142,37 @@ struct fxp_desc_list { bus_dma_tag_t rx_tag; }; +struct fxp_ident { + uint16_t devid; + int16_t revid; /* -1 matches anything */ + uint8_t ich; + const char *name; +}; + +struct fxp_hwstats { + uint32_t tx_good; + uint32_t tx_maxcols; + uint32_t tx_latecols; + uint32_t tx_underruns; + uint32_t tx_lostcrs; + uint32_t tx_deffered; + uint32_t tx_single_collisions; + uint32_t tx_multiple_collisions; + uint32_t tx_total_collisions; + uint32_t tx_pause; + uint32_t tx_tco; + uint32_t rx_good; + uint32_t rx_crc_errors; + uint32_t rx_alignment_errors; + uint32_t rx_rnr_errors; + uint32_t rx_overrun_errors; + uint32_t rx_cdt_errors; + uint32_t rx_shortframes; + uint32_t rx_pause; + uint32_t rx_controls; + uint32_t rx_tco; +}; + /* * NOTE: Elements are ordered for optimal cacheline behavior, and NOT * for functional grouping. @@ -145,8 +182,10 @@ struct fxp_softc { struct resource *fxp_res[2]; /* I/O and IRQ resources */ struct resource_spec *fxp_spec; /* the resource spec we used */ void *ih; /* interrupt handler cookie */ + const struct fxp_ident *ident; struct mtx sc_mtx; - bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ + bus_dma_tag_t fxp_txmtag; /* bus DMA tag for Tx mbufs */ + bus_dma_tag_t fxp_rxmtag; /* bus DMA tag for Rx mbufs */ bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ bus_dmamap_t fxp_smap; /* bus DMA map for stats */ bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ @@ -156,10 +195,11 @@ struct fxp_softc { bus_dmamap_t spare_map; /* spare DMA map */ struct fxp_desc_list fxp_desc; /* descriptors management struct */ int maxtxseg; /* maximum # of TX segments */ + int maxsegsize; /* maximum size of a TX segment */ int tx_queued; /* # of active TxCB's */ - int need_mcsetup; /* multicast filter needs programming */ struct fxp_stats *fxp_stats; /* Pointer to interface stats */ uint32_t stats_addr; /* DMA address of the stats structure */ + struct fxp_hwstats fxp_hwstats; int rx_idle_secs; /* # of seconds RX has been idle */ struct callout stat_ch; /* stat callout */ int watchdog_timer; /* seconds until chip reset */ @@ -170,13 +210,13 @@ struct fxp_softc { device_t dev; int tunable_int_delay; /* interrupt delay value for ucode */ int tunable_bundle_max; /* max # frames per interrupt (ucode) */ - int tunable_noflow; /* flow control disabled */ int rnr; /* RNR events */ int eeprom_size; /* size of serial EEPROM */ int suspended; /* 0 = normal 1 = suspended or dead */ int cu_resume_bug; int revision; int flags; + int if_flags; uint8_t rfa_size; uint32_t tx_cmd; }; @@ -187,12 +227,15 @@ struct fxp_softc { #define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ #define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ #define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ -#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ #define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ #define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ #define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ #define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ #define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */ +#define FXP_FLAG_82559_RXCSUM 0x1000 /* 82559 compatible RX checksum */ +#define FXP_FLAG_WOLCAP 0x2000 /* WOL capability */ +#define FXP_FLAG_WOL 0x4000 /* WOL active */ +#define FXP_FLAG_RXBUG 0x8000 /* Rx lock-up bug */ /* Macros to ease CSR access. */ #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/rcvbundl.h b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/rcvbundl.h index ef994002e8..39e70e96e2 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/rcvbundl.h +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/rcvbundl.h @@ -29,7 +29,7 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* - * $FreeBSD: src/sys/dev/fxp/rcvbundl.h,v 1.3 2005/04/21 19:34:57 mux Exp $ + * $FreeBSD: src/sys/dev/fxp/rcvbundl.h,v 1.3.22.1.6.1 2010/12/21 17:09:25 kensmith Exp $ */ /* rcvbundl.h diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphy.c b/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphy.c index bd729381f2..2fb705064e 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphy.c +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphy.c @@ -29,7 +29,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/inphy.c,v 1.17 2007/01/12 22:27:46 marius Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/inphy.c,v 1.17.10.7.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * driver for Intel 82553 and 82555 PHYs @@ -77,6 +77,7 @@ DRIVER_MODULE(inphy, miibus, inphy_driver, inphy_devclass, 0, 0); static int inphy_service(struct mii_softc *, struct mii_data *, int); static void inphy_status(struct mii_softc *); +static void inphy_reset(struct mii_softc *); static const struct mii_phydesc inphys[] = { MII_PHY_DESC(INTEL, I82553C), @@ -104,20 +105,22 @@ inphy_attach(device_t dev) sc = device_get_softc(dev); ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); - mii = device_get_softc(sc->mii_dev); + mii = ma->mii_data; LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); - sc->mii_inst = mii->mii_instance; + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = inphy_service; sc->mii_pdata = mii; - mii->mii_instance++; + + sc->mii_flags |= MIIF_NOMANPAUSE; ifmedia_add(&mii->mii_media, IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), MII_MEDIA_100_TX, NULL); - mii_phy_reset(sc); + inphy_reset(sc); sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; device_printf(dev, " "); @@ -132,22 +135,12 @@ inphy_attach(device_t dev) static int inphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { - struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - int reg; switch (cmd) { case MII_POLLSTAT: - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); break; case MII_MEDIACHG: - if (IFM_INST(ife->ifm_media) != sc->mii_inst) { - reg = PHY_READ(sc, MII_BMCR); - PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); - return (0); - } - /* * If the interface is not up, don't do anything. */ @@ -158,8 +151,6 @@ inphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) break; case MII_TICK: - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - return (0); if (mii_phy_tick(sc) == EJUSTRETURN) return (0); break; @@ -209,7 +200,21 @@ inphy_status(struct mii_softc *sc) else mii->mii_media_active |= IFM_10_T; if (scr & SCR_FDX) - mii->mii_media_active |= IFM_FDX; + mii->mii_media_active |= + IFM_FDX | mii_phy_flowstatus(sc); + else + mii->mii_media_active |= IFM_HDX; } else mii->mii_media_active = ife->ifm_media; } + +static void +inphy_reset(struct mii_softc *sc) +{ + + mii_phy_reset(sc); + + /* Ensure Bay flow control is disabled. */ + PHY_WRITE(sc, MII_INPHY_SCR, + PHY_READ(sc, MII_INPHY_SCR) & ~SCR_FLOWCTL); +} diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphyreg.h b/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphyreg.h index c7a9888ced..6cf39c0a9d 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphyreg.h +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/mii/inphyreg.h @@ -26,7 +26,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/mii/inphyreg.h,v 1.1 2001/03/12 02:41:57 jlemon Exp $ + * $FreeBSD: src/sys/dev/mii/inphyreg.h,v 1.1.38.1.6.1 2010/12/21 17:09:25 kensmith Exp $ */ #define MII_INPHY_SCR 0x10 /* status and control register */ diff --git a/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c b/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c index b7fa7fad31..e9f06d0dc6 100644 --- a/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c +++ b/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c @@ -31,7 +31,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/rlphy.c,v 1.31 2007/06/06 07:07:23 yongari Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/mii/rlphy.c,v 1.32.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * driver for RealTek 8139 internal PHYs @@ -109,8 +109,13 @@ rlphy_probe(device_t dev) int rv; rv = mii_phy_dev_probe(dev, rlphys, BUS_PROBE_DEFAULT); +#ifdef __HAIKU__ if (rv == BUS_PROBE_DEFAULT) return (rv); +#else + if (rv <= 0) + return (rv); +#endif nic = device_get_name(device_get_parent(device_get_parent(dev))); if (strcmp(nic, "rl") == 0 || strcmp(nic, "re") == 0) @@ -129,7 +134,7 @@ rlphy_attach(device_t dev) sc = device_get_softc(dev); ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); - mii = device_get_softc(sc->mii_dev); + mii = ma->mii_data; /* * Check whether we're the RTL8201L PHY and remember so the status @@ -139,23 +144,17 @@ rlphy_attach(device_t dev) if (mii_phy_dev_probe(dev, rlphys, 0) == 0) rsc->sc_is_RTL8201L++; - /* - * The RealTek PHY can never be isolated, so never allow non-zero - * instances! - */ - if (mii->mii_instance != 0) { - device_printf(dev, "ignoring this PHY, non-zero instance\n"); - return (ENXIO); - } - LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); - sc->mii_inst = mii->mii_instance; + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = rlphy_service; sc->mii_pdata = mii; - mii->mii_instance++; + /* + * The RealTek PHY can never be isolated. + */ sc->mii_flags |= MIIF_NOISOLATE; #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) @@ -165,8 +164,7 @@ rlphy_attach(device_t dev) mii_phy_reset(sc); - sc->mii_capabilities = - PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); @@ -178,13 +176,6 @@ rlphy_attach(device_t dev) static int rlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { - struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - - /* - * We can't isolate the RealTek PHY, so it has to be the only one! - */ - if (IFM_INST(ife->ifm_media) != sc->mii_inst) - panic("rlphy_service: can't isolate RealTek PHY"); switch (cmd) { case MII_POLLSTAT: @@ -261,16 +252,16 @@ rlphy_status(struct mii_softc *phy) if ((anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR))) { - if (anlpar & ANLPAR_T4) - mii->mii_media_active |= IFM_100_T4; - else if (anlpar & ANLPAR_TX_FD) + if (anlpar & ANLPAR_TX_FD) mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4|IFM_HDX; else if (anlpar & ANLPAR_TX) - mii->mii_media_active |= IFM_100_TX; + mii->mii_media_active |= IFM_100_TX|IFM_HDX; else if (anlpar & ANLPAR_10_FD) mii->mii_media_active |= IFM_10_T|IFM_FDX; else if (anlpar & ANLPAR_10) - mii->mii_media_active |= IFM_10_T; + mii->mii_media_active |= IFM_10_T|IFM_HDX; else mii->mii_media_active |= IFM_NONE; return; @@ -314,6 +305,7 @@ rlphy_status(struct mii_softc *phy) else mii->mii_media_active |= IFM_100_TX; } + mii->mii_media_active |= IFM_HDX; } else mii->mii_media_active = ife->ifm_media; } diff --git a/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rl.c b/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rl.c index 0f757e66d0..7809f4e4ee 100644 --- a/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rl.c +++ b/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rl.c @@ -31,7 +31,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/pci/if_rl.c,v 1.170.2.1 2007/12/02 08:38:31 remko Exp $"); +__FBSDID("$FreeBSD: src/sys/pci/if_rl.c,v 1.189.2.8.2.1 2010/12/21 17:09:25 kensmith Exp $"); /* * RealTek 8129/8139 PCI NIC driver @@ -96,6 +96,7 @@ __FBSDID("$FreeBSD: src/sys/pci/if_rl.c,v 1.170.2.1 2007/12/02 08:38:31 remko Ex #include #include #include +#include #include #include @@ -124,16 +125,6 @@ MODULE_DEPEND(rl, miibus, 1, 1, 1); /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" -/* - * Default to using PIO access for this driver. On SMP systems, - * there appear to be problems with memory mapped mode: it looks like - * doing too many memory mapped access back to back in rapid succession - * can hang the bus. I'm inclined to blame this on crummy design/construction - * on the part of RealTek. Memory mapped mode does appear to work on - * uniprocessor systems though. - */ -#define RL_USEIOSPACE - #include /* @@ -144,6 +135,8 @@ static struct rl_type rl_devs[] = { "RealTek 8129 10/100BaseTX" }, { RT_VENDORID, RT_DEVICEID_8139, RL_8139, "RealTek 8139 10/100BaseTX" }, + { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, + "RealTek 8139 10/100BaseTX" }, { RT_VENDORID, RT_DEVICEID_8138, RL_8139, "RealTek 8139 10/100BaseTX CardBus" }, { RT_VENDORID, RT_DEVICEID_8100, RL_8139, @@ -153,7 +146,7 @@ static struct rl_type rl_devs[] = { { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, "Delta Electronics 8139 10/100BaseTX" }, { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, - "Addtron Technolgy 8139 10/100BaseTX" }, + "Addtron Technology 8139 10/100BaseTX" }, { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, "D-Link DFE-530TX+ 10/100BaseTX" }, { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, @@ -175,18 +168,19 @@ static struct rl_type rl_devs[] = { { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, "LevelOne FPC-0106TX" }, { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, - "Edimax EP-4103DL CardBus" }, - { 0, 0, 0, NULL } + "Edimax EP-4103DL CardBus" } }; static int rl_attach(device_t); static int rl_detach(device_t); -static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); -static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); +static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); +static int rl_dma_alloc(struct rl_softc *); +static void rl_dma_free(struct rl_softc *); static void rl_eeprom_putbyte(struct rl_softc *, int); static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); -static int rl_encap(struct rl_softc *, struct mbuf * ); +static int rl_encap(struct rl_softc *, struct mbuf **); static int rl_list_tx_init(struct rl_softc *); +static int rl_list_rx_init(struct rl_softc *); static int rl_ifmedia_upd(struct ifnet *); static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int rl_ioctl(struct ifnet *, u_long, caddr_t); @@ -201,16 +195,16 @@ static int rl_miibus_readreg(device_t, int, int); static void rl_miibus_statchg(device_t); static int rl_miibus_writereg(device_t, int, int, int); #ifdef DEVICE_POLLING -static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); -static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); +static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); +static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); #endif static int rl_probe(device_t); static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); static void rl_reset(struct rl_softc *); static int rl_resume(device_t); -static void rl_rxeof(struct rl_softc *); -static void rl_setmulti(struct rl_softc *); -static void rl_shutdown(device_t); +static int rl_rxeof(struct rl_softc *); +static void rl_rxfilter(struct rl_softc *); +static int rl_shutdown(device_t); static void rl_start(struct ifnet *); static void rl_start_locked(struct ifnet *); static void rl_stop(struct rl_softc *); @@ -218,14 +212,8 @@ static int rl_suspend(device_t); static void rl_tick(void *); static void rl_txeof(struct rl_softc *); static void rl_watchdog(struct rl_softc *); - -#ifdef RL_USEIOSPACE -#define RL_RES SYS_RES_IOPORT -#define RL_RID RL_PCI_LOIO -#else -#define RL_RES SYS_RES_MEMORY -#define RL_RID RL_PCI_LOMEM -#endif +static void rl_setwol(struct rl_softc *); +static void rl_clrwol(struct rl_softc *); static device_method_t rl_methods[] = { /* Device interface */ @@ -268,22 +256,6 @@ DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); CSR_WRITE_1(sc, RL_EECMD, \ CSR_READ_1(sc, RL_EECMD) & ~x) -static void -rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - struct rl_softc *sc = arg; - - CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); -} - -static void -rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - struct rl_softc *sc = arg; - - CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); -} - /* * Send a read command and address to the EEPROM, check for ACK. */ @@ -547,10 +519,6 @@ rl_miibus_readreg(device_t dev, int phy, int reg) sc = device_get_softc(dev); if (sc->rl_type == RL_8139) { - /* Pretend the internal PHY is only at address 0 */ - if (phy) { - return (0); - } switch (reg) { case MII_BMCR: rl8139_reg = RL_BMCR; @@ -605,10 +573,6 @@ rl_miibus_writereg(device_t dev, int phy, int reg, int data) sc = device_get_softc(dev); if (sc->rl_type == RL_8139) { - /* Pretend the internal PHY is only at address 0 */ - if (phy) { - return (0); - } switch (reg) { case MII_BMCR: rl8139_reg = RL_BMCR; @@ -649,60 +613,85 @@ rl_miibus_writereg(device_t dev, int phy, int reg, int data) static void rl_miibus_statchg(device_t dev) { + struct rl_softc *sc; + struct ifnet *ifp; + struct mii_data *mii; + + sc = device_get_softc(dev); + mii = device_get_softc(sc->rl_miibus); + ifp = sc->rl_ifp; + if (mii == NULL || ifp == NULL || + (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + return; + + sc->rl_flags &= ~RL_FLAG_LINK; + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->rl_flags |= RL_FLAG_LINK; + break; + default: + break; + } + } + /* + * RealTek controllers do not provide any interface to + * Tx/Rx MACs for resolved speed, duplex and flow-control + * parameters. + */ } /* * Program the 64-bit multicast hash filter. */ static void -rl_setmulti(struct rl_softc *sc) +rl_rxfilter(struct rl_softc *sc) { struct ifnet *ifp = sc->rl_ifp; int h = 0; uint32_t hashes[2] = { 0, 0 }; struct ifmultiaddr *ifma; uint32_t rxfilt; - int mcnt = 0; RL_LOCK_ASSERT(sc); rxfilt = CSR_READ_4(sc, RL_RXCFG); - + rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | + RL_RXCFG_RX_MULTI); + /* Always accept frames destined for this host. */ + rxfilt |= RL_RXCFG_RX_INDIV; + /* Set capture broadcast bit to capture broadcast frames. */ + if (ifp->if_flags & IFF_BROADCAST) + rxfilt |= RL_RXCFG_RX_BROAD; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { rxfilt |= RL_RXCFG_RX_MULTI; - CSR_WRITE_4(sc, RL_RXCFG, rxfilt); - CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); - CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); - return; + if (ifp->if_flags & IFF_PROMISC) + rxfilt |= RL_RXCFG_RX_ALLPHYS; + hashes[0] = 0xFFFFFFFF; + hashes[1] = 0xFFFFFFFF; + } else { + /* Now program new ones. */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ether_crc32_be(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + if_maddr_runlock(ifp); + if (hashes[0] != 0 || hashes[1] != 0) + rxfilt |= RL_RXCFG_RX_MULTI; } - /* first, zot all the existing hash bits */ - CSR_WRITE_4(sc, RL_MAR0, 0); - CSR_WRITE_4(sc, RL_MAR4, 0); - - /* now program new ones */ - IF_ADDR_LOCK(ifp); - TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { - if (ifma->ifma_addr->sa_family != AF_LINK) - continue; - h = ether_crc32_be(LLADDR((struct sockaddr_dl *) - ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; - if (h < 32) - hashes[0] |= (1 << h); - else - hashes[1] |= (1 << (h - 32)); - mcnt++; - } - IF_ADDR_UNLOCK(ifp); - - if (mcnt) - rxfilt |= RL_RXCFG_RX_MULTI; - else - rxfilt &= ~RL_RXCFG_RX_MULTI; - - CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4(sc, RL_MAR0, hashes[0]); CSR_WRITE_4(sc, RL_MAR4, hashes[1]); + CSR_WRITE_4(sc, RL_RXCFG, rxfilt); } static void @@ -730,53 +719,49 @@ rl_reset(struct rl_softc *sc) static int rl_probe(device_t dev) { - struct rl_softc *sc; - struct rl_type *t = rl_devs; - int rid; - uint32_t hwrev; - - sc = device_get_softc(dev); - - while (t->rl_name != NULL) { - if ((pci_get_vendor(dev) == t->rl_vid) && - (pci_get_device(dev) == t->rl_did)) { - /* - * Temporarily map the I/O space - * so we can read the chip ID register. - */ - rid = RL_RID; - sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, - RF_ACTIVE); - if (sc->rl_res == NULL) { - device_printf(dev, - "couldn't map ports/memory\n"); - return (ENXIO); - } - sc->rl_btag = rman_get_bustag(sc->rl_res); - sc->rl_bhandle = rman_get_bushandle(sc->rl_res); - - hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; - bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); - - /* Don't attach to 8139C+ or 8169/8110 chips. */ - if (hwrev == RL_HWREV_8139CPLUS || - (hwrev == RL_HWREV_8169 && - t->rl_did == RT_DEVICEID_8169) || - hwrev == RL_HWREV_8169S || - hwrev == RL_HWREV_8110S) { - t++; - continue; - } + struct rl_type *t; + uint16_t devid, revid, vendor; + int i; + + vendor = pci_get_vendor(dev); + devid = pci_get_device(dev); + revid = pci_get_revid(dev); + if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { + if (revid == 0x20) { + /* 8139C+, let re(4) take care of this device. */ + return (ENXIO); + } + } + t = rl_devs; + for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) { + if (vendor == t->rl_vid && devid == t->rl_did) { device_set_desc(dev, t->rl_name); return (BUS_PROBE_DEFAULT); } - t++; } return (ENXIO); } +struct rl_dmamap_arg { + bus_addr_t rl_busaddr; +}; + +static void +rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + struct rl_dmamap_arg *ctx; + + if (error != 0) + return; + + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + ctx = (struct rl_dmamap_arg *)arg; + ctx->rl_busaddr = segs[0].ds_addr; +} + /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. @@ -789,24 +774,56 @@ rl_attach(device_t dev) struct ifnet *ifp; struct rl_softc *sc; struct rl_type *t; - int error = 0, i, rid; - int unit; + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *children; + int error = 0, hwrev, i, phy, pmc, rid; + int prefer_iomap, unit; uint16_t rl_did = 0; + char tn[32]; sc = device_get_softc(dev); unit = device_get_unit(dev); sc->rl_dev = dev; + sc->rl_twister_enable = 0; + snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit); + TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable); + ctx = device_get_sysctl_ctx(sc->rl_dev); + children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD, + &sc->rl_twister_enable, 0, ""); + mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); pci_enable_busmaster(dev); - /* Map control/status registers. */ - rid = RL_RID; - sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); + /* + * Map control/status registers. + * Default to using PIO access for this driver. On SMP systems, + * there appear to be problems with memory mapped mode: it looks + * like doing too many memory mapped access back to back in rapid + * succession can hang the bus. I'm inclined to blame this on + * crummy design/construction on the part of RealTek. Memory + * mapped mode does appear to work on uniprocessor systems though. + */ + prefer_iomap = 1; + snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit); + TUNABLE_INT_FETCH(tn, &prefer_iomap); + if (prefer_iomap) { + sc->rl_res_id = PCIR_BAR(0); + sc->rl_res_type = SYS_RES_IOPORT; + sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, + &sc->rl_res_id, RF_ACTIVE); + } + if (prefer_iomap == 0 || sc->rl_res == NULL) { + sc->rl_res_id = PCIR_BAR(1); + sc->rl_res_type = SYS_RES_MEMORY; + sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, + &sc->rl_res_id, RF_ACTIVE); + } if (sc->rl_res == NULL) { device_printf(dev, "couldn't map ports/memory\n"); error = ENXIO; @@ -878,64 +895,20 @@ rl_attach(device_t dev) } if (sc->rl_type == 0) { - device_printf(dev, "unknown device ID: %x\n", rl_did); - error = ENXIO; - goto fail; + device_printf(dev, "unknown device ID: %x assuming 8139\n", + rl_did); + sc->rl_type = RL_8139; + /* + * Read RL_IDR register to get ethernet address as accessing + * EEPROM may not extract correct address. + */ + for (i = 0; i < ETHER_ADDR_LEN; i++) + eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); } - /* - * Allocate the parent bus DMA tag appropriate for PCI. - */ -#define RL_NSEG_NEW 32 - error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - BUS_DMA_ALLOCNOW, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &sc->rl_parent_tag); - if (error) + if ((error = rl_dma_alloc(sc)) != 0) goto fail; - /* - * Now allocate a tag for the DMA descriptor lists. - * All of our lists are allocated as a contiguous block - * of memory. - */ - error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - BUS_DMA_ALLOCNOW, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &sc->rl_tag); - if (error) - goto fail; - - /* - * Now allocate a chunk of DMA-able memory based on the - * tag we just created. - */ - error = bus_dmamem_alloc(sc->rl_tag, - (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, - &sc->rl_cdata.rl_rx_dmamap); - if (error) { - device_printf(dev, "no memory for list buffers!\n"); - bus_dma_tag_destroy(sc->rl_tag); - sc->rl_tag = NULL; - goto fail; - } - - /* Leave a few bytes before the start of the RX ring buffer. */ - sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; - sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); - ifp = sc->rl_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "can not if_alloc()\n"); @@ -943,11 +916,16 @@ rl_attach(device_t dev) goto fail; } +#define RL_PHYAD_INTERNAL 0 + /* Do MII setup */ - if (mii_phy_probe(dev, &sc->rl_miibus, - rl_ifmedia_upd, rl_ifmedia_sts)) { - device_printf(dev, "MII without any phy!\n"); - error = ENXIO; + phy = MII_PHY_ANY; + if (sc->rl_type == RL_8139) + phy = RL_PHYAD_INTERNAL; + error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd, + rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); + if (error != 0) { + device_printf(dev, "attaching PHYs failed\n"); goto fail; } @@ -959,12 +937,31 @@ rl_attach(device_t dev) ifp->if_start = rl_start; ifp->if_init = rl_init; ifp->if_capabilities = IFCAP_VLAN_MTU; + /* Check WOL for RTL8139B or newer controllers. */ + if (sc->rl_type == RL_8139 && + pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { + hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; + switch (hwrev) { + case RL_HWREV_8139B: + case RL_HWREV_8130: + case RL_HWREV_8139C: + case RL_HWREV_8139D: + case RL_HWREV_8101: + case RL_HWREV_8100: + ifp->if_capabilities |= IFCAP_WOL; + /* Disable WOL. */ + rl_clrwol(sc); + break; + default: + break; + } + } ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; #endif - IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); - ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); + ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); /* @@ -1029,25 +1026,161 @@ rl_detach(device_t dev) if (sc->rl_irq[0]) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); if (sc->rl_res) - bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); + bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, + sc->rl_res); if (ifp) if_free(ifp); - if (sc->rl_tag) { - bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); - bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, - sc->rl_cdata.rl_rx_dmamap); - bus_dma_tag_destroy(sc->rl_tag); - } - if (sc->rl_parent_tag) - bus_dma_tag_destroy(sc->rl_parent_tag); + rl_dma_free(sc); mtx_destroy(&sc->rl_mtx); return (0); } +static int +rl_dma_alloc(struct rl_softc *sc) +{ + struct rl_dmamap_arg ctx; + int error, i; + + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->rl_parent_tag); + if (error) { + device_printf(sc->rl_dev, + "failed to create parent DMA tag.\n"); + goto fail; + } + /* Create DMA tag for Rx memory block. */ + error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ + RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ + RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->rl_cdata.rl_rx_tag); + if (error) { + device_printf(sc->rl_dev, + "failed to create Rx memory block DMA tag.\n"); + goto fail; + } + /* Create DMA tag for Tx buffer. */ + error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ + RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES, 1, /* maxsize, nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->rl_cdata.rl_tx_tag); + if (error) { + device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); + goto fail; + } + + /* + * Allocate DMA'able memory and load DMA map for Rx memory block. + */ + error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, + (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | + BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); + if (error != 0) { + device_printf(sc->rl_dev, + "failed to allocate Rx DMA memory block.\n"); + goto fail; + } + ctx.rl_busaddr = 0; + error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, + sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, + RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, + BUS_DMA_NOWAIT); + if (error != 0 || ctx.rl_busaddr == 0) { + device_printf(sc->rl_dev, + "could not load Rx DMA memory block.\n"); + goto fail; + } + sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; + + /* Create DMA maps for Tx buffers. */ + for (i = 0; i < RL_TX_LIST_CNT; i++) { + sc->rl_cdata.rl_tx_chain[i] = NULL; + sc->rl_cdata.rl_tx_dmamap[i] = NULL; + error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, + &sc->rl_cdata.rl_tx_dmamap[i]); + if (error != 0) { + device_printf(sc->rl_dev, + "could not create Tx dmamap.\n"); + goto fail; + } + } + + /* Leave a few bytes before the start of the RX ring buffer. */ + sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; + sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; + +fail: + return (error); +} + +static void +rl_dma_free(struct rl_softc *sc) +{ + int i; + + /* Rx memory block. */ + if (sc->rl_cdata.rl_rx_tag != NULL) { + if (sc->rl_cdata.rl_rx_dmamap != NULL) + bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, + sc->rl_cdata.rl_rx_dmamap); + if (sc->rl_cdata.rl_rx_dmamap != NULL && + sc->rl_cdata.rl_rx_buf_ptr != NULL) + bus_dmamem_free(sc->rl_cdata.rl_rx_tag, + sc->rl_cdata.rl_rx_buf_ptr, + sc->rl_cdata.rl_rx_dmamap); + sc->rl_cdata.rl_rx_buf_ptr = NULL; + sc->rl_cdata.rl_rx_buf = NULL; + sc->rl_cdata.rl_rx_dmamap = NULL; + bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); + sc->rl_cdata.rl_tx_tag = NULL; + } + + /* Tx buffers. */ + if (sc->rl_cdata.rl_tx_tag != NULL) { + for (i = 0; i < RL_TX_LIST_CNT; i++) { + if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { + bus_dmamap_destroy( + sc->rl_cdata.rl_tx_tag, + sc->rl_cdata.rl_tx_dmamap[i]); + sc->rl_cdata.rl_tx_dmamap[i] = NULL; + } + } + bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); + sc->rl_cdata.rl_tx_tag = NULL; + } + + if (sc->rl_parent_tag != NULL) { + bus_dma_tag_destroy(sc->rl_parent_tag); + sc->rl_parent_tag = NULL; + } +} + /* * Initialize the transmit descriptors. */ @@ -1072,6 +1205,20 @@ rl_list_tx_init(struct rl_softc *sc) return (0); } +static int +rl_list_rx_init(struct rl_softc *sc) +{ + + RL_LOCK_ASSERT(sc); + + bzero(sc->rl_cdata.rl_rx_buf_ptr, + RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); + bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (0); +} + /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. @@ -1093,7 +1240,7 @@ rl_list_tx_init(struct rl_softc *sc) * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) * as the offset argument to m_devget(). */ -static void +static int rl_rxeof(struct rl_softc *sc) { struct mbuf *m; @@ -1101,6 +1248,7 @@ rl_rxeof(struct rl_softc *sc) uint8_t *rxbufpos; int total_len = 0; int wrap = 0; + int rx_npkts = 0; uint32_t rxstat; uint16_t cur_rx; uint16_t limit; @@ -1108,8 +1256,8 @@ rl_rxeof(struct rl_softc *sc) RL_LOCK_ASSERT(sc); - bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, - BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; @@ -1140,17 +1288,20 @@ rl_rxeof(struct rl_softc *sc) * datasheet makes absolutely no mention of this and * RealTek should be shot for this. */ - if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) + total_len = rxstat >> 16; + if (total_len == RL_RXSTAT_UNFINISHED) break; - if (!(rxstat & RL_RXSTAT_RXOK)) { + if (!(rxstat & RL_RXSTAT_RXOK) || + total_len < ETHER_MIN_LEN || + total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { ifp->if_ierrors++; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; rl_init_locked(sc); - return; + return (rx_npkts); } /* No errors; receive the packet. */ - total_len = rxstat >> 16; rx_bytes += total_len + 4; /* @@ -1178,18 +1329,13 @@ rl_rxeof(struct rl_softc *sc) if (total_len > wrap) { m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, NULL); - if (m == NULL) { - ifp->if_ierrors++; - } else { + if (m != NULL) m_copyback(m, wrap, total_len - wrap, sc->rl_cdata.rl_rx_buf); - } cur_rx = (total_len - wrap + ETHER_CRC_LEN); } else { m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, NULL); - if (m == NULL) - ifp->if_ierrors++; cur_rx += total_len + 4 + ETHER_CRC_LEN; } @@ -1197,14 +1343,20 @@ rl_rxeof(struct rl_softc *sc) cur_rx = (cur_rx + 3) & ~3; CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); - if (m == NULL) + if (m == NULL) { + ifp->if_iqdrops++; continue; + } ifp->if_ipackets++; RL_UNLOCK(sc); (*ifp->if_input)(ifp, m); RL_LOCK(sc); + rx_npkts++; } + + /* No need to sync Rx memory block as we didn't modify it. */ + return (rx_npkts); } /* @@ -1233,8 +1385,9 @@ rl_txeof(struct rl_softc *sc) ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; - bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); - bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); + bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); m_freem(RL_LAST_TXMBUF(sc)); RL_LAST_TXMBUF(sc) = NULL; /* @@ -1255,7 +1408,7 @@ rl_txeof(struct rl_softc *sc) CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); oldthresh = sc->rl_txthresh; /* error recovery */ - rl_reset(sc); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; rl_init_locked(sc); /* restore original threshold */ sc->rl_txthresh = oldthresh; @@ -1267,8 +1420,105 @@ rl_txeof(struct rl_softc *sc) if (RL_LAST_TXMBUF(sc) == NULL) sc->rl_watchdog_timer = 0; - else if (sc->rl_watchdog_timer == 0) - sc->rl_watchdog_timer = 5; +} + +static void +rl_twister_update(struct rl_softc *sc) +{ + uint16_t linktest; + /* + * Table provided by RealTek (Kinston ) for + * Linux driver. Values undocumented otherwise. + */ + static const uint32_t param[4][4] = { + {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, + {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, + {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, + {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} + }; + + /* + * Tune the so-called twister registers of the RTL8139. These + * are used to compensate for impedance mismatches. The + * method for tuning these registers is undocumented and the + * following procedure is collected from public sources. + */ + switch (sc->rl_twister) + { + case CHK_LINK: + /* + * If we have a sufficient link, then we can proceed in + * the state machine to the next stage. If not, then + * disable further tuning after writing sane defaults. + */ + if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { + CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); + sc->rl_twister = FIND_ROW; + } else { + CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); + CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); + CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); + CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); + sc->rl_twister = DONE; + } + break; + case FIND_ROW: + /* + * Read how long it took to see the echo to find the tuning + * row to use. + */ + linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; + if (linktest == RL_CSCFG_ROW3) + sc->rl_twist_row = 3; + else if (linktest == RL_CSCFG_ROW2) + sc->rl_twist_row = 2; + else if (linktest == RL_CSCFG_ROW1) + sc->rl_twist_row = 1; + else + sc->rl_twist_row = 0; + sc->rl_twist_col = 0; + sc->rl_twister = SET_PARAM; + break; + case SET_PARAM: + if (sc->rl_twist_col == 0) + CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); + CSR_WRITE_4(sc, RL_PARA7C, + param[sc->rl_twist_row][sc->rl_twist_col]); + if (++sc->rl_twist_col == 4) { + if (sc->rl_twist_row == 3) + sc->rl_twister = RECHK_LONG; + else + sc->rl_twister = DONE; + } + break; + case RECHK_LONG: + /* + * For long cables, we have to double check to make sure we + * don't mistune. + */ + linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; + if (linktest == RL_CSCFG_ROW3) + sc->rl_twister = DONE; + else { + CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE); + sc->rl_twister = RETUNE; + } + break; + case RETUNE: + /* Retune for a shorter cable (try column 2) */ + CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); + CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); + CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); + CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); + sc->rl_twist_row--; + sc->rl_twist_col = 0; + sc->rl_twister = SET_PARAM; + break; + + case DONE: + break; + } + } static void @@ -1276,37 +1526,65 @@ rl_tick(void *xsc) { struct rl_softc *sc = xsc; struct mii_data *mii; + int ticks; RL_LOCK_ASSERT(sc); + /* + * If we're doing the twister cable calibration, then we need to defer + * watchdog timeouts. This is a no-op in normal operations, but + * can falsely trigger when the cable calibration takes a while and + * there was traffic ready to go when rl was started. + * + * We don't defer mii_tick since that updates the mii status, which + * helps the twister process, at least according to similar patches + * for the Linux driver I found online while doing the fixes. Worst + * case is a few extra mii reads during calibration. + */ mii = device_get_softc(sc->rl_miibus); mii_tick(mii); + if ((sc->rl_flags & RL_FLAG_LINK) == 0) + rl_miibus_statchg(sc->rl_dev); + if (sc->rl_twister_enable) { + if (sc->rl_twister == DONE) + rl_watchdog(sc); + else + rl_twister_update(sc); + if (sc->rl_twister == DONE) + ticks = hz; + else + ticks = hz / 10; + } else { + rl_watchdog(sc); + ticks = hz; + } - rl_watchdog(sc); - - callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); + callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); } #ifdef DEVICE_POLLING -static void +static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct rl_softc *sc = ifp->if_softc; + int rx_npkts = 0; RL_LOCK(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) - rl_poll_locked(ifp, cmd, count); + rx_npkts = rl_poll_locked(ifp, cmd, count); RL_UNLOCK(sc); + return (rx_npkts); } -static void +static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct rl_softc *sc = ifp->if_softc; + int rx_npkts; RL_LOCK_ASSERT(sc); sc->rxcycles = count; - rl_rxeof(sc); + rx_npkts = rl_rxeof(sc); rl_txeof(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) @@ -1318,17 +1596,18 @@ rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) /* We should also check the status register. */ status = CSR_READ_2(sc, RL_ISR); if (status == 0xffff) - return; + return (rx_npkts); if (status != 0) CSR_WRITE_2(sc, RL_ISR, status); /* XXX We should check behaviour on receiver stalls. */ if (status & RL_ISR_SYSTEM_ERR) { - rl_reset(sc); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; rl_init_locked(sc); } } + return (rx_npkts); } #endif /* DEVICE_POLLING */ @@ -1338,6 +1617,7 @@ rl_intr(void *arg) struct rl_softc *sc = arg; struct ifnet *ifp = sc->rl_ifp; uint16_t status; + int count; RL_LOCK(sc); @@ -1349,30 +1629,41 @@ rl_intr(void *arg) goto done_locked; #endif - for (;;) { + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + goto done_locked2; + status = CSR_READ_2(sc, RL_ISR); + if (status == 0xffff || (status & RL_INTRS) == 0) + goto done_locked; + /* + * Ours, disable further interrupts. + */ + CSR_WRITE_2(sc, RL_IMR, 0); + for (count = 16; count > 0; count--) { + CSR_WRITE_2(sc, RL_ISR, status); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR)) + rl_rxeof(sc); + if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR)) + rl_txeof(sc); + if (status & RL_ISR_SYSTEM_ERR) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + rl_init_locked(sc); + RL_UNLOCK(sc); + return; + } + } status = CSR_READ_2(sc, RL_ISR); /* If the card has gone away, the read returns 0xffff. */ - if (status == 0xffff) + if (status == 0xffff || (status & RL_INTRS) == 0) break; - if (status != 0) - CSR_WRITE_2(sc, RL_ISR, status); - if ((status & RL_INTRS) == 0) - break; - if (status & RL_ISR_RX_OK) - rl_rxeof(sc); - if (status & RL_ISR_RX_ERR) - rl_rxeof(sc); - if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) - rl_txeof(sc); - if (status & RL_ISR_SYSTEM_ERR) { - rl_reset(sc); - rl_init_locked(sc); - } } if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) rl_start_locked(ifp); +done_locked2: + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + CSR_WRITE_2(sc, RL_IMR, RL_INTRS); done_locked: RL_UNLOCK(sc); } @@ -1382,41 +1673,64 @@ done_locked: * pointers to the fragment pointers. */ static int -rl_encap(struct rl_softc *sc, struct mbuf *m_head) +rl_encap(struct rl_softc *sc, struct mbuf **m_head) { - struct mbuf *m_new = NULL; + struct mbuf *m; + bus_dma_segment_t txsegs[1]; + int error, nsegs, padlen; RL_LOCK_ASSERT(sc); + m = *m_head; + padlen = 0; + /* + * Hardware doesn't auto-pad, so we have to make sure + * pad short frames out to the minimum frame length. + */ + if (m->m_pkthdr.len < RL_MIN_FRAMELEN) + padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; /* * The RealTek is brain damaged and wants longword-aligned * TX buffers, plus we can only have one fragment buffer * per packet. We have to copy pretty much all the time. */ - m_new = m_defrag(m_head, M_DONTWAIT); - - if (m_new == NULL) { - m_freem(m_head); - return (1); + if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || + (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { + m = m_defrag(*m_head, M_DONTWAIT); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOMEM); + } } - m_head = m_new; + *m_head = m; - /* Pad frames to at least 60 bytes. */ - if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { + if (padlen > 0) { /* - * Make security concious people happy: zero out the + * Make security-conscious people happy: zero out the * bytes in the pad area, since we don't know what * this mbuf cluster buffer's previous user might * have left in it. */ - bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, - RL_MIN_FRAMELEN - m_head->m_pkthdr.len); - m_head->m_pkthdr.len += - (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); - m_head->m_len = m_head->m_pkthdr.len; + bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); + m->m_pkthdr.len += padlen; + m->m_len = m->m_pkthdr.len; } - RL_CUR_TXMBUF(sc) = m_head; + error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, + RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); + if (error != 0) + return (error); + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + RL_CUR_TXMBUF(sc) = m; + bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), + BUS_DMASYNC_PREWRITE); + CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); return (0); } @@ -1442,6 +1756,10 @@ rl_start_locked(struct ifnet *ifp) RL_LOCK_ASSERT(sc); + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) + return; + while (RL_CUR_TXMBUF(sc) == NULL) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); @@ -1449,19 +1767,18 @@ rl_start_locked(struct ifnet *ifp) if (m_head == NULL) break; - if (rl_encap(sc, m_head)) + if (rl_encap(sc, &m_head)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; + } /* Pass a copy of this mbuf chain to the bpf subsystem. */ BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); /* Transmit the frame. */ - bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); - bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), - mtod(RL_CUR_TXMBUF(sc), void *), - RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); - bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), - BUS_DMASYNC_PREREAD); CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), RL_TXTHRESH(sc->rl_txthresh) | RL_CUR_TXMBUF(sc)->m_pkthdr.len); @@ -1496,18 +1813,31 @@ rl_init_locked(struct rl_softc *sc) { struct ifnet *ifp = sc->rl_ifp; struct mii_data *mii; - uint32_t rxcfg = 0; uint32_t eaddr[2]; RL_LOCK_ASSERT(sc); mii = device_get_softc(sc->rl_miibus); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + return; + /* * Cancel pending I/O and free all RX/TX buffers. */ rl_stop(sc); + rl_reset(sc); + if (sc->rl_twister_enable) { + /* + * Reset twister register tuning state. The twister + * registers and their tuning are undocumented, but + * are necessary to cope with bad links. rl_twister = + * DONE here will disable this entirely. + */ + sc->rl_twister = CHK_LINK; + } + /* * Init our MAC address. Even though the chipset * documentation doesn't mention it, we need to enter "Config @@ -1520,14 +1850,13 @@ rl_init_locked(struct rl_softc *sc) CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); - /* Init the RX buffer pointer register. */ - bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, - sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); - bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, - BUS_DMASYNC_PREWRITE); - + /* Init the RX memory block pointer register. */ + CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + + RL_RX_8139_BUF_RESERVE); /* Init TX descriptors. */ rl_list_tx_init(sc); + /* Init Rx memory block. */ + rl_list_rx_init(sc); /* * Enable transmit and receive. @@ -1540,30 +1869,8 @@ rl_init_locked(struct rl_softc *sc) CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); - /* Set the individual bit to receive frames for this host only. */ - rxcfg = CSR_READ_4(sc, RL_RXCFG); - rxcfg |= RL_RXCFG_RX_INDIV; - - /* If we want promiscuous mode, set the allframes bit. */ - if (ifp->if_flags & IFF_PROMISC) { - rxcfg |= RL_RXCFG_RX_ALLPHYS; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } else { - rxcfg &= ~RL_RXCFG_RX_ALLPHYS; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } - - /* Set capture broadcast bit to capture broadcast frames. */ - if (ifp->if_flags & IFF_BROADCAST) { - rxcfg |= RL_RXCFG_RX_BROAD; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } else { - rxcfg &= ~RL_RXCFG_RX_BROAD; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } - - /* Program the multicast filter, if necessary. */ - rl_setmulti(sc); + /* Set RX filter. */ + rl_rxfilter(sc); #ifdef DEVICE_POLLING /* Disable interrupts if we are polling. */ @@ -1583,6 +1890,7 @@ rl_init_locked(struct rl_softc *sc) /* Enable receiver and transmitter. */ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); + sc->rl_flags &= ~RL_FLAG_LINK; mii_mediachg(mii); CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); @@ -1635,26 +1943,28 @@ rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) struct ifreq *ifr = (struct ifreq *)data; struct mii_data *mii; struct rl_softc *sc = ifp->if_softc; - int error = 0; + int error = 0, mask; switch (command) { case SIOCSIFFLAGS: RL_LOCK(sc); if (ifp->if_flags & IFF_UP) { - rl_init_locked(sc); - } else { - if (ifp->if_drv_flags & IFF_DRV_RUNNING) - rl_stop(sc); - } + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + ((ifp->if_flags ^ sc->rl_if_flags) & + (IFF_PROMISC | IFF_ALLMULTI))) + rl_rxfilter(sc); + else + rl_init_locked(sc); + } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) + rl_stop(sc); + sc->rl_if_flags = ifp->if_flags; RL_UNLOCK(sc); - error = 0; break; case SIOCADDMULTI: case SIOCDELMULTI: RL_LOCK(sc); - rl_setmulti(sc); + rl_rxfilter(sc); RL_UNLOCK(sc); - error = 0; break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: @@ -1662,6 +1972,7 @@ rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; #ifdef DEVICE_POLLING if (ifr->ifr_reqcap & IFCAP_POLLING && !(ifp->if_capenable & IFCAP_POLLING)) { @@ -1687,6 +1998,15 @@ rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) return (error); } #endif /* DEVICE_POLLING */ + if ((mask & IFCAP_WOL) != 0 && + (ifp->if_capabilities & IFCAP_WOL) != 0) { + if ((mask & IFCAP_WOL_UCAST) != 0) + ifp->if_capenable ^= IFCAP_WOL_UCAST; + if ((mask & IFCAP_WOL_MCAST) != 0) + ifp->if_capenable ^= IFCAP_WOL_MCAST; + if ((mask & IFCAP_WOL_MAGIC) != 0) + ifp->if_capenable ^= IFCAP_WOL_MAGIC; + } break; default: error = ether_ioctl(ifp, command, data); @@ -1710,6 +2030,7 @@ rl_watchdog(struct rl_softc *sc) rl_txeof(sc); rl_rxeof(sc); + sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; rl_init_locked(sc); } @@ -1728,22 +2049,33 @@ rl_stop(struct rl_softc *sc) sc->rl_watchdog_timer = 0; callout_stop(&sc->rl_stat_callout); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + sc->rl_flags &= ~RL_FLAG_LINK; CSR_WRITE_1(sc, RL_COMMAND, 0x00); CSR_WRITE_2(sc, RL_IMR, 0x0000); - bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); + for (i = 0; i < RL_TIMEOUT; i++) { + DELAY(10); + if ((CSR_READ_1(sc, RL_COMMAND) & + (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) + break; + } + if (i == RL_TIMEOUT) + device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); /* * Free the TX list buffers. */ for (i = 0; i < RL_TX_LIST_CNT; i++) { if (sc->rl_cdata.rl_tx_chain[i] != NULL) { - bus_dmamap_unload(sc->rl_tag, - sc->rl_cdata.rl_tx_dmamap[i]); - bus_dmamap_destroy(sc->rl_tag, - sc->rl_cdata.rl_tx_dmamap[i]); - m_freem(sc->rl_cdata.rl_tx_chain[i]); - sc->rl_cdata.rl_tx_chain[i] = NULL; + if (sc->rl_cdata.rl_tx_chain[i] != NULL) { + bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, + sc->rl_cdata.rl_tx_dmamap[i], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, + sc->rl_cdata.rl_tx_dmamap[i]); + m_freem(sc->rl_cdata.rl_tx_chain[i]); + sc->rl_cdata.rl_tx_chain[i] = NULL; + } CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); } @@ -1764,6 +2096,7 @@ rl_suspend(device_t dev) RL_LOCK(sc); rl_stop(sc); + rl_setwol(sc); sc->suspended = 1; RL_UNLOCK(sc); @@ -1780,12 +2113,31 @@ rl_resume(device_t dev) { struct rl_softc *sc; struct ifnet *ifp; + int pmc; + uint16_t pmstat; sc = device_get_softc(dev); ifp = sc->rl_ifp; RL_LOCK(sc); + if ((ifp->if_capabilities & IFCAP_WOL) != 0 && + pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { + /* Disable PME and clear PME status. */ + pmstat = pci_read_config(sc->rl_dev, + pmc + PCIR_POWER_STATUS, 2); + if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { + pmstat &= ~PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->rl_dev, + pmc + PCIR_POWER_STATUS, pmstat, 2); + } + /* + * Clear WOL matching such that normal Rx filtering + * wouldn't interfere with WOL patterns. + */ + rl_clrwol(sc); + } + /* reinitialize interface if necessary */ if (ifp->if_flags & IFF_UP) rl_init_locked(sc); @@ -1801,7 +2153,7 @@ rl_resume(device_t dev) * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ -static void +static int rl_shutdown(device_t dev) { struct rl_softc *sc; @@ -1810,5 +2162,93 @@ rl_shutdown(device_t dev) RL_LOCK(sc); rl_stop(sc); + /* + * Mark interface as down since otherwise we will panic if + * interrupt comes in later on, which can happen in some + * cases. + */ + sc->rl_ifp->if_flags &= ~IFF_UP; + rl_setwol(sc); RL_UNLOCK(sc); + + return (0); +} + +static void +rl_setwol(struct rl_softc *sc) +{ + struct ifnet *ifp; + int pmc; + uint16_t pmstat; + uint8_t v; + + RL_LOCK_ASSERT(sc); + + ifp = sc->rl_ifp; + if ((ifp->if_capabilities & IFCAP_WOL) == 0) + return; + if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) + return; + + /* Enable config register write. */ + CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); + + /* Enable PME. */ + v = CSR_READ_1(sc, RL_CFG1); + v &= ~RL_CFG1_PME; + if ((ifp->if_capenable & IFCAP_WOL) != 0) + v |= RL_CFG1_PME; + CSR_WRITE_1(sc, RL_CFG1, v); + + v = CSR_READ_1(sc, RL_CFG3); + v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) + v |= RL_CFG3_WOL_MAGIC; + CSR_WRITE_1(sc, RL_CFG3, v); + + /* Config register write done. */ + CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); + + v = CSR_READ_1(sc, RL_CFG5); + v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); + v &= ~RL_CFG5_WOL_LANWAKE; + if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) + v |= RL_CFG5_WOL_UCAST; + if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) + v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; + if ((ifp->if_capenable & IFCAP_WOL) != 0) + v |= RL_CFG5_WOL_LANWAKE; + CSR_WRITE_1(sc, RL_CFG5, v); + /* Request PME if WOL is requested. */ + pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); + pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); + if ((ifp->if_capenable & IFCAP_WOL) != 0) + pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); +} + +static void +rl_clrwol(struct rl_softc *sc) +{ + struct ifnet *ifp; + uint8_t v; + + ifp = sc->rl_ifp; + if ((ifp->if_capabilities & IFCAP_WOL) == 0) + return; + + /* Enable config register write. */ + CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); + + v = CSR_READ_1(sc, RL_CFG3); + v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); + CSR_WRITE_1(sc, RL_CFG3, v); + + /* Config register write done. */ + CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); + + v = CSR_READ_1(sc, RL_CFG5); + v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); + v &= ~RL_CFG5_WOL_LANWAKE; + CSR_WRITE_1(sc, RL_CFG5, v); } diff --git a/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rlreg.h b/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rlreg.h index ea608090eb..de5aeb5261 100644 --- a/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rlreg.h +++ b/src/add-ons/kernel/drivers/network/rtl8139/pci/if_rlreg.h @@ -29,198 +29,218 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.67.2.2 2007/12/15 02:57:18 yongari Exp $ + * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.97.2.8.2.1 2010/12/21 17:09:25 kensmith Exp $ */ /* * RealTek 8129/8139 register offsets */ #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ -#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ -#define RL_IDR2 0x0002 -#define RL_IDR3 0x0003 -#define RL_IDR4 0x0004 -#define RL_IDR5 0x0005 +#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ +#define RL_IDR2 0x0002 +#define RL_IDR3 0x0003 +#define RL_IDR4 0x0004 +#define RL_IDR5 0x0005 /* 0006-0007 reserved */ -#define RL_MAR0 0x0008 /* Multicast hash table */ -#define RL_MAR1 0x0009 -#define RL_MAR2 0x000A -#define RL_MAR3 0x000B -#define RL_MAR4 0x000C -#define RL_MAR5 0x000D -#define RL_MAR6 0x000E -#define RL_MAR7 0x000F +#define RL_MAR0 0x0008 /* Multicast hash table */ +#define RL_MAR1 0x0009 +#define RL_MAR2 0x000A +#define RL_MAR3 0x000B +#define RL_MAR4 0x000C +#define RL_MAR5 0x000D +#define RL_MAR6 0x000E +#define RL_MAR7 0x000F -#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ -#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ -#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ -#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ +#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ +#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ +#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ +#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ -#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ -#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ -#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ -#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ +#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ +#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ +#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ +#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ -#define RL_RXADDR 0x0030 /* RX ring start address */ -#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ -#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ -#define RL_COMMAND 0x0037 /* command register */ -#define RL_CURRXADDR 0x0038 /* current address of packet read */ -#define RL_CURRXBUF 0x003A /* current RX buffer address */ -#define RL_IMR 0x003C /* interrupt mask register */ -#define RL_ISR 0x003E /* interrupt status register */ -#define RL_TXCFG 0x0040 /* transmit config */ -#define RL_RXCFG 0x0044 /* receive config */ -#define RL_TIMERCNT 0x0048 /* timer count register */ -#define RL_MISSEDPKT 0x004C /* missed packet counter */ -#define RL_EECMD 0x0050 /* EEPROM command register */ -#define RL_CFG0 0x0051 /* config register #0 */ -#define RL_CFG1 0x0052 /* config register #1 */ - /* 0053-0057 reserved */ -#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ +#define RL_RXADDR 0x0030 /* RX ring start address */ +#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ +#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ +#define RL_COMMAND 0x0037 /* command register */ +#define RL_CURRXADDR 0x0038 /* current address of packet read */ +#define RL_CURRXBUF 0x003A /* current RX buffer address */ +#define RL_IMR 0x003C /* interrupt mask register */ +#define RL_ISR 0x003E /* interrupt status register */ +#define RL_TXCFG 0x0040 /* transmit config */ +#define RL_RXCFG 0x0044 /* receive config */ +#define RL_TIMERCNT 0x0048 /* timer count register */ +#define RL_MISSEDPKT 0x004C /* missed packet counter */ +#define RL_EECMD 0x0050 /* EEPROM command register */ +#define RL_CFG0 0x0051 /* config register #0 */ +#define RL_CFG1 0x0052 /* config register #1 */ +#define RL_CFG2 0x0053 /* config register #2 */ +#define RL_CFG3 0x0054 /* config register #3 */ +#define RL_CFG4 0x0055 /* config register #4 */ +#define RL_CFG5 0x0056 /* config register #5 */ + /* 0057 reserved */ +#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ /* 0059-005A reserved */ -#define RL_MII 0x005A /* 8129 chip only */ -#define RL_HALTCLK 0x005B -#define RL_MULTIINTR 0x005C /* multiple interrupt */ -#define RL_PCIREV 0x005E /* PCI revision value */ +#define RL_MII 0x005A /* 8129 chip only */ +#define RL_HALTCLK 0x005B +#define RL_MULTIINTR 0x005C /* multiple interrupt */ +#define RL_PCIREV 0x005E /* PCI revision value */ /* 005F reserved */ -#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ +#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ /* Direct PHY access registers only available on 8139 */ -#define RL_BMCR 0x0062 /* PHY basic mode control */ -#define RL_BMSR 0x0064 /* PHY basic mode status */ -#define RL_ANAR 0x0066 /* PHY autoneg advert */ -#define RL_LPAR 0x0068 /* PHY link partner ability */ -#define RL_ANER 0x006A /* PHY autoneg expansion */ +#define RL_BMCR 0x0062 /* PHY basic mode control */ +#define RL_BMSR 0x0064 /* PHY basic mode status */ +#define RL_ANAR 0x0066 /* PHY autoneg advert */ +#define RL_LPAR 0x0068 /* PHY link partner ability */ +#define RL_ANER 0x006A /* PHY autoneg expansion */ -#define RL_DISCCNT 0x006C /* disconnect counter */ -#define RL_FALSECAR 0x006E /* false carrier counter */ -#define RL_NWAYTST 0x0070 /* NWAY test register */ -#define RL_RX_ER 0x0072 /* RX_ER counter */ -#define RL_CSCFG 0x0074 /* CS configuration register */ +#define RL_DISCCNT 0x006C /* disconnect counter */ +#define RL_FALSECAR 0x006E /* false carrier counter */ +#define RL_NWAYTST 0x0070 /* NWAY test register */ +#define RL_RX_ER 0x0072 /* RX_ER counter */ +#define RL_CSCFG 0x0074 /* CS configuration register */ /* * When operating in special C+ mode, some of the registers in an * 8139C+ chip have different definitions. These are also used for * the 8169 gigE chip. */ -#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ -#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ -#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ -#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ -#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ -#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ -#define RL_CFG2 0x0053 -#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ -#define RL_TXSTART 0x00D9 /* 8 bits */ -#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ -#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ -#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ -#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ +#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ +#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ +#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ +#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ +#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ +#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ +#define RL_CFG2 0x0053 +#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ +#define RL_TXSTART 0x00D9 /* 8 bits */ +#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ +#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ +#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ +#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ /* * Registers specific to the 8169 gigE chip */ -#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ -#define RL_PHYAR 0x0060 -#define RL_TBICSR 0x0064 -#define RL_TBI_ANAR 0x0068 -#define RL_TBI_LPAR 0x006A -#define RL_GMEDIASTAT 0x006C /* 8 bits */ -#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ -#define RL_GTXSTART 0x0038 /* 16 bits */ +#define RL_GTXSTART 0x0038 /* 8 bits */ +#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ +#define RL_PHYAR 0x0060 +#define RL_TBICSR 0x0064 +#define RL_TBI_ANAR 0x0068 +#define RL_TBI_LPAR 0x006A +#define RL_GMEDIASTAT 0x006C /* 8 bits */ +#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ +#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ +#define RL_PMCH 0x006F /* 8 bits */ +#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ +#define RL_INTRMOD 0x00E2 /* 16 bits */ /* * TX config register bits */ -#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ -#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ -#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ -#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ -#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ -#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ -#define RL_TXCFG_HWREV 0x7CC00000 +#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ +#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ +#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ +#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ +#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ +#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ +#define RL_TXCFG_HWREV 0x7CC00000 -#define RL_LOOPTEST_OFF 0x00000000 -#define RL_LOOPTEST_ON 0x00020000 -#define RL_LOOPTEST_ON_CPLUS 0x00060000 +#define RL_LOOPTEST_OFF 0x00000000 +#define RL_LOOPTEST_ON 0x00020000 +#define RL_LOOPTEST_ON_CPLUS 0x00060000 /* Known revision codes. */ -#define RL_HWREV_8169 0x00000000 -#define RL_HWREV_8110S 0x00800000 -#define RL_HWREV_8169S 0x04000000 -#define RL_HWREV_8169_8110SB 0x10000000 -#define RL_HWREV_8169_8110SC 0x18000000 -#define RL_HWREV_8168_SPIN1 0x30000000 -#define RL_HWREV_8100E 0x30800000 -#define RL_HWREV_8101E 0x34000000 -#define RL_HWREV_8168_SPIN2 0x38000000 -#define RL_HWREV_8168_SPIN3 0x38400000 -#define RL_HWREV_8139 0x60000000 -#define RL_HWREV_8139A 0x70000000 -#define RL_HWREV_8139AG 0x70800000 -#define RL_HWREV_8139B 0x78000000 -#define RL_HWREV_8130 0x7C000000 -#define RL_HWREV_8139C 0x74000000 -#define RL_HWREV_8139D 0x74400000 -#define RL_HWREV_8139CPLUS 0x74800000 -#define RL_HWREV_8101 0x74c00000 -#define RL_HWREV_8100 0x78800000 +#define RL_HWREV_8169 0x00000000 +#define RL_HWREV_8169S 0x00800000 +#define RL_HWREV_8110S 0x04000000 +#define RL_HWREV_8169_8110SB 0x10000000 +#define RL_HWREV_8169_8110SC 0x18000000 +#define RL_HWREV_8102EL 0x24800000 +#define RL_HWREV_8102EL_SPIN1 0x24C00000 +#define RL_HWREV_8168D 0x28000000 +#define RL_HWREV_8168DP 0x28800000 +#define RL_HWREV_8168E 0x2C000000 +#define RL_HWREV_8168_SPIN1 0x30000000 +#define RL_HWREV_8100E 0x30800000 +#define RL_HWREV_8101E 0x34000000 +#define RL_HWREV_8102E 0x34800000 +#define RL_HWREV_8103E 0x34C00000 +#define RL_HWREV_8168_SPIN2 0x38000000 +#define RL_HWREV_8168_SPIN3 0x38400000 +#define RL_HWREV_8168C 0x3C000000 +#define RL_HWREV_8168C_SPIN2 0x3C400000 +#define RL_HWREV_8168CP 0x3C800000 +#define RL_HWREV_8139 0x60000000 +#define RL_HWREV_8139A 0x70000000 +#define RL_HWREV_8139AG 0x70800000 +#define RL_HWREV_8139B 0x78000000 +#define RL_HWREV_8130 0x7C000000 +#define RL_HWREV_8139C 0x74000000 +#define RL_HWREV_8139D 0x74400000 +#define RL_HWREV_8139CPLUS 0x74800000 +#define RL_HWREV_8101 0x74C00000 +#define RL_HWREV_8100 0x78800000 +#define RL_HWREV_8169_8110SBL 0x7CC00000 +#define RL_HWREV_8169_8110SCE 0x98000000 -#define RL_TXDMA_16BYTES 0x00000000 -#define RL_TXDMA_32BYTES 0x00000100 -#define RL_TXDMA_64BYTES 0x00000200 -#define RL_TXDMA_128BYTES 0x00000300 -#define RL_TXDMA_256BYTES 0x00000400 -#define RL_TXDMA_512BYTES 0x00000500 -#define RL_TXDMA_1024BYTES 0x00000600 -#define RL_TXDMA_2048BYTES 0x00000700 +#define RL_TXDMA_16BYTES 0x00000000 +#define RL_TXDMA_32BYTES 0x00000100 +#define RL_TXDMA_64BYTES 0x00000200 +#define RL_TXDMA_128BYTES 0x00000300 +#define RL_TXDMA_256BYTES 0x00000400 +#define RL_TXDMA_512BYTES 0x00000500 +#define RL_TXDMA_1024BYTES 0x00000600 +#define RL_TXDMA_2048BYTES 0x00000700 /* * Transmit descriptor status register bits. */ -#define RL_TXSTAT_LENMASK 0x00001FFF -#define RL_TXSTAT_OWN 0x00002000 -#define RL_TXSTAT_TX_UNDERRUN 0x00004000 -#define RL_TXSTAT_TX_OK 0x00008000 -#define RL_TXSTAT_EARLY_THRESH 0x003F0000 -#define RL_TXSTAT_COLLCNT 0x0F000000 -#define RL_TXSTAT_CARR_HBEAT 0x10000000 -#define RL_TXSTAT_OUTOFWIN 0x20000000 -#define RL_TXSTAT_TXABRT 0x40000000 -#define RL_TXSTAT_CARRLOSS 0x80000000 +#define RL_TXSTAT_LENMASK 0x00001FFF +#define RL_TXSTAT_OWN 0x00002000 +#define RL_TXSTAT_TX_UNDERRUN 0x00004000 +#define RL_TXSTAT_TX_OK 0x00008000 +#define RL_TXSTAT_EARLY_THRESH 0x003F0000 +#define RL_TXSTAT_COLLCNT 0x0F000000 +#define RL_TXSTAT_CARR_HBEAT 0x10000000 +#define RL_TXSTAT_OUTOFWIN 0x20000000 +#define RL_TXSTAT_TXABRT 0x40000000 +#define RL_TXSTAT_CARRLOSS 0x80000000 /* * Interrupt status register bits. */ -#define RL_ISR_RX_OK 0x0001 -#define RL_ISR_RX_ERR 0x0002 -#define RL_ISR_TX_OK 0x0004 -#define RL_ISR_TX_ERR 0x0008 -#define RL_ISR_RX_OVERRUN 0x0010 -#define RL_ISR_PKT_UNDERRUN 0x0020 -#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ -#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ -#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ -#define RL_ISR_SWI 0x0100 /* C+ only */ -#define RL_ISR_CABLE_LEN_CHGD 0x2000 -#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ -#define RL_ISR_TIMEOUT_EXPIRED 0x4000 -#define RL_ISR_SYSTEM_ERR 0x8000 +#define RL_ISR_RX_OK 0x0001 +#define RL_ISR_RX_ERR 0x0002 +#define RL_ISR_TX_OK 0x0004 +#define RL_ISR_TX_ERR 0x0008 +#define RL_ISR_RX_OVERRUN 0x0010 +#define RL_ISR_PKT_UNDERRUN 0x0020 +#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ +#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ +#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ +#define RL_ISR_SWI 0x0100 /* C+ only */ +#define RL_ISR_CABLE_LEN_CHGD 0x2000 +#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ +#define RL_ISR_TIMEOUT_EXPIRED 0x4000 +#define RL_ISR_SYSTEM_ERR 0x8000 -#define RL_INTRS \ +#define RL_INTRS \ (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) #ifdef RE_TX_MODERATION -#define RL_INTRS_CPLUS \ +#define RL_INTRS_CPLUS \ (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) #else -#define RL_INTRS_CPLUS \ +#define RL_INTRS_CPLUS \ (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) @@ -229,144 +249,201 @@ /* * Media status register. (8139 only) */ -#define RL_MEDIASTAT_RXPAUSE 0x01 -#define RL_MEDIASTAT_TXPAUSE 0x02 -#define RL_MEDIASTAT_LINK 0x04 -#define RL_MEDIASTAT_SPEED10 0x08 -#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ -#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ +#define RL_MEDIASTAT_RXPAUSE 0x01 +#define RL_MEDIASTAT_TXPAUSE 0x02 +#define RL_MEDIASTAT_LINK 0x04 +#define RL_MEDIASTAT_SPEED10 0x08 +#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ +#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ /* * Receive config register. */ -#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ -#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ -#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ -#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ -#define RL_RXCFG_RX_RUNT 0x00000010 -#define RL_RXCFG_RX_ERRPKT 0x00000020 -#define RL_RXCFG_WRAP 0x00000080 -#define RL_RXCFG_MAXDMA 0x00000700 -#define RL_RXCFG_BUFSZ 0x00001800 -#define RL_RXCFG_FIFOTHRESH 0x0000E000 -#define RL_RXCFG_EARLYTHRESH 0x07000000 +#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ +#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ +#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ +#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ +#define RL_RXCFG_RX_RUNT 0x00000010 +#define RL_RXCFG_RX_ERRPKT 0x00000020 +#define RL_RXCFG_WRAP 0x00000080 +#define RL_RXCFG_MAXDMA 0x00000700 +#define RL_RXCFG_BUFSZ 0x00001800 +#define RL_RXCFG_FIFOTHRESH 0x0000E000 +#define RL_RXCFG_EARLYTHRESH 0x07000000 -#define RL_RXDMA_16BYTES 0x00000000 -#define RL_RXDMA_32BYTES 0x00000100 -#define RL_RXDMA_64BYTES 0x00000200 -#define RL_RXDMA_128BYTES 0x00000300 -#define RL_RXDMA_256BYTES 0x00000400 -#define RL_RXDMA_512BYTES 0x00000500 -#define RL_RXDMA_1024BYTES 0x00000600 -#define RL_RXDMA_UNLIMITED 0x00000700 +#define RL_RXDMA_16BYTES 0x00000000 +#define RL_RXDMA_32BYTES 0x00000100 +#define RL_RXDMA_64BYTES 0x00000200 +#define RL_RXDMA_128BYTES 0x00000300 +#define RL_RXDMA_256BYTES 0x00000400 +#define RL_RXDMA_512BYTES 0x00000500 +#define RL_RXDMA_1024BYTES 0x00000600 +#define RL_RXDMA_UNLIMITED 0x00000700 -#define RL_RXBUF_8 0x00000000 -#define RL_RXBUF_16 0x00000800 -#define RL_RXBUF_32 0x00001000 -#define RL_RXBUF_64 0x00001800 +#define RL_RXBUF_8 0x00000000 +#define RL_RXBUF_16 0x00000800 +#define RL_RXBUF_32 0x00001000 +#define RL_RXBUF_64 0x00001800 -#define RL_RXFIFO_16BYTES 0x00000000 -#define RL_RXFIFO_32BYTES 0x00002000 -#define RL_RXFIFO_64BYTES 0x00004000 -#define RL_RXFIFO_128BYTES 0x00006000 -#define RL_RXFIFO_256BYTES 0x00008000 -#define RL_RXFIFO_512BYTES 0x0000A000 -#define RL_RXFIFO_1024BYTES 0x0000C000 -#define RL_RXFIFO_NOTHRESH 0x0000E000 +#define RL_RXFIFO_16BYTES 0x00000000 +#define RL_RXFIFO_32BYTES 0x00002000 +#define RL_RXFIFO_64BYTES 0x00004000 +#define RL_RXFIFO_128BYTES 0x00006000 +#define RL_RXFIFO_256BYTES 0x00008000 +#define RL_RXFIFO_512BYTES 0x0000A000 +#define RL_RXFIFO_1024BYTES 0x0000C000 +#define RL_RXFIFO_NOTHRESH 0x0000E000 /* * Bits in RX status header (included with RX'ed packet * in ring buffer). */ -#define RL_RXSTAT_RXOK 0x00000001 -#define RL_RXSTAT_ALIGNERR 0x00000002 -#define RL_RXSTAT_CRCERR 0x00000004 -#define RL_RXSTAT_GIANT 0x00000008 -#define RL_RXSTAT_RUNT 0x00000010 -#define RL_RXSTAT_BADSYM 0x00000020 -#define RL_RXSTAT_BROAD 0x00002000 -#define RL_RXSTAT_INDIV 0x00004000 -#define RL_RXSTAT_MULTI 0x00008000 -#define RL_RXSTAT_LENMASK 0xFFFF0000 +#define RL_RXSTAT_RXOK 0x00000001 +#define RL_RXSTAT_ALIGNERR 0x00000002 +#define RL_RXSTAT_CRCERR 0x00000004 +#define RL_RXSTAT_GIANT 0x00000008 +#define RL_RXSTAT_RUNT 0x00000010 +#define RL_RXSTAT_BADSYM 0x00000020 +#define RL_RXSTAT_BROAD 0x00002000 +#define RL_RXSTAT_INDIV 0x00004000 +#define RL_RXSTAT_MULTI 0x00008000 +#define RL_RXSTAT_LENMASK 0xFFFF0000 -#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ +#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ /* * Command register. */ -#define RL_CMD_EMPTY_RXBUF 0x0001 -#define RL_CMD_TX_ENB 0x0004 -#define RL_CMD_RX_ENB 0x0008 -#define RL_CMD_RESET 0x0010 +#define RL_CMD_EMPTY_RXBUF 0x0001 +#define RL_CMD_TX_ENB 0x0004 +#define RL_CMD_RX_ENB 0x0008 +#define RL_CMD_RESET 0x0010 +#define RL_CMD_STOPREQ 0x0080 +/* + * Twister register values. These are completely undocumented and derived + * from public sources. + */ +#define RL_CSCFG_LINK_OK 0x0400 +#define RL_CSCFG_CHANGE 0x0800 +#define RL_CSCFG_STATUS 0xf000 +#define RL_CSCFG_ROW3 0x7000 +#define RL_CSCFG_ROW2 0x3000 +#define RL_CSCFG_ROW1 0x1000 +#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 +#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 + +#define RL_NWAYTST_RESET 0 +#define RL_NWAYTST_CBL_TEST 0x20 + +#define RL_PARA78 0x78 +#define RL_PARA78_DEF 0x78fa8388 +#define RL_PARA7C 0x7C +#define RL_PARA7C_DEF 0xcb38de43 +#define RL_PARA7C_RETUNE 0xfb38de03 /* * EEPROM control register */ -#define RL_EE_DATAOUT 0x01 /* Data out */ -#define RL_EE_DATAIN 0x02 /* Data in */ -#define RL_EE_CLK 0x04 /* clock */ -#define RL_EE_SEL 0x08 /* chip select */ -#define RL_EE_MODE (0x40|0x80) +#define RL_EE_DATAOUT 0x01 /* Data out */ +#define RL_EE_DATAIN 0x02 /* Data in */ +#define RL_EE_CLK 0x04 /* clock */ +#define RL_EE_SEL 0x08 /* chip select */ +#define RL_EE_MODE (0x40|0x80) -#define RL_EEMODE_OFF 0x00 -#define RL_EEMODE_AUTOLOAD 0x40 -#define RL_EEMODE_PROGRAM 0x80 -#define RL_EEMODE_WRITECFG (0x80|0x40) +#define RL_EEMODE_OFF 0x00 +#define RL_EEMODE_AUTOLOAD 0x40 +#define RL_EEMODE_PROGRAM 0x80 +#define RL_EEMODE_WRITECFG (0x80|0x40) /* 9346 EEPROM commands */ -#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ -#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ +#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ +#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ -#define RL_9346_WRITE 0x5 -#define RL_9346_READ 0x6 -#define RL_9346_ERASE 0x7 -#define RL_9346_EWEN 0x4 -#define RL_9346_EWEN_ADDR 0x30 -#define RL_9456_EWDS 0x4 -#define RL_9346_EWDS_ADDR 0x00 +#define RL_9346_WRITE 0x5 +#define RL_9346_READ 0x6 +#define RL_9346_ERASE 0x7 +#define RL_9346_EWEN 0x4 +#define RL_9346_EWEN_ADDR 0x30 +#define RL_9456_EWDS 0x4 +#define RL_9346_EWDS_ADDR 0x00 -#define RL_EECMD_WRITE 0x140 -#define RL_EECMD_READ_6BIT 0x180 -#define RL_EECMD_READ_8BIT 0x600 -#define RL_EECMD_ERASE 0x1c0 +#define RL_EECMD_WRITE 0x140 +#define RL_EECMD_READ_6BIT 0x180 +#define RL_EECMD_READ_8BIT 0x600 +#define RL_EECMD_ERASE 0x1c0 -#define RL_EE_ID 0x00 -#define RL_EE_PCI_VID 0x01 -#define RL_EE_PCI_DID 0x02 +#define RL_EE_ID 0x00 +#define RL_EE_PCI_VID 0x01 +#define RL_EE_PCI_DID 0x02 /* Location of station address inside EEPROM */ -#define RL_EE_EADDR 0x07 +#define RL_EE_EADDR 0x07 /* * MII register (8129 only) */ -#define RL_MII_CLK 0x01 -#define RL_MII_DATAIN 0x02 -#define RL_MII_DATAOUT 0x04 -#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ +#define RL_MII_CLK 0x01 +#define RL_MII_DATAIN 0x02 +#define RL_MII_DATAOUT 0x04 +#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ /* * Config 0 register */ -#define RL_CFG0_ROM0 0x01 -#define RL_CFG0_ROM1 0x02 -#define RL_CFG0_ROM2 0x04 -#define RL_CFG0_PL0 0x08 -#define RL_CFG0_PL1 0x10 -#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ -#define RL_CFG0_PCS 0x40 -#define RL_CFG0_SCR 0x80 +#define RL_CFG0_ROM0 0x01 +#define RL_CFG0_ROM1 0x02 +#define RL_CFG0_ROM2 0x04 +#define RL_CFG0_PL0 0x08 +#define RL_CFG0_PL1 0x10 +#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ +#define RL_CFG0_PCS 0x40 +#define RL_CFG0_SCR 0x80 /* * Config 1 register */ -#define RL_CFG1_PWRDWN 0x01 -#define RL_CFG1_SLEEP 0x02 -#define RL_CFG1_IOMAP 0x04 -#define RL_CFG1_MEMMAP 0x08 -#define RL_CFG1_RSVD 0x10 -#define RL_CFG1_DRVLOAD 0x20 -#define RL_CFG1_LED0 0x40 -#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ -#define RL_CFG1_LED1 0x80 +#define RL_CFG1_PWRDWN 0x01 +#define RL_CFG1_PME 0x01 +#define RL_CFG1_SLEEP 0x02 +#define RL_CFG1_VPDEN 0x02 +#define RL_CFG1_IOMAP 0x04 +#define RL_CFG1_MEMMAP 0x08 +#define RL_CFG1_RSVD 0x10 +#define RL_CFG1_LWACT 0x10 +#define RL_CFG1_DRVLOAD 0x20 +#define RL_CFG1_LED0 0x40 +#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ +#define RL_CFG1_LED1 0x80 + +/* + * Config 2 register + */ +#define RL_CFG2_PCI33MHZ 0x00 +#define RL_CFG2_PCI66MHZ 0x01 +#define RL_CFG2_PCI64BIT 0x08 +#define RL_CFG2_AUXPWR 0x10 +#define RL_CFG2_MSI 0x20 + +/* + * Config 3 register + */ +#define RL_CFG3_GRANTSEL 0x80 +#define RL_CFG3_WOL_MAGIC 0x20 +#define RL_CFG3_WOL_LINK 0x10 +#define RL_CFG3_FAST_B2B 0x01 + +/* + * Config 4 register + */ +#define RL_CFG4_LWPTN 0x04 +#define RL_CFG4_LWPME 0x10 + +/* + * Config 5 register + */ +#define RL_CFG5_WOL_BCAST 0x40 +#define RL_CFG5_WOL_MCAST 0x20 +#define RL_CFG5_WOL_UCAST 0x10 +#define RL_CFG5_WOL_LANWAKE 0x02 +#define RL_CFG5_PME_STS 0x01 /* * 8139C+ register definitions @@ -374,59 +451,68 @@ /* RL_DUMPSTATS_LO register */ -#define RL_DUMPSTATS_START 0x00000008 +#define RL_DUMPSTATS_START 0x00000008 /* Transmit start register */ -#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ -#define RL_TXSTART_START 0x40 /* start normal queue transmit */ -#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ +#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ +#define RL_TXSTART_START 0x40 /* start normal queue transmit */ +#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ /* * Config 2 register, 8139C+/8169/8169S/8110S only */ -#define RL_CFG2_BUSFREQ 0x07 -#define RL_CFG2_BUSWIDTH 0x08 -#define RL_CFG2_AUXPWRSTS 0x10 +#define RL_CFG2_BUSFREQ 0x07 +#define RL_CFG2_BUSWIDTH 0x08 +#define RL_CFG2_AUXPWRSTS 0x10 -#define RL_BUSFREQ_33MHZ 0x00 -#define RL_BUSFREQ_66MHZ 0x01 - -#define RL_BUSWIDTH_32BITS 0x00 -#define RL_BUSWIDTH_64BITS 0x08 +#define RL_BUSFREQ_33MHZ 0x00 +#define RL_BUSFREQ_66MHZ 0x01 + +#define RL_BUSWIDTH_32BITS 0x00 +#define RL_BUSWIDTH_64BITS 0x08 /* C+ mode command register */ -#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ -#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ -#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ -#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ -#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ -#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ +#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ +#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ +#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ +#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ +#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ +#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ +#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ +#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ +#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ +#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ +#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ +#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ +#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ +#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ +#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ /* C+ early transmit threshold */ -#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ +#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ /* * Gigabit PHY access register (8169 only) */ -#define RL_PHYAR_PHYDATA 0x0000FFFF -#define RL_PHYAR_PHYREG 0x001F0000 -#define RL_PHYAR_BUSY 0x80000000 +#define RL_PHYAR_PHYDATA 0x0000FFFF +#define RL_PHYAR_PHYREG 0x001F0000 +#define RL_PHYAR_BUSY 0x80000000 /* * Gigabit media status (8169 only) */ -#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ -#define RL_GMEDIASTAT_LINK 0x02 /* link up */ -#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ -#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ -#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ -#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ -#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ -#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ +#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ +#define RL_GMEDIASTAT_LINK 0x02 /* link up */ +#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ +#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ +#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ +#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ +#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ +#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ /* * The RealTek doesn't use a fragment-based descriptor mechanism. @@ -443,42 +529,56 @@ * all received packets. */ -#define RL_RX_BUF_SZ RL_RXBUF_64 -#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) -#define RL_TX_LIST_CNT 4 -#define RL_MIN_FRAMELEN 60 -#define RL_TXTHRESH(x) ((x) << 11) -#define RL_TX_THRESH_INIT 96 -#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH -#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED -#define RL_TX_MAXDMA RL_TXDMA_2048BYTES +#define RL_RX_BUF_SZ RL_RXBUF_64 +#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) +#define RL_TX_LIST_CNT 4 +#define RL_MIN_FRAMELEN 60 +#define RL_TX_8139_BUF_ALIGN 4 +#define RL_RX_8139_BUF_ALIGN 8 +#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) +#define RL_RX_8139_BUF_GUARD_SZ \ + (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) +#define RL_TXTHRESH(x) ((x) << 11) +#define RL_TX_THRESH_INIT 96 +#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH +#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED +#define RL_TX_MAXDMA RL_TXDMA_2048BYTES -#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) -#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) +#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) +#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) -#define RL_ETHER_ALIGN 2 +#define RL_ETHER_ALIGN 2 + +/* + * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. + */ +#define RL_IP4CSUMTX_MINLEN 28 +#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) struct rl_chain_data { uint16_t cur_rx; uint8_t *rl_rx_buf; uint8_t *rl_rx_buf_ptr; - bus_dmamap_t rl_rx_dmamap; struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; + bus_dma_tag_t rl_tx_tag; + bus_dma_tag_t rl_rx_tag; + bus_dmamap_t rl_rx_dmamap; + bus_addr_t rl_rx_buf_paddr; uint8_t last_tx; uint8_t cur_tx; }; -#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) -#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) -#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) -#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) -#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) -#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) -#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) -#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) -#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) +#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) +#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) +#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) +#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) +#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) +#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) +#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) +#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) +#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) struct rl_type { uint16_t rl_vid; @@ -505,17 +605,17 @@ struct rl_mii_frame { /* * MII constants */ -#define RL_MII_STARTDELIM 0x01 -#define RL_MII_READOP 0x02 -#define RL_MII_WRITEOP 0x01 -#define RL_MII_TURNAROUND 0x02 +#define RL_MII_STARTDELIM 0x01 +#define RL_MII_READOP 0x02 +#define RL_MII_WRITEOP 0x01 +#define RL_MII_TURNAROUND 0x02 -#define RL_8129 1 -#define RL_8139 2 -#define RL_8139CPLUS 3 -#define RL_8169 4 +#define RL_8129 1 +#define RL_8139 2 +#define RL_8139CPLUS 3 +#define RL_8169 4 -#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ +#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ (x)->rl_type == RL_8169) /* @@ -539,95 +639,101 @@ struct rl_desc { uint32_t rl_bufaddr_hi; }; -#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF -#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ -#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ -#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ -#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ -#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ -#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ -#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ -#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ -#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ -#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ +#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF +#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ +#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ +#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ +#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ +#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ +#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ +#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ +#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ +#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ +#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ -#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ -#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ +#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ +#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ +/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ +#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 +#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 +#define RL_TDESC_CMD_IPCSUMV2 0x20000000 /* * Error bits are valid only on the last descriptor of a frame * (i.e. RL_TDESC_CMD_EOF == 1) */ -#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ -#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ -#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ -#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ -#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ -#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ -#define RL_TDESC_STAT_OWN 0x80000000 +#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ +#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ +#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ +#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ +#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ +#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ +#define RL_TDESC_STAT_OWN 0x80000000 /* * RX descriptor cmd/vlan definitions */ -#define RL_RDESC_CMD_EOR 0x40000000 -#define RL_RDESC_CMD_OWN 0x80000000 -#define RL_RDESC_CMD_BUFLEN 0x00001FFF +#define RL_RDESC_CMD_EOR 0x40000000 +#define RL_RDESC_CMD_OWN 0x80000000 +#define RL_RDESC_CMD_BUFLEN 0x00001FFF -#define RL_RDESC_STAT_OWN 0x80000000 -#define RL_RDESC_STAT_EOR 0x40000000 -#define RL_RDESC_STAT_SOF 0x20000000 -#define RL_RDESC_STAT_EOF 0x10000000 -#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ -#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ -#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ -#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ -#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ -#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ -#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ -#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ -#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ -#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ -#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ -#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ -#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ -#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ -#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ -#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ -#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ +#define RL_RDESC_STAT_OWN 0x80000000 +#define RL_RDESC_STAT_EOR 0x40000000 +#define RL_RDESC_STAT_SOF 0x20000000 +#define RL_RDESC_STAT_EOF 0x10000000 +#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ +#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ +#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ +#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ +#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ +#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ +#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ +#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ +#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ +#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ +#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ +#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ +#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ +#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ +#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ +#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ +#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ +#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ +#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ RL_RDESC_STAT_CRCERR) -#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available +#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available (rl_vlandata valid)*/ -#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ +#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ +/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ +#define RL_RDESC_IPV6 0x80000000 +#define RL_RDESC_IPV4 0x40000000 -#define RL_PROTOID_NONIP 0x00000000 -#define RL_PROTOID_TCPIP 0x00010000 -#define RL_PROTOID_UDPIP 0x00020000 -#define RL_PROTOID_IP 0x00030000 -#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ +#define RL_PROTOID_NONIP 0x00000000 +#define RL_PROTOID_TCPIP 0x00010000 +#define RL_PROTOID_UDPIP 0x00020000 +#define RL_PROTOID_IP 0x00030000 +#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ RL_PROTOID_TCPIP) -#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ +#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ RL_PROTOID_UDPIP) /* * Statistics counter structure (8139C+ and 8169 only) */ struct rl_stats { - uint32_t rl_tx_pkts_lo; - uint32_t rl_tx_pkts_hi; - uint32_t rl_tx_errs_lo; - uint32_t rl_tx_errs_hi; - uint32_t rl_tx_errs; + uint64_t rl_tx_pkts; + uint64_t rl_rx_pkts; + uint64_t rl_tx_errs; + uint32_t rl_rx_errs; uint16_t rl_missed_pkts; uint16_t rl_rx_framealign_errs; uint32_t rl_tx_onecoll; uint32_t rl_tx_multicolls; - uint32_t rl_rx_ucasts_hi; - uint32_t rl_rx_ucasts_lo; - uint32_t rl_rx_bcasts_lo; - uint32_t rl_rx_bcasts_hi; + uint64_t rl_rx_ucasts; + uint64_t rl_rx_bcasts; uint32_t rl_rx_mcasts; uint16_t rl_tx_aborts; uint16_t rl_rx_underruns; @@ -636,63 +742,89 @@ struct rl_stats { /* * Rx/Tx descriptor parameters (8139C+ and 8169 only) * - * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. - * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors - * due to the 8139C+. We need to put the number of descriptors in the ring - * structure and use that value instead. + * 8139C+ + * Number of descriptors supported : up to 64 + * Descriptor alignment : 256 bytes + * Tx buffer : At least 4 bytes in length. + * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. + * + * 8169 + * Number of descriptors supported : up to 1024 + * Descriptor alignment : 256 bytes + * Tx buffer : At least 4 bytes in length. + * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. */ #ifndef __NO_STRICT_ALIGNMENT -#define RE_FIXUP_RX 1 +#define RE_FIXUP_RX 1 #endif -#define RL_TX_DESC_CNT 64 -#define RL_TX_DESC_THLD 4 -#define RL_RX_DESC_CNT RL_TX_DESC_CNT +#define RL_8169_TX_DESC_CNT 256 +#define RL_8169_RX_DESC_CNT 256 +#define RL_8139_TX_DESC_CNT 64 +#define RL_8139_RX_DESC_CNT 64 +#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT +#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT +#define RL_NTXSEGS 32 -#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) -#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) -#define RL_RING_ALIGN 256 -#define RL_IFQ_MAXLEN 512 -#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) -#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) -#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) -#define RL_PKTSZ(x) ((x)/* >> 3*/) +#define RL_RING_ALIGN 256 +#define RL_DUMP_ALIGN 64 +#define RL_IFQ_MAXLEN 512 +#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) +#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) +#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) +#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) +#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) +#define RL_PKTSZ(x) ((x)/* >> 3*/) #ifdef RE_FIXUP_RX -#define RE_ETHER_ALIGN sizeof(uint64_t) -#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) +#define RE_ETHER_ALIGN sizeof(uint64_t) +#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) #else -#define RE_ETHER_ALIGN 0 -#define RE_RX_DESC_BUFLEN MCLBYTES +#define RE_ETHER_ALIGN 0 +#define RE_RX_DESC_BUFLEN MCLBYTES #endif -#define RL_MSI_MESSAGES 2 +#define RL_MSI_MESSAGES 1 -#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) -#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) +#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) +#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) + +/* + * The number of bits reserved for MSS in RealTek controllers is + * 11bits. This limits the maximum interface MTU size in TSO case + * as upper stack should not generate TCP segments with MSS greater + * than the limit. + */ +#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) /* see comment in dev/re/if_re.c */ -#define RL_JUMBO_FRAMELEN 7440 -#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define RL_JUMBO_FRAMELEN 7440 +#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define RL_MAX_FRAMELEN \ + (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) -struct rl_softc; +struct rl_txdesc { + struct mbuf *tx_m; + bus_dmamap_t tx_dmamap; +}; -struct rl_dmaload_arg { - int rl_idx; - int rl_maxsegs; - uint32_t rl_flags; - struct rl_desc *rl_ring; +struct rl_rxdesc { + struct mbuf *rx_m; + bus_dmamap_t rx_dmamap; + bus_size_t rx_size; }; struct rl_list_data { - struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; - struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; + struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; + struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; + int rl_tx_desc_cnt; + int rl_rx_desc_cnt; int rl_tx_prodidx; int rl_rx_prodidx; int rl_tx_considx; int rl_tx_free; - bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; - bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; - bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ + bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ + bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ + bus_dmamap_t rl_rx_sparemap; bus_dma_tag_t rl_stag; /* stats mapping tag */ bus_dmamap_t rl_smap; /* stats map */ struct rl_stats *rl_stats; @@ -707,17 +839,20 @@ struct rl_list_data { bus_addr_t rl_tx_list_addr; }; +enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; + struct rl_softc { struct ifnet *rl_ifp; /* interface info */ bus_space_handle_t rl_bhandle; /* bus space handle */ bus_space_tag_t rl_btag; /* bus space tag */ device_t rl_dev; struct resource *rl_res; + int rl_res_id; + int rl_res_type; struct resource *rl_irq[RL_MSI_MESSAGES]; void *rl_intrhand[RL_MSI_MESSAGES]; device_t rl_miibus; bus_dma_tag_t rl_parent_tag; - bus_dma_tag_t rl_tag; uint8_t rl_type; int rl_eecmd_read; int rl_eewidth; @@ -734,6 +869,10 @@ struct rl_softc { uint32_t rl_rxlenmask; int rl_testmode; int rl_if_flags; + int rl_twister_enable; + enum rl_twist rl_twister; + int rl_twist_row; + int rl_twist_col; int suspended; /* 0 = normal 1 = suspended */ #ifdef DEVICE_POLLING int rxcycles; @@ -742,10 +881,23 @@ struct rl_softc { struct task rl_txtask; struct task rl_inttask; - struct mtx rl_intlock; int rl_txstart; - int rl_link; - int rl_msi; + uint32_t rl_flags; +#define RL_FLAG_MSI 0x0001 +#define RL_FLAG_AUTOPAD 0x0002 +#define RL_FLAG_PHYWAKE_PM 0x0004 +#define RL_FLAG_PHYWAKE 0x0008 +#define RL_FLAG_NOJUMBO 0x0010 +#define RL_FLAG_PAR 0x0020 +#define RL_FLAG_DESCV2 0x0040 +#define RL_FLAG_MACSTAT 0x0080 +#define RL_FLAG_FASTETHER 0x0100 +#define RL_FLAG_CMDSTOP 0x0200 +#define RL_FLAG_MACRESET 0x0400 +#define RL_FLAG_WOLRXENB 0x1000 +#define RL_FLAG_MACSLEEP 0x2000 +#define RL_FLAG_PCIE 0x4000 +#define RL_FLAG_LINK 0x8000 }; #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) @@ -755,41 +907,42 @@ struct rl_softc { /* * register space access macros */ -#define CSR_WRITE_STREAM_4(sc, reg, val) \ +#define CSR_WRITE_STREAM_4(sc, reg, val) \ bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) -#define CSR_WRITE_4(sc, reg, val) \ +#define CSR_WRITE_4(sc, reg, val) \ bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) -#define CSR_WRITE_2(sc, reg, val) \ +#define CSR_WRITE_2(sc, reg, val) \ bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) -#define CSR_WRITE_1(sc, reg, val) \ +#define CSR_WRITE_1(sc, reg, val) \ bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) -#define CSR_READ_4(sc, reg) \ +#define CSR_READ_4(sc, reg) \ bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) -#define CSR_READ_2(sc, reg) \ +#define CSR_READ_2(sc, reg) \ bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) -#define CSR_READ_1(sc, reg) \ +#define CSR_READ_1(sc, reg) \ bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) -#define CSR_SETBIT_1(sc, offset, val) \ +#define CSR_SETBIT_1(sc, offset, val) \ CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) -#define CSR_CLRBIT_1(sc, offset, val) \ +#define CSR_CLRBIT_1(sc, offset, val) \ CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) -#define CSR_SETBIT_2(sc, offset, val) \ +#define CSR_SETBIT_2(sc, offset, val) \ CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) -#define CSR_CLRBIT_2(sc, offset, val) \ +#define CSR_CLRBIT_2(sc, offset, val) \ CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) -#define CSR_SETBIT_4(sc, offset, val) \ +#define CSR_SETBIT_4(sc, offset, val) \ CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) -#define CSR_CLRBIT_4(sc, offset, val) \ +#define CSR_CLRBIT_4(sc, offset, val) \ CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) -#define RL_TIMEOUT 1000 +#define RL_TIMEOUT 1000 +#define RL_PHY_TIMEOUT 2000 /* * General constants that are fun to know. @@ -801,196 +954,162 @@ struct rl_softc { /* * RealTek chip device IDs. */ +#define RT_DEVICEID_8139D 0x8039 #define RT_DEVICEID_8129 0x8129 -#define RT_DEVICEID_8101E 0x8136 +#define RT_DEVICEID_8101E 0x8136 #define RT_DEVICEID_8138 0x8138 #define RT_DEVICEID_8139 0x8139 -#define RT_DEVICEID_8169SC 0x8167 -#define RT_DEVICEID_8168 0x8168 -#define RT_DEVICEID_8169 0x8169 -#define RT_DEVICEID_8100 0x8100 +#define RT_DEVICEID_8169SC 0x8167 +#define RT_DEVICEID_8168 0x8168 +#define RT_DEVICEID_8169 0x8169 +#define RT_DEVICEID_8100 0x8100 -#define RT_REVID_8139CPLUS 0x20 +#define RT_REVID_8139CPLUS 0x20 /* * Accton PCI vendor ID */ -#define ACCTON_VENDORID 0x1113 +#define ACCTON_VENDORID 0x1113 /* * Accton MPX 5030/5038 device ID. */ -#define ACCTON_DEVICEID_5030 0x1211 +#define ACCTON_DEVICEID_5030 0x1211 /* * Nortel PCI vendor ID */ -#define NORTEL_VENDORID 0x126C +#define NORTEL_VENDORID 0x126C /* * Delta Electronics Vendor ID. */ -#define DELTA_VENDORID 0x1500 +#define DELTA_VENDORID 0x1500 /* * Delta device IDs. */ -#define DELTA_DEVICEID_8139 0x1360 +#define DELTA_DEVICEID_8139 0x1360 /* * Addtron vendor ID. */ -#define ADDTRON_VENDORID 0x4033 +#define ADDTRON_VENDORID 0x4033 /* * Addtron device IDs. */ -#define ADDTRON_DEVICEID_8139 0x1360 +#define ADDTRON_DEVICEID_8139 0x1360 /* * D-Link vendor ID. */ -#define DLINK_VENDORID 0x1186 +#define DLINK_VENDORID 0x1186 /* * D-Link DFE-530TX+ device ID */ -#define DLINK_DEVICEID_530TXPLUS 0x1300 +#define DLINK_DEVICEID_530TXPLUS 0x1300 /* * D-Link DFE-5280T device ID */ -#define DLINK_DEVICEID_528T 0x4300 +#define DLINK_DEVICEID_528T 0x4300 /* * D-Link DFE-690TXD device ID */ -#define DLINK_DEVICEID_690TXD 0x1340 +#define DLINK_DEVICEID_690TXD 0x1340 /* * Corega K.K vendor ID */ -#define COREGA_VENDORID 0x1259 +#define COREGA_VENDORID 0x1259 /* * Corega FEther CB-TXD device ID */ -#define COREGA_DEVICEID_FETHERCBTXD 0xa117 +#define COREGA_DEVICEID_FETHERCBTXD 0xa117 /* * Corega FEtherII CB-TXD device ID */ -#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e +#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e /* * Corega CG-LAPCIGT device ID */ -#define COREGA_DEVICEID_CGLAPCIGT 0xc107 +#define COREGA_DEVICEID_CGLAPCIGT 0xc107 /* * Linksys vendor ID */ -#define LINKSYS_VENDORID 0x1737 +#define LINKSYS_VENDORID 0x1737 /* * Linksys EG1032 device ID */ -#define LINKSYS_DEVICEID_EG1032 0x1032 +#define LINKSYS_DEVICEID_EG1032 0x1032 /* * Linksys EG1032 rev 3 sub-device ID */ -#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 +#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 /* * Peppercon vendor ID */ -#define PEPPERCON_VENDORID 0x1743 +#define PEPPERCON_VENDORID 0x1743 /* * Peppercon ROL-F device ID */ -#define PEPPERCON_DEVICEID_ROLF 0x8139 +#define PEPPERCON_DEVICEID_ROLF 0x8139 /* * Planex Communications, Inc. vendor ID */ -#define PLANEX_VENDORID 0x14ea +#define PLANEX_VENDORID 0x14ea /* * Planex FNW-3603-TX device ID */ -#define PLANEX_DEVICEID_FNW3603TX 0xab06 +#define PLANEX_DEVICEID_FNW3603TX 0xab06 /* * Planex FNW-3800-TX device ID */ -#define PLANEX_DEVICEID_FNW3800TX 0xab07 +#define PLANEX_DEVICEID_FNW3800TX 0xab07 /* * LevelOne vendor ID */ -#define LEVEL1_VENDORID 0x018A +#define LEVEL1_VENDORID 0x018A /* * LevelOne FPC-0106TX devide ID */ -#define LEVEL1_DEVICEID_FPC0106TX 0x0106 +#define LEVEL1_DEVICEID_FPC0106TX 0x0106 /* * Compaq vendor ID */ -#define CP_VENDORID 0x021B +#define CP_VENDORID 0x021B /* * Edimax vendor ID */ -#define EDIMAX_VENDORID 0x13D1 +#define EDIMAX_VENDORID 0x13D1 /* * Edimax EP-4103DL cardbus device ID */ -#define EDIMAX_DEVICEID_EP4103DL 0xAB06 +#define EDIMAX_DEVICEID_EP4103DL 0xAB06 /* US Robotics vendor ID */ -#define USR_VENDORID 0x16EC +#define USR_VENDORID 0x16EC /* US Robotics 997902 device ID */ -#define USR_DEVICEID_997902 0x0116 - -/* - * PCI low memory base and low I/O base register, and - * other PCI registers. - */ - -#define RL_PCI_VENDOR_ID 0x00 -#define RL_PCI_DEVICE_ID 0x02 -#define RL_PCI_COMMAND 0x04 -#define RL_PCI_STATUS 0x06 -#define RL_PCI_CLASSCODE 0x09 -#define RL_PCI_LATENCY_TIMER 0x0D -#define RL_PCI_HEADER_TYPE 0x0E -#define RL_PCI_LOIO 0x10 -#define RL_PCI_LOMEM 0x14 -#define RL_PCI_BIOSROM 0x30 -#define RL_PCI_INTLINE 0x3C -#define RL_PCI_INTPIN 0x3D -#define RL_PCI_MINGNT 0x3E -#define RL_PCI_MINLAT 0x0F -#define RL_PCI_RESETOPT 0x48 -#define RL_PCI_EEPROM_DATA 0x4C - -#define RL_PCI_CAPID 0x50 /* 8 bits */ -#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ -#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ -#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ - -#define RL_PSTATE_MASK 0x0003 -#define RL_PSTATE_D0 0x0000 -#define RL_PSTATE_D1 0x0002 -#define RL_PSTATE_D2 0x0002 -#define RL_PSTATE_D3 0x0003 -#define RL_PME_EN 0x0010 -#define RL_PME_STATUS 0x8000 +#define USR_DEVICEID_997902 0x0116 diff --git a/src/libs/compat/freebsd_network/bus.c b/src/libs/compat/freebsd_network/bus.c index b7b9a0d372..f7597a7f28 100644 --- a/src/libs/compat/freebsd_network/bus.c +++ b/src/libs/compat/freebsd_network/bus.c @@ -600,6 +600,25 @@ pci_get_domain(device_t dev) return 0; } +uint32_t +pci_get_devid(device_t dev) +{ + return pci_read_config(dev, PCI_device_id, 2) << 16 | + pci_read_config(dev, PCI_vendor_id, 2); +} + +uint8_t +pci_get_cachelnsz(device_t dev) +{ + return pci_read_config(dev, PCI_line_size, 1); +} + +uint8_t * +pci_get_ether(device_t dev) +{ + /* used in if_dc to get the MAC from CardBus CIS for Xircom card */ + return NULL; /* NULL is handled in the caller correctly */ +} uint8_t pci_get_bus(device_t dev) diff --git a/src/libs/compat/freebsd_network/compat/dev/mii/miidevs b/src/libs/compat/freebsd_network/compat/dev/mii/miidevs index 325107005c..ecaed6527c 100644 --- a/src/libs/compat/freebsd_network/compat/dev/mii/miidevs +++ b/src/libs/compat/freebsd_network/compat/dev/mii/miidevs @@ -133,7 +133,9 @@ model ATHEROS F2 0x0002 Atheros F2 10/100 PHY model BROADCOM 3C905B 0x0012 3c905B 10/100 internal PHY model BROADCOM 3C905C 0x0017 3c905C 10/100 internal PHY model BROADCOM BCM5201 0x0021 BCM5201 10/100baseTX PHY +model BROADCOM BCM5214 0x0028 BCM5214 Quad 10/100 PHY model BROADCOM BCM5221 0x001e BCM5221 10/100baseTX PHY +model BROADCOM BCM5222 0x0032 BCM5222 Dual 10/100 PHY model BROADCOM BCM4401 0x0036 BCM4401 10/100baseTX PHY model xxBROADCOM BCM5400 0x0004 Broadcom 1000baseTX PHY model xxBROADCOM BCM5401 0x0005 BCM5401 10/100/1000baseTX PHY diff --git a/src/libs/compat/freebsd_network/compat/dev/pci/pcivar.h b/src/libs/compat/freebsd_network/compat/dev/pci/pcivar.h index c5e96b884b..0d0d9dab75 100644 --- a/src/libs/compat/freebsd_network/compat/dev/pci/pcivar.h +++ b/src/libs/compat/freebsd_network/compat/dev/pci/pcivar.h @@ -32,6 +32,8 @@ uint16_t pci_get_device(device_t dev); uint16_t pci_get_subvendor(device_t dev); uint16_t pci_get_subdevice(device_t dev); uint8_t pci_get_revid(device_t dev); +uint8_t pci_get_cachelnsz(device_t dev); +uint8_t *pci_get_ether(device_t dev); uint32_t pci_read_config(device_t dev, int reg, int width); void pci_write_config(device_t dev, int reg, uint32_t val, int width); diff --git a/src/libs/compat/freebsd_network/compat/net/if_media.h b/src/libs/compat/freebsd_network/compat/net/if_media.h index 69b2459567..456163705e 100644 --- a/src/libs/compat/freebsd_network/compat/net/if_media.h +++ b/src/libs/compat/freebsd_network/compat/net/if_media.h @@ -258,6 +258,7 @@ uint64_t ifmedia_baudrate(int); */ #define IFM_FDX 0x00100000 /* Force full duplex */ #define IFM_HDX 0x00200000 /* Force half duplex */ +#define IFM_FLOW 0x00400000 /* Enable hardware flow control */ #define IFM_FLAG0 0x01000000 /* Driver defined flag */ #define IFM_FLAG1 0x02000000 /* Driver defined flag */ #define IFM_FLAG2 0x04000000 /* Driver defined flag */ diff --git a/src/libs/compat/freebsd_network/compat/sys/kernel.h b/src/libs/compat/freebsd_network/compat/sys/kernel.h index 6502c2b532..6c8c545f7d 100644 --- a/src/libs/compat/freebsd_network/compat/sys/kernel.h +++ b/src/libs/compat/freebsd_network/compat/sys/kernel.h @@ -45,6 +45,7 @@ struct __system_init { struct __system_init __uninit_##uniquifier = { (system_init_func_t) func } #define TUNABLE_INT(path, var) +#define TUNABLE_INT_FETCH(path, var) extern int ticks; diff --git a/src/libs/compat/freebsd_network/compat/sys/types.h b/src/libs/compat/freebsd_network/compat/sys/types.h index 8b32a832f5..babd91bc8c 100644 --- a/src/libs/compat/freebsd_network/compat/sys/types.h +++ b/src/libs/compat/freebsd_network/compat/sys/types.h @@ -17,5 +17,6 @@ typedef int boolean_t; typedef __const char* c_caddr_t; +typedef uint64_t u_quad_t; #endif diff --git a/src/libs/compat/freebsd_network/fbsd_mii_physubr.c b/src/libs/compat/freebsd_network/fbsd_mii_physubr.c index 1fa0b65869..2c2015e119 100644 --- a/src/libs/compat/freebsd_network/fbsd_mii_physubr.c +++ b/src/libs/compat/freebsd_network/fbsd_mii_physubr.c @@ -551,3 +551,54 @@ mii_phy_dev_probe(device_t dev, const struct mii_phydesc *mpd, int mrv) return (ENXIO); } +/* + * Return the flow control status flag from MII_ANAR & MII_ANLPAR. + */ +u_int +mii_phy_flowstatus(struct mii_softc *sc) +{ + int anar, anlpar; + + if ((sc->mii_flags & MIIF_DOPAUSE) == 0) + return (0); + + anar = PHY_READ(sc, MII_ANAR); + anlpar = PHY_READ(sc, MII_ANLPAR); + + /* + * Check for 1000BASE-X. Autonegotiation is a bit + * different on such devices. + */ + if ((sc->mii_flags & MIIF_IS_1000X) != 0) { + anar <<= 3; + anlpar <<= 3; + } + + if ((anar & ANAR_PAUSE_SYM) != 0 && (anlpar & ANLPAR_PAUSE_SYM) != 0) + return (IFM_FLOW | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); + + if ((anar & ANAR_PAUSE_SYM) == 0) { + if ((anar & ANAR_PAUSE_ASYM) != 0 && + (anlpar & ANLPAR_PAUSE_TOWARDS) != 0) + return (IFM_FLOW | IFM_ETH_TXPAUSE); + else + return (0); + } + + if ((anar & ANAR_PAUSE_ASYM) == 0) { + if ((anlpar & ANLPAR_PAUSE_SYM) != 0) + return (IFM_FLOW | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); + else + return (0); + } + + switch ((anlpar & ANLPAR_PAUSE_TOWARDS)) { + case ANLPAR_PAUSE_NONE: + return (0); + case ANLPAR_PAUSE_ASYM: + return (IFM_FLOW | IFM_ETH_RXPAUSE); + default: + return (IFM_FLOW | IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); + } + /* NOTREACHED */ +}