diff --git a/headers/private/kernel/arch/arm/arch_cpu.h b/headers/private/kernel/arch/arm/arch_cpu.h
index 6364313670..a165f1ca09 100644
--- a/headers/private/kernel/arch/arm/arch_cpu.h
+++ b/headers/private/kernel/arch/arm/arch_cpu.h
@@ -53,15 +53,62 @@ typedef struct arch_cpu_info {
 extern "C" {
 #endif
 
-extern uint32 arm_get_dfsr(void);
-extern uint32 arm_get_ifsr(void);
-extern addr_t arm_get_dfar(void);
-extern addr_t arm_get_ifar(void);
 
-extern addr_t arm_get_fp(void);
+#define DEFINE_ARM_GET_REG(name, cp, opc1, crn, crm, opc2) \
+	static inline uint32 \
+	arm_get_##name(void) \
+	{ \
+		uint32 res; \
+		asm volatile ("mrc " #cp ", " #opc1 ", %0, " #crn ", " #crm ", " #opc2 : "=r" (res)); \
+		return res; \
+	}
+
+
+#define DEFINE_ARM_SET_REG(name, cp, opc1, crn, crm, opc2) \
+	static inline void \
+	arm_set_##name(uint32 val) \
+	{ \
+		asm volatile ("mcr " #cp ", " #opc1 ", %0, " #crn ", " #crm ", " #opc2 :: "r" (val)); \
+	}
+
+
+/* CP15 c1, System Control Register */
+DEFINE_ARM_GET_REG(sctlr, p15, 0, c1, c0, 0)
+DEFINE_ARM_SET_REG(sctlr, p15, 0, c1, c0, 0)
+
+/* CP15 c2, Translation table support registers */
+DEFINE_ARM_GET_REG(ttbr0, p15, 0, c2, c0, 0)
+DEFINE_ARM_SET_REG(ttbr0, p15, 0, c2, c0, 0)
+DEFINE_ARM_GET_REG(ttbr1, p15, 0, c2, c0, 1)
+DEFINE_ARM_SET_REG(ttbr1, p15, 0, c2, c0, 1)
+DEFINE_ARM_GET_REG(ttbcr, p15, 0, c2, c0, 2)
+DEFINE_ARM_SET_REG(ttbcr, p15, 0, c2, c0, 2)
+
+/* CP15 c5 and c6, Memory system fault registers */
+DEFINE_ARM_GET_REG(dfsr, p15, 0, c5, c0, 0)
+DEFINE_ARM_GET_REG(ifsr, p15, 0, c5, c0, 1)
+DEFINE_ARM_GET_REG(dfar, p15, 0, c6, c0, 0)
+DEFINE_ARM_GET_REG(ifar, p15, 0, c6, c0, 2)
+
+/* CP15 c13, Process, context and thread ID registers */
+DEFINE_ARM_GET_REG(tpidruro, p15, 0, c13, c0, 3)
+DEFINE_ARM_SET_REG(tpidruro, p15, 0, c13, c0, 3)
+DEFINE_ARM_GET_REG(tpidrprw, p15, 0, c13, c0, 4)
+DEFINE_ARM_SET_REG(tpidrprw, p15, 0, c13, c0, 4)
+
+
+#undef DEFINE_ARM_GET_REG
+#undef DEFINE_ARM_SET_REG
+
+
+static inline addr_t
+arm_get_fp(void)
+{
+	uint32 res;
+	asm volatile ("mov %0, fp": "=r" (res));
+	return res;
+}
 
-extern int arm_get_sctlr(void);
-extern int arm_set_sctlr(int val);
 
 void arch_cpu_invalidate_TLB_page(addr_t page);
 
diff --git a/src/system/kernel/arch/arm/arch_asm.S b/src/system/kernel/arch/arm/arch_asm.S
index 6d66c19f6a..e93a1c258a 100644
--- a/src/system/kernel/arch/arm/arch_asm.S
+++ b/src/system/kernel/arch/arm/arch_asm.S
@@ -20,20 +20,6 @@
 .text
 
 
-/* int arm_get_sctlr(void); */
-FUNCTION(arm_get_sctlr):
-	mrc	p15, 0, r0, c1, c0, 0
-	bx	lr
-FUNCTION_END(arm_get_sctlr)
-
-
-/* void arm_set_sctlr(int val); */
-FUNCTION(arm_set_sctlr):
-	mcr	p15, 0, r0, c1, c0, 0
-	bx	lr
-FUNCTION_END(arm_set_sctlr)
-
-
 /* NOTE: the I bit in cpsr (bit 7) is *set* to disable... */
 
 
@@ -108,41 +94,6 @@ FUNCTION(arm_restore_fpu):
 FUNCTION_END(arm_restore_fpu)
 
 
-/* uint32 arm_get_dfsr(void); */
-FUNCTION(arm_get_dfsr):
-	mrc	p15, 0, r0, c5, c0, 0		@ get DFSR
-	bx	lr
-FUNCTION_END(arm_get_dfsr)
-
-
-/* uint32 arm_get_ifsr(void) */
-FUNCTION(arm_get_ifsr):
-	mrc p15, 0, r0, c5, c0, 1		@ get IFSR
-	bx	lr
-FUNCTION_END(arm_get_ifsr)
-
-
-/* addr_t arm_get_dfar(void); */
-FUNCTION(arm_get_dfar):
-	mrc	p15, 0, r0, c6, c0, 0		@ get DFAR
-	bx	lr
-FUNCTION_END(arm_get_dfar)
-
-
-/* addr_t arm_get_ifar(void) */
-FUNCTION(arm_get_ifar):
-	MRC p15, 0, r0, c6, c0, 2		@ get IFAR
-	bx	lr
-FUNCTION_END(arm_get_ifar)
-
-
-/* addr_t arm_get_fp(void); */
-FUNCTION(arm_get_fp):
-	mov	r0, fp				@ get framepointer
-	bx	lr
-FUNCTION_END(arm_get_fp);
-
-
 /* status_t arch_cpu_user_memcpy(void *to, const void *from, size_t size, addr_t *faultHandler) */
 FUNCTION(_arch_cpu_user_memcpy):
 	stmfd   sp!, { r4-r6, lr }
diff --git a/src/system/kernel/arch/arm/arch_thread.cpp b/src/system/kernel/arch/arm/arch_thread.cpp
index 004ab26806..66a0f642f3 100644
--- a/src/system/kernel/arch/arm/arch_thread.cpp
+++ b/src/system/kernel/arch/arm/arch_thread.cpp
@@ -125,8 +125,7 @@ arch_thread_init_tls(Thread *thread)
 void
 arm_swap_pgdir(uint32_t pageDirectoryAddress)
 {
-	// Set translation table base
-	asm volatile("MCR p15, 0, %[addr], c2, c0, 0"::[addr] "r" (pageDirectoryAddress));
+	arm_set_ttbr0(pageDirectoryAddress);
 	isb();
 
 	arch_cpu_global_TLB_invalidate();
@@ -136,19 +135,10 @@ arm_swap_pgdir(uint32_t pageDirectoryAddress)
 }
 
 
-void
-arm_set_tls_context(Thread *thread)
-{
-	// Set TPIDRURO to point to TLS base
-	asm volatile("MCR p15, 0, %0, c13, c0, 3"
-		: : "r" (thread->user_local_storage));
-}
-
-
 void
 arch_thread_context_switch(Thread *from, Thread *to)
 {
-	arm_set_tls_context(to);
+	arm_set_tpidruro(to->user_local_storage);
 
 	VMAddressSpace *oldAddressSpace = from->team->address_space;
 	VMTranslationMap *oldTranslationMap = oldAddressSpace->TranslationMap();
@@ -189,7 +179,7 @@ status_t
 arch_thread_enter_userspace(Thread *thread, addr_t entry,
 	void *args1, void *args2)
 {
-	arm_set_tls_context(thread);
+	arm_set_tpidruro(thread->user_local_storage);
 
 	addr_t stackTop = thread->user_stack_base + thread->user_stack_size;