removed PIO mode acceleration completely.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25907 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c

@@ -3,7 +3,7 @@
 	This file may be used under the terms of the Be Sample Code License.
 
 	Other authors:
-	Rudolf Cornelissen 9/2003-2/2005.
+	Rudolf Cornelissen 9/2003-6/2008.
 */
 
 /*
@@ -11,149 +11,8 @@
 	moved DMA acceleration 'top-level' routines to be integrated in the engine:
 	it is costly to call the engine for every single function within a loop!
 	(measured with BeRoMeter 1.2.6: upto 15% speed increase on all CPU's.)
-	Leaving PIO acceleration as it is for now, for the purpose of benchmarking :-)
-
-	note also:
-	attempting DMA on NV40 and higher because without it I can't get them going ATM.
-	Maybe later we can forget about PIO mode acceleration totally (depends on 3D
-	acceleration attempts).
 */
 
 #define MODULE_BIT 0x40000000
 
 #include "acc_std.h"
-
-void SCREEN_TO_SCREEN_BLIT_PIO(engine_token *et, blit_params *list, uint32 count)
-{
-	int i;
-
-	/* init acc engine for blit function */
-	nv_acc_setup_blit();
-
-	/* do each blit */
-	i=0;
-	while (count--)
-	{
-		nv_acc_blit
-		(
-			list[i].src_left,
-			list[i].src_top,
-			list[i].dest_left,
-			list[i].dest_top,
-			list[i].width,
-			list[i].height
-		);
-		i++;
-	}
-}
-
-void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_PIO(engine_token *et, scaled_blit_params *list, uint32 count)
-{
-	int i;
-
-	/* do each blit */
-	i=0;
-	while (count--)
-	{
-		nv_acc_video_blit
-		(
-			list[i].src_left,
-			list[i].src_top,
-			list[i].src_width,
-			list[i].src_height,
-			list[i].dest_left,
-			list[i].dest_top,
-			list[i].dest_width,
-			list[i].dest_height
-		);
-		i++;
-	}
-}
-
-void SCREEN_TO_SCREEN_TRANSPARENT_BLIT_PIO(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count)
-{
-	int i;
-
-	/* do each blit */
-	i=0;
-	while (count--)
-	{
-		nv_acc_transparent_blit
-		(
-			list[i].src_left,
-			list[i].src_top,
-			list[i].dest_left,
-			list[i].dest_top,
-			list[i].width,
-			list[i].height,
-			transparent_colour
-		);
-		i++;
-	}
-}
-
-void FILL_RECTANGLE_PIO(engine_token *et, uint32 colorIndex, fill_rect_params *list, uint32 count)
-{
-	int i;
-
-	/* init acc engine for fill function */
-	nv_acc_setup_rectangle(colorIndex);
-
-	/* draw each rectangle */
-	i=0;
-	while (count--)
-	{
-		nv_acc_rectangle
-		(
-			list[i].left,
-			(list[i].right)+1,
-			list[i].top,
-			(list[i].bottom-list[i].top)+1
-		);
-		i++;
-	}
-}
-
-void INVERT_RECTANGLE_PIO(engine_token *et, fill_rect_params *list, uint32 count)
-{
-	int i;
-
-	/* init acc engine for invert function */
-	nv_acc_setup_rect_invert();
-
-	/* invert each rectangle */
-	i=0;
-	while (count--)
-	{
-		nv_acc_rectangle_invert
-		(
-			list[i].left,
-			(list[i].right)+1,
-			list[i].top,
-			(list[i].bottom-list[i].top)+1
-		);
-		i++;
-	}
-}
-
-void FILL_SPAN_PIO(engine_token *et, uint32 colorIndex, uint16 *list, uint32 count)
-{
-	int i;
-
-	/* init acc engine for fill function */
-	nv_acc_setup_rectangle(colorIndex);
-
-	/* draw each span */
-	i=0;
-	while (count--)
-	{
-		nv_acc_rectangle
-		(
-			list[i+1],
-			list[i+2]+1,
-			list[i],
-			1
-		);
-		i+=3;
-	}
-}

src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c

@@ -4,14 +4,7 @@
 
 	other authors:
 	Mark Watson
-	Rudolf Cornelissen 3/2004-2/2005
+	Rudolf Cornelissen 3/2004-6/2008
-*/
-
-/*
-	note:
-	attempting DMA on NV40 and higher because without it I can't get it going ATM.
-	Later on this can become a nv.settings switch, and maybe later we can even
-	forget about non-DMA completely (depends on 3D acceleration attempts).
 */
 
 #define MODULE_BIT 0x10000000
@@ -27,21 +20,6 @@ uint32 ACCELERANT_ENGINE_COUNT(void)
 	return 1;
 }
 
-status_t ACQUIRE_ENGINE_PIO(uint32 capabilities, uint32 max_wait, sync_token *st, engine_token **et)
-{
-	/* acquire the shared benaphore */
-	AQUIRE_BEN(si->engine.lock)
-	/* sync if required */
-	if (st) SYNC_TO_TOKEN(st);
-
-	/* make sure all needed engine cmd's are mapped to the FIFO */
-	nv_acc_assert_fifo();
-
-	/* return an engine token */
-	*et = &nv_engine_token;
-	return B_OK;
-}
-
 status_t ACQUIRE_ENGINE_DMA(uint32 capabilities, uint32 max_wait, sync_token *st, engine_token **et)
 {
 	/* acquire the shared benaphore */
@@ -70,9 +48,6 @@ status_t RELEASE_ENGINE(engine_token *et, sync_token *st)
 void WAIT_ENGINE_IDLE(void)
 {
 	/*wait for the engine to be totally idle*/
-	if (!si->settings.dma_acc)
-		nv_acc_wait_idle();
-	else
 	nv_acc_wait_idle_dma();
 }
 

src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c

@@ -28,10 +28,10 @@ These definitions are out of pure lazyness.
 	if (check_overlay_capability(B_##x) == B_OK) return (void *)x; else return (void *)0
 #define CHKA(x) case B_##x: \
 	if (check_acc_capability(B_##x) == B_OK) \
-	{if(!si->settings.dma_acc) return (void *)x##_PIO; else return (void *)x##_DMA;} \
+		return (void *)x##_DMA; \
-	else return (void *)0
+	else						\
-#define CHKS(x) case B_##x: \
+		return (void *)0
-	if(!si->settings.dma_acc) return (void *)x##_PIO; else return (void *)x##_DMA
+#define CHKS(x) case B_##x: return (void *)x##_DMA
 #define HOOK(x) case B_##x: return (void *)x
 #define ZERO(x) case B_##x: return (void *)0
 #define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed
@@ -212,10 +212,9 @@ status_t check_acc_capability(uint32 feature)
 		break;
 	case B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT:
 		msg = "B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT";
-		/* this function is only defined for DMA acceleration,
+		/* this function doesn't support the B_CMAP8 colorspace */
-		 * but doesn't support the B_CMAP8 colorspace */
 		//fixme: checkout B_CMAP8 support sometime, as some cards seem to support it?
-		if (!si->settings.dma_acc || (si->dm.space == B_CMAP8))
+		if (si->dm.space == B_CMAP8)
 		{
 			LOG(4, ("Acc: Not exporting hook %s.\n", msg));
 			return B_ERROR;

src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c

@@ -4,7 +4,7 @@
 
 	Other authors:
 	Mark Watson,
-	Rudolf Cornelissen 10/2002-4/2006.
+	Rudolf Cornelissen 10/2002-6/2008.
 */
 
 #define MODULE_BIT 0x00800000
@@ -40,8 +40,8 @@ static status_t init_common(int the_fd) {
 	// LOG is now available, si !NULL
 	LOG(4,("init_common: logmask 0x%08x, memory %dMB, hardcursor %d, usebios %d, switchhead %d\n",
 		si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead));
-	LOG(4,("init_common: dumprom %d, pgm_panel %d, dma_acc %d, tv_output %d, vga_on_tv %d\n",
+	LOG(4,("init_common: dumprom %d, pgm_panel %d, tv_output %d, vga_on_tv %d\n",
-		si->settings.dumprom, si->settings.pgm_panel, si->settings.dma_acc, si->settings.tv_output, si->settings.vga_on_tv));
+		si->settings.dumprom, si->settings.pgm_panel, si->settings.tv_output, si->settings.vga_on_tv));
 	LOG(4,("init_common: force_sync %d, gpu_clk %dMhz, ram_clk %dMhz, force_ws %d\n",
 		si->settings.force_sync, si->settings.gpu_clk, si->settings.ram_clk, si->settings.force_ws));
 

src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c

@@ -6,7 +6,7 @@
 	Other authors:
 	Mark Watson,
 	Apsed,
-	Rudolf Cornelissen 11/2002-10/2007
+	Rudolf Cornelissen 11/2002-6/2008
 */
 
 #define MODULE_BIT 0x00200000
@@ -295,9 +295,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 //no acc support for G8x yet!
 if (si->ps.card_arch < NV50A)
 {
-	if (!si->settings.dma_acc)
-		nv_acc_init();
-	else
 	nv_acc_init_dma();
 }
 	/* set up overlay unit for this mode */

src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile

@@ -6,7 +6,6 @@ UsePrivateHeaders graphics ;
 UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ;
 
 StaticLibrary libnvidia_gpgpu_engine.a :
-	nv_acc.c
 	nv_acc_dma.c
 	nv_bes.c
 	nv_brooktreetv.c

src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h

@@ -104,18 +104,6 @@ status_t nv_crtc2_start_tvout(void);
 
 /* acceleration functions */
 status_t check_acc_capability(uint32 feature);
-status_t nv_acc_init(void);
-void nv_acc_assert_fifo(void);
-status_t nv_acc_setup_blit(void);
-status_t nv_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 );
-status_t nv_acc_setup_rectangle(uint32 color);
-status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
-status_t nv_acc_setup_rect_invert(void);
-status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
-status_t nv_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32);
-status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
-	uint16 xd,uint16 yd,uint16 wd,uint16 hd);
-status_t nv_acc_wait_idle(void);
 /* DMA versions */
 status_t nv_acc_wait_idle_dma(void);
 status_t nv_acc_init_dma(void);

src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c

@@ -129,7 +129,6 @@ static nv_settings sSettings = { // see comments in nvidia_gpgpu.settings
 	true,       			// hardcursor
 	false,					// switchhead
 	true,					// pgm_panel
-	true,					// dma_acc
 	false,					// vga_on_tv
 	false,					// force_sync
 	false,					// force_ws
@@ -1146,8 +1145,6 @@ init_driver(void)
 			"switchhead", false, false);
 		sSettings.pgm_panel = get_driver_boolean_parameter(settings,
 			"pgm_panel", false, false);
-		sSettings.dma_acc = get_driver_boolean_parameter(settings,
-			"dma_acc", false, false);
 		sSettings.vga_on_tv = get_driver_boolean_parameter(settings,
 			"vga_on_tv", false, false);
 		sSettings.force_sync = get_driver_boolean_parameter(settings,

src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings

@@ -17,7 +17,6 @@ hardcursor	true			# if true use on-chip cursor capabilities
 #logmask	0x08000604	# log overlay use in full to file (in home folder)
 #logmask	0xffffffff		# log everything to file (in home folder)
 switchhead	false			# switch head assignment (dualhead cards only)
-dma_acc	true			# if true enable DMA cmd fetching for 2D acc (instead of using PIO)
 #tv_output	0			# disabled or 0 = autodetect, 1 = Y/C (and CVBS if possible), 2 = CVBS
 force_sync	false			# if true forces 3D rendering to be synchronized to the vertical retrace
 force_ws	false			# if true forces widescreen type detection for all connected screens