From 715a9925f12bb62e6a86b7f8505d438390a503a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Revol?= Date: Thu, 13 Aug 2009 21:09:48 +0000 Subject: [PATCH] [ARM] Move ARM MMU definitions to a separate header file. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32332 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- headers/private/kernel/arch/arm/arm_mmu.h | 67 +++++++++++++++++++++++ src/system/boot/platform/u-boot/mmu.cpp | 56 +------------------ 2 files changed, 68 insertions(+), 55 deletions(-) create mode 100644 headers/private/kernel/arch/arm/arm_mmu.h diff --git a/headers/private/kernel/arch/arm/arm_mmu.h b/headers/private/kernel/arch/arm/arm_mmu.h new file mode 100644 index 0000000000..5ceaa10216 --- /dev/null +++ b/headers/private/kernel/arch/arm/arm_mmu.h @@ -0,0 +1,67 @@ +#ifndef _ARCH_ARM_ARM_MMU_H +#define _ARCH_ARM_ARM_MMU_H + +/* + * generic arm mmu definitions + */ + + +/* + * defines for the page directory (aka Master/Section Table) + */ + +#define MMU_L1_TYPE_COARSEPAGETABLE 0x1 + //only type used in Haiku by now (4k pages) + +// coarse pagetable entry : +// +// 31 10 9 8 5 432 10 +// | page table address |?| domain |000|01 +// +// the domain is not used so and the ? is implementation specified... have not +// found it in the cortex A8 reference... so I set t to 0 +// page table must obviously be on multiple of 1KB + +#define MMU_L1_TYPE_SECTION 0x2 + //map 1MB directly instead of using a page table (not used) +#define MMU_L1_TYPE_FINEEPAGETABLE 0x3 + //map 1kb pages (not used and not supported on newer ARMs) + +/* + * L2-Page descriptors... now things get really complicated... + * there are three different types of pages large pages (64KB) and small(4KB) + * and "small extended". + * only small extende is used by now.... + * and there is a new and a old format of page table entries + * I will use the old format... + */ + +#define MMU_L2_TYPE_SMALLEXT 0x3 +// for B C and TEX see ARM arm B4-11 +#define MMU_L2_FLAG_B 0x4 +#define MMU_L2_FLAG_C 0x8 +#define MMU_L2_FLAG_TEX 0 // use 0b000 as TEX +#define MMU_L2_FLAG_AP_RW 0x30 // allow read and write for user and system +// #define MMU_L2_FLAG_AP_ + + +#define MMU_L1_TABLE_SIZE (4096 * 4) + //4096 entries (one entry per MB) -> 16KB +#define MMU_L2_COARSE_TABLE_SIZE (256 * 4) + //256 entries (one entry per 4KB) -> 1KB + + +/* + * definitions for CP15 r1 + */ + +#define CR_R1_MMU 0x1 // enable MMU +#define CP_R1_XP 0x800000 // if XP=0 then use backwards comaptible + // translation tables + + + + + + +#endif /* _ARCH_ARM_ARM_MMU_H */ diff --git a/src/system/boot/platform/u-boot/mmu.cpp b/src/system/boot/platform/u-boot/mmu.cpp index 5b566627e6..711c192fdf 100644 --- a/src/system/boot/platform/u-boot/mmu.cpp +++ b/src/system/boot/platform/u-boot/mmu.cpp @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -66,61 +67,6 @@ TODO: - - - - - -//defines for the page directory (aka Master/Section Table) -#define MMU_L1_TYPE_COARSEPAGETABLE 0x1//only type used in Haiku by now (4k pages) -//coarse pagetable entry : -// -//31 10 9 8 5 432 10 -//| page table address |?| domain |000|01 -// -// the domain is not used so and the ? is implementation specified... have not -// found it in the cortex A8 reference... so I set t to 0 -// page table must obviously be on multiple of 1KB - -#define MMU_L1_TYPE_SECTION 0x2//map 1MB directly instead of using a page table (not used) -#define MMU_L1_TYPE_FINEEPAGETABLE 0x3//map 1kb pages (not used and not supported on newer ARMs) - - - - -/* -L2-Page descriptors... now things get really complicated... -there are three different types of pages large pages (64KB) and small(4KB) and "small extended" -only small extende is used by now.... -and there is a new and a old format of page table entries I will use the old format... -*/ - -#define MMU_L2_TYPE_SMALLEXT 0x3 -//for B C and TEX see ARM arm B4-11 -#define MMU_L2_FLAG_B 0x4 -#define MMU_L2_FLAG_C 0x8 -#define MMU_L2_FLAG_TEX 0 //use 0b000 as TEX -#define MMU_L2_FLAG_AP_RW 0x30 // allow read and write for user and system -//#define MMU_L2_FLAG_AP_ - - -#define MMU_L1_TABLE_SIZE (4096 * 4) //4096 entries (one entry per MB) -> 16KB -#define MMU_L2_COARSE_TABLE_SIZE (256 * 4)//256 entries (one entry per 4KB) -> 1KB - - - - - - - -//definitions for CP15 r1 -#define CR_R1_MMU 0x1 //enable MMU -#define CP_R1_XP 0x800000 //if XP=0 then use backwards comaptible translation tables - - - - - /* *defines a block in memory */