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Use correct PCI register base address for newer Radeon chips

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* Radeon chips since Bonaire use a different PCI register base
  address. Select the correct one depending on chipset generation
  (values from Linux driver).

* Makes radeon_hd work for newer APUs/GPUs (tested with Kabini APU).
This commit is contained in:
Julian Harnath
2014-08-28 22:21:50 +02:00
parent 49b9fce5ec
commit 72ec5a3630
2 changed files with 13 additions and 3 deletions
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src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
+13 -2
View File
@@ -517,6 +517,16 @@ radeon_hd_getbios_avivo(radeon_info &info)
} }
static uint32
radeon_hd_pci_bar_mmio(uint16 chipsetID)
{
if (chipsetID < RADEON_BONAIRE)
return 2;
else
return 5;
}
status_t status_t
radeon_hd_init(radeon_info &info) radeon_hd_init(radeon_info &info)
{ {
@@ -542,9 +552,10 @@ radeon_hd_init(radeon_info &info)
// *** Map Memory mapped IO // *** Map Memory mapped IO
AreaKeeper mmioMapper; AreaKeeper mmioMapper;
const uint32 pciBarMmio = radeon_hd_pci_bar_mmio(info.chipsetID);
info.registers_area = mmioMapper.Map("radeon hd mmio", info.registers_area = mmioMapper.Map("radeon hd mmio",
info.pci->u.h0.base_registers[PCI_BAR_MMIO], info.pci->u.h0.base_registers[pciBarMmio],
info.pci->u.h0.base_register_sizes[PCI_BAR_MMIO], info.pci->u.h0.base_register_sizes[pciBarMmio],
B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
(void**)&info.registers); (void**)&info.registers);
if (mmioMapper.InitCheck() < B_OK) { if (mmioMapper.InitCheck() < B_OK) {
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd_private.h
-1
View File
@@ -21,7 +21,6 @@
// PCI Base Address Registers // PCI Base Address Registers
#define PCI_BAR_FB 0 #define PCI_BAR_FB 0
#define PCI_BAR_MMIO 2
#define RADEON_BIOS8(adr, v) (adr[v]) #define RADEON_BIOS8(adr, v) (adr[v])
#define RADEON_BIOS16(adr, v) ((adr[v]) | (adr[(v) + 1] << 8)) #define RADEON_BIOS16(adr, v) ((adr[v]) | (adr[(v) + 1] << 8))