From 730ebb158cb546bd84796b8dd86b9cbc71edd778 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Wed, 11 Jun 2008 18:14:15 +0000 Subject: [PATCH] removed all pre-NV20 refs, removed all TVout stuff except clearing some flags, re-enabled force_ws option, force_ws is now default true, pgm_panel is now default false. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25929 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../graphics/nvidia_gpgpu/DriverInterface.h | 44 - .../accelerants/nvidia_gpgpu/InitAccelerant.c | 9 +- .../nvidia_gpgpu/ProposeDisplayMode.c | 126 +- .../accelerants/nvidia_gpgpu/SetDisplayMode.c | 115 +- .../accelerants/nvidia_gpgpu/engine/Jamfile | 1 - .../nvidia_gpgpu/engine/nv_acc_dma.c | 241 +-- .../nvidia_gpgpu/engine/nv_brooktreetv.c | 1749 ----------------- .../accelerants/nvidia_gpgpu/engine/nv_crtc.c | 232 +-- .../nvidia_gpgpu/engine/nv_crtc2.c | 205 +- .../nvidia_gpgpu/engine/nv_general.c | 49 +- .../nvidia_gpgpu/engine/nv_globals.h | 6 - .../accelerants/nvidia_gpgpu/engine/nv_info.c | 636 ++---- .../nvidia_gpgpu/engine/nv_proto.h | 12 - .../drivers/graphics/nvidia_gpgpu/driver.c | 13 +- .../nvidia_gpgpu/nvidia_gpgpu.settings | 7 +- 15 files changed, 229 insertions(+), 3216 deletions(-) delete mode 100644 src/add-ons/accelerants/nvidia_gpgpu/engine/nv_brooktreetv.c diff --git a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h b/headers/private/graphics/nvidia_gpgpu/DriverInterface.h index 8881d16108..c8d4b7f265 100644 --- a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h +++ b/headers/private/graphics/nvidia_gpgpu/DriverInterface.h @@ -73,18 +73,6 @@ enum { /* card_type in order of date of NV chip design */ enum { - NV04 = 0, - NV05, - NV05M64, - NV06, - NV10, - NV11, - NV11M, - NV15, - NV17, - NV17M, - NV18, - NV18M, NV20, NV25, NV28, @@ -118,27 +106,6 @@ enum { NV50A }; -/* card info - information gathered from PINS (and other sources) */ -enum -{ // tv_encoder_type in order of capability (more or less) - NONE = 0, - CH7003, - CH7004, - CH7005, - CH7006, - CH7007, - CH7008, - SAA7102, - SAA7103, - SAA7104, - SAA7105, - BT868, - BT869, - CX25870, - CX25871, - NVIDIA -}; - /* handles to pre-defined engine commands */ #define NV_ROP5_SOLID 0x00000000 /* 2D */ #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ @@ -214,12 +181,10 @@ typedef struct { // apsed, see comments in nv.settings // for accelerant uint32 logmask; uint32 memory; - uint32 tv_output; bool usebios; bool hardcursor; bool switchhead; bool pgm_panel; - bool vga_on_tv; bool force_sync; bool force_ws; uint32 gpu_clk; @@ -287,7 +252,6 @@ typedef struct { display_mode dm; /* current display mode configuration: head1 */ uint32 dpms_flags; /* current DPMS mode */ bool acc_mode; /* signals (non)accelerated mode */ - bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ /*frame buffer config - for BDirectScreen*/ @@ -343,13 +307,6 @@ typedef struct { bool i2c_bus1; /* we have a wired I2C bus 1 on board */ bool i2c_bus2; /* we have a wired I2C bus 2 on board */ bool i2c_bus3; /* we have a wired I2C bus 3 on board */ - struct - { - uint32 type; /* see tvchip_type enum above */ - uint8 version; /* chip silicon version */ - uint8 bus; /* I2C bus on which TVout chip resides */ - uint8 adress; /* I2C adress on which TVout chip resides */ - } tv_encoder; uint8 monitors; /* output devices connection matrix */ bool int_assigned; /* card has a useable INT assigned to it */ status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ @@ -378,7 +335,6 @@ typedef struct { uint32 max_dac2_clock_32; uint32 max_dac2_clock_32dh; bool secondary_head; /* presence of functions */ - bool tvout; bool primary_dvi; bool secondary_dvi; uint32 memory_size; /* memory (in bytes) */ diff --git a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c b/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c index bcd100c3e3..ad5ac9b319 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c @@ -40,8 +40,8 @@ static status_t init_common(int the_fd) { // LOG is now available, si !NULL LOG(4,("init_common: logmask 0x%08x, memory %dMB, hardcursor %d, usebios %d, switchhead %d\n", si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead)); - LOG(4,("init_common: dumprom %d, pgm_panel %d, tv_output %d, vga_on_tv %d\n", - si->settings.dumprom, si->settings.pgm_panel, si->settings.tv_output, si->settings.vga_on_tv)); + LOG(4,("init_common: dumprom %d, pgm_panel %d\n", + si->settings.dumprom, si->settings.pgm_panel)); LOG(4,("init_common: force_sync %d, gpu_clk %dMhz, ram_clk %dMhz, force_ws %d\n", si->settings.force_sync, si->settings.gpu_clk, si->settings.ram_clk, si->settings.force_ws)); @@ -202,11 +202,6 @@ status_t INIT_ACCELERANT(int the_fd) /* ensure DPMS state */ si->dpms_flags = B_DPMS_ON; - /* ensure TVout state: - * TVencoder is on head to be assigned primary, no dualhead switch mode active. */ - //fixme: actually check on what CRTC TVout was active during boot (if any)... - si->dm.flags = TV_PRIMARY; - /* make sure a possible 3D add-on will block rendering and re-initialize itself. * note: update in _this_ order only */ /* SET_DISPLAY_MODE will reset this flag when it's done. */ diff --git a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c b/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c index 352a2c7275..361eec7ac6 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c @@ -4,7 +4,7 @@ Other authors for NV driver: Mark Watson, - Rudolf Cornelissen 9/2002-4/2006 + Rudolf Cornelissen 9/2002-6/2008 */ #define MODULE_BIT 0x00400000 @@ -188,69 +188,60 @@ PROPOSE_DISPLAY_MODE(display_mode *target, const display_mode *low, const displa return result; } - /* disable aspect checks for a requested TVout mode when mode is TVout capable */ - if (!si->ps.tvout - || !(BT_check_tvmode(*target) && (target->flags & TV_BITS))) { - /* check if all connected output devices can display the requested mode's aspect: */ - /* calculate display mode aspect */ - target_aspect = (target->timing.h_display / ((float)target->timing.v_display)); - /* NOTE: - * allow 0.10 difference so 5:4 aspect panels will be able to use 4:3 aspect modes! */ - switch (si->ps.monitors) { - case 0x01: /* digital panel on head 1, nothing on head 2 */ - if (si->ps.panel1_aspect < (target_aspect - 0.10)) { - LOG(4, ("PROPOSEMODE: connected panel1 is not widescreen type, aborted.\n")); - return B_ERROR; - } - break; - case 0x10: /* nothing on head 1, digital panel on head 2 */ - if (si->ps.panel2_aspect < (target_aspect - 0.10)) { - LOG(4, ("PROPOSEMODE: connected panel2 is not widescreen type, aborted.\n")); - return B_ERROR; - } - break; - case 0x11: /* digital panels on both heads */ - if ((si->ps.panel1_aspect < (target_aspect - 0.10)) - || (si->ps.panel2_aspect < (target_aspect - 0.10))) { - LOG(4, ("PROPOSEMODE: not all connected panels are widescreen type, aborted.\n")); - return B_ERROR; - } - break; - default: -#if 0 - /* at least one analog monitor is connected, or nothing detected at all */ - /* (if forcing widescreen type was requested don't block mode) */ - if (target_aspect > 1.34 && !si->settings.force_ws) { - LOG(4, ("PROPOSEMODE: not all output devices can display widescreen modes, aborted.\n")); - return B_ERROR; - } -#endif - break; - } - -// Wide screen modes are pretty common these days... - better use EDID! -#if 0 - /* only export widescreen panel-TV modes when an exact resolution match exists, - * to prevent the modelist from becoming too crowded */ - if (target_aspect > 1.61 && !si->settings.force_ws) { - status_t panel_TV_stat = B_ERROR; - - if (si->ps.tmds1_active) { - if (target->timing.h_display == si->ps.p1_timing.h_display - && target->timing.v_display == si->ps.p1_timing.v_display) - panel_TV_stat = B_OK; - } - if (si->ps.tmds2_active) { - if (target->timing.h_display == si->ps.p2_timing.h_display - && target->timing.v_display == si->ps.p2_timing.v_display) - panel_TV_stat = B_OK; - } - if (panel_TV_stat != B_OK) { - LOG(4, ("PROPOSEMODE: WS panel_TV mode requested but no such TV here, aborted.\n")); + /* check if all connected output devices can display the requested mode's aspect: */ + /* calculate display mode aspect */ + target_aspect = (target->timing.h_display / ((float)target->timing.v_display)); + /* NOTE: + * allow 0.10 difference so 5:4 aspect panels will be able to use 4:3 aspect modes! */ + switch (si->ps.monitors) { + case 0x01: /* digital panel on head 1, nothing on head 2 */ + if (si->ps.panel1_aspect < (target_aspect - 0.10)) { + LOG(4, ("PROPOSEMODE: connected panel1 is not widescreen type, aborted.\n")); return B_ERROR; } + break; + case 0x10: /* nothing on head 1, digital panel on head 2 */ + if (si->ps.panel2_aspect < (target_aspect - 0.10)) { + LOG(4, ("PROPOSEMODE: connected panel2 is not widescreen type, aborted.\n")); + return B_ERROR; + } + break; + case 0x11: /* digital panels on both heads */ + if ((si->ps.panel1_aspect < (target_aspect - 0.10)) + || (si->ps.panel2_aspect < (target_aspect - 0.10))) { + LOG(4, ("PROPOSEMODE: not all connected panels are widescreen type, aborted.\n")); + return B_ERROR; + } + break; + default: + /* at least one analog monitor is connected, or nothing detected at all */ + /* (if forcing widescreen type was requested don't block mode) */ + if (target_aspect > 1.34 && !si->settings.force_ws) { + LOG(4, ("PROPOSEMODE: not all output devices can display widescreen modes, aborted.\n")); + return B_ERROR; + } + break; + } + + /* only export widescreen panel-TV modes when an exact resolution match exists, + * to prevent the modelist from becoming too crowded */ + if (target_aspect > 1.61 && !si->settings.force_ws) { + status_t panel_TV_stat = B_ERROR; + + if (si->ps.tmds1_active) { + if (target->timing.h_display == si->ps.p1_timing.h_display + && target->timing.v_display == si->ps.p1_timing.v_display) + panel_TV_stat = B_OK; + } + if (si->ps.tmds2_active) { + if (target->timing.h_display == si->ps.p2_timing.h_display + && target->timing.v_display == si->ps.p2_timing.v_display) + panel_TV_stat = B_OK; + } + if (panel_TV_stat != B_OK) { + LOG(4, ("PROPOSEMODE: WS panel_TV mode requested but no such TV here, aborted.\n")); + return B_ERROR; } -#endif } /* check if panel(s) can display the requested resolution (if connected) */ @@ -444,23 +435,10 @@ PROPOSE_DISPLAY_MODE(display_mode *target, const display_mode *low, const displa if (!(target->flags & DUALHEAD_CAPABLE)) target->flags &= ~DUALHEAD_BITS; - /* set TV_CAPABLE if suitable: pixelclock is not important (defined by TVstandard) */ - if (si->ps.tvout && BT_check_tvmode(*target)) - target->flags |= TV_CAPABLE; - /* if not TVout capable card clear TVout flags */ if (!(target->flags & TV_CAPABLE)) target->flags &= ~TV_BITS; - /* make sure TV head assignment is sane */ - if (target->flags & TV_BITS) { - if (!si->ps.secondary_head) - target->flags |= TV_PRIMARY; - else if ((target->flags & DUALHEAD_BITS) == DUALHEAD_OFF) - target->flags |= TV_PRIMARY; - } else - target->flags &= ~TV_PRIMARY; - /* set HARDWARE_CURSOR mode if suitable */ if (si->settings.hardcursor) target->flags |= B_HARDWARE_CURSOR; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c b/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c index 68a843fd06..726b9d33f8 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c @@ -62,13 +62,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) // head1_interrupt_enable(false); // if (si->ps.secondary_head) head2_interrupt_enable(false); - /* disable TVout if supported */ -// if (si->ps.tvout) BT_stop_tvout(); - - /* turn off screen(s) _after_ TVout is disabled (if applicable) */ + /* turn off screen(s) */ // head1_dpms(false, false, false, true); // if (si->ps.secondary_head) head2_dpms(false, false, false, true); -// if (si->ps.tvout) BT_dpms(false); /*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/ startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; @@ -86,15 +82,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) LOG(1,("SETMODE: setting DUALHEAD mode\n")); - /* validate flags for secondary TVout */ - //fixme: remove or block on autodetect fail. (is now shutoff) - if ((0) && (target2.flags & TV_BITS)) - { - target.flags &= ~TV_BITS;//still needed for some routines... - target2.flags &= ~TV_BITS; - LOG(1,("SETMODE: blocking TVout: no TVout cable connected!\n")); - } - /* detect which connectors have a CRT connected */ //fixme: 'hot-plugging' for analog monitors removed: remove code as well; //or make it work with digital panels connected as well. @@ -180,10 +167,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) break; } - /* check if we are doing interlaced TVout mode */ - //fixme: we don't support interlaced mode? - si->interlaced_tv_mode = false; - /*set the display(s) pitches*/ // head1_set_display_pitch (); //fixme: seperate for real dualhead modes: @@ -210,9 +193,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) /* set the timing */ // head1_set_timing(target); // head2_set_timing(target2); - - /* TVout support: program TVout encoder and modify CRTC timing */ -// if (si->ps.tvout && (target2.flags & TV_BITS)) BT_setmode(target2); } else /* single head mode */ { @@ -275,9 +255,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) /* set the timing */ // head1_set_timing(target); - /* TVout support: program TVout encoder and modify CRTC timing */ -// if (si->ps.tvout && (target.flags & TV_BITS)) BT_setmode(target); - //fixme: shut-off the videoPLL if it exists... } @@ -493,100 +470,10 @@ status_t SET_DPMS_MODE(uint32 dpms_flags) return B_ERROR; } - /* CRTC used for TVout needs specific DPMS programming */ - if (si->dm.flags & TV_BITS) - { - /* TV_PRIMARY tells us that the head to be used with TVout is the head that's - * actually assigned as being the primary head at powerup: - * so non dualhead-mode-dependant, and not 'fixed' CRTC1! */ - if (si->dm.flags & TV_PRIMARY) - { - LOG(4,("SET_DPMS_MODE: tuning primary head DPMS settings for TVout compatibility\n")); - - if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - { - if (!(si->settings.vga_on_tv)) - { - /* block VGA output on head displaying on TV */ - /* Note: - * this specific sync setting is required: Vsync is used to keep TVout - * synchronized to the CRTC 'vertically' (otherwise 'rolling' occurs). - * This leaves Hsync only for shutting off the VGA screen. */ - h1h = false; - h1v = true; - /* block panel DPMS updates */ - do_p1 = false; - } - else - { - /* when concurrent VGA is used alongside TVout on a head, DPMS is safest - * applied this way: Vsync is needed for stopping TVout successfully when - * a (new) modeswitch occurs. - * (see routine BT_stop_tvout() in nv_brooktreetv.c) */ - /* Note: - * applying 'normal' DPMS here and forcing Vsync on in the above mentioned - * routine seems to not always be enough: sometimes image generation will - * not resume in that case. */ - h1h = display; - h1v = true; - } - } - else - { - if (!(si->settings.vga_on_tv)) - { - h2h = false; - h2v = true; - do_p2 = false; - } - else - { - h2h = display; - h2v = true; - } - } - } - else - { - LOG(4,("SET_DPMS_MODE: tuning secondary head DPMS settings for TVout compatibility\n")); - - if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - { - if (!(si->settings.vga_on_tv)) - { - h2h = false; - h2v = true; - do_p2 = false; - } - else - { - h2h = display; - h2v = true; - } - } - else - { - if (!(si->settings.vga_on_tv)) - { - h1h = false; - h1v = true; - do_p1 = false; - } - else - { - h1h = display; - h1v = true; - } - } - } - } - /* issue actual DPMS commands as far as applicable */ head1_dpms(display, h1h, h1v, do_p1); if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS)) head2_dpms(display, h2h, h2v, do_p2); - if (si->dm.flags & TV_BITS) - BT_dpms(display); //fixme: //add head2 once we use one driver instance 'per head' (instead of 'per card') diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile b/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile index f243b768da..584e5e339a 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile @@ -8,7 +8,6 @@ UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ; StaticLibrary libnvidia_gpgpu_engine.a : nv_acc_dma.c nv_bes.c - nv_brooktreetv.c nv_crtc.c nv_crtc2.c nv_dac.c diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c index 2179cc3b84..095b01f7cb 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c @@ -1,7 +1,7 @@ /* NV Acceleration functions */ /* Author: - Rudolf Cornelissen 8/2003-9/2007. + Rudolf Cornelissen 8/2003-6/2008. This code was possible thanks to: - the Linux XFree86 NV driver, @@ -270,14 +270,6 @@ status_t nv_acc_init_dma() ACCW(HT_HANDL_13, (0x80000000 | NV_SCALED_IMAGE_FROM_MEMORY)); /* 32bit handle */ ACCW(HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */ - - //2007 3D tests.. - if (si->ps.card_type == NV15) - { - ACCW(HT_HANDL_14, (0x80000000 | NV_TCL_PRIMITIVE_3D)); /* 32bit handle */ - ACCW(HT_VALUE_14, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */ - } - } /* program CTX registers: CTX1 is mostly done later (colorspace dependant) */ @@ -359,201 +351,6 @@ status_t nv_acc_init_dma() * table is located at end of cardRAM (b12-31): * It's adress needs to be at a 4kb boundary! */ } - else - { - /* setup a DMA define for use by command defines below. */ - ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type; - * DMA target node is NVM (non-volatile memory?) - * (instead of doing PCI or AGP transfers) */ - ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */ - ACCW(PR_CTX2_R, ((0x00000000 & 0xfffff000) | 0x00000002)); - /* DMA access type is READ_AND_WRITE; - * memory starts at start of cardRAM (b12-31): - * It's adress needs to be at a 4kb boundary! */ - ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */ - /* setup set '0' for cmd NV_ROP5_SOLID */ - ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_0, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */ - /* setup set '1' for cmd NV_IMAGE_BLACK_RECTANGLE */ - ACCW(PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_1, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_1, 0x00000000); /* method traps disabled */ - /* setup set '2' for cmd NV_IMAGE_PATTERN */ - ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_2, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */ - ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */ - /* setup set '3' for ... */ - if(si->ps.card_arch >= NV10A) - { - /* ... cmd NV10_CONTEXT_SURFACES_2D */ - ACCW(PR_CTX0_3, 0x01008062); /* NVclass $062, nv10+: little endian */ - } - else - { - /* ... cmd NV4_SURFACE */ - ACCW(PR_CTX0_3, 0x01008042); /* NVclass $042, nv10+: little endian */ - } - ACCW(PR_CTX1_3, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_3, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_3, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */ - /* setup set '4' for ... */ - if (si->ps.card_type >= NV11) - { - /* ... cmd NV12_IMAGE_BLIT */ - ACCW(PR_CTX0_4, 0x0100809f); /* NVclass $09f, patchcfg ROP_AND, nv10+: little endian */ - } - else - { - /* ... cmd NV_IMAGE_BLIT */ - ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */ - } - ACCW(PR_CTX1_4, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_4, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_4, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */ - /* setup set '5' for cmd NV4_GDI_RECTANGLE_TEXT */ - ACCW(PR_CTX0_5, 0x0100804a); /* NVclass $04a, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_5, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */ - ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */ - /* setup set '6' ... */ - if (si->ps.card_arch >= NV10A) - { - /* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */ - ACCW(PR_CTX0_6, 0x00000093); /* NVclass $093, nv10+: little endian */ - } - else - { - /* ... for cmd NV4_CONTEXT_SURFACES_ARGB_ZS */ - ACCW(PR_CTX0_6, 0x00000053); /* NVclass $053, nv10+: little endian */ - } - ACCW(PR_CTX1_6, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */ - /* setup set '7' ... */ - if (si->ps.card_arch >= NV10A) - { - /* ... for cmd NV10_DX5_TEXTURE_TRIANGLE */ - ACCW(PR_CTX0_7, 0x0300a094); /* NVclass $094, patchcfg ROP_AND, userclip enable, - * context surface0 valid, nv10+: little endian */ - } - else - { - /* ... for cmd NV4_DX5_TEXTURE_TRIANGLE */ - ACCW(PR_CTX0_7, 0x0300a054); /* NVclass $054, patchcfg ROP_AND, userclip enable, - * context surface0 valid */ - } - ACCW(PR_CTX1_7, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_7, 0x00000000); /* method traps disabled */ - /* setup set '8' ... */ - if (si->ps.card_arch >= NV10A) - { - /* ... for cmd NV10_DX6_MULTI_TEXTURE_TRIANGLE (not used) */ - ACCW(PR_CTX0_8, 0x0300a095); /* NVclass $095, patchcfg ROP_AND, userclip enable, - * context surface0 valid, nv10+: little endian */ - } - else - { - /* ... for cmd NV4_DX6_MULTI_TEXTURE_TRIANGLE (not used) */ - ACCW(PR_CTX0_8, 0x0300a055); /* NVclass $055, patchcfg ROP_AND, userclip enable, - * context surface0 valid */ - } - ACCW(PR_CTX1_8, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */ - /* setup set '9' for cmd NV_SCALED_IMAGE_FROM_MEMORY */ - ACCW(PR_CTX0_9, 0x01018077); /* NVclass $077, patchcfg SRC_COPY, - * context surface0 valid, nv10+: little endian */ - ACCW(PR_CTX1_9, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */ - /* setup set 'A' for cmd NV1_RENDER_SOLID_LIN (not used) */ - ACCW(PR_CTX0_A, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, - * context surface0 valid, nv10+: little endian */ - ACCW(PR_CTX1_A, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */ - //2007 3D tests.. - /* setup set 'B' ... */ - if (si->ps.card_type == NV15) - { - /* ... for cmd NV11_TCL_PRIMITIVE_3D */ - ACCW(PR_CTX0_B, 0x0300a096); /* NVclass $096, patchcfg ROP_AND, userclip enable, - * context surface0 valid, nv10+: little endian */ - ACCW(PR_CTX1_B, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_B, 0x00000000); /* method traps disabled */ - } - /* setup DMA set pointed at by PF_CACH1_DMAI */ - if (0)//si->engine.agp_mode) - { - /* DMA page table present and of linear type; - * DMA class is $002 (b0-11); - * DMA target node is AGP */ - ACCW(PR_CTX0_C, 0x00033002); - } - else - { - /* DMA page table present and of linear type; - * DMA class is $002 (b0-11); - * DMA target node is PCI */ - ACCW(PR_CTX0_C, 0x00023002); - } - ACCW(PR_CTX1_C, 0x000fffff); /* DMA limit: tablesize is 1M bytes */ - ACCW(PR_CTX2_C, (((uint32)((uint8 *)(si->dma_buffer_pci))) | 0x00000002)); - /* DMA access type is READ_AND_WRITE; - * table is located in main system RAM (b12-31): - * It's adress needs to be at a 4kb boundary! */ - - /* set the 3D rendering functions colordepth via BPIXEL's 'depth 2' */ - /* note: - * setting a depth to 'invalid' (zero) makes the engine report - * ready with drawing 'immediately'. */ - //fixme: NV30A and above (probably) needs to be corrected... - switch(si->dm.space) - { - case B_CMAP8: - if (si->ps.card_arch < NV30A) - /* set depth 2: $1 = Y8 */ - ACCW(BPIXEL, 0x00000100); - else - /* set depth 0-1: $1 = Y8, $2 = X1R5G5B5_Z1R5G5B5 */ - ACCW(BPIXEL, 0x00000021); - break; - case B_RGB15_LITTLE: - if (si->ps.card_arch < NV30A) - /* set depth 2: $4 = A1R5G5B5 */ - ACCW(BPIXEL, 0x00000400); - else - /* set depth 0-1: $2 = X1R5G5B5_Z1R5G5B5, $4 = A1R5G5B5 */ - ACCW(BPIXEL, 0x00000042); - break; - case B_RGB16_LITTLE: - if (si->ps.card_arch < NV30A) - /* set depth 2: $5 = R5G6B5 */ - ACCW(BPIXEL, 0x00000500); - else - /* set depth 0-1: $5 = R5G6B5, $a = X1A7R8G8B8_O1A7R8G8B8 */ - ACCW(BPIXEL, 0x000000a5); - break; - case B_RGB32_LITTLE: - case B_RGBA32_LITTLE: - if (si->ps.card_arch < NV30A) - /* set depth 2: $c = A8R8G8B8 */ - ACCW(BPIXEL, 0x00000c00); - else - /* set depth 0-1: $7 = X8R8G8B8_Z8R8G8B8, $e = V8YB8U8YA8 */ - ACCW(BPIXEL, 0x000000e7); - break; - default: - LOG(8,("ACC: init, invalid bit depth\n")); - return B_ERROR; - } - } if (si->ps.card_arch == NV04A) { @@ -921,11 +718,8 @@ status_t nv_acc_init_dma() /* setup sync parameters for NV12_IMAGE_BLIT command for the current mode: * values given are CRTC vertical counter limit values. The NV12 command will wait * for the specified's CRTC's vertical counter to be in between the given values */ - if (si->ps.card_type >= NV11) - { - ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1); - ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1); - } + ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1); + ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1); /*** PFIFO ***/ /* (setup caches) */ @@ -1773,26 +1567,15 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */ } - /* TNT1 has fixed operation mode 'SRCcopy' while the rest can be programmed: */ - if (si->ps.card_type != NV04) - { - /* wait for room in fifo for cmds if needed. */ - if (nv_acc_fifofree_dma(5) != B_OK) return; - /* now setup source bitmap colorspace */ - nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT, 2); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ - /* now setup operation mode to SRCcopy */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000003; /* SetOperation */ - } - else - { - /* wait for room in fifo for cmd if needed. */ - if (nv_acc_fifofree_dma(4) != B_OK) return; - /* now setup source bitmap colorspace */ - nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ - /* TNT1 has fixed operation mode SRCcopy */ - } + /* program operation mode 'SRCcopy' */ + /* wait for room in fifo for cmds if needed. */ + if (nv_acc_fifofree_dma(5) != B_OK) return; + /* now setup source bitmap colorspace */ + nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT, 2); + ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ + /* now setup operation mode to SRCcopy */ + ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000003; /* SetOperation */ + /* now setup fill color (writing 2 32bit words) */ nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_COLOR1A, 1); ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */ diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_brooktreetv.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_brooktreetv.c deleted file mode 100644 index fa7bc12166..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_brooktreetv.c +++ /dev/null @@ -1,1749 +0,0 @@ -/* - Author: - Rudolf Cornelissen 4/2002-11/2005 -*/ - -#define MODULE_BIT 0x00100000 - -#include "nv_std.h" - -#define PRADR 0x88 -#define SCADR 0x8a -#define WR 0x00 -#define RD 0x01 - -enum -{ // TVoutput mode to set - NOT_SUPPORTED = 0, - NTSC640_TST, - NTSC640, - NTSC800, - PAL800_TST, - PAL640, - PAL800, - NTSC720, - PAL720, - NTSC640_OS, - PAL800_OS -}; - -/* Dirk Thierbach's Macro setup for registers 0xda-0xfe. - * (also see http://sourceforge.net/projects/nv-tv-out/) */ -static uint8 BtNtscMacro0 [] = { - 0x0f,0xfc,0x20,0xd0,0x6f,0x0f,0x00,0x00,0x0c,0xf3,0x09, - 0xbd,0x67,0xb5,0x90,0xb2,0x7d,0x00,0x00}; -static uint8 BtNtscMacro1 [] = { - 0x0f,0xfc,0x20,0xd0,0x6f,0x0f,0x00,0x00,0x0c,0xf3,0x09, - 0xbd,0x67,0xb5,0x90,0xb2,0x7d,0x63,0x00}; -static uint8 BtNtscMacro2 [] = { - 0x0f,0xfc,0x20,0xd0,0x6f,0x0f,0x00,0x00,0x0c,0xf3,0x09, - 0xbd,0x6c,0x31,0x92,0x32,0xdd,0xe3,0x00}; -static uint8 BtNtscMacro3 [] = { - 0x0f,0xfc,0x20,0xd0,0x6f,0x0f,0x00,0x00,0x0c,0xf3,0x09, - 0xbd,0x66,0xb5,0x90,0xb2,0x7d,0xe3,0x00}; - -static uint8 BtPalMacro0 [] = { - 0x05,0x57,0x20,0x40,0x6e,0x7e,0xf4,0x51,0x0f,0xf1,0x05, - 0xd3,0x78,0xa2,0x25,0x54,0xa5,0x00,0x00}; -static uint8 BtPalMacro1 [] = { - 0x05,0x57,0x20,0x40,0x6e,0x7e,0xf4,0x51,0x0f,0xf1,0x05, - 0xd3,0x78,0xa2,0x25,0x54,0xa5,0x63,0x00}; - -static uint8 BT_set_macro (int std, int mode) -{ - uint8 stat; - uint8 buffer[21]; - - LOG(4,("Brooktree: Setting Macro:\n")); - - if ((std < 0) | (std > 1) | (mode < 0) | (mode > 3)) - { - LOG(4,("Brooktree: Non existing mode or standard selected, aborting.\n")); - return 0x80; - } - - switch (std) - { - case 0: - /* NTSC */ - switch (mode) - { - case 0: - /* disabled */ - LOG(4,("Brooktree: NTSC, disabled\n")); - memcpy(&buffer[2], &BtNtscMacro0, 19); - break; - case 1: - /* enabled mode 1 */ - LOG(4,("Brooktree: NTSC, mode 1\n")); - memcpy(&buffer[2], &BtNtscMacro1, 19); - break; - case 2: - /* enabled mode 2 */ - LOG(4,("Brooktree: NTSC, mode 2\n")); - memcpy(&buffer[2], &BtNtscMacro2, 19); - break; - case 3: - /* enabled mode 3 */ - LOG(4,("Brooktree: NTSC, mode 3\n")); - memcpy(&buffer[2], &BtNtscMacro3, 19); - break; - } - break; - case 1: - /* PAL */ - switch (mode) - { - case 0: - /* disabled */ - LOG(4,("Brooktree: PAL, disabled\n")); - memcpy(&buffer[2], &BtPalMacro0, 19); - break; - case 1: - case 2: - case 3: - /* enabled */ - LOG(4,("Brooktree: PAL, enabled\n")); - memcpy(&buffer[2], &BtPalMacro1, 19); - break; - } - break; - } - - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select first register to write to */ - buffer[1] = 0xda; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting Macro\n")); - - return stat; -}//end BT_set_macro. - -/* - see if a (possible) BT/CX chip resides at the given adress. - Return zero if no errors occurred. -*/ -static uint8 BT_check (uint8 bus, uint8 adress) -{ - uint8 buffer[3]; - - buffer[0] = adress + WR; - /* set ESTATUS at b'00'; and enable bt chip-outputs - * WARNING: - * If bit0 = 0 is issued below (EN_OUT = disabled), the BT will lock SDA - * after writing adress $A0 (setting EN_XCLK)!!! - * Until a reboot the corresponding I2C bus will be inacessable then!!! */ - buffer[1] = 0xc4; - /* fixme: if testimage 'was' active txbuffer[3] should become 0x05... - * (currently this cannot be detected in a 'foolproof' way so don't touch...) */ - /* (ESTATUS b'0x' means: RX ID and VERSION info later..) */ - buffer[2] = 0x01; - - /* reset status */ - i2c_flag_error (-1); - - /* do check */ - i2c_bstart(bus); - i2c_writebuffer(bus, buffer, sizeof(buffer)); - i2c_bstop(bus); - return i2c_flag_error(0); -} - -/* identify chiptype */ -static uint8 BT_read_type (void) -{ - uint8 id, type, stat; - uint8 buffer[3]; - - /* Make sure a CX (Conexant) chip (if this turns out to be there) is set to - * BT-compatibility mode! (This command will do nothing on a BT chip...) */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select CX reg. for BT-compatible readback, video still off */ - buffer[1] = 0x6c; - /* set it up */ - buffer[2] = 0x02; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* abort on errors */ - stat = i2c_flag_error(0); - if (stat) return stat; - - /* Do actual readtype command */ - i2c_bstart(si->ps.tv_encoder.bus); - /* issue I2C read command */ - i2c_writebyte(si->ps.tv_encoder.bus, si->ps.tv_encoder.adress + RD); - /* receive 1 byte; - * ACK level to TX after last byte to RX should be 1 (= NACK) (see I2C spec). */ - /* note: - * While the BT's don't care, CX chips will block the SDA line if - * an ACK gets sent! */ - id = i2c_readbyte(si->ps.tv_encoder.bus, true); - i2c_bstop(si->ps.tv_encoder.bus); - /* abort on errors */ - stat = i2c_flag_error(0); - if (stat) return stat; - - /* check type to be supported one */ - type = (id & 0xe0) >> 5; - if (type > 3) - { - LOG(4,("Brooktree: Found unsupported encoder type %d, aborting.\n", type)); - return 0x80; - } - - /* inform driver about TV encoder found */ - si->ps.tvout = true; - si->ps.tv_encoder.type = BT868 + type; - si->ps.tv_encoder.version = id & 0x1f; - - return stat; -} - -bool BT_probe() -{ - uint8 bus; - bool btfound = false; - bool *i2c_bus = &(si->ps.i2c_bus0); - - LOG(4,("Brooktree: Checking wired I2C bus(ses) for first possible TV encoder...\n")); - for (bus = 0; bus < 3; bus++) - { - if (i2c_bus[bus] && !btfound) - { - /* try primary adress on bus */ - if (!BT_check(bus, PRADR)) - { - btfound = true; - si->ps.tv_encoder.adress = PRADR; - si->ps.tv_encoder.bus = bus; - } - else - { - /* try secondary adress on bus */ - if (!BT_check(bus, SCADR)) - { - btfound = true; - si->ps.tv_encoder.adress = SCADR; - si->ps.tv_encoder.bus = bus; - } - } - } - } - - /* identify exact TV encoder type */ - if (btfound) - { - /* if errors are found, retry */ - /* note: - * NACK: occurs on some ASUS V7700 GeForce cards! - * (apparantly the video-in chip or another chip resides at 'BT' adresses - * there..) */ - uint8 stat; - uint8 cnt = 0; - while ((stat = BT_read_type()) && (cnt < 3)) - { - /* don't retry on unsupported chiptype */ - if (stat == 0x80) - { - btfound = 0; - break; - } - cnt++; - } - if (stat & 0x7f) - { - LOG(4,("Brooktree: Too much errors occurred, aborting.\n")); - btfound = 0; - } - } - - if (btfound) - LOG(4,("Brooktree: Found TV encoder on bus %d, adress $%02x\n", - si->ps.tv_encoder.bus, si->ps.tv_encoder.adress)); - else - LOG(4,("Brooktree: No TV encoder Found\n")); - - return btfound; -} - -static uint8 BT_init_PAL640() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting PAL 640x480 desktop mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to - buffer[2] = 0x60; - buffer[3] = 0x80; - buffer[4] = 0x8a; - buffer[5] = 0xa6; - buffer[6] = 0x68; - buffer[7] = 0xc1; - buffer[8] = 0x2e; - buffer[9] = 0xf2; - buffer[10] = 0x27; - buffer[11] = 0x00; - buffer[12] = 0xb0; - buffer[13] = 0x0a; - buffer[14] = 0x0b; - buffer[15] = 0x71; - buffer[16] = 0x5a; - buffer[17] = 0xe0; - buffer[18] = 0x36; - buffer[19] = 0x00; - buffer[20] = 0x50; - buffer[21] = 0x72; - buffer[22] = 0x1c; - buffer[23] = 0x8d; //chip-pin CLKI is pixel clock (only non-default here!) - buffer[24] = 0x24; - buffer[25] = 0xf0; - buffer[26] = 0x58; - buffer[27] = 0x81; - buffer[28] = 0x49; - buffer[29] = 0x8c; - buffer[30] = 0x0c; - buffer[31] = 0x8c; - buffer[32] = 0x79; - buffer[33] = 0x26; - buffer[34] = 0x00; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode PAL640\n")); - - return stat; -}//end BT_init_PAL640. - -static uint8 BT_init_PAL800() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting PAL 800x600 desktop mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to - buffer[2] = 0x00; - buffer[3] = 0x20; - buffer[4] = 0xaa; - buffer[5] = 0xca; - buffer[6] = 0x9a; - buffer[7] = 0x0d; - buffer[8] = 0x29; - buffer[9] = 0xfc; - buffer[10] = 0x39; - buffer[11] = 0x00; - buffer[12] = 0xc0; - buffer[13] = 0x8c; - buffer[14] = 0x03; - buffer[15] = 0xee; - buffer[16] = 0x5f; - buffer[17] = 0x58; - buffer[18] = 0x3a; - buffer[19] = 0x66; - buffer[20] = 0x96; - buffer[21] = 0x00; - buffer[22] = 0x00; - buffer[23] = 0x90; //chip-pin CLKI is pixel clock (only non-default here!) - buffer[24] = 0x24; - buffer[25] = 0xf0; - buffer[26] = 0x57; - buffer[27] = 0x80; - buffer[28] = 0x48; - buffer[29] = 0x8c; - buffer[30] = 0x18; - buffer[31] = 0x28; - buffer[32] = 0x87; - buffer[33] = 0x1f; - buffer[34] = 0x00; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode PAL800\n")); - - return stat; -}//end BT_init_PAL800. - -static uint8 BT_init_NTSC640() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting NTSC 640x480 desktop mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to - buffer[2] = 0x00; - buffer[3] = 0x80; - buffer[4] = 0x84; - buffer[5] = 0x96; - buffer[6] = 0x60; - buffer[7] = 0x7d; - buffer[8] = 0x22; - buffer[9] = 0xd4; - buffer[10] = 0x27; - buffer[11] = 0x00; - buffer[12] = 0x10; - buffer[13] = 0x7e; - buffer[14] = 0x03; - buffer[15] = 0x58; - buffer[16] = 0x4b; - buffer[17] = 0xe0; - buffer[18] = 0x36; - buffer[19] = 0x92; - buffer[20] = 0x54; - buffer[21] = 0x0e; - buffer[22] = 0x88; - buffer[23] = 0x8c; //chip-pin CLKI is pixel clock (only non-default here!) - buffer[24] = 0x0a; - buffer[25] = 0xe5; - buffer[26] = 0x76; - buffer[27] = 0x79; - buffer[28] = 0x44; - buffer[29] = 0x85; - buffer[30] = 0x00; - buffer[31] = 0x00; - buffer[32] = 0x80; - buffer[33] = 0x20; - buffer[34] = 0x00; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode NTSC640\n")); - - return stat; -}//end BT_init_NTSC640. - -static uint8 BT_init_NTSC800() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting NTSC 800x600 desktop mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to - buffer[2] = 0xa0; - buffer[3] = 0x20; - buffer[4] = 0xb6; - buffer[5] = 0xce; - buffer[6] = 0x84; - buffer[7] = 0x55; - buffer[8] = 0x20; - buffer[9] = 0xd8; - buffer[10] = 0x39; - buffer[11] = 0x00; - buffer[12] = 0x70; - buffer[13] = 0x42; - buffer[14] = 0x03; - buffer[15] = 0xdf; - buffer[16] = 0x56; - buffer[17] = 0x58; - buffer[18] = 0x3a; - buffer[19] = 0xcd; - buffer[20] = 0x9c; - buffer[21] = 0x14; - buffer[22] = 0x3b; - buffer[23] = 0x91; //chip-pin CLKI is pixel clock (only non-default here!) - buffer[24] = 0x0a; - buffer[25] = 0xe5; - buffer[26] = 0x74; - buffer[27] = 0x77; - buffer[28] = 0x43; - buffer[29] = 0x85; - buffer[30] = 0xba; - buffer[31] = 0xe8; - buffer[32] = 0xa2; - buffer[33] = 0x17; - buffer[34] = 0x00; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode PAL800\n")); - - return stat; -}//end BT_init_NTSC800. - -static uint8 BT_init_PAL720() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting PAL 720x576 overscanning DVD mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to - buffer[2] = 0xf0; - buffer[3] = 0xd0; - buffer[4] = 0x82; - buffer[5] = 0x9c; - buffer[6] = 0x5a; - buffer[7] = 0x31; - buffer[8] = 0x16; - buffer[9] = 0x22; - buffer[10] = 0xa6; - buffer[11] = 0x00; - buffer[12] = 0x78; - buffer[13] = 0x93; - buffer[14] = 0x03; - buffer[15] = 0x71; - buffer[16] = 0x2a; - buffer[17] = 0x40; - buffer[18] = 0x0a; - buffer[19] = 0x00; - buffer[20] = 0x50; - buffer[21] = 0x55; - buffer[22] = 0x55; - buffer[23] = 0x8c; //chip-pin CLKI is pixel clock (only non-default here!) - buffer[24] = 0x24; - buffer[25] = 0xf0; - buffer[26] = 0x59; - buffer[27] = 0x82; - buffer[28] = 0x49; - buffer[29] = 0x8c; - buffer[30] = 0x8e; - buffer[31] = 0xb0; - buffer[32] = 0xe6; - buffer[33] = 0x28; - buffer[34] = 0x00; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode PAL720\n")); - - return stat; -}//end BT_init_PAL720. - -static uint8 BT_init_NTSC720() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting NTSC 720x480 overscanning DVD mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to. - buffer[2] = 0xf0; //lsb h_clk_o: overscan comp = 0, so h_clk_o = 2 * h_clk_i (VSR=2 = scaling=1) - buffer[3] = 0xd0; //lsb h_active: h_active = 720 pixels wide port - buffer[4] = 0x83; //scope: OK hsync_width: (hsync_width / h_clk_o) * 63.55556uS = 4.70uS for NTSC - buffer[5] = 0x98; //scope: OK hburst_begin: (hburst_begin / h_clk_o) * 63.55556uS = 5.3uS for NTSC - buffer[6] = 0x5e; //scope: OK hburst_end: ((hburst_end + 128) / h_clk_o) * 63.55556uS = 7.94uS for NTSC - - //How to find the correct values for h_blank_o and v_blank_o: - // 1. Calculate h_blank_o according to initial setting guideline mentioned below; - // 2. Set v_blank_o in the neighbourhood of $18, so that TV picture does not have ghosts on right side in it while - // horizontal position is about OK; - // 3. Then tune h_blank_o for centered output on scope (look at front porch and back porch); - // 4. Now shift the TV output using Hsync_offset for centered output while looking at TV (in method 'SetBT_Hphase' above); - // 5. If no vertical shivering occurs when image is centered, you're done. Else: - // 6. Modify the RIVA (BeScreen) h_sync_start setting somewhat to get stable centered picture possible on TV AND!: - // 7. Make sure you update the Chrontel horizontal Phase setting also then! - - if (si->ps.tv_encoder.type >= CX25870)//set CX value - { - /* confirmed on NV11 using 4:3 TV and 16:9 TV */ - buffer[7] = 0x0c; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV - //(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC) - } - else //set BT value - { - /* confirmed on TNT1 using 4:3 TV and 16:9 TV */ - buffer[7] = 0x28; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV - //(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC) - } - buffer[8] = 0x18; //try-out; scope: checked against other modes, looks OK. v_blank_o: 1e active line ('pixel') - - buffer[9] = 0xf2; //v_active_o: = (active output lines + 2) / field (on TV) - buffer[10] = 0x26; //lsn = msn h_clk_o; - //b4-5 = msbits h_active; - //b7 = b8 v_avtive_o. - buffer[11] = 0x00; //h_fract is always 0. - buffer[12] = 0x78; //lsb h_clk_i: h_clk_i is horizontal total = 888. - buffer[13] = 0x90; //try-out; lsb h_blank_i: #clks between start sync and new line 1st pixel; copy to VGA delta-sync! - buffer[14] = 0x03; //b2-0 = msn h_clk_i; - //try-out: b3 = msn h_blank_i; - //b4 = vblankdly is always 0. - buffer[15] = 0x0d; //lsb v_lines_i: v_lines_i = 525 - buffer[16] = 0x1a; //try-out; v_blank_i: #input lines between start sync and new line (pixel); copy to VGA delta-sync! - //Make sure though that this value for the BT is *even*, or image will shiver a *lot* horizontally on TV. - buffer[17] = 0xe0; //lsb v_active_i: v_active_i = 480 - buffer[18] = 0x36; //b1-0 = msn v_lines_i; - //b3-2 = msn v_active_i; - //b5-4 = ylpf = 3; - //b7-6 = clpf = 0. - buffer[19] = 0x00; //lsb v_scale: v_scale = off = $1000 - buffer[20] = 0x50; //b5-0 = msn v_scale; - //scope: tuned. b7-6 = msn h_blank_o. - //(((PLL_INT + (PLL_FRACT/65536)) / 6) * 13500000) = PIXEL_CLK = (hor.tot. * v_lines_i * 60Hz) - buffer[21] = 0x98; //lsb PLL fract: PLL fract = 0x6e98 - buffer[22] = 0x6e; //msb PLL fract - buffer[23] = 0x8c; //b5-0 = PLL int: PLL int = 0x0c; - //b6 = by_pll: by_pll = 0; - //b7 = EN_XCLK: chip-pin CLKI is pixel clock. - buffer[24] = 0x0a; //b0 = ni_out is always 0; - //b1 = setup = 1 for NTSC; - //b2 = 625line = 0 for NTSC; - //b3 = vsync_dur = 1 for NTSC; - //b4 = dic_screset is always 0; - //b5 = pal_md = 0 for NTSC; - //b6 = eclip is always 0; - //b7 = reserved (en_scart) is always 0. - buffer[25] = 0xe5; //sync_amp $e5 for NTSC - buffer[26] = 0x75; //bst_amp $74-$76 for NTSC - buffer[27] = 0x78; //mcr: r-y $77-$79 for NTSC - buffer[28] = 0x44; //mcb: b-y $43-$44 for NTSC - buffer[29] = 0x85; //my: y $85 for NTSC - buffer[30] = 0x3c; //lsb msc: msc b31-0: NTSC formula: ((3579545 / pixelclk) * 2^32) = MSC - buffer[31] = 0x91; //msc = $20c2913c - buffer[32] = 0xc2; - buffer[33] = 0x20; //msb msc. - buffer[34] = 0x00; //phase_off always $00 - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode NTSC720\n")); - - return stat; -}//end BT_init_NTSC720. - -static uint8 BT_init_PAL800_OS() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting PAL 800x600 overscanning VCD mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to. - buffer[2] = 0x60; //lsb h_clk_o: overscan comp = 0, so h_clk_o = 2 * h_clk_i (VSR=2 = scaling=1) - buffer[3] = 0x20; //lsb h_active: h_active = 800 pixels wide port - buffer[4] = 0x8b; //scope: OK hsync_width: (hsync_width / h_clk_o) * 64.0uS = 4.70uS for PAL - buffer[5] = 0xa5; //scope: OK hburst_begin: (hburst_begin / h_clk_o) * 64.0uS = 5.6uS for PAL - buffer[6] = 0x6b; //scope: OK hburst_end: ((hburst_end + 128) / h_clk_o) * 64.0uS = 7.97uS for PAL - - //How to find the correct values for h_blank_o and v_blank_o: - // 1. Calculate h_blank_o according to initial setting guideline mentioned below; - // 2. Set v_blank_o in the neighbourhood of $18, so that TV picture does not have ghosts on right side in it while - // horizontal position is about OK; - // 3. Then tune h_blank_o for centered output on scope (look at front porch and back porch); - // 4. Now shift the TV output using Hsync_offset for centered output while looking at TV (in method 'SetBT_Hphase' above); - // 5. If no vertical shivering occurs when image is centered, you're done. Else: - // 6. Modify the RIVA (BeScreen) h_sync_start setting somewhat to get stable centered picture possible on TV AND!: - // 7. Make sure you update the Chrontel horizontal Phase setting also then! - - if (si->ps.tv_encoder.type >= CX25870)//set CX value - { - /* confirmed on NV11 using 4:3 TV and 16:9 TV */ - buffer[7] = 0xf0; - buffer[8] = 0x17; - } - else //set BT value - { - /* confirmed on TNT1 using 4:3 TV and 16:9 TV */ - buffer[7] = 0xd0;//scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV - //(guideline for initial setting: (h_blank_o / h_clk_0) * 64.0uS = 10.0uS for PAL) - buffer[8] = 0x18;//try-out; scope: checked against other modes, looks OK. v_blank_o: 1e active line ('pixel') - } - - buffer[9] = 0x2e; //v_active_o: = (active output lines + 2) / field (on TV) - buffer[10] = 0xb7; //lsn = msn h_clk_o; - //b4-5 = msbits h_active; - //b7 = b8 v_avtive_o. - buffer[11] = 0x00; //h_fract is always 0. - buffer[12] = 0xb0; //lsb h_clk_i: h_clk_i is horizontal total = 944. - - if (si->ps.tv_encoder.type >= CX25870)//set CX value - buffer[13] = 0x20; - else //set BT value - buffer[13] = 0x14;//try-out; lsb h_blank_i: #clks between start sync and new line 1st pixel; copy to VGA delta-sync! - - buffer[14] = 0x03; //b2-0 = msn h_clk_i; - //try-out: b3 = msn h_blank_i; - //b4 = vblankdly is always 0. - buffer[15] = 0x71; //lsb v_lines_i: v_lines_i = 625 - - if (si->ps.tv_encoder.type >= CX25870)//set CX value - buffer[16] = 0x08; - else //set BT value - buffer[16] = 0x2a;//try-out; v_blank_i: #input lines between start sync and new line (pixel); copy to VGA delta-sync! - //Make sure though that this value for the BT is *even*, or image will shiver a *lot* horizontally on TV. - - buffer[17] = 0x58; //lsb v_active_i: v_active_i = 600 - buffer[18] = 0x3a; //b1-0 = msn v_lines_i; - //b3-2 = msn v_active_i; - //b5-4 = ylpf = 3; - //b7-6 = clpf = 0. - buffer[19] = 0x00; //lsb v_scale: v_scale = off = $1000 - buffer[20] = 0x10; //b5-0 = msn v_scale; - //scope: tuned. b7-6 = msn h_blank_o. - //(((PLL_INT + (PLL_FRACT/65536)) / 6) * 13500000) = PIXEL_CLK = (hor.tot. * v_lines_i * 50Hz) - buffer[21] = 0x72; //lsb PLL fract: PLL fract = 0x1c72 - buffer[22] = 0x1c; //msb PLL fract - buffer[23] = 0x8d; //b5-0 = PLL int: PLL int = 0x0d; - //b6 = by_pll: by_pll = 0; - //b7 = EN_XCLK: chip-pin CLKI is pixel clock. - buffer[24] = 0x24; //b0 = ni_out is always 0; - //b1 = setup = 0 for PAL; - //b2 = 625line = 1 for PAL; - //b3 = vsync_dur = 0 for PAL; - //b4 = dic_screset is always 0; - //b5 = pal_md = 1 for PAL; - //b6 = eclip is always 0; - //b7 = reserved (en_scart) is always 0. - buffer[25] = 0xf0; //sync_amp $f0 for PAL - buffer[26] = 0x57; //bst_amp $57-$58 for PAL - buffer[27] = 0x80; //mcr: r-y $80-$81 for PAL - buffer[28] = 0x48; //mcb: b-y $48-$49 for PAL - buffer[29] = 0x8c; //my: y $8c for PAL - buffer[30] = 0x31; //lsb msc: msc b31-0: PAL formula: ((4433619 / pixelclk) * 2^32) = MSC - buffer[31] = 0x8c; //msc = $26798c31 - buffer[32] = 0x79; - buffer[33] = 0x26; //msb msc. - buffer[34] = 0x00; //phase_off always $00 - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode PAL800 OS\n")); - - return stat; -}//end BT_init_PAL800_OS. - -static uint8 BT_init_NTSC640_OS() -{ - uint8 stat; - - uint8 buffer[35]; - - LOG(4,("Brooktree: Setting NTSC 640x480 overscanning VCD mode\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command - buffer[1] = 0x76; //select first bt register to write to. - buffer[2] = 0x20; //lsb h_clk_o: overscan comp = 0, so h_clk_o = 2 * h_clk_i (VSR=2 = scaling=1) - buffer[3] = 0x80; //lsb h_active: h_active = 640 pixels wide port - buffer[4] = 0x74; //scope: OK hsync_width: (hsync_width / h_clk_o) * 63.55556uS = 4.70uS for NTSC - buffer[5] = 0x83; //scope: OK hburst_begin: (hburst_begin / h_clk_o) * 63.55556uS = 5.3uS for NTSC - buffer[6] = 0x44; //scope: OK hburst_end: ((hburst_end + 128) / h_clk_o) * 63.55556uS = 7.94uS for NTSC - - //How to find the correct values for h_blank_o and v_blank_o: - // 1. Calculate h_blank_o according to initial setting guideline mentioned below; - // 2. Set v_blank_o in the neighbourhood of $18, so that TV picture does not have ghosts on right side in it while - // horizontal position is about OK; - // 3. Then tune h_blank_o for centered output on scope (look at front porch and back porch); - // 4. Now shift the TV output using Hsync_offset for centered output while looking at TV (in method 'SetBT_Hphase' above); - // 5. If no vertical shivering occurs when image is centered, you're done. Else: - // 6. Modify the RIVA (BeScreen) h_sync_start setting somewhat to get stable centered picture possible on TV AND!: - // 7. Make sure you update the Chrontel horizontal Phase setting also then! - - buffer[7] = 0xf7; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV: - //(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC) - - if (si->ps.tv_encoder.type >= CX25870)//set CX value - buffer[8] = 0x1d; - else //set BT value - buffer[8] = 0x1c;//try-out; scope: checked against other modes, looks OK. v_blank_o: 1e active line ('pixel') - - buffer[9] = 0xf2; //v_active_o: = (active output lines + 2) / field (on TV) - buffer[10] = 0x26; //lsn = msn h_clk_o; - //b4-5 = msbits h_active; - //b7 = b8 v_avtive_o. - buffer[11] = 0x00; //h_fract is always 0. - buffer[12] = 0x10; //lsb h_clk_i: h_clk_i is horizontal total = 784. - buffer[13] = 0x14; //try-out; lsb h_blank_i: #clks between start sync and new line 1st pixel; copy to VGA delta-sync! - buffer[14] = 0x03; //b2-0 = msn h_clk_i; - //try-out: b3 = msn h_blank_i; - //b4 = vblankdly is always 0. - buffer[15] = 0x0d; //lsb v_lines_i: v_lines_i = 525 - buffer[16] = 0x18; //try-out; v_blank_i: #input lines between start sync and new line (pixel); copy to VGA delta-sync! - //Make sure though that this value for the BT is *even*, or image will shiver a *lot* horizontally on TV. - buffer[17] = 0xe0; //lsb v_active_i: v_active_i = 480 - buffer[18] = 0x36; //b1-0 = msn v_lines_i; - //b3-2 = msn v_active_i; - //b5-4 = ylpf = 3; - //b7-6 = clpf = 0. - buffer[19] = 0x00; //lsb v_scale: v_scale = off = $1000 - buffer[20] = 0x10; //b5-0 = msn v_scale; - //scope: tuned. b7-6 = msn h_blank_o. - //(((PLL_INT + (PLL_FRACT/65536)) / 6) * 13500000) = PIXEL_CLK = (hor.tot. * v_lines_i * 60Hz) - buffer[21] = 0xdb; //lsb PLL fract: PLL fract = 0xf9db - buffer[22] = 0xf9; //msb PLL fract - buffer[23] = 0x8a; //b5-0 = PLL int: PLL int = 0x0a; - //b6 = by_pll: by_pll = 0; - //b7 = EN_XCLK: chip-pin CLKI is pixel clock. - buffer[24] = 0x0a; //b0 = ni_out is always 0; - //b1 = setup = 1 for NTSC; - //b2 = 625line = 0 for NTSC; - //b3 = vsync_dur = 1 for NTSC; - //b4 = dic_screset is always 0; - //b5 = pal_md = 0 for NTSC; - //b6 = eclip is always 0; - //b7 = reserved (en_scart) is always 0. - buffer[25] = 0xe5; //sync_amp $e5 for NTSC - buffer[26] = 0x75; //bst_amp $74-$76 for NTSC - buffer[27] = 0x78; //mcr: r-y $77-$79 for NTSC - buffer[28] = 0x44; //mcb: b-y $43-$44 for NTSC - buffer[29] = 0x85; //my: y $85 for NTSC - buffer[30] = 0x37; //lsb msc: msc b31-0: NTSC formula: ((3579545 / pixelclk) * 2^32) = MSC - buffer[31] = 0x12; //msc = $251b1237 - buffer[32] = 0x1b; - buffer[33] = 0x25; //msb msc. - buffer[34] = 0x00; //phase_off always $00 - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting mode NTSC640 OS\n")); - - return stat; -}//end BT_init_NTSC640_OS. - -static uint8 BT_testsignal(void) -{ - uint8 stat; - - uint8 buffer[3]; - - LOG(4,("Brooktree: Enabling testsignal\n")); - - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select bt register for enabling colorbars and outputs */ - buffer[1] = 0xc4; - /* issue the actual command */ - buffer[2] = 0x05; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting up flickerfilter and outputs\n")); - - return stat; -}//end BT_testsignal. - -static uint8 BT_setup_output(uint8 monstat, uint8 output, uint8 ffilter) -{ - uint8 stat; - - uint8 buffer[7]; - - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select first TV config register to write */ - buffer[1] = 0xc6; - /* input is 24bit mpx'd RGB, BLANK = out, sync = act. hi */ - buffer[2] = 0x98; - /* disable all filters, exept flicker filter */ - buffer[3] = 0x98; - if (!ffilter) - { - /* disable flicker filter */ - buffer[3] = 0xc0; - LOG(4,("Brooktree: Disabling flickerfilter\n")); - } - else - LOG(4,("Brooktree: Enabling flickerfilter\n")); - - /* (disable filters) */ - buffer[4] = 0xc0; - /* (disable filters) */ - buffer[5] = 0xc0; - switch (output) - /* Description of ELSA Erazor III hardware layout: - * (This is the default (recommended) layout by NVIDIA) - * DAC A = CVBS - * DAC B = C (chrominance) - * DAC C = Y (luminance) */ - - /* Description of Diamond VIPER550: - * DAC A = Not connected - * DAC B = C (chrominance) - * DAC C = Y (luminance) - * To be able to connect to CVBS TV's a special cable is supplied: - * This cable connects the Y (DAC C) output to the TV CVBS input. */ - { - case 1: - LOG(4,("Brooktree: Forcing both Y/C and CVBS signals where supported by hardware\n")); - buffer[6] = 0x18; // Y/C and CVBS out if all ports implemented - // in hardware, else only Y/C or CVBS out. - break; - case 2: - LOG(4,("Brooktree: Forcing CVBS signals on all outputs\n")); - buffer[6] = 0x00; // put CVBS on all outputs. Used for cards - break; // with only Y/C out and 'translation cable'. - default: - LOG(4,("Brooktree: Outputting signals according to autodetect status:\n")); - switch (monstat) // only 'autodetect' remains... - { - case 1: - LOG(4,("Brooktree: Only Y connected, outputting CVBS on all outputs\n")); - buffer[6] = 0x00; //only Y connected: must be CVBS! - break; - case 2: - LOG(4,("Brooktree: Only C connected, outputting CVBS on all outputs\n")); - buffer[6] = 0x00; //only C connected: must be CVBS! - break; //(though cable is wired wrong...) - case 5: - LOG(4,("Brooktree: CVBS and only Y connected, outputting CVBS on all outputs\n")); - buffer[6] = 0x00; //CVBS and only Y connected: 2x CVBS! - break; //(officially not supported...) - case 6: - LOG(4,("Brooktree: CVBS and only C connected, outputting CVBS on all outputs\n")); - buffer[6] = 0x00; //CVBS and only C connected: 2x CVBS! - break; //(officially not supported...) - default: - LOG(4,("Brooktree: Outputting both Y/C and CVBS where supported by hardware\n")); - buffer[6] = 0x18; //nothing, or - //Y/C only, or - //CVBS only (but on CVBS output), or - //Y/C and CVBS connected: - //So activate recommended signals. - } - } - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting up flickerfilter and outputs\n")); - - return stat; -}//end BT_setup_output. - -static uint8 BT_setup_hphase(uint8 mode) -{ - uint8 stat, hoffset; - - uint8 buffer[7]; - - LOG(4,("Brooktree: Tuning horizontal phase\n")); - - /* CX needs timing reset (advised on BT also), first 1mS delay needed! */ - snooze(1000); - - /* values below are all tested on TNT1, TNT2 and GeForce2MX */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select first TV output timing register to write */ - buffer[1] = 0x6c; - /* turn on active video & generate timing reset on CX chips! */ - buffer[2] = 0x86; - /* (set fail save values...) */ - buffer[3] = 0x00; //set default horizontal sync offset - buffer[4] = 0x02; //set default horizontal sync width - buffer[5] = 0x00; //set default vertical sync offset - - /* do specific timing setup for all chips and modes: */ - switch (si->ps.card_type) - { - case NV05: - case NV05M64: - case NV15: - /* confirmed TNT2, TNT2M64, GeForce2Ti. - * (8 pixels delayed hpos, so picture more to the right) */ - hoffset = 8; - break; - default: - /* confirmed TNT1, GeForce256, GeForce2MX. - * (std hpos) - * NOTE: It might be that GeForce needs TNT2 offset: - * for now CX chips get seperate extra offset, until sure. - * (CX is only found AFAIK on GeForce cards, no BT tested - * on GeForce yet. CH was tested on GeForce and seemed to - * indicate TNT1 offset was needed.) */ - hoffset = 0; - break; - } - - switch (mode) - { - case NTSC640_TST: - case NTSC640: - if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more... - /* confirmed on TNT1 with BT869 using 4:3 TV and 16:9 TV */ - buffer[3] = (0x1e + hoffset); //set horizontal sync offset - break; - case NTSC800: - if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more... - buffer[3] = (0xe1 + hoffset); //set horizontal sync offset - buffer[4] = 0xc2; - //Vsync offset reg. does not exist on CX: mode is checked and OK. - buffer[5] = 0x40; //set VSync offset (on BT's only) - break; - case PAL640: - if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more... - buffer[3] = (0xa8 + hoffset); - break; - case PAL800_TST: - case PAL800: - if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more... - buffer[3] = (0x2c + hoffset); - break; - case NTSC720: - if (si->ps.tv_encoder.type >= CX25870) - buffer[3] = (0xb2 + hoffset); //set horizontal sync offset CX - else - buffer[3] = (0xd0 + hoffset); //set horizontal sync offset BT - buffer[4] = 0xff; //hsync width = max: - break; //to prevent vertical image 'shivering'. - case PAL720: - buffer[3] = (0xd4 + hoffset); - buffer[4] = 0xff; - break; - case NTSC640_OS: - buffer[3] = (0xc8 + hoffset); - buffer[4] = 0xff; - break; - case PAL800_OS: - if (si->ps.tv_encoder.type >= CX25870) - buffer[3] = (0x78 + hoffset); //set horizontal sync offset CX - else - buffer[3] = (0xc4 + hoffset); //set horizontal sync offset BT - buffer[4] = 0xff; - break; - default: //nothing to be done here... - break; - } - - buffer[6] = 0x01; //set default vertical sync width - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - LOG(4,("Brooktree: I2C errors occurred while setting up h_phase\n")); - - return stat; -}//end BT_setup_hphase. - -static uint8 BT_read_monstat(uint8* monstat) -{ - uint8 stat; - uint8 buffer[3]; - - /* make sure we have the recommended failsafe selected */ - *monstat = 0; - - LOG(4,("Brooktree: Autodetecting connected output devices\n")); - - /* set BT to return connection status in ESTATUS on next read CMD: */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* set ESTATUS at b'01' (return conn.stat.) */ - buffer[1] = 0xc4; - /* and leave chip outputs on. */ - buffer[2] = 0x41; - - /* reset status */ - i2c_flag_error (-1); - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while reading connection status (1)\n")); - return stat; - } - - /* do actual read connection status: */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select register with CHECK_STAT CMD */ - buffer[1] = 0xba; - /* issue actual command. */ - buffer[2] = 0x40; - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while reading connection status (2)\n")); - return stat; - } - - /* CX: Wait 600uS for signals to stabilize (see datasheet) */ - /* warning, note: - * datasheet is in error! 60mS needed!! */ - snooze(60000); - - /* read back updated connection status: */ - buffer[0] = si->ps.tv_encoder.adress + RD; - - /* transmit 1 byte */ - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 1); - - /* receive 1 byte */ - /* ACK level to TX after last byte to RX should be 1 (= NACK) (see I2C spec) - * While the BT's don't care, CX chips will block the SDA line if an ACK gets sent! */ - buffer[0] = 1; - i2c_readbuffer(si->ps.tv_encoder.bus, buffer, 1); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while reading connection status (3)\n")); - return stat; - } - - *monstat = ((buffer[0] & 0xe0) >> 5); - LOG(4,("Brooktree: TV output monitor status = %d\n", *monstat)); - - /* instruct BT to go back to normal operation: */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select register with CHECK_STAT CMD */ - buffer[1] = 0xba; - /* issue actual command. */ - buffer[2] = 0x00; - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while reading connection status (4)\n")); - return stat; - } - - return stat; -}//end BT_read_monstat. - -static uint8 BT_killclk_blackout(void) -{ - uint8 stat; - - uint8 buffer[4]; - - LOG(4,("Brooktree: Killing clock and/or blacking out (blocking output signals)\n")); - - /* reset status */ - i2c_flag_error (-1); - - if (si->ps.tv_encoder.type <= BT869) //BT... - { - /* Only disable external pixelclock input on BT's. - * CX chips will lock the bus if you do this. - * (It looks like the external pixelclock is always OK as long as a valid - * mode is programmed for the TVout chip. This means that disabling the use - * of this clock is not needed anyway. - * If you do disable this input, this pixelclock will rise to about 60Mhz BTW..) */ - - /* disable use of external pixelclock source... */ - /* (should prevent BT for being 'overclocked' by RIVA in VGA-only mode...) */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select BT register for setting EN_XCLK */ - buffer[1] = 0xa0; - /* clear it */ - buffer[2] = 0x00; - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while doing killclk_blackout (1-BT)\n")); - return stat; - } - } - else //CX... - { - /* Disable CX video out (or wild output will be seen on TV..) */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select register in CX */ - buffer[1] = 0x6c; - /* disable active video out. */ - buffer[2] = 0x02; - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while doing killclk_blackout (1-CX)\n")); - return stat; - } - } - - /* black-out TVout while outputs are enabled... */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select first TV config register to write */ - buffer[1] = 0xc4; - /* disable testimage while outputs remain enabled */ - buffer[2] = 0x01; - /* input is 24bit mpx'd RGB, BLANK = in, sync = act. hi */ - buffer[3] = 0x18; - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer)); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while doing killclk_blackout (2)\n")); - return stat; - } - - return stat; -}//end BT_killclk_blackout. - -uint8 BT_dpms(bool display) -{ - uint8 stat; - - uint8 buffer[3]; - - LOG(4,("Brooktree: setting DPMS: ")); - - /* reset status */ - i2c_flag_error (-1); - - /* shutdown all analog electronics... */ - buffer[0] = si->ps.tv_encoder.adress + WR; - /* select first TV config register to write */ - buffer[1] = 0xba; - if (display) - { - /* enable all DACs */ - buffer[2] = 0x00; - LOG(4,("display on\n")); - } - else - { - /* shutdown all DACs */ - buffer[2] = 0x10; - LOG(4,("display off\n")); - } - - i2c_bstart(si->ps.tv_encoder.bus); - i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3); - i2c_bstop(si->ps.tv_encoder.bus); - /* log on errors */ - stat = i2c_flag_error(0); - if (stat) - { - LOG(4,("Brooktree: I2C errors occurred while setting DPMS\n")); - return stat; - } - - return stat; -}//end BT_dpms. - -uint8 BT_check_tvmode(display_mode target) -{ - uint8 status = NOT_SUPPORTED; - uint32 mode = ((target.timing.h_display) | ((target.timing.v_display) << 16)); - - switch (mode) - { - case (640 | (480 << 16)): - if (((target.flags & TV_BITS) == TV_PAL) && (!(target.flags & TV_VIDEO))) - status = PAL640; - if ((target.flags & TV_BITS) == TV_NTSC) - { - if (!(target.flags & TV_VIDEO)) status = NTSC640; - else status = NTSC640_OS; - } - break; - case (768 | (576 << 16)): - if (((target.flags & TV_BITS) == TV_PAL) && (target.flags & TV_VIDEO)) - status = PAL800_OS; - break; - case (800 | (600 << 16)): - if (((target.flags & TV_BITS) == TV_PAL) && (!(target.flags & TV_VIDEO))) - status = PAL800; - if (((target.flags & TV_BITS) == TV_NTSC) && (!(target.flags & TV_VIDEO))) - status = NTSC800; - break; - case (720 | (480 << 16)): - if (((target.flags & TV_BITS) == TV_NTSC) && (target.flags & TV_VIDEO)) - status = NTSC720; - break; - case (720 | (576 << 16)): - if (((target.flags & TV_BITS) == TV_PAL) && (target.flags & TV_VIDEO)) - status = PAL720; - break; - } - - return status; -}//end BT_check_tvmode. - - -/* -//BeTVOut's SwitchRIVAtoTV(vtot) timing formula: (note: vtot = (v_total - 2)) -//----------------------------------------------------------------------------------- -//HORIZONTAL: -//----------- -h_sync_start = h_display; - -//fixme, note, checkout: -//feels like in fact TNT2-M64 nv_crtc.c registerprogramming should be adapted... -if (TNT2-M64) -{ - h_sync_end = h_display + 8; - h_total = h_display + 56; -} -else //TNT1, TNT2, Geforce2... (so default) -{ - h_sync_end = h_display + 16; - h_total = h_display + 48; -} - -//fixme, note, checkout: -//BeTVOut uses two 'tweaks': -// - on TNT2-M64 only: -// register h_blank_e is increased with 1 (so should be done in nv_crtc.c here) -// - 'all cards': -// register h_blank_e b6 = 0 (only influences TNT2-M64 in modes NTSC800 and PAL800). -//----------------------------------------------------------------------------------- -//VERTICAL: -//--------- -v_sync_start = v_display; -v_total = vtot + 2; -v_sync_end = v_total - 1; //(This takes care of the 'cursor trash' on TNT1's...) -//----------------------------------------------------------------------------------- -*/ -static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode) -{ - //fixme if needed: - //pixelclock is not actually pgm'd because PLL is pgm' earlier during setmode... - switch (tvmode) - { - case NTSC640: - case NTSC640_TST: - target->timing.h_display = 640; - target->timing.h_sync_start = 640; - if (si->ps.card_type == NV05M64) - { - target->timing.h_sync_end = 648; - target->timing.h_total = 696; - } - else - { - //fixme if possible: - //see if tweaking h_sync_end can shift picture 8 pixels right to fix - //ws tv's tuning fault (always going for max. compatibility :) - target->timing.h_sync_end = 656; - target->timing.h_total = 688; - } - target->timing.v_display = 480; - target->timing.v_sync_start = 480; - target->timing.v_sync_end = 555; //This prevents 'cursor trash' on TNT1's - target->timing.v_total = 556; //Above 525 because mode scales down - if (si->ps.card_type == NV05M64) - target->timing.pixel_clock = ((696 * 556 * 60) / 1000); - else - target->timing.pixel_clock = ((688 * 556 * 60) / 1000); - break; - case NTSC800: - target->timing.h_display = 800; - target->timing.h_sync_start = 800; - if (si->ps.card_type == NV05M64) - { - target->timing.h_sync_end = 808; - target->timing.h_total = 856; - } - else - { - target->timing.h_sync_end = 816; - target->timing.h_total = 848; - } - target->timing.v_display = 600; - target->timing.v_sync_start = 600; - target->timing.v_sync_end = 685; //This prevents 'cursor trash' on TNT1's - target->timing.v_total = 686; //Above 525 because mode scales down - if (si->ps.card_type == NV05M64) - target->timing.pixel_clock = ((856 * 686 * 60) / 1000); - else - target->timing.pixel_clock = ((848 * 686 * 60) / 1000); - break; - case PAL640: - target->timing.h_display = 640; - target->timing.h_sync_start = 640; - if (si->ps.card_type == NV05M64) - { - target->timing.h_sync_end = 648; - target->timing.h_total = 696; - } - else - { - target->timing.h_sync_end = 656; - target->timing.h_total = 688; - } - target->timing.v_display = 480; - target->timing.v_sync_start = 480; - target->timing.v_sync_end = 570; //This prevents 'cursor trash' on TNT1's - target->timing.v_total = 571; //Below 625 because mode scales up - if (si->ps.card_type == NV05M64) - target->timing.pixel_clock = ((696 * 571 * 50) / 1000); - else - target->timing.pixel_clock = ((688 * 571 * 50) / 1000); - break; - case PAL800: - case PAL800_TST: - target->timing.h_display = 800; - target->timing.h_sync_start = 800; - if (si->ps.card_type == NV05M64) - { - target->timing.h_sync_end = 808; - target->timing.h_total = 856; - } - else - { - target->timing.h_sync_end = 816; - target->timing.h_total = 848; - } - target->timing.v_display = 600; - target->timing.v_sync_start = 600; - target->timing.v_sync_end = 695; //This prevents 'cursor trash' on TNT1's - target->timing.v_total = 696; //Above 625 because mode scales down - if (si->ps.card_type == NV05M64) - target->timing.pixel_clock = ((856 * 696 * 50) / 1000); - else - target->timing.pixel_clock = ((848 * 696 * 50) / 1000); - break; - case NTSC640_OS: - target->timing.h_display = 640; //BT H_ACTIVE - target->timing.h_sync_start = 744; //set for CH/BT compatible TV output - target->timing.h_sync_end = 744+20; //delta is BT H_BLANKI - target->timing.h_total = 784; //BT H_CLKI - target->timing.v_display = 480; //BT V_ACTIVEI - target->timing.v_sync_start = 490; //set for centered sync pulse - target->timing.v_sync_end = 490+25; //delta is BT V_BLANKI - target->timing.v_total = 525; //BT V_LINESI (== 525: 1:1 scaled mode) - target->timing.pixel_clock = ((784 * 525 * 60) / 1000); //refresh - break; - case PAL800_OS: - target->timing.h_display = 768; //H_ACTIVE - if (si->ps.tv_encoder.type <= BT869) - { - /* confirmed on TNT1 using 4:3 TV and 16:9 TV */ - target->timing.h_sync_start = 856; //set for centered TV output - target->timing.h_sync_end = 856+20; //delta is BT H_BLANKI - } - else - { - /* confirmed on NV11 using 4:3 TV and 16:9 TV */ - target->timing.h_sync_start = 848; //set for centered TV output - target->timing.h_sync_end = 848+20; //delta is BT H_BLANKI - } - target->timing.h_total = 944; //BT H_CLKI - target->timing.v_display = 576; //V_ACTIVEI - target->timing.v_sync_start = 579; //set for centered sync pulse - target->timing.v_sync_end = 579+42; //delta is BT V_BLANKI - target->timing.v_total = 625; //BT V_LINESI (== 625: 1:1 scaled mode) - target->timing.pixel_clock = ((944 * 625 * 50) / 1000); //refresh - break; - case NTSC720: - /* (tested on TNT2 with BT869) */ - target->timing.h_display = 720; //H_ACTIVE - if (si->ps.tv_encoder.type <= BT869) - { - /* confirmed on TNT1 using 4:3 TV and 16:9 TV */ - target->timing.h_sync_start = 744; //do not change! - target->timing.h_sync_end = 744+144; //delta is H_sync_pulse - } - else - { - /* confirmed on NV11 using 4:3 TV and 16:9 TV */ - target->timing.h_sync_start = 728; //do not change! - target->timing.h_sync_end = 728+160; //delta is H_sync_pulse - } - target->timing.h_total = 888; //BT H_TOTAL - target->timing.v_display = 480; //V_ACTIVEI - target->timing.v_sync_start = 490; //set for centered sync pulse - target->timing.v_sync_end = 490+26; //delta is V_sync_pulse - target->timing.v_total = 525; //CH V_TOTAL (== 525: 1:1 scaled mode) - target->timing.pixel_clock = ((888 * 525 * 60) / 1000); //refresh - break; - case PAL720: - target->timing.h_display = 720; //BT H_ACTIVE - target->timing.h_sync_start = 744; //set for centered sync pulse - target->timing.h_sync_end = 744+140; //delta is BT H_BLANKI - target->timing.h_total = 888; //BT H_CLKI - target->timing.v_display = 576; //BT V_ACTIVEI - target->timing.v_sync_start = 579; //set for centered sync pulse - target->timing.v_sync_end = 579+42; //delta is BT V_BLANKI - target->timing.v_total = 625; //BT V_LINESI (== 625: 1:1 scaled mode) - target->timing.pixel_clock = ((888 * 625 * 50) / 1000); //refresh - break; - default: - return B_ERROR; - } - - return B_OK; -}//end BT_update_mode_for_gpu. - -/* note: - * tested on ELSA Erazor III 32Mb AGP (TNT2/BT869), - * Diamond Viper V550 16Mb PCI (TNT1/BT869), - * and ASUS V7100 GeForce2 MX200 AGP/32Mb (CH7007). */ -static status_t BT_start_tvout(display_mode tv_target) -{ - /* TV_PRIMARY tells us that the head to be used with TVout is the head that's - * actually assigned as being the primary head at powerup: - * so non dualhead-mode-dependant, and not 'fixed' CRTC1! */ - if (tv_target.flags & TV_PRIMARY) - { - if ((tv_target.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head1_start_tvout(); - else - head2_start_tvout(); - } - else - { - if ((tv_target.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head2_start_tvout(); - else - head1_start_tvout(); - } - - return B_OK; -}//end BT_start_tvout. - -/* note: - * tested on ELSA Erazor III 32Mb AGP (TNT2/BT869), - * Diamond Viper V550 16Mb PCI (TNT1/BT869), - * and ASUS V7100 GeForce2 MX200 AGP/32Mb (CH7007). */ -status_t BT_stop_tvout(void) -{ - /* prevent BT from being overclocked by VGA-only modes & black-out TV-out */ - BT_killclk_blackout(); - - /* TV_PRIMARY tells us that the head to be used with TVout is the head that's - * actually assigned as being the primary head at powerup: - * so non dualhead-mode-dependant, and not 'fixed' CRTC1! */ - if (si->dm.flags & TV_PRIMARY) - { - if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head1_stop_tvout(); - else - head2_stop_tvout(); - } - else - { - if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head2_stop_tvout(); - else - head1_stop_tvout(); - } - - /* fixme if needed: - * a full encoder chip reset could be done here (so after decoupling crtc)... */ - /* (but: beware of the 'locked SDA' syndrome then!) */ - - /* fixme if needed: we _could_ setup a TVout mode and apply the testsignal here... */ - if (0) - { - //set mode (selecting PAL/NTSC according to board wiring for example) etc, then: - BT_testsignal(); - } - - return B_OK; -}//end BT_stop_tvout. - -status_t BT_setmode(display_mode target) -{ - uint8 tvmode, monstat; - /* enable flickerfilter in desktop modes, disable it in video modes. */ - uint8 ffilter = 0; - - /* use a display_mode copy because we might tune it for TVout compatibility */ - display_mode tv_target = target; - - /* preset new TVout mode */ - tvmode = BT_check_tvmode(tv_target); - if (!tvmode) return B_ERROR; - - /* read current output devices connection status */ - BT_read_monstat(&monstat); - - /* (pre)set TV mode */ - /* note: - * Manual config is non-dependent of the state of the PAL hardware input pin; - * Also SDA lockups occur when setting EN_XCLK after autoconfig! - * Make sure PAL_MD=0 for NTSC and PAL_MD = 1 for PAL... */ - switch (tvmode) - { - case NTSC640: - case NTSC640_TST: - ffilter = 1; - BT_init_NTSC640(); - break; - case NTSC800: - ffilter = 1; - BT_init_NTSC800(); - break; - case PAL640: - ffilter = 1; - BT_init_PAL640(); - break; - case PAL800: - case PAL800_TST: - ffilter = 1; - BT_init_PAL800(); - break; - case NTSC640_OS: - BT_init_NTSC640_OS(); - break; - case PAL800_OS: - BT_init_PAL800_OS(); - break; - case NTSC720: - BT_init_NTSC720(); - break; - case PAL720: - BT_init_PAL720(); - break; - } - - /* modify BT Hphase signal to center TV image... */ - BT_setup_hphase(tvmode); - - /* disable Macro mode */ - switch (tvmode) - { - case NTSC640: - case NTSC640_TST: - case NTSC800: - case NTSC640_OS: - case NTSC720: - /* NTSC */ - BT_set_macro (0, 0); - break; - default: - /* PAL */ - BT_set_macro (1, 0); - break; - } - - /* setup output signal routing and flickerfilter */ - BT_setup_output(monstat, (uint8)(si->settings.tv_output), ffilter); - - /* update the GPU CRTC timing for the requested mode */ - BT_update_mode_for_gpu(&tv_target, tvmode); - - /* setup GPU CRTC timing */ - /* TV_PRIMARY tells us that the head to be used with TVout is the head that's - * actually assigned as being the primary head at powerup: - * so non dualhead-mode-dependant, and not 'fixed' CRTC1! */ - if (tv_target.flags & TV_PRIMARY) - { - if ((tv_target.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head1_set_timing(tv_target); - else - head2_set_timing(tv_target); - } - else - { - if ((tv_target.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH) - head2_set_timing(tv_target); - else - head1_set_timing(tv_target); - } - - /* now set GPU CRTC to slave mode */ - BT_start_tvout(tv_target); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c index 02a5abed3c..5f382a0eb0 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c @@ -1,6 +1,6 @@ /* CTRC functionality */ /* Author: - Rudolf Cornelissen 11/2002-2/2006 + Rudolf Cornelissen 11/2002-6/2008 */ #define MODULE_BIT 0x00040000 @@ -29,79 +29,8 @@ status_t nv_crtc_interrupt_enable(bool flag) return result; } -/* doing general fail-safe default setup here */ -//fixme: this is a _very_ basic setup, and it's preliminary... status_t nv_crtc_update_fifo() { - uint8 bytes_per_pixel = 1; - uint32 drain; - - /* we are only using this on >>coldstarted<< cards which really need this */ - //fixme: re-enable or remove after general user confirmation of behaviour... - if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV05M64)) return B_OK; - - /* enable access to primary head */ - set_crtc_owner(0); - - /* set CRTC FIFO low watermark according to memory drain */ - switch(si->dm.space) - { - case B_CMAP8: - bytes_per_pixel = 1; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - bytes_per_pixel = 2; - break; - case B_RGB24_LITTLE: - bytes_per_pixel = 3; - break; - case B_RGB32_LITTLE: - bytes_per_pixel = 4; - break; - } - /* fixme: - * - I should probably include the refreshrate as well; - * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ - drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; - - /* Doesn't work for other than 32bit space (yet?) */ - if (si->dm.space != B_RGB32_LITTLE) - { - /* BIOS defaults */ - CRTCW(FIFO, 0x03); - CRTCW(FIFO_LWM, 0x20); - LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); - return B_OK; - } - - if (drain > (((uint32)1280) * 1024 * 4)) - { - /* set CRTC FIFO burst size for 'smaller' bursts */ - CRTCW(FIFO, 0x01); - /* Instruct CRTC to fetch new data 'earlier' */ - CRTCW(FIFO_LWM, 0x40); - LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 64\n")); - } - else - { - if (drain > (((uint32)1024) * 768 * 4)) - { - /* BIOS default */ - CRTCW(FIFO, 0x02); - /* Instruct CRTC to fetch new data 'earlier' */ - CRTCW(FIFO_LWM, 0x40); - LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 128\n")); - } - else - { - /* BIOS defaults */ - CRTCW(FIFO, 0x03); - CRTCW(FIFO_LWM, 0x20); - LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); - } - } - return B_OK; } @@ -127,14 +56,7 @@ status_t nv_crtc_validate_timing( /* NOTE: keep horizontal timing at multiples of 8! */ /* confine to a reasonable width */ if (*hd_e < 640) *hd_e = 640; - if (si->ps.card_type > NV04) - { - if (*hd_e > 2048) *hd_e = 2048; - } - else - { - if (*hd_e > 1920) *hd_e = 1920; - } + if (*hd_e > 2048) *hd_e = 2048; /* if hor. total does not leave room for a sensible sync pulse, increase it! */ if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); @@ -160,14 +82,7 @@ status_t nv_crtc_validate_timing( /* confine to a reasonable height */ if (*vd_e < 480) *vd_e = 480; - if (si->ps.card_type > NV04) - { - if (*vd_e > 1536) *vd_e = 1536; - } - else - { - if (*vd_e > 1440) *vd_e = 1440; - } + if (*vd_e > 1536) *vd_e = 1536; /*if vertical total does not leave room for a sync pulse, increase it!*/ if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); @@ -238,12 +153,8 @@ status_t nv_crtc_set_timing(display_mode target) * OTOH the overlay unit distorts if we reserve too much time! */ if (target.timing.h_display == si->ps.p1_timing.h_display) { - /* NV11 timing has different constraints than later cards */ - if (si->ps.card_type == NV11) - target.timing.h_total -= 56; - else - /* confirmed NV34 with 1680x1050 panel */ - target.timing.h_total -= 32; + /* confirmed NV34 with 1680x1050 panel */ + target.timing.h_total -= 32; } if (target.timing.h_sync_start == target.timing.h_display) @@ -409,7 +320,6 @@ status_t nv_crtc_set_timing(display_mode target) CRTCW(INTERLACE, 0xff); /* disable CRTC slaved mode unless a panel is in use */ - // fixme: this kills TVout when it was in use... if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); /* setup flatpanel if connected and active */ @@ -622,7 +532,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel) { //fixme? linux only does this on dualhead cards... //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds2_active && (si->ps.card_type != NV11)) + if (!si->ps.tmds2_active) { /* b2 = 0 = enable laptop panel backlight */ /* note: this seems to be a write-only register. */ @@ -665,7 +575,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel) { //fixme? linux only does this on dualhead cards... //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds2_active && (si->ps.card_type != NV11)) + if (!si->ps.tmds2_active) { /* b2 = 1 = disable laptop panel backlight */ /* note: this seems to be a write-only register. */ @@ -984,131 +894,3 @@ status_t nv_crtc_cursor_position(uint16 x, uint16 y) return B_OK; } - -status_t nv_crtc_stop_tvout(void) -{ - uint16 cnt; - - LOG(4,("CRTC: stopping TV output\n")); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* just to be sure Vsync is _really_ enabled */ - CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); - - /* wait for one image to be generated to make sure VGA has kicked in and is - * running OK before continuing... - * (Kicking in will fail often if we do not wait here) */ - /* Note: - * The used CRTC's Vsync is required to be enabled here. The DPMS state - * programming in the driver makes sure this is the case. - * (except for driver startup: see nv_general.c.) */ - - /* make sure we are 'in' active VGA picture: wait with timeout! */ - cnt = 1; - while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) - { - snooze(1); - cnt++; - } - /* wait for next vertical retrace start on VGA: wait with timeout! */ - cnt = 1; - while ((!(NV_REG8(NV8_INSTAT1) & 0x08)) && cnt) - { - snooze(1); - cnt++; - } - /* now wait until we are 'in' active VGA picture again: wait with timeout! */ - cnt = 1; - while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) - { - snooze(1); - cnt++; - } - - /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ - if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03)); - - /* CAUTION: - * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but - * write actions do succeed ... - * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ - - /* setup TVencoder connection */ - /* b1-0 = %00: encoder type is SLAVE; - * b24 = 1: VIP datapos is b0-7 */ - //fixme if needed: setup completely instead of relying on pre-init by BIOS.. - //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) - DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000003) | 0x01000000)); - - /* tell GPU to use pixelclock from internal source instead of using TVencoder */ - if (si->ps.secondary_head) - DACW(PLLSEL, 0x30000f00); - else - DACW(PLLSEL, 0x10000700); - - /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of - * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ - CRTCW(TREG, 0x00); - - /* select panel encoder, not TV encoder if needed (b0 = 1). - * Note: - * Both are devices (often) using the CRTC in slaved mode. */ - if (si->ps.slaved_tmds1) CRTCW(LCD, (CRTCR(LCD) | 0x01)); - - return B_OK; -} - -status_t nv_crtc_start_tvout(void) -{ - LOG(4,("CRTC: starting TV output\n")); - - if (si->ps.secondary_head) - { - /* switch TV encoder to CRTC1 */ - NV_REG32(NV32_2FUNCSEL) &= ~0x00000100; - NV_REG32(NV32_FUNCSEL) |= 0x00000100; - } - - /* enable access to primary head */ - set_crtc_owner(0); - - /* CAUTION: - * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but - * write actions do succeed ... - * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ - - /* setup TVencoder connection */ - /* b1-0 = %01: encoder type is MASTER; - * b24 = 1: VIP datapos is b0-7 */ - //fixme if needed: setup completely instead of relying on pre-init by BIOS.. - //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) - DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001)); - - /* tell GPU to use pixelclock from TVencoder instead of using internal source */ - /* (nessecary or display will 'shiver' on both TV and VGA.) */ - if (si->ps.secondary_head) - DACW(PLLSEL, 0x20030f00); - else - DACW(PLLSEL, 0x00030700); - - /* Set overscan color to 'black' */ - /* note: - * Change this instruction for a visible overscan color if you're trying to - * center the output on TV. Use it as a guide-'line' then ;-) */ - ATBW(OSCANCOLOR, 0x00); - - /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ - CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xc7) | 0x80)); - /* select TV encoder, not panel encoder (b0 = 0). - * Note: - * Both are devices (often) using the CRTC in slaved mode. */ - CRTCW(LCD, (CRTCR(LCD) & 0xfe)); - - /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of - * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ - CRTCW(TREG, 0x80); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c index 70871502b9..92d2d1d388 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c @@ -1,6 +1,6 @@ /* second CTRC functionality for GeForce cards */ /* Author: - Rudolf Cornelissen 11/2002-2/2006 + Rudolf Cornelissen 11/2002-6/2008 */ #define MODULE_BIT 0x00020000 @@ -29,79 +29,8 @@ status_t nv_crtc2_interrupt_enable(bool flag) return result; } -/* doing general fail-safe default setup here */ -//fixme: this is a _very_ basic setup, and it's preliminary... status_t nv_crtc2_update_fifo() { - uint8 bytes_per_pixel = 1; - uint32 drain; - - /* we are only using this on >>coldstarted<< cards which really need this */ - //fixme: re-enable or remove after general user confirmation of behaviour... - if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK; - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* set CRTC FIFO low watermark according to memory drain */ - switch(si->dm.space) - { - case B_CMAP8: - bytes_per_pixel = 1; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - bytes_per_pixel = 2; - break; - case B_RGB24_LITTLE: - bytes_per_pixel = 3; - break; - case B_RGB32_LITTLE: - bytes_per_pixel = 4; - break; - } - /* fixme: - * - I should probably include the refreshrate as well; - * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ - drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; - - /* Doesn't work for other than 32bit space (yet?) */ - if (si->dm.space != B_RGB32_LITTLE) - { - /* BIOS defaults */ - CRTC2W(FIFO, 0x03); - CRTC2W(FIFO_LWM, 0x20); - LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); - return B_OK; - } - - if (drain > (((uint32)1280) * 1024 * 4)) - { - /* set CRTC FIFO burst size for 'smaller' bursts */ - CRTC2W(FIFO, 0x01); - /* Instruct CRTC to fetch new data 'earlier' */ - CRTC2W(FIFO_LWM, 0x40); - LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 64\n")); - } - else - { - if (drain > (((uint32)1024) * 768 * 4)) - { - /* BIOS default */ - CRTC2W(FIFO, 0x02); - /* Instruct CRTC to fetch new data 'earlier' */ - CRTC2W(FIFO_LWM, 0x40); - LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 128\n")); - } - else - { - /* BIOS defaults */ - CRTC2W(FIFO, 0x03); - CRTC2W(FIFO_LWM, 0x20); - LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); - } - } - return B_OK; } @@ -224,12 +153,8 @@ status_t nv_crtc2_set_timing(display_mode target) * OTOH the overlay unit distorts if we reserve too much time! */ if (target.timing.h_display == si->ps.p2_timing.h_display) { - /* NV11 timing has different constraints than later cards */ - if (si->ps.card_type == NV11) - target.timing.h_total -= 56; - else - /* confirmed NV34 with 1680x1050 panel */ - target.timing.h_total -= 32; + /* confirmed NV34 with 1680x1050 panel */ + target.timing.h_total -= 32; } if (target.timing.h_sync_start == target.timing.h_display) @@ -392,7 +317,6 @@ status_t nv_crtc2_set_timing(display_mode target) CRTC2W(INTERLACE, 0xff); /* disable CRTC slaved mode unless a panel is in use */ - // fixme: this kills TVout when it was in use... if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); /* setup flatpanel if connected and active */ @@ -604,7 +528,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel) else { //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds1_active && (si->ps.card_type != NV11)) + if (!si->ps.tmds1_active) { /* b2 = 0 = enable laptop panel backlight */ /* note: this seems to be a write-only register. */ @@ -646,7 +570,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel) else { //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds1_active && (si->ps.card_type != NV11)) + if (!si->ps.tmds1_active) { /* b2 = 1 = disable laptop panel backlight */ /* note: this seems to be a write-only register. */ @@ -899,122 +823,3 @@ status_t nv_crtc2_cursor_position(uint16 x, uint16 y) return B_OK; } - -status_t nv_crtc2_stop_tvout(void) -{ - uint16 cnt; - - LOG(4,("CRTC2: stopping TV output\n")); - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* just to be sure Vsync is _really_ enabled */ - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); - - /* wait for one image to be generated to make sure VGA has kicked in and is - * running OK before continuing... - * (Kicking in will fail often if we do not wait here) */ - /* Note: - * The used CRTC's Vsync is required to be enabled here. The DPMS state - * programming in the driver makes sure this is the case. - * (except for driver startup: see nv_general.c.) */ - - /* make sure we are 'in' active VGA picture: wait with timeout! */ - cnt = 1; - while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) - { - snooze(1); - cnt++; - } - /* wait for next vertical retrace start on VGA: wait with timeout! */ - cnt = 1; - while ((!(NV_REG8(NV8_INSTAT1) & 0x08)) && cnt) - { - snooze(1); - cnt++; - } - /* now wait until we are 'in' active VGA picture again: wait with timeout! */ - cnt = 1; - while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) - { - snooze(1); - cnt++; - } - - /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ - if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03)); - - /* CAUTION: - * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but - * write actions do succeed ... - * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ - - /* setup TVencoder connection */ - /* b1-0 = %00: encoder type is SLAVE; - * b24 = 1: VIP datapos is b0-7 */ - //fixme if needed: setup completely instead of relying on pre-init by BIOS.. - //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) - DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000003) | 0x01000000)); - - /* tell GPU to use pixelclock from internal source instead of using TVencoder */ - DACW(PLLSEL, 0x30000f00); - - /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of - * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ - CRTC2W(TREG, 0x00); - - /* select panel encoder, not TV encoder if needed (b0 = 1). - * Note: - * Both are devices (often) using the CRTC in slaved mode. */ - if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01)); - - return B_OK; -} - -status_t nv_crtc2_start_tvout(void) -{ - LOG(4,("CRTC2: starting TV output\n")); - - /* switch TV encoder to CRTC2 */ - NV_REG32(NV32_FUNCSEL) &= ~0x00000100; - NV_REG32(NV32_2FUNCSEL) |= 0x00000100; - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* CAUTION: - * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but - * write actions do succeed ... - * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ - - /* setup TVencoder connection */ - /* b1-0 = %01: encoder type is MASTER; - * b24 = 1: VIP datapos is b0-7 */ - //fixme if needed: setup completely instead of relying on pre-init by BIOS.. - //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) - DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000002) | 0x01000001)); - - /* tell GPU to use pixelclock from TVencoder instead of using internal source */ - /* (nessecary or display will 'shiver' on both TV and VGA.) */ - DACW(PLLSEL, 0x100c0f00); - - /* Set overscan color to 'black' */ - /* note: - * Change this instruction for a visible overscan color if you're trying to - * center the output on TV. Use it as a guide-'line' then ;-) */ - ATB2W(OSCANCOLOR, 0x00); - - /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ - CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xc7) | 0x80)); - /* select TV encoder, not panel encoder (b0 = 0). - * Note: - * Both are devices (often) using the CRTC in slaved mode. */ - CRTC2W(LCD, (CRTC2R(LCD) & 0xfe)); - - /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of - * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ - CRTC2W(TREG, 0x80); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c index 2a21350eff..b96bd96fb7 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c @@ -250,8 +250,6 @@ void setup_virtualized_heads(bool cross) head1_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide; head1_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define; head1_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position; - head1_stop_tvout = (crtc_stop_tvout) nv_crtc2_stop_tvout; - head1_start_tvout = (crtc_start_tvout) nv_crtc2_start_tvout; head1_mode = (dac_mode) nv_dac2_mode; head1_palette = (dac_palette) nv_dac2_palette; @@ -271,8 +269,6 @@ void setup_virtualized_heads(bool cross) head2_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide; head2_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define; head2_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position; - head2_stop_tvout = (crtc_stop_tvout) nv_crtc_stop_tvout; - head2_start_tvout = (crtc_start_tvout) nv_crtc_start_tvout; head2_mode = (dac_mode) nv_dac_mode; head2_palette = (dac_palette) nv_dac_palette; @@ -294,8 +290,6 @@ void setup_virtualized_heads(bool cross) head1_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide; head1_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define; head1_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position; - head1_stop_tvout = (crtc_stop_tvout) nv_crtc_stop_tvout; - head1_start_tvout = (crtc_start_tvout) nv_crtc_start_tvout; head1_mode = (dac_mode) nv_dac_mode; head1_palette = (dac_palette) nv_dac_palette; @@ -315,8 +309,6 @@ void setup_virtualized_heads(bool cross) head2_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide; head2_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define; head2_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position; - head2_stop_tvout = (crtc_stop_tvout) nv_crtc2_stop_tvout; - head2_start_tvout = (crtc_start_tvout) nv_crtc2_start_tvout; head2_mode = (dac_mode) nv_dac2_mode; head2_palette = (dac_palette) nv_dac2_palette; @@ -391,8 +383,7 @@ static status_t nvxx_general_powerup() // unlock_card(); - /* get RAM size, detect TV encoder and do fake panel startup (panel init code - * is still missing). */ + /* get RAM size and do fake panel startup (panel init code is still missing). */ // fake_panel_start(); /* log the final card specifications */ @@ -417,34 +408,26 @@ status_t nv_general_output_select(bool cross) /* make sure this call is warranted */ if (si->ps.secondary_head) { - /* NV11 cards can't switch heads (confirmed) */ - if (si->ps.card_type != NV11) + if (cross) { - if (cross) - { - LOG(4,("INIT: switching analog outputs to be cross-connected\n")); + LOG(4,("INIT: switching analog outputs to be cross-connected\n")); - /* enable head 2 on connector 1 */ - /* (b8 = select CRTC (head) for output, - * b4 = ??? (confirmed not to be a FP switch), - * b0 = enable CRT) */ - DACW(OUTPUT, 0x00000101); - /* enable head 1 on connector 2 */ - DAC2W(OUTPUT, 0x00000001); - } - else - { - LOG(4,("INIT: switching analog outputs to be straight-through\n")); - - /* enable head 1 on connector 1 */ - DACW(OUTPUT, 0x00000001); - /* enable head 2 on connector 2 */ - DAC2W(OUTPUT, 0x00000101); - } + /* enable head 2 on connector 1 */ + /* (b8 = select CRTC (head) for output, + * b4 = ??? (confirmed not to be a FP switch), + * b0 = enable CRT) */ + DACW(OUTPUT, 0x00000101); + /* enable head 1 on connector 2 */ + DAC2W(OUTPUT, 0x00000001); } else { - LOG(4,("INIT: NV11 analog outputs are hardwired to be straight-through\n")); + LOG(4,("INIT: switching analog outputs to be straight-through\n")); + + /* enable head 1 on connector 1 */ + DACW(OUTPUT, 0x00000001); + /* enable head 2 on connector 2 */ + DAC2W(OUTPUT, 0x00000101); } return B_OK; } diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h index c31f202c12..8c51383865 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h @@ -24,8 +24,6 @@ typedef status_t (*crtc_cursor_show)(void); typedef status_t (*crtc_cursor_hide)(void); typedef status_t (*crtc_cursor_define)(uint8*, uint8*); typedef status_t (*crtc_cursor_position)(uint16, uint16); -typedef status_t (*crtc_stop_tvout)(void); -typedef status_t (*crtc_start_tvout)(void); typedef status_t (*dac_mode)(int, float); typedef status_t (*dac_palette)(uint8[256], uint8[256], uint8[256]); @@ -45,8 +43,6 @@ crtc_cursor_show head1_cursor_show; crtc_cursor_hide head1_cursor_hide; crtc_cursor_define head1_cursor_define; crtc_cursor_position head1_cursor_position; -crtc_stop_tvout head1_stop_tvout; -crtc_start_tvout head1_start_tvout; crtc_interrupt_enable head2_interrupt_enable; crtc_update_fifo head2_update_fifo; @@ -61,8 +57,6 @@ crtc_cursor_show head2_cursor_show; crtc_cursor_hide head2_cursor_hide; crtc_cursor_define head2_cursor_define; crtc_cursor_position head2_cursor_position; -crtc_stop_tvout head2_stop_tvout; -crtc_start_tvout head2_start_tvout; dac_mode head1_mode; dac_palette head1_palette; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c index 17e18a6d7d..f2f4447d53 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c @@ -1,7 +1,7 @@ /* Read initialisation information from card */ /* some bits are hacks, where PINS is not known */ /* Author: - Rudolf Cornelissen 7/2003-3/2006 + Rudolf Cornelissen 7/2003-6/2008 */ #define MODULE_BIT 0x00002000 @@ -21,10 +21,7 @@ typedef struct { static void detect_panels(void); static void setup_output_matrix(void); -static void pinsnv4_fake(void); -static void pinsnv5_nv5m64_fake(void); -static void pinsnv6_fake(void); -static void pinsnv10_arch_fake(void); + static void pinsnv20_arch_fake(void); static void pinsnv30_arch_fake(void); static void getRAMsize_arch_nv4(void); @@ -2104,36 +2101,18 @@ void set_specs(void) LOG(8,("INFO: setting up card specifications\n")); /* set failsave speeds */ - switch (si->ps.card_type) + switch (si->ps.card_arch) { - case NV04: - pinsnv4_fake(); + case NV20A: + pinsnv20_arch_fake(); break; - case NV05: - case NV05M64: - pinsnv5_nv5m64_fake(); - break; - case NV06: - pinsnv6_fake(); + case NV30A: + case NV40A: + pinsnv30_arch_fake(); break; default: - switch (si->ps.card_arch) - { - case NV10A: - pinsnv10_arch_fake(); - break; - case NV20A: - pinsnv20_arch_fake(); - break; - case NV30A: - case NV40A: - pinsnv30_arch_fake(); - break; - default: - /* 'failsafe' values... */ - pinsnv10_arch_fake(); - break; - } + /* 'failsafe' values... */ + pinsnv20_arch_fake(); break; } @@ -2172,13 +2151,7 @@ void fake_panel_start(void) si->ps.memory_size = si->settings.memory * 1024 * 1024; } - /* find out if the card has a tvout chip */ - si->ps.tvout = false; - si->ps.tv_encoder.type = NONE; - si->ps.tv_encoder.version = 0; i2c_init(); - //fixme: add support for more encoders... - BT_probe(); LOG(8,("INFO: faking panel startup\n")); @@ -2198,14 +2171,13 @@ void fake_panel_start(void) static void detect_panels() { - /* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */ + /* detect if the BIOS enabled LCD's (internal panels or DVI) */ /* both external TMDS transmitters (used for LCD/DVI) and external TVencoders * (can) use the CRTC's in slaved mode. */ /* Note: * DFP's are programmed with standard VESA modelines by the card's BIOS! */ bool slaved_for_dev1 = false, slaved_for_dev2 = false; - bool tvout1 = false, tvout2 = false; /* check primary head: */ /* enable access to primary head */ @@ -2236,11 +2208,6 @@ static void detect_panels() /* detect active slave device (if any) */ slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); - if (slaved_for_dev1) - { - /* if the panel isn't selected, tvout is.. */ - tvout1 = !(CRTCR(LCD) & 0x01); - } if (si->ps.secondary_head) { @@ -2258,11 +2225,6 @@ static void detect_panels() /* detect active slave device (if any) */ slaved_for_dev2 = (CRTC2R(PIXEL) & 0x80); - if (slaved_for_dev2) - { - /* if the panel isn't selected, tvout is.. */ - tvout2 = !(CRTC2R(LCD) & 0x01); - } } LOG(2,("INFO: End flatpanel related CRTC registers dump.\n")); @@ -2283,29 +2245,22 @@ static void detect_panels() /* determine the situation we are in... (regarding flatpanels) */ /* fixme: add VESA DDC EDID stuff one day... */ /* fixme: find out how to program those transmitters one day instead of - * relying on the cards BIOS to do it. This adds TVout options where panels - * are used! + * relying on the cards BIOS to do it. * Currently we'd loose the panel setup while not being able to restore it. */ /* note: (facts) - * -> NV11 and NV17 laptops have LVDS panels, programmed in both sets registers; - * -> NV34 laptops have TMDS panels, programmed in only one set of registers; - * -> NV11, NV25 and NV34 DVI cards, so external panels (TMDS) are programmed - * in only one set of registers; * -> a register-set's FP_TG_CTRL register, bit 31 tells you if a LVDS panel is - * connected to the primary head (0), or to the secondary head (1) except - * on some NV11's if this bit is '0' there; + * connected to the primary head (0), or to the secondary head (1); * -> for LVDS panels both registersets are programmed identically by the card's * BIOSes; * -> the programmed set of registers tells you where a TMDS (DVI) panel is * connected; - * -> On all cards a CRTC is used in slaved mode when a panel is connected, - * except on NV11: here master mode is (might be?) detected. */ + * -> On all cards a CRTC is used in slaved mode when a panel is connected. */ /* note also: * external TMDS encoders are only used for logic-level translation: it's * modeline registers are not used. Instead the GPU's internal modeline registers * are used. The external encoder is not connected to a I2C bus (confirmed NV34). */ - if (slaved_for_dev1 && !tvout1) + if (slaved_for_dev1) { uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); @@ -2318,7 +2273,7 @@ static void detect_panels() } } - if (si->ps.secondary_head && slaved_for_dev2 && !tvout2) + if (si->ps.secondary_head && slaved_for_dev2) { uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); @@ -2331,34 +2286,6 @@ static void detect_panels() } } - if ((si->ps.card_type == NV11) && - !si->ps.slaved_tmds1 && !tvout1) - { - uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); - uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); - if ((width >= 640) && (height >= 480)) - { - si->ps.master_tmds1 = true; - si->ps.tmds1_active = true; - si->ps.p1_timing.h_display = width; - si->ps.p1_timing.v_display = height; - } - } - - if ((si->ps.card_type == NV11) && - si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2) - { - uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); - uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); - if ((width >= 640) && (height >= 480)) - { - si->ps.master_tmds2 = true; - si->ps.tmds2_active = true; - si->ps.p2_timing.h_display = width; - si->ps.p2_timing.v_display = height; - } - } - //fixme...: //we are assuming that no DVI is used as external monitor on laptops; //otherwise we probably get into trouble here if the checked specs match. @@ -2369,9 +2296,9 @@ static void detect_panels() { LOG(2,("INFO: correcting double detection of single panel!\n")); - if (si->ps.card_type == NV11) + if (DACR(FP_TG_CTRL) & 0x80000000) { - /* LVDS panel is _always_ on CRTC2, so clear false primary detection */ + /* LVDS panel is on CRTC2, so clear false primary detection */ si->ps.slaved_tmds1 = false; si->ps.master_tmds1 = false; si->ps.tmds1_active = false; @@ -2380,24 +2307,12 @@ static void detect_panels() } else { - if (DACR(FP_TG_CTRL) & 0x80000000) - { - /* LVDS panel is on CRTC2, so clear false primary detection */ - si->ps.slaved_tmds1 = false; - si->ps.master_tmds1 = false; - si->ps.tmds1_active = false; - si->ps.p1_timing.h_display = 0; - si->ps.p1_timing.v_display = 0; - } - else - { - /* LVDS panel is on CRTC1, so clear false secondary detection */ - si->ps.slaved_tmds2 = false; - si->ps.master_tmds2 = false; - si->ps.tmds2_active = false; - si->ps.p2_timing.h_display = 0; - si->ps.p2_timing.v_display = 0; - } + /* LVDS panel is on CRTC1, so clear false secondary detection */ + si->ps.slaved_tmds2 = false; + si->ps.master_tmds2 = false; + si->ps.tmds2_active = false; + si->ps.p2_timing.h_display = 0; + si->ps.p2_timing.v_display = 0; } } @@ -2516,12 +2431,9 @@ static void detect_panels() } /* determine flatpanel type(s) */ - /* note: - * on NV11 accessing registerset(s) hangs card. */ - //fixme: how about NV11's with panels? //fixme?: linux checks on (only and) all dualhead cards, and only on DAC1... //fixme: testing... - if (/*si->ps.tmds1_active && */(si->ps.card_type != NV11)) + if (/*si->ps.tmds1_active && */1) { /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. * b0-7 = adress, b16 = 1 = write_enable */ @@ -2533,8 +2445,8 @@ static void detect_panels() LOG(2,("INFO: Flatpanel on head 1 is TMDS type\n")); } //fixme: testing... -// if (si->ps.tmds2_active && (si->ps.card_type != NV11)) - if (si->ps.secondary_head && (si->ps.card_type != NV11)) +// if (si->ps.tmds2_active) + if (si->ps.secondary_head) { /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. * b0-7 = adress, b16 = 1 = write_enable */ @@ -2560,178 +2472,113 @@ static void setup_output_matrix() /* setup output devices and heads */ if (si->ps.secondary_head) { - if (si->ps.card_type != NV11) + /* setup defaults: */ + /* connect analog outputs straight through */ + nv_general_output_select(false); + + /* presetup by the card's BIOS, we can't change this (lack of info) */ + if (si->ps.tmds1_active) si->ps.monitors |= 0x01; + if (si->ps.tmds2_active) si->ps.monitors |= 0x10; + /* detect analog monitors (confirmed working OK on NV18, NV28 and NV34): */ + /* sense analog monitor on primary connector */ + if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; + /* sense analog monitor on secondary connector */ + if (nv_dac2_crt_connected()) si->ps.monitors |= 0x20; + + /* setup correct output and head use */ + switch (si->ps.monitors) { - /* setup defaults: */ - /* connect analog outputs straight through */ - nv_general_output_select(false); - - /* presetup by the card's BIOS, we can't change this (lack of info) */ - if (si->ps.tmds1_active) si->ps.monitors |= 0x01; - if (si->ps.tmds2_active) si->ps.monitors |= 0x10; - /* detect analog monitors (confirmed working OK on NV18, NV28 and NV34): */ - /* sense analog monitor on primary connector */ - if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; - /* sense analog monitor on secondary connector */ - if (nv_dac2_crt_connected()) si->ps.monitors |= 0x20; - - /* setup correct output and head use */ - //fixme? add TVout (only, so no CRT(s) connected) support... - switch (si->ps.monitors) + case 0x00: /* no monitor found at all */ + LOG(2,("INFO: head 1 has nothing connected;\n")); + LOG(2,("INFO: head 2 has nothing connected:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x01: /* digital panel on head 1, nothing on head 2 */ + LOG(2,("INFO: head 1 has a digital panel;\n")); + LOG(2,("INFO: head 2 has nothing connected:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ + LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); + LOG(2,("INFO: head 2 has nothing connected:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x03: /* both types on head 1, nothing on head 2 */ + LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); + LOG(2,("INFO: head 2 has nothing connected:\n")); + LOG(2,("INFO: correcting...\n")); + /* cross connect analog outputs so analog panel or CRT gets head 2 */ + nv_general_output_select(true); + LOG(2,("INFO: head 1 has a digital panel;\n")); + LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x10: /* nothing on head 1, digital panel on head 2 */ + LOG(2,("INFO: head 1 has nothing connected;\n")); + LOG(2,("INFO: head 2 has a digital panel:\n")); + LOG(2,("INFO: defaulting to head 2 for primary use.\n")); + si->ps.crtc2_prim = true; + break; + case 0x20: /* nothing on head 1, analog panel or CRT on head 2 */ + LOG(2,("INFO: head 1 has nothing connected;\n")); + LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); + LOG(2,("INFO: defaulting to head 2 for primary use.\n")); + si->ps.crtc2_prim = true; + break; + case 0x30: /* nothing on head 1, both types on head 2 */ + LOG(2,("INFO: head 1 has nothing connected;\n")); + LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n")); + LOG(2,("INFO: correcting...\n")); + /* cross connect analog outputs so analog panel or CRT gets head 1 */ + nv_general_output_select(true); + LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); + LOG(2,("INFO: head 2 has a digital panel:\n")); + LOG(2,("INFO: defaulting to head 2 for primary use.\n")); + si->ps.crtc2_prim = true; + break; + case 0x11: /* digital panels on both heads */ + LOG(2,("INFO: head 1 has a digital panel;\n")); + LOG(2,("INFO: head 2 has a digital panel:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ + LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); + LOG(2,("INFO: head 2 has a digital panel:\n")); + LOG(2,("INFO: defaulting to head 2 for primary use.\n")); + si->ps.crtc2_prim = true; + break; + case 0x21: /* digital panel on head 1, analog panel or CRT on head 2 */ + LOG(2,("INFO: head 1 has a digital panel;\n")); + LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x22: /* analog panel(s) or CRT(s) on both heads */ + LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); + LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; + case 0x32: /* more than two monitors connected to just two outputs: illegal! */ + //general fixme: + //NV40 architecture contains (an) additional switch(es) to + //connect a CRTC/DAC combination to a connector. We can't work as + //usual (yet) because this interferes via BIOS card pre-programming. + // + //Also: it looks as if each pixelclock PLL can select different CRTC's + //as well now via a new register: one PLL can be driving both CRTC's + //and there's nothing we can do about that (yet). (DVI/dualhead trouble) + if (si->ps.card_arch < NV40A) { - case 0x00: /* no monitor found at all */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x01: /* digital panel on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x03: /* both types on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: correcting...\n")); - /* cross connect analog outputs so analog panel or CRT gets head 2 */ - nv_general_output_select(true); - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x10: /* nothing on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x20: /* nothing on head 1, analog panel or CRT on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x30: /* nothing on head 1, both types on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n")); - LOG(2,("INFO: correcting...\n")); - /* cross connect analog outputs so analog panel or CRT gets head 1 */ - nv_general_output_select(true); - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x11: /* digital panels on both heads */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x21: /* digital panel on head 1, analog panel or CRT on head 2 */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x22: /* analog panel(s) or CRT(s) on both heads */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x32: /* more than two monitors connected to just two outputs: illegal! */ - //general fixme: - //NV40 architecture contains (an) additional switch(es) to - //connect a CRTC/DAC combination to a connector. We can't work as - //usual (yet) because this interferes via BIOS card pre-programming. - // - //Also: it looks as if each pixelclock PLL can select different CRTC's - //as well now via a new register: one PLL can be driving both CRTC's - //and there's nothing we can do about that (yet). (DVI/dualhead trouble) - if (si->ps.card_arch < NV40A) - { - LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); - /* head 2 takes precedence because it has a digital panel while - * head 1 has not. */ - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - } - default: /* more than two monitors connected to just two outputs: illegal! */ LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - } - } - else /* dualhead NV11 cards */ - { - /* confirmed no analog output switch-options for NV11 */ - LOG(2,("INFO: NV11 outputs are hardwired to be straight-through\n")); - - /* presetup by the card's BIOS, we can't change this (lack of info) */ - if (si->ps.tmds1_active) si->ps.monitors |= 0x01; - if (si->ps.tmds2_active) si->ps.monitors |= 0x10; - /* detect analog monitor (confirmed working OK on NV11): */ - /* sense analog monitor on primary connector */ - if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; - /* (sense analog monitor on secondary connector is impossible on NV11) */ - - /* setup correct output and head use */ - //fixme? add TVout (only, so no CRT(s) connected) support... - switch (si->ps.monitors) - { - case 0x00: /* no monitor found at all */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x01: /* digital panel on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x03: /* both types on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: correction not possible...\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x10: /* nothing on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x11: /* digital panels on both heads */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - default: /* more than two monitors connected to just two outputs: illegal! */ - LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + /* head 2 takes precedence because it has a digital panel while + * head 1 has not. */ + LOG(2,("INFO: defaulting to head 2 for primary use.\n")); + si->ps.crtc2_prim = true; break; } + default: /* more than two monitors connected to just two outputs: illegal! */ + LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); + LOG(2,("INFO: defaulting to head 1 for primary use.\n")); + break; } } else /* singlehead cards */ @@ -2741,8 +2588,6 @@ static void setup_output_matrix() /* detect analog monitor (confirmed working OK on all cards): */ /* sense analog monitor on primary connector */ if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; - - //fixme? add TVout (only, so no CRT connected) support... } } @@ -2781,160 +2626,6 @@ void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2) *pan2 = false; } -static void pinsnv4_fake(void) -{ - /* we have a standard PLL */ - si->ps.ext_pll = false; - /* carefull not to take to high limits, and high should be >= 2x low. */ - si->ps.max_system_vco = 256; - si->ps.min_system_vco = 128; - si->ps.max_pixel_vco = 256; - si->ps.min_pixel_vco = 128; - si->ps.max_video_vco = 0; - si->ps.min_video_vco = 0; - si->ps.max_dac1_clock = 250; - si->ps.max_dac1_clock_8 = 250; - si->ps.max_dac1_clock_16 = 250; - /* 'failsave' values */ - si->ps.max_dac1_clock_24 = 220; - si->ps.max_dac1_clock_32 = 180; - si->ps.max_dac1_clock_32dh = 180; - /* secondary head */ - si->ps.max_dac2_clock = 0; - si->ps.max_dac2_clock_8 = 0; - si->ps.max_dac2_clock_16 = 0; - si->ps.max_dac2_clock_24 = 0; - si->ps.max_dac2_clock_32 = 0; - /* 'failsave' values */ - si->ps.max_dac2_clock_32dh = 0; - //fixme: primary & secondary_dvi should be overrule-able via nv.settings - si->ps.primary_dvi = false; - si->ps.secondary_dvi = false; - /* not used (yet) because no coldstart will be attempted (yet) */ - si->ps.std_engine_clock = 90; - si->ps.std_memory_clock = 110; -} - -static void pinsnv5_nv5m64_fake(void) -{ - /* we have a standard PLL */ - si->ps.ext_pll = false; - /* carefull not to take to high limits, and high should be >= 2x low. */ - si->ps.max_system_vco = 300; - si->ps.min_system_vco = 128; - si->ps.max_pixel_vco = 300; - si->ps.min_pixel_vco = 128; - si->ps.max_video_vco = 0; - si->ps.min_video_vco = 0; - si->ps.max_dac1_clock = 300; - si->ps.max_dac1_clock_8 = 300; - si->ps.max_dac1_clock_16 = 300; - /* 'failsave' values */ - si->ps.max_dac1_clock_24 = 270; - si->ps.max_dac1_clock_32 = 230; - si->ps.max_dac1_clock_32dh = 230; - /* secondary head */ - si->ps.max_dac2_clock = 0; - si->ps.max_dac2_clock_8 = 0; - si->ps.max_dac2_clock_16 = 0; - si->ps.max_dac2_clock_24 = 0; - si->ps.max_dac2_clock_32 = 0; - /* 'failsave' values */ - si->ps.max_dac2_clock_32dh = 0; - //fixme: primary & secondary_dvi should be overrule-able via nv.settings - si->ps.primary_dvi = false; - si->ps.secondary_dvi = false; - /* not used (yet) because no coldstart will be attempted (yet) */ - si->ps.std_engine_clock = 125; - si->ps.std_memory_clock = 150; -} - -static void pinsnv6_fake(void) -{ - /* we have a standard PLL */ - si->ps.ext_pll = false; - /* carefull not to take to high limits, and high should be >= 2x low. */ - si->ps.max_system_vco = 300; - si->ps.min_system_vco = 128; - si->ps.max_pixel_vco = 300; - si->ps.min_pixel_vco = 128; - si->ps.max_video_vco = 0; - si->ps.min_video_vco = 0; - si->ps.max_dac1_clock = 300; - si->ps.max_dac1_clock_8 = 300; - si->ps.max_dac1_clock_16 = 300; - /* 'failsave' values */ - si->ps.max_dac1_clock_24 = 270; - si->ps.max_dac1_clock_32 = 230; - si->ps.max_dac1_clock_32dh = 230; - /* secondary head */ - si->ps.max_dac2_clock = 0; - si->ps.max_dac2_clock_8 = 0; - si->ps.max_dac2_clock_16 = 0; - si->ps.max_dac2_clock_24 = 0; - si->ps.max_dac2_clock_32 = 0; - /* 'failsave' values */ - si->ps.max_dac2_clock_32dh = 0; - //fixme: primary & secondary_dvi should be overrule-able via nv.settings - si->ps.primary_dvi = false; - si->ps.secondary_dvi = false; - /* not used (yet) because no coldstart will be attempted (yet) */ - si->ps.std_engine_clock = 100; - si->ps.std_memory_clock = 125; -} - -static void pinsnv10_arch_fake(void) -{ - /* we have a standard PLL */ - si->ps.ext_pll = false; - /* carefull not to take to high limits, and high should be >= 2x low. */ - si->ps.max_system_vco = 350; - si->ps.min_system_vco = 128; - si->ps.max_pixel_vco = 350; - si->ps.min_pixel_vco = 128; - si->ps.max_video_vco = 350; - si->ps.min_video_vco = 128; - si->ps.max_dac1_clock = 350; - si->ps.max_dac1_clock_8 = 350; - si->ps.max_dac1_clock_16 = 350; - /* 'failsave' values */ - si->ps.max_dac1_clock_24 = 320; - si->ps.max_dac1_clock_32 = 280; - si->ps.max_dac1_clock_32dh = 250; - /* secondary head */ - if (si->ps.card_type < NV17) - { - /* if a GeForce2 has analog VGA dualhead capability, - * it uses an external secondary DAC probably with limited capability. */ - /* (called twinview technology) */ - si->ps.max_dac2_clock = 200; - si->ps.max_dac2_clock_8 = 200; - si->ps.max_dac2_clock_16 = 200; - si->ps.max_dac2_clock_24 = 200; - si->ps.max_dac2_clock_32 = 200; - /* 'failsave' values */ - si->ps.max_dac2_clock_32dh = 180; - } - else - { - /* GeForce4 cards have dual integrated DACs with identical capaability */ - /* (called nview technology) */ - si->ps.max_dac2_clock = 350; - si->ps.max_dac2_clock_8 = 350; - si->ps.max_dac2_clock_16 = 350; - /* 'failsave' values */ - si->ps.max_dac2_clock_24 = 320; - si->ps.max_dac2_clock_32 = 280; - si->ps.max_dac2_clock_32dh = 250; - } - //fixme: primary & secondary_dvi should be overrule-able via nv.settings - si->ps.primary_dvi = false; - si->ps.secondary_dvi = false; - /* not used (yet) because no coldstart will be attempted (yet) */ - si->ps.std_engine_clock = 120; - si->ps.std_memory_clock = 150; -} - static void pinsnv20_arch_fake(void) { /* we have a standard PLL */ @@ -3139,12 +2830,6 @@ static void getstrap_arch_nv10_20_30_40(void) si->ps.secondary_head = false; switch (si->ps.card_type) { - case NV04: - case NV05: - case NV05M64: - case NV06: - case NV10: - case NV15: case NV20: break; default: @@ -3164,7 +2849,7 @@ static void getstrap_arch_nv10_20_30_40(void) else si->ps.f_ref = 13.50000; - if ((si->ps.secondary_head) && (si->ps.card_type != NV11)) + if (si->ps.secondary_head) { if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000; } @@ -3172,8 +2857,6 @@ static void getstrap_arch_nv10_20_30_40(void) void dump_pins(void) { - char *msg = ""; - LOG(2,("INFO: pinsdump follows:\n")); LOG(2,("PLL type: ")); if (si->ps.ext_pll) LOG(2,("extended\n")); else LOG(2,("standard\n")); @@ -3200,65 +2883,6 @@ void dump_pins(void) LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh)); LOG(2,("secondary_head: ")); if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n")); - LOG(2,("tvout: ")); - if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n")); - /* setup TVout logmessage text */ - switch (si->ps.tv_encoder.type) - { - case NONE: - msg = "No"; - break; - case CH7003: - msg = "Chrontel CH7003"; - break; - case CH7004: - msg = "Chrontel CH7004"; - break; - case CH7005: - msg = "Chrontel CH7005"; - break; - case CH7006: - msg = "Chrontel CH7006"; - break; - case CH7007: - msg = "Chrontel CH7007"; - break; - case CH7008: - msg = "Chrontel CH7008"; - break; - case SAA7102: - msg = "Philips SAA7102"; - break; - case SAA7103: - msg = "Philips SAA7103"; - break; - case SAA7104: - msg = "Philips SAA7104"; - break; - case SAA7105: - msg = "Philips SAA7105"; - break; - case BT868: - msg = "Brooktree/Conexant BT868"; - break; - case BT869: - msg = "Brooktree/Conexant BT869"; - break; - case CX25870: - msg = "Conexant CX25870"; - break; - case CX25871: - msg = "Conexant CX25871"; - break; - case NVIDIA: - msg = "Nvidia internal"; - break; - default: - msg = "Unknown"; - break; - } - LOG(2, ("%s TV encoder detected; silicon revision is $%02x\n", - msg, si->ps.tv_encoder.version)); // LOG(2,("primary_dvi: ")); // if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); // LOG(2,("secondary_dvi: ")); diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h index 59777fcaab..b72faf9867 100644 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h +++ b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h @@ -22,7 +22,6 @@ void delay(bigtime_t i); void nv_log(char *format, ...); /* i2c functions */ -status_t i2c_sec_tv_adapter(void); char i2c_flag_error (char ErrNo); void i2c_bstart (uint8 BusNR); void i2c_bstop (uint8 BusNR); @@ -55,13 +54,6 @@ status_t nv_dac2_palette(uint8*,uint8*,uint8*); status_t nv_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8); status_t nv_dac2_set_pix_pll(display_mode target); -/* Brooktree TV functions */ -bool BT_probe(void); -uint8 BT_dpms(bool display); -uint8 BT_check_tvmode(display_mode target); -status_t BT_stop_tvout(void); -status_t BT_setmode(display_mode target); - /* CRTC1 functions */ status_t nv_crtc_interrupt_enable(bool); status_t nv_crtc_update_fifo(void); @@ -79,8 +71,6 @@ status_t nv_crtc_cursor_define(uint8*,uint8*); status_t nv_crtc_cursor_position(uint16 x ,uint16 y); status_t nv_crtc_cursor_show(void); status_t nv_crtc_cursor_hide(void); -status_t nv_crtc_stop_tvout(void); -status_t nv_crtc_start_tvout(void); /* CRTC2 functions */ status_t nv_crtc2_interrupt_enable(bool); @@ -99,8 +89,6 @@ status_t nv_crtc2_cursor_define(uint8*,uint8*); status_t nv_crtc2_cursor_position(uint16 x ,uint16 y); status_t nv_crtc2_cursor_show(void); status_t nv_crtc2_cursor_hide(void); -status_t nv_crtc2_stop_tvout(void); -status_t nv_crtc2_start_tvout(void); /* acceleration functions */ status_t check_acc_capability(uint32 feature); diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c index 85e1734d60..81b95d6bd3 100644 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c +++ b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c @@ -124,14 +124,12 @@ static nv_settings sSettings = { // see comments in nvidia_gpgpu.settings /* for accelerant */ 0x00000000, // logmask 0, // memory - 0, // tv_output true, // usebios true, // hardcursor false, // switchhead - true, // pgm_panel - false, // vga_on_tv + false, // pgm_panel false, // force_sync - false, // force_ws + true, // force_ws 0, // gpu_clk 0, // ram_clk }; @@ -1132,11 +1130,6 @@ init_driver(void) if (*end == '\0') sSettings.memory = value; - item = get_driver_parameter(settings, "tv_output", "0", "0"); - value = strtoul(item, &end, 0); - if (*end == '\0') - sSettings.tv_output = value; - sSettings.hardcursor = get_driver_boolean_parameter(settings, "hardcursor", false, false); sSettings.usebios = get_driver_boolean_parameter(settings, @@ -1145,8 +1138,6 @@ init_driver(void) "switchhead", false, false); sSettings.pgm_panel = get_driver_boolean_parameter(settings, "pgm_panel", false, false); - sSettings.vga_on_tv = get_driver_boolean_parameter(settings, - "vga_on_tv", false, false); sSettings.force_sync = get_driver_boolean_parameter(settings, "force_sync", false, false); sSettings.force_ws = get_driver_boolean_parameter(settings, diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings index 8acf1f23f2..8090ee00ac 100644 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings +++ b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings @@ -17,13 +17,11 @@ hardcursor true # if true use on-chip cursor capabilities #logmask 0x08000604 # log overlay use in full to file (in home folder) #logmask 0xffffffff # log everything to file (in home folder) switchhead false # switch head assignment (dualhead cards only) -#tv_output 0 # disabled or 0 = autodetect, 1 = Y/C (and CVBS if possible), 2 = CVBS force_sync false # if true forces 3D rendering to be synchronized to the vertical retrace -force_ws false # if true forces widescreen type detection for all connected screens +force_ws true # if true forces widescreen type detection for all connected screens # WARNING: tweak alert! modify stuff below on your own risk... -pgm_panel true # if false don't program DVI and laptop panel pixelclocks (refreshrates) -vga_on_tv false # if true enables VGA output on the head outputting to TV +pgm_panel false # if false don't program DVI and laptop panel pixelclocks (refreshrates) #gpu_clk 150 # in Mhz, (tries to) override default GPU clockspeed (be carefull!!!) #ram_clk 150 # in Mhz, (tries to) override default cardRAM clockspeed (be carefull!!!) @@ -55,7 +53,6 @@ vga_on_tv false # if true enables VGA output on the head outputting to TV #logmask 0x00020000 # engine: crtc2 #logmask 0x00040000 # engine: crtc1 #logmask 0x00080000 # engine: acc (both PIO and DMA) -#logmask 0x00100000 # engine: brooktree tv #logmask 0x00200000 # set displaymode #logmask 0x00400000 # propose displaymode #logmask 0x00800000 # init accelerant