diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp b/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
index c7295f909c..e94b576de1 100644
--- a/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
+++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
@@ -165,24 +165,51 @@ AHCIController::Init()
 		fPortCount = highestPort;
 	}
 
-	TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n",	(fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK);
-	TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n",	fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK);
-	TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n",			fPortCount, (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK);
-	TRACE("cap: Supports Port Multiplier: %s\n",		(fRegs->cap & CAP_SPM) ? "yes" : "no");
-	TRACE("cap: Supports External SATA: %s\n",			(fRegs->cap & CAP_SXS) ? "yes" : "no");
-	TRACE("cap: Enclosure Management Supported: %s\n",	(fRegs->cap & CAP_EMS) ? "yes" : "no");
+	TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n",
+		(fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK);
+	TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n",
+		fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK);
+	TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n", fPortCount,
+		(fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK);
+	TRACE("cap: Supports Port Multiplier: %s\n",
+		(fRegs->cap & CAP_SPM) ? "yes" : "no");
+	TRACE("cap: Supports External SATA: %s\n",
+		(fRegs->cap & CAP_SXS) ? "yes" : "no");
+	TRACE("cap: Enclosure Management Supported: %s\n",
+		(fRegs->cap & CAP_EMS) ? "yes" : "no");
 
-	TRACE("cap: Supports Command List Override: %s\n",	(fRegs->cap & CAP_SCLO) ? "yes" : "no");
-	TRACE("cap: Supports Staggered Spin-up: %s\n",	(fRegs->cap & CAP_SSS) ? "yes" : "no");
-	TRACE("cap: Supports Mechanical Presence Switch: %s\n",	(fRegs->cap & CAP_SMPS) ? "yes" : "no");
-
-	TRACE("cap: Supports 64-bit Addressing: %s\n",		(fRegs->cap & CAP_S64A) ? "yes" : "no");
-	TRACE("cap: Supports Native Command Queuing: %s\n",	(fRegs->cap & CAP_SNCQ) ? "yes" : "no");
-	TRACE("cap: Supports SNotification Register: %s\n",	(fRegs->cap & CAP_SSNTF) ? "yes" : "no");
-	TRACE("cap: Supports Command List Override: %s\n",	(fRegs->cap & CAP_SCLO) ? "yes" : "no");
+	TRACE("cap: Supports Command List Override: %s\n",
+		(fRegs->cap & CAP_SCLO) ? "yes" : "no");
+	TRACE("cap: Supports Staggered Spin-up: %s\n",
+		(fRegs->cap & CAP_SSS) ? "yes" : "no");
+	TRACE("cap: Supports Mechanical Presence Switch: %s\n",
+		(fRegs->cap & CAP_SMPS) ? "yes" : "no");
 
+	TRACE("cap: Supports 64-bit Addressing: %s\n",
+		(fRegs->cap & CAP_S64A) ? "yes" : "no");
+	TRACE("cap: Supports Native Command Queuing: %s\n",
+		(fRegs->cap & CAP_SNCQ) ? "yes" : "no");
+	TRACE("cap: Supports SNotification Register: %s\n",
+		(fRegs->cap & CAP_SSNTF) ? "yes" : "no");
+	TRACE("cap: Supports Command List Override: %s\n",
+		(fRegs->cap & CAP_SCLO) ? "yes" : "no");
 
 	TRACE("cap: Supports AHCI mode only: %s\n",			(fRegs->cap & CAP_SAM) ? "yes" : "no");
+
+	if (fRegs->vs >= 0x00010200) {
+		TRACE("cap2: DevSleep Entrance from Slumber Only: %s\n",
+			(fRegs->cap2 & CAP2_DESO) ? "yes" : "no");
+		TRACE("cap2: Supports Aggressive Device Sleep Management: %s\n",
+			(fRegs->cap2 & CAP2_SADM) ? "yes" : "no");
+		TRACE("cap2: Supports Device Sleep: %s\n",
+			(fRegs->cap2 & CAP2_SDS) ? "yes" : "no");
+		TRACE("cap2: Automatic Partial to Slumber Transitions: %s\n",
+			(fRegs->cap2 & CAP2_APST) ? "yes" : "no");
+		TRACE("cap2: NVMHCI Present: %s\n",
+			(fRegs->cap2 & CAP2_NVMP) ? "yes" : "no");
+		TRACE("cap2: BIOS/OS Handoff: %s\n",
+			(fRegs->cap2 & CAP2_BOH) ? "yes" : "no");
+	}
 	TRACE("ghc: AHCI Enable: %s\n",						(fRegs->ghc & GHC_AE) ? "yes" : "no");
 	TRACE("Ports Implemented Mask: %#08" B_PRIx32 "\n",	fPortImplementedMask);
 	TRACE("Number of Available Ports: %d\n",			count_bits_set(fPortImplementedMask));
diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
index e291e1f8d4..c4b0101c18 100644
--- a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
+++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
@@ -94,8 +94,9 @@ typedef struct {
 	uint32		sact;			// Serial ATA Active (SCR3: SActive) **RW1**
 	uint32		ci;				// Command Issue **RW1**
 	uint32		sntf;			// SNotification
-	uint32		res2;			// Reserved for FIS-based Switching Definition
-	uint32		res[11];		// Reserved
+	uint32		fbs;			// FIS-based Switching Control
+	uint32		devslp;			// Device Sleep
+	uint32		res[10];		// Reserved
 	uint32		vendor[4];		// Vendor Specific
 } _PACKED ahci_port;
 
@@ -151,6 +152,43 @@ enum {
 };
 
 
+enum {
+	PORT_FBS_DWE_SHIFT		= 16,	// Device With Error
+	PORT_FBS_DWE_MASK 		= 0xf,
+	PORT_FBS_ADO_SHIFT		= 12,	// Active Device Optimization
+	PORT_FBS_ADO_MASK 		= 0xf,
+	PORT_FBS_DEV_SHIFT		= 8,	// Device To Issue
+	PORT_FBS_DEV_MASK 		= 0xf,
+	PORT_FBS_SDE			= 0x04,	// Single Device Error
+	PORT_FBS_DEC			= 0x02,	// Device Error Clear
+	PORT_FBS_EN				= 0x01,	// Enable
+};
+
+
+enum {
+	PORT_DEVSLP_DM_SHIFT	= 25,	// DITO Multiplier
+	PORT_DEVSLP_DM_MASK 	= 0xf,
+	PORT_DEVSLP_DITO_SHIFT	= 15,	// Device Sleep Idle Timeout
+	PORT_DEVSLP_DITO_MASK	= 0x3ff,
+	PORT_DEVSLP_MDAT_SHIFT	= 10,	// Minimum Device Sleep Assertion Time
+	PORT_DEVSLP_MDAT_MASK	= 0x1f,
+	PORT_DEVSLP_DETO_SHIFT	= 2,	// Device Sleep Exit Timeout
+	PORT_DEVSLP_DETO_MASK	= 0xff,
+	PORT_DEVSLP_DSP			= 0x02,	// Device Sleep Present
+	PORT_DEVSLP_ADSE		= 0x01,	// Aggressive Device Sleep Enable
+};
+
+
+enum {
+	CAP2_DESO 		= (1 << 5),		// DevSleep Entrance from Slumber Only
+	CAP2_SADM 		= (1 << 4),		// Supports Aggressive Device Sleep Management
+	CAP2_SDS 		= (1 << 3), 	// Supports Device Sleep
+	CAP2_APST 		= (1 << 2),		// Automatic Partial to Slumber Transitions
+	CAP2_NVMP 		= (1 << 1),		// NVMHCI Present
+	CAP2_BOH 		= (1 << 0), 	// BIOS/OS Handoff
+};
+
+
 typedef struct {
 	uint32		cap;			// Host Capabilities
 	uint32		ghc;			// Global Host Control
@@ -161,7 +199,9 @@ typedef struct {
 	uint32		ccc_ports;		// Command Completion Coalsecing Ports
 	uint32		em_loc;			// Enclosure Management Location
 	uint32		em_ctl;			// Enclosure Management Control
-	uint32		res[31];		// Reserved
+	uint32		cap2;			// Host Capabilities Extended
+	uint32		bohc;			// BIOS/OS Handoff Control and Status
+	uint32		res[29];		// Reserved
 	uint32		vendor[24];		// Vendor Specific registers
 	ahci_port	port[32];
 } _PACKED ahci_hba;