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Added x2APIC support.

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* Mostly useful for virtualization at the moment. Works in QEmu.
* Can be enabled by safemode settings/menu.
* Please note that x2APIC normally requires use of VT-d interrupt remapping feature
on real hardware, which we don't support yet.
This commit is contained in:
Jérôme Duval
2013-08-26 21:08:21 +02:00
parent e9eb899aa4
commit 787773400c
7 changed files with 312 additions and 35 deletions
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headers/private/kernel/arch/x86/apic.h
+19
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@@ -113,10 +113,29 @@ bool apic_available();
uint32 apic_read(uint32 offset);
void apic_write(uint32 offset, uint32 data);
uint32 apic_local_id();
uint32 apic_local_version();
uint32 apic_task_priority();
void apic_set_task_priority(uint32 config);
void apic_end_of_interrupt();
void apic_disable_local_ints();
uint32 apic_spurious_intr_vector();
void apic_set_spurious_intr_vector(uint32 config);
uint32 apic_intr_command_1();
void apic_set_intr_command_1(uint32 config);
uint32 apic_intr_command_2();
void apic_set_intr_command_2(uint32 config);
uint32 apic_lvt_timer();
void apic_set_lvt_timer(uint32 config);
uint32 apic_lvt_error();
void apic_set_lvt_error(uint32 config);
uint32 apic_lvt_initial_timer_count();
void apic_set_lvt_initial_timer_count(uint32 config);
uint32 apic_lvt_timer_divide_config();
void apic_set_lvt_timer_divide_config(uint32 config);
status_t apic_init(kernel_args *args);
status_t apic_per_cpu_init(kernel_args *args, int32 cpu);
headers/private/kernel/arch/x86/arch_cpu.h
+27
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@@ -39,11 +39,38 @@
#define IA32_MSR_EFER 0xc0000080
// MSR APIC BASE bits
#define IA32_MSR_APIC_BASE_BSP 0x00000100
#define IA32_MSR_APIC_BASE_X2APIC 0x00000400
#define IA32_MSR_APIC_BASE_ENABLED 0x00000800
#define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000
// MSR EFER bits
// reference
#define IA32_MSR_EFER_SYSCALL (1 << 0)
#define IA32_MSR_EFER_NX (1 << 11)
// X2APIC MSRs.
#define IA32_MSR_APIC_ID 0x00000802
#define IA32_MSR_APIC_VERSION 0x00000803
#define IA32_MSR_APIC_TASK_PRIORITY 0x00000808
#define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a
#define IA32_MSR_APIC_EOI 0x0000080b
#define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d
#define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f
#define IA32_MSR_APIC_ERROR_STATUS 0x00000828
#define IA32_MSR_APIC_INTR_COMMAND 0x00000830
#define IA32_MSR_APIC_LVT_TIMER 0x00000832
#define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833
#define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834
#define IA32_MSR_APIC_LVT_LINT0 0x00000835
#define IA32_MSR_APIC_LVT_LINT1 0x00000836
#define IA32_MSR_APIC_LVT_ERROR 0x00000837
#define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838
#define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839
#define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e
// x86_64 MSRs.
#define IA32_MSR_STAR 0xc0000081
#define IA32_MSR_LSTAR 0xc0000082
headers/private/system/safemode_defs.h
+1
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@@ -11,6 +11,7 @@
#define B_SAFEMODE_DISABLE_IOAPIC "disable_ioapic"
#define B_SAFEMODE_DISABLE_ACPI "disable_acpi"
#define B_SAFEMODE_DISABLE_APIC "disable_apic"
#define B_SAFEMODE_ENABLE_X2APIC "enable_x2apic"
#define B_SAFEMODE_DISABLE_APM "disable_apm"
#define B_SAFEMODE_DISABLE_SMP "disable_smp"
#define B_SAFEMODE_DISABLE_HYPER_THREADING "disable_hyperthreading"