From 7a3806ce873ee0cf43f14028b1593222b5d44adf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Axel=20D=C3=B6rfler?= Date: Sat, 25 Mar 2006 17:47:10 +0000 Subject: [PATCH] Now you can also select the refresh rate you like under R5. Looks like there is room for improvements left in our screen preferences application, which ignores the pixel clock values completely. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16876 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/intel_extreme/mode.cpp | 6 +++--- .../kernel/drivers/graphics/intel_extreme/intel_extreme.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index 74fd18bd4e..bfbba49ae1 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -356,9 +356,9 @@ intel_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high) // lower limit of about 48Hz vertical refresh uint32 totalClocks = (uint32)mode->timing.h_total * (uint32)mode->timing.v_total; uint32 low = (totalClocks * 48L) / 1000L; - if (low < gInfo->shared_info->pll_info.max_frequency) - low = gInfo->shared_info->pll_info.max_frequency; - else if (low > gInfo->shared_info->pll_info.max_frequency) + if (low < gInfo->shared_info->pll_info.min_frequency) + low = gInfo->shared_info->pll_info.min_frequency; + else if (low > gInfo->shared_info->pll_info.max_frequency) return B_ERROR; *_low = low; diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 3ded9aed90..397f5a5bcb 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -175,7 +175,7 @@ if (file >= 0) { info.shared_info->graphics_memory_size = memorySize; info.shared_info->dpms_mode = B_DPMS_ON; info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz - info.shared_info->pll_info.min_frequency = 100000; // 100 MHz (not tested) + info.shared_info->pll_info.min_frequency = 25000; // 25 MHz (not tested) info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed info.shared_info->pll_info.divisor_register = INTEL_DISPLAY_PLL_DIVISOR_0;