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intel_extreme: handle 64-bit PCI BARs

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This commit is contained in:
Jérôme Duval
2022-03-14 16:19:51 +01:00
parent d9df712ebc
commit 7a5f5dc504
1 changed files with 7 additions and 3 deletions
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src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+7 -3
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@@ -530,10 +530,14 @@ intel_extreme_init(intel_info &info)
// TODO: registers are mapped twice (by us and intel_gart), maybe we // TODO: registers are mapped twice (by us and intel_gart), maybe we
// can share it between the drivers // can share it between the drivers
phys_addr_t addr = info.pci->u.h0.base_registers[mmioIndex];
uint64 barSize = info.pci->u.h0.base_register_sizes[mmioIndex];
if ((info.pci->u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) {
addr |= (uint64)info.pci->u.h0.base_registers[mmioIndex + 1] << 32;
barSize |= (uint64)info.pci->u.h0.base_register_sizes[mmioIndex + 1] << 32;
}
AreaKeeper mmioMapper; AreaKeeper mmioMapper;
info.registers_area = mmioMapper.Map("intel extreme mmio", info.registers_area = mmioMapper.Map("intel extreme mmio", addr, barSize,
info.pci->u.h0.base_registers[mmioIndex],
info.pci->u.h0.base_register_sizes[mmioIndex],
B_ANY_KERNEL_ADDRESS, B_ANY_KERNEL_ADDRESS,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA,
(void**)&info.registers); (void**)&info.registers);