diff --git a/src/add-ons/accelerants/nvidia/Cursor.c b/src/add-ons/accelerants/nvidia/Cursor.c index 6b3a1aa30f..aa8bd7178e 100644 --- a/src/add-ons/accelerants/nvidia/Cursor.c +++ b/src/add-ons/accelerants/nvidia/Cursor.c @@ -142,7 +142,8 @@ void MOVE_CURSOR(uint16 x, uint16 y) else y = 0; /* account for switched CRTC's */ - if (si->switched_crtcs) x -= si->dm.timing.h_display; +//fixme: we need new tweaking to get the cursors working together in dualhead modes... +// if (si->switched_crtcs) x -= si->dm.timing.h_display; /* position the cursor on the display */ nv_crtc_cursor_position(x,y); diff --git a/src/add-ons/accelerants/nvidia/SetDisplayMode.c b/src/add-ons/accelerants/nvidia/SetDisplayMode.c index 6527252e0e..e6817b0a58 100644 --- a/src/add-ons/accelerants/nvidia/SetDisplayMode.c +++ b/src/add-ons/accelerants/nvidia/SetDisplayMode.c @@ -76,10 +76,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) } LOG(1, ("SETMODE: (CONT.) validated command modeflags: $%08x\n", target.flags)); - /* overlay engine, cursor and MOVE_DISPLAY need to know the status even when - * in singlehead mode */ - si->switched_crtcs = false; - /* disable interrupts using the kernel driver */ interrupt_enable(false); @@ -171,120 +167,24 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) /* set the outputs */ switch (si->ps.card_type) { - case NV11: + case G550: switch (target.flags & DUALHEAD_BITS) { case DUALHEAD_ON: case DUALHEAD_CLONE: + //fixme: set output connectors only nv_general_dac_select(DS_CRTC1DAC_CRTC2MAVEN); - si->switched_crtcs = false; break; case DUALHEAD_SWITCH: - if (i2c_sec_tv_adapter() == B_OK) - { - /* Don't switch CRTC's because MAVEN YUV is impossible then, - * and primary head output will be limited to 135Mhz pixelclock. */ - LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n")); - nv_general_dac_select(DS_CRTC1DAC_CRTC2MAVEN); - si->switched_crtcs = true; - } - else - { - /* This limits the pixelclocks on both heads to 135Mhz, - * but you can use overlay on the other output now. */ - LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n")); - nv_general_dac_select(DS_CRTC1MAVEN_CRTC2DAC); - si->switched_crtcs = false; - } + //fixme: set output connectors only + nv_general_dac_select(DS_CRTC1MAVEN_CRTC2DAC); break; } break; - //fixme: - //setup crtc_delay and vertical timing adjust for G450(?)/G550, - //and remove the '+1' in crtc2 vertical timing(?) - case NV17: - if (!si->ps.primary_dvi) - /* output connector use is always 'straight-through' */ - //fixme: re-evaluate when DVI is setup... - { - switch (target.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_CLONE: - nv_general_dac_select(DS_CRTC1CON1_CRTC2CON2); - si->switched_crtcs = false; - break; - case DUALHEAD_SWITCH: - if (i2c_sec_tv_adapter() == B_OK) - { - /* Don't switch CRTC's because MAVEN YUV and TVout is impossible then, - * and primary head output will be limited to 235Mhz pixelclock. */ - LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n")); - nv_general_dac_select(DS_CRTC1CON1_CRTC2CON2); - si->switched_crtcs = true; - } - else - { - /* This limits the pixelclocks on both heads to 235Mhz, - * but you can use overlay on the other output now. */ - LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n")); - nv_general_dac_select(DS_CRTC1CON2_CRTC2CON1); - si->switched_crtcs = false; - } - break; - } - } - else - /* output connector use is cross-linked if no TV cable connected! */ - //fixme: re-evaluate when DVI is setup... - { - switch (target.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_CLONE: - if (i2c_sec_tv_adapter() == B_OK) - { - nv_general_dac_select(DS_CRTC1CON1_CRTC2CON2); - si->switched_crtcs = false; - } - else - { - /* This limits the pixelclocks on both heads to 235Mhz, - * but you can use overlay on the other output now. */ - nv_general_dac_select(DS_CRTC1CON2_CRTC2CON1); - si->switched_crtcs = false; - } - break; - case DUALHEAD_SWITCH: - if (i2c_sec_tv_adapter() == B_OK) - { - /* Don't switch CRTC's because MAVEN YUV and TVout is impossible then, - * and primary head output will be limited to 235Mhz pixelclock. */ - LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n")); - nv_general_dac_select(DS_CRTC1CON1_CRTC2CON2); - si->switched_crtcs = true; - } - else - { - LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n")); - nv_general_dac_select(DS_CRTC1CON1_CRTC2CON2); - si->switched_crtcs = false; - } - break; - } - } - break; default: break; } - if (si->switched_crtcs) - { - uint32 temp = startadd; - startadd = startadd_right; - startadd_right = temp; - } - /*Tell card what memory to display*/ switch (target.flags & DUALHEAD_BITS) { @@ -305,11 +205,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) if (!(target2.flags & TV_BITS)) result = nv_crtc2_set_timing(target2); /* TVout support: setup CRTC2 and it's pixelclock */ - if (si->ps.tvout && (target2.flags & TV_BITS)) - { - si->crtc_delay += 5; - maventv_init(target2); - } + if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2); } else /* single head mode */ { @@ -471,14 +367,6 @@ status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) { startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3); - /* account for switched CRTC's */ - if (si->switched_crtcs) - { - uint32 temp = startadd; - startadd = startadd_right; - startadd_right = temp; - } - interrupt_enable(false); switch (si->dm.flags & DUALHEAD_BITS) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_bes.c b/src/add-ons/accelerants/nvidia/engine/nv_bes.c index b661063a65..77604e4921 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_bes.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_bes.c @@ -1,5 +1,5 @@ /* Nvidia TNT and GeForce Back End Scaler functions */ -/* Written by Rudolf Cornelissen 05/2002-12/2003 */ +/* Written by Rudolf Cornelissen 05/2002-1/2004 */ #define MODULE_BIT 0x00000200 @@ -104,10 +104,12 @@ status_t nv_configure_bes * constraints only */ crtc_hstart = si->dm.h_display_start; /* make dualhead switch mode with TVout enabled work while we're at it.. */ - if (si->switched_crtcs) +//fixme: probably no fix at all needed on NV cards... +/* if (si->switched_crtcs) { crtc_hstart += si->dm.timing.h_display; } +*/ /* horizontal end is the first position beyond the displayed range on the CRTC */ crtc_hend = crtc_hstart + si->dm.timing.h_display; crtc_vstart = si->dm.v_display_start; diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index 0f964f4846..cf65528c64 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -80,7 +80,7 @@ status_t nv_general_powerup() { status_t status; - LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.08-3 running.\n")); + LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.08-4 running.\n")); /* preset no laptop */ si->ps.laptop = false; @@ -296,7 +296,7 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia Quadro4 XGL (NV25)\n")); status = nvxx_general_powerup(); break; - case 0x028010de: /* Nvidia GeForce4 Ti 4600 AGP8X (4800?) */ + case 0x028010de: /* Nvidia GeForce4 Ti 4800 AGP8X */ case 0x028110de: /* Nvidia GeForce4 Ti 4200 AGP8X */ si->ps.card_type = NV28; si->ps.card_arch = NV20A; @@ -436,7 +436,7 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV34)\n")); status = nvxx_general_powerup(); break; - case 0x032810de: /* Nvidia GeForce FX 5200 Go */ + case 0x032810de: /* Nvidia GeForce FX 5200 Go 32M/64M */ si->ps.card_type = NV34; si->ps.card_arch = NV30A; si->ps.laptop = true; diff --git a/src/add-ons/accelerants/nvidia/engine/nv_maventv.c b/src/add-ons/accelerants/nvidia/engine/nv_maventv.c index 718f8a7f42..d0a2633935 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_maventv.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_maventv.c @@ -689,41 +689,41 @@ int maventv_init(display_mode target) // if (si->ps.card_type <= G400MAX) { /* setup TV-mode 'copy' of CRTC2, setup PLL, inputs, outputs and sync-locks */ - MAVW(MONSET, 0x00); - MAVW(MONEN, 0xA2); +// MAVW(MONSET, 0x00); +// MAVW(MONEN, 0xA2); /* xmiscctrl */ //unknown regs: - MAVWW(WREG_0X8E_L, 0x1EFF); - MAVW(BREG_0XC6, 0x01); +// MAVWW(WREG_0X8E_L, 0x1EFF); +// MAVW(BREG_0XC6, 0x01); - MAVW(LOCK, 0x01); - MAVW(OUTMODE, 0x08); - MAVW(LUMA, 0x78); - MAVW(STABLE, 0x02); - MAVW(MONEN, 0xB3); +// MAVW(LOCK, 0x01); +// MAVW(OUTMODE, 0x08); +// MAVW(LUMA, 0x78); +// MAVW(STABLE, 0x02); +// MAVW(MONEN, 0xB3); /* setup video PLL */ g100_g400max_maventv_vid_pll_find( tv_target, &ht_new, &ht_last_line, &m_result, &n_result, &p_result); - MAVW(PIXPLLM, m_result); - MAVW(PIXPLLN, n_result); - MAVW(PIXPLLP, (p_result | 0x80)); +// MAVW(PIXPLLM, m_result); +// MAVW(PIXPLLN, n_result); +// MAVW(PIXPLLP, (p_result | 0x80)); - MAVW(MONSET, 0x20); +// MAVW(MONSET, 0x20); - MAVW(TEST, 0x10); +// MAVW(TEST, 0x10); /* htotal - 2 */ - MAVWW(HTOTALL, ht_new); +// MAVWW(HTOTALL, ht_new); /* last line in field can have different length */ /* hlen - 2 */ - MAVWW(LASTLINEL, ht_last_line); +// MAVWW(LASTLINEL, ht_last_line); /* horizontal vidrst pos: 0 <= vidrst pos <= htotal - 2 */ - MAVWW(HVIDRSTL, (ht_last_line - si->crtc_delay - - (tv_target.timing.h_sync_end - tv_target.timing.h_sync_start))); +// MAVWW(HVIDRSTL, (ht_last_line - si->crtc_delay - +// (tv_target.timing.h_sync_end - tv_target.timing.h_sync_start))); //ORG (does the same but with limit checks but these limits should never occur!): // slen = tv_target.timing.h_sync_end - tv_target.timing.h_sync_start; // hcrt = tv_target.timing.h_total - slen - si->crtc_delay; @@ -733,35 +733,35 @@ int maventv_init(display_mode target) // MAVWW(HVIDRSTL, hcrt); /* who knows */ - MAVWW(HSYNCSTRL, 0x0004);//must be 4!! +// MAVWW(HSYNCSTRL, 0x0004);//must be 4!! /* hblanking end: 100% */ - MAVWW(HSYNCLENL, (tv_target.timing.h_total - tv_target.timing.h_sync_end)); +// MAVWW(HSYNCLENL, (tv_target.timing.h_total - tv_target.timing.h_sync_end)); /* vertical line count - 1 */ - MAVWW(VTOTALL, (tv_target.timing.v_total - 1)); +// MAVWW(VTOTALL, (tv_target.timing.v_total - 1)); /* vertical vidrst pos */ - MAVWW(VVIDRSTL, (tv_target.timing.v_total - 2)); +// MAVWW(VVIDRSTL, (tv_target.timing.v_total - 2)); /* something end... [A6]+1..[A8] */ - MAVWW(VSYNCSTRL, 0x0001); +// MAVWW(VSYNCSTRL, 0x0001); /* vblanking end: stop vblanking */ - MAVWW(VSYNCLENL, (tv_target.timing.v_sync_end - tv_target.timing.v_sync_start - 1)); +// MAVWW(VSYNCLENL, (tv_target.timing.v_sync_end - tv_target.timing.v_sync_start - 1)); //org: no visible diff: //MAVWW(VSYNCLENL, (tv_target.timing.v_total - tv_target.timing.v_sync_start - 1)); /* something start... 0..[A4]-1 */ - MAVWW(VDISPLAYL, 0x0000); +// MAVWW(VDISPLAYL, 0x0000); //std setmode (no visible difference) //MAVWW(VDISPLAYL, (tv_target.timing.v_total - 1)); /* ... */ - MAVWW(WREG_0X98_L, 0x0000); +// MAVWW(WREG_0X98_L, 0x0000); /* moves picture up/down and so on... */ - MAVWW(VSOMETHINGL, 0x0001); /* Fix this... 0..VTotal */ +// MAVWW(VSOMETHINGL, 0x0001); /* Fix this... 0..VTotal */ { uint32 h_display_tv; @@ -810,8 +810,8 @@ int maventv_init(display_mode target) h_display_tv = h_display_tv >> 1; /* limit value to register contraints */ if (h_display_tv > 0xFF) h_display_tv = 0xFF; - MAVW(HSCALETV, h_scale_tv); - MAVW(HDISPLAYTV, h_display_tv); +// MAVW(HSCALETV, h_scale_tv); +// MAVW(HDISPLAYTV, h_display_tv); /* calculate line inputbuffer length */ @@ -848,7 +848,7 @@ int maventv_init(display_mode target) ib_length = ib_min_length; LOG(4,("MAVENTV: limiting line inputbuffer length, setting minimal usable: %d\n", ib_length)); } - MAVWW(HDISPLAYL, ib_length); +// MAVWW(HDISPLAYL, ib_length); } { @@ -899,34 +899,34 @@ int maventv_init(display_mode target) /* make sure we get no round-off error artifacts on screen */ t_scale_tv--; - MAVWW(TSCALETVL, t_scale_tv); - MAVW(VDISPLAYTV, v_display_tv); +// MAVWW(TSCALETVL, t_scale_tv); +// MAVW(VDISPLAYTV, v_display_tv); } - MAVW(TEST, 0x00); +// MAVW(TEST, 0x00); /* gamma correction registers */ - MAVW(GAMMA1, 0x00); - MAVW(GAMMA2, 0x00); - MAVW(GAMMA3, 0x00); - MAVW(GAMMA4, 0x1F); - MAVW(GAMMA5, 0x10); - MAVW(GAMMA6, 0x10); - MAVW(GAMMA7, 0x10); - MAVW(GAMMA8, 0x64); /* 100 */ - MAVW(GAMMA9, 0xC8); /* 200 */ +// MAVW(GAMMA1, 0x00); +// MAVW(GAMMA2, 0x00); +// MAVW(GAMMA3, 0x00); +// MAVW(GAMMA4, 0x1F); +// MAVW(GAMMA5, 0x10); +// MAVW(GAMMA6, 0x10); +// MAVW(GAMMA7, 0x10); +// MAVW(GAMMA8, 0x64); /* 100 */ +// MAVW(GAMMA9, 0xC8); /* 200 */ /* set flickerfilter */ /* OFF: is dependant on MAVEN chip version(?): NV_TVO_B = $40, else $00. * ON : always set $a2. */ - MAVW(FFILTER, 0xa2); +// MAVW(FFILTER, 0xa2); /* 0x10 or anything ored with it */ //fixme? linux uses 0x14... - MAVW(TEST, (MAVR(TEST) & 0x10)); +// MAVW(TEST, (MAVR(TEST) & 0x10)); /* output: SVideo/Composite */ - MAVW(OUTMODE, 0x08); +// MAVW(OUTMODE, 0x08); } // else /* card_type is >= G450 */ {