From 7c012c2316c5831cb8521f6a4e8823628987fa43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Axel=20D=C3=B6rfler?= Date: Fri, 3 Dec 2004 08:25:34 +0000 Subject: [PATCH] Accidently used level 2 cache format to print out level 1 instruction cache on AMD and other CPUs - thanks to BiPolar for reporting this! git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10354 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/apps/bin/sysinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/apps/bin/sysinfo.c b/src/apps/bin/sysinfo.c index e0122279ec..43c81d6fbc 100644 --- a/src/apps/bin/sysinfo.c +++ b/src/apps/bin/sysinfo.c @@ -191,7 +191,7 @@ print_cache_descriptors(int32 cpu) print_TLB(info.regs.ebx, info.regs.eax ? "4K-byte" : NULL); print_level1_cache(info.regs.ecx, "L1 inst cache"); - print_level2_cache(info.regs.edx, "L1 data cache"); + print_level1_cache(info.regs.edx, "L1 data cache"); get_cpuid(&info, 0x80000006, cpu); print_level2_cache(info.regs.ecx, "L2 cache");