Preparation for MTRR support, code is completely untested, though.

The CPU specific MTRR code will be in modules.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15520 a95241bf-73f2-0310-859d-f6bbb57e9c96

headers/private/kernel/arch/vm.h

@@ -22,6 +22,10 @@ status_t arch_vm_init_post_area(struct kernel_args *args);
 status_t arch_vm_init_end(struct kernel_args *args);
 void arch_vm_aspace_swap(vm_address_space *aspace);
 bool arch_vm_supports_protection(uint32 protection);
+void arch_vm_init_area(vm_area *area);
+
+status_t arch_vm_set_memory_type(vm_area *area, uint32 type);
+void arch_vm_unset_memory_type(vm_area *area);
 
 #ifdef __cplusplus
 }

headers/private/kernel/arch/vm_types.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright 2005, Axel Dörfler, [email protected].
+ * Distributed under the terms of the MIT License.
+ */
+#ifndef KERNEL_ARCH_VM_TYPES_H
+#define KERNEL_ARCH_VM_TYPES_H
+
+#include <arch_vm_types.h>
+
+#endif	/* KERNEL_ARCH_VM_TYPES_H */

headers/private/kernel/arch/x86/arch_cpu.h

@@ -9,13 +9,22 @@
 #define _KERNEL_ARCH_x86_CPU_H
 
 
-#include <SupportDefs.h>
+#include <module.h>
 #include <arch/x86/descriptors.h>
 
 
 // MSR registers (possibly Intel specific)
 #define IA32_MSR_APIC_BASE	0x1b
 
+
+typedef struct x86_cpu_module_info {
+	module_info	info;
+	uint32		(*count_mtrrs)(void);
+	status_t	(*set_mtrr)(uint32 index, addr_t base, addr_t length, uint32 type);
+	status_t	(*unset_mtrr)(uint32 index);
+} x86_cpu_module_info;
+
+
 struct tss {
 	uint16 prev_task;
 	uint16 unused0;
@@ -78,9 +87,12 @@ void i386_frstor(const void *fpu_state);
 void i386_fxrstor(const void *fpu_state);
 void i386_fsave_swap(void *old_fpu_state, const void *new_fpu_state);
 void i386_fxsave_swap(void *old_fpu_state, const void *new_fpu_state);
-uint64 x86_read_msr(uint32 register);
-void x86_write_msr(uint32 register, uint64 value);
+uint64 x86_read_msr(uint32 registerNumber);
+void x86_write_msr(uint32 registerNumber, uint64 value);
 void x86_set_task_gate(int32 n, int32 segment);
+uint32 x86_count_mtrrs(void);
+status_t x86_set_mtrr(uint32 index, addr_t base, addr_t length, uint32 type);
+status_t x86_unset_mtrr(uint32 index);
 struct tss *x86_get_main_tss(void);
 
 #define read_ebp(value) \

headers/private/kernel/arch/x86/arch_vm_types.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright 2005, Axel Dörfler, [email protected]. All rights reserved.
+ * Distributed under the terms of the MIT License.
+ */
+#ifndef _KERNEL_ARCH_x86_VM_TYPES_H
+#define _KERNEL_ARCH_x86_VM_TYPES_H
+
+
+#include <SupportDefs.h>
+
+
+struct arch_vm_memory_type {
+	uint16	type;
+	uint16	index;
+};
+
+#endif	/* _KERNEL_ARCH_x86_VM_TYPES_H */

headers/private/kernel/cpu.h

@@ -19,18 +19,14 @@
 typedef union cpu_ent {
 	struct {
 		int cpu_num;
-		
+
 		// thread.c: used to force a reschedule at quantum expiration time
 		int preempted;
 		timer quantum_timer;
 	} info;
-	// ToDo: align manually on CPU cache lines if possible
-	uint32 align[16];
-} cpu_ent;
+} cpu_ent __attribute__((aligned(64)));
+
 
-/**
- * Defined in core/cpu.c
- */
 extern cpu_ent cpu[MAX_BOOT_CPUS];
 
 

headers/private/kernel/vm_types.h

@@ -1,5 +1,5 @@
 /* 
- * Copyright 2002-2004, Axel Dörfler, [email protected].
+ * Copyright 2002-2005, Axel Dörfler, [email protected].
  * Distributed under the terms of the MIT License.
  *
  * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
@@ -11,6 +11,7 @@
 
 #include <kernel.h>
 #include <sys/uio.h>
+#include <arch/vm_types.h>
 #include <arch/vm_translation_map.h>
 
 
@@ -84,6 +85,7 @@ typedef struct vm_area {
 	uint32				protection;
 	uint32				wiring;
 	int32				ref_count;
+	struct arch_vm_memory_type memory_type;
 
 	struct vm_cache_ref	*cache_ref;
 	off_t				cache_offset;