Merge remote-tracking branch 'haiku/master' into package-management

Conflicts: build/jam/HaikuImage build/jam/OptionalPackageDependencies build/jam/OptionalPackages build/scripts/build_cross_tools_gcc4 src/add-ons/translators/icns/Jamfile src/add-ons/translators/jpeg/Jamfile
2013-07-08 14:01:00 +02:00
parent 2f3dc946cd 5d4ef3e417
commit 7e78b434f4
438 changed files with 15612 additions and 25171 deletions
@@ -131,18 +131,18 @@ struct pci_module_info {
 						pci_info 	*info	/* caller-supplied buffer for info */
 					);
 	uint32			(*read_pci_config) (
-						uchar	bus,		/* bus number */
-						uchar	device,		/* device # on bus */
-						uchar	function,	/* function # in device */
-						uchar	offset,		/* offset in configuration space */
-						uchar	size		/* # bytes to read (1, 2 or 4) */
+						uint8	bus,		/* bus number */
+						uint8	device,		/* device # on bus */
+						uint8	function,	/* function # in device */
+						uint16	offset,		/* offset in configuration space */
+						uint8	size		/* # bytes to read (1, 2 or 4) */
 					);
 	void			(*write_pci_config) (
-						uchar	bus,		/* bus number */
-						uchar	device,		/* device # on bus */
-						uchar	function,	/* function # in device */
-						uchar	offset,		/* offset in configuration space */
-						uchar	size,		/* # bytes to write (1, 2 or 4) */
+						uint8	bus,		/* bus number */
+						uint8	device,		/* device # on bus */
+						uint8	function,	/* function # in device */
+						uint16	offset,		/* offset in configuration space */
+						uint8	size,		/* # bytes to write (1, 2 or 4) */
 						uint32	value		/* value to write */
 					);

@@ -174,6 +174,14 @@ struct pci_module_info {
 						uchar device,
 						uchar function,
 						uchar newInterruptLineValue);
+
+	status_t		(*find_pci_extended_capability) (
+						uint8	bus,
+						uint8	device,
+						uint8	function,
+						uint16	cap_id,
+						uint16	*offset
+					);
 };

 #define	B_PCI_MODULE_NAME		"bus_managers/pci/v1"
@@ -196,6 +204,7 @@ struct pci_module_info {
 #define PCI_header_type			0x0e		/* (1 byte) header type */
 #define PCI_bist				0x0f		/* (1 byte) built-in self-test */

+#define PCI_extended_capability 0x100		/* (4 bytes) extended capability */


 /* ---
@@ -690,6 +699,41 @@ struct pci_module_info {
 #define PCI_cap_id_sata		0x12	/* Serial ATA Capability */
 #define PCI_cap_id_pciaf	0x13	/* PCI Advanced Features */

+/** PCI Extended Capabilities */
+#define PCI_extcap_id(x)		(x & 0x0000ffff)
+#define PCI_extcap_version(x)	((x & 0x000f0000) >> 16)
+#define PCI_extcap_next_ptr(x)	((x & 0xfff00000) >> 20)
+
+#define PCI_extcap_id_aer			0x0001	/* Advanced Error Reporting */
+#define PCI_extcap_id_vc			0x0002	/* Virtual Channel */
+#define PCI_extcap_id_serial		0x0003	/* Serial Number */
+#define PCI_extcap_id_power_budget	0x0004	/* Power Budgeting */
+#define PCI_extcap_id_rcl_decl		0x0005	/* Root Complex Link Declaration */
+#define PCI_extcap_id_rcil_ctl		0x0006	/* Root Complex Internal Link Control */
+#define PCI_extcap_id_rcec_assoc	0x0007	/* Root Complex Event Collector Association */
+#define PCI_extcap_id_mfvc			0x0008	/* MultiFunction Virtual Channel */
+#define PCI_extcap_id_vc2			0x0009	/* Virtual Channel 2 */
+#define PCI_extcap_id_rcrb_header	0x000a	/* RCRB Header */
+#define PCI_extcap_id_vendor		0x000b	/* Vendor Unique */
+#define PCI_extcap_id_acs			0x000d	/* Access Control Services */
+#define PCI_extcap_id_ari			0x000e	/* Alternative Routing Id Interpretation */
+#define PCI_extcap_id_ats			0x000f	/* Address Translation Services */
+#define PCI_extcap_id_srio_virtual	0x0010	/* Single Root I/O Virtualization */
+#define PCI_extcap_id_mrio_virtual	0x0011	/* Multiple Root I/O Virtual */
+#define PCI_extcap_id_multicast		0x0012	/* Multicast */
+#define PCI_extcap_id_page_request	0x0013	/* Page Request */
+#define PCI_extcap_id_amd			0x0014	/* AMD Reserved */
+#define PCI_extcap_id_resizable_bar	0x0015	/* Resizable Bar */
+#define PCI_extcap_id_dyn_power_alloc	0x0016	/* Dynamic Power Allocation */
+#define PCI_extcap_id_tph_requester	0x0017	/* TPH Requester */
+#define PCI_extcap_id_latency_tolerance	0x0018	/* Latency Tolerance Reporting */
+#define PCI_extcap_id_2ndpcie		0x0019	/* Secondary PCIe */
+#define PCI_extcap_id_pmux			0x001a	/* Protocol Multiplexing */
+#define PCI_extcap_id_pasid			0x001b	/* Process Address Space Id */
+#define PCI_extcap_id_ln_requester	0x001c	/* LN Requester */
+#define PCI_extcap_id_dpc			0x001d	/* Downstream Porto Containment */
+#define PCI_extcap_id_l1pm			0x001e	/* L1 Power Management Substates */
+
 /** Power Management Control Status Register settings */
 #define PCI_pm_mask             0x03
 #define PCI_pm_ctrl             0x02
@@ -27,13 +27,15 @@ typedef struct pci_device_module_info {

 	void	*(*ram_address)(pci_device *device, const void *physicalAddress);

-	uint32	(*read_pci_config)(pci_device *device, uint8 offset,
+	uint32	(*read_pci_config)(pci_device *device, uint16 offset,
 				uint8 size);
-	void	(*write_pci_config)(pci_device *device, uint8 offset,
+	void	(*write_pci_config)(pci_device *device, uint16 offset,
 				uint8 size, uint32 value);
 	status_t (*find_pci_capability)(pci_device *device, uint8 capID,
 				uint8 *offset);
 	void 	(*get_pci_info)(pci_device *device, struct pci_info *info);
+	status_t (*find_pci_extended_capability)(pci_device *device, uint16 capID,
+				uint16 *offset);
 } pci_device_module_info;


@@ -256,7 +256,7 @@ typedef struct {
 	uint32		sim_priv;				/* Size of SIM private data area */
 	uchar		vuhba_flags[SCSI_VUHBA];/* Vendor unique capabilities */
 	uchar		initiator_id;			/* ID of the HBA on the SCSI bus */
-	uint32		hba_queue_size;			// size of adapaters command queue
+	uint32		hba_queue_size;			// size of adapters command queue
 	char		sim_vid[SCSI_SIM_ID];	/* Vendor ID of the SIM */
 	char		hba_vid[SCSI_HBA_ID];	/* Vendor ID of the HBA */