diff --git a/headers/private/graphics/radeon_hd/car_reg.h b/headers/private/graphics/radeon_hd/car_reg.h index f745a38d7d..875bdb007f 100644 --- a/headers/private/graphics/radeon_hd/car_reg.h +++ b/headers/private/graphics/radeon_hd/car_reg.h @@ -21,7628 +21,12 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +/* This header has been modified from its original version: + * it has been formatted to contain only the constants Haiku needs. */ + #ifndef DCE_11_0_D_H #define DCE_11_0_D_H -#define CAR_mmPIPE0_PG_CONFIG 0x2c0 -#define CAR_mmPIPE0_PG_ENABLE 0x2c1 -#define CAR_mmPIPE0_PG_STATUS 0x2c2 -#define CAR_mmPIPE1_PG_CONFIG 0x2c3 -#define CAR_mmPIPE1_PG_ENABLE 0x2c4 -#define CAR_mmPIPE1_PG_STATUS 0x2c5 -#define CAR_mmPIPE2_PG_CONFIG 0x2c6 -#define CAR_mmPIPE2_PG_ENABLE 0x2c7 -#define CAR_mmPIPE2_PG_STATUS 0x2c8 -#define CAR_mmDCFEV0_PG_CONFIG 0x2db -#define CAR_mmDCFEV0_PG_ENABLE 0x2dc -#define CAR_mmDCFEV0_PG_STATUS 0x2dd -#define CAR_mmDCPG_INTERRUPT_STATUS 0x2de -#define CAR_mmDCPG_INTERRUPT_CONTROL 0x2df -#define CAR_mmDC_IP_REQUEST_CNTL 0x2d2 -#define CAR_mmDC_PGFSM_CONFIG_REG 0x2d3 -#define CAR_mmDC_PGFSM_WRITE_REG 0x2d4 -#define CAR_mmDC_PGCNTL_STATUS_REG 0x2d5 -#define CAR_mmDCPG_TEST_DEBUG_INDEX 0x2d6 -#define CAR_mmDCPG_TEST_DEBUG_DATA 0x2d7 -#define CAR_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 -#define CAR_mmBL1_PWM_USER_LEVEL 0x1629 -#define CAR_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a -#define CAR_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b -#define CAR_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c -#define CAR_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d -#define CAR_mmBL1_PWM_ABM_CNTL 0x162e -#define CAR_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f -#define CAR_mmBL1_PWM_GRP2_REG_LOCK 0x1630 -#define CAR_mmDC_ABM1_CNTL 0x1638 -#define CAR_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 -#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a -#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b -#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c -#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d -#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e -#define CAR_mmDC_ABM1_ACE_THRES_12 0x163f -#define CAR_mmDC_ABM1_ACE_THRES_34 0x1640 -#define CAR_mmDC_ABM1_ACE_CNTL_MISC 0x1641 -#define CAR_mmDC_ABM1_DEBUG_MISC 0x1649 -#define CAR_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a -#define CAR_mmDC_ABM1_HG_MISC_CTRL 0x164b -#define CAR_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c -#define CAR_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d -#define CAR_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e -#define CAR_mmDC_ABM1_LS_PIXEL_COUNT 0x164f -#define CAR_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 -#define CAR_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 -#define CAR_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 -#define CAR_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 -#define CAR_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 -#define CAR_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 -#define CAR_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 -#define CAR_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 -#define CAR_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 -#define CAR_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 -#define CAR_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a -#define CAR_mmDC_ABM1_HG_RESULT_1 0x165b -#define CAR_mmDC_ABM1_HG_RESULT_2 0x165c -#define CAR_mmDC_ABM1_HG_RESULT_3 0x165d -#define CAR_mmDC_ABM1_HG_RESULT_4 0x165e -#define CAR_mmDC_ABM1_HG_RESULT_5 0x165f -#define CAR_mmDC_ABM1_HG_RESULT_6 0x1660 -#define CAR_mmDC_ABM1_HG_RESULT_7 0x1661 -#define CAR_mmDC_ABM1_HG_RESULT_8 0x1662 -#define CAR_mmDC_ABM1_HG_RESULT_9 0x1663 -#define CAR_mmDC_ABM1_HG_RESULT_10 0x1664 -#define CAR_mmDC_ABM1_HG_RESULT_11 0x1665 -#define CAR_mmDC_ABM1_HG_RESULT_12 0x1666 -#define CAR_mmDC_ABM1_HG_RESULT_13 0x1667 -#define CAR_mmDC_ABM1_HG_RESULT_14 0x1668 -#define CAR_mmDC_ABM1_HG_RESULT_15 0x1669 -#define CAR_mmDC_ABM1_HG_RESULT_16 0x166a -#define CAR_mmDC_ABM1_HG_RESULT_17 0x166b -#define CAR_mmDC_ABM1_HG_RESULT_18 0x166c -#define CAR_mmDC_ABM1_HG_RESULT_19 0x166d -#define CAR_mmDC_ABM1_HG_RESULT_20 0x166e -#define CAR_mmDC_ABM1_HG_RESULT_21 0x166f -#define CAR_mmDC_ABM1_HG_RESULT_22 0x1670 -#define CAR_mmDC_ABM1_HG_RESULT_23 0x1671 -#define CAR_mmDC_ABM1_HG_RESULT_24 0x1672 -#define CAR_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b -#define CAR_mmDC_ABM1_BL_MASTER_LOCK 0x169c -#define CAR_mmABM_TEST_DEBUG_INDEX 0x169e -#define CAR_mmABM_TEST_DEBUG_DATA 0x169f -#define CAR_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d -#define CAR_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d -#define CAR_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d -#define CAR_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d -#define CAR_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d -#define CAR_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d -#define CAR_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d -#define CAR_mmCRTC_H_TOTAL 0x1b80 -#define CAR_mmCRTC0_CRTC_H_TOTAL 0x1b80 -#define CAR_mmCRTC1_CRTC_H_TOTAL 0x1d80 -#define CAR_mmCRTC2_CRTC_H_TOTAL 0x1f80 -#define CAR_mmCRTC3_CRTC_H_TOTAL 0x4180 -#define CAR_mmCRTC4_CRTC_H_TOTAL 0x4380 -#define CAR_mmCRTC5_CRTC_H_TOTAL 0x4580 -#define CAR_mmCRTC_H_BLANK_START_END 0x1b81 -#define CAR_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 -#define CAR_mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 -#define CAR_mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 -#define CAR_mmCRTC3_CRTC_H_BLANK_START_END 0x4181 -#define CAR_mmCRTC4_CRTC_H_BLANK_START_END 0x4381 -#define CAR_mmCRTC5_CRTC_H_BLANK_START_END 0x4581 -#define CAR_mmCRTC_H_SYNC_A 0x1b82 -#define CAR_mmCRTC0_CRTC_H_SYNC_A 0x1b82 -#define CAR_mmCRTC1_CRTC_H_SYNC_A 0x1d82 -#define CAR_mmCRTC2_CRTC_H_SYNC_A 0x1f82 -#define CAR_mmCRTC3_CRTC_H_SYNC_A 0x4182 -#define CAR_mmCRTC4_CRTC_H_SYNC_A 0x4382 -#define CAR_mmCRTC5_CRTC_H_SYNC_A 0x4582 -#define CAR_mmCRTC_H_SYNC_A_CNTL 0x1b83 -#define CAR_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 -#define CAR_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 -#define CAR_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 -#define CAR_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 -#define CAR_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 -#define CAR_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 -#define CAR_mmCRTC_H_SYNC_B 0x1b84 -#define CAR_mmCRTC0_CRTC_H_SYNC_B 0x1b84 -#define CAR_mmCRTC1_CRTC_H_SYNC_B 0x1d84 -#define CAR_mmCRTC2_CRTC_H_SYNC_B 0x1f84 -#define CAR_mmCRTC3_CRTC_H_SYNC_B 0x4184 -#define CAR_mmCRTC4_CRTC_H_SYNC_B 0x4384 -#define CAR_mmCRTC5_CRTC_H_SYNC_B 0x4584 -#define CAR_mmCRTC_H_SYNC_B_CNTL 0x1b85 -#define CAR_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 -#define CAR_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 -#define CAR_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 -#define CAR_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 -#define CAR_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 -#define CAR_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 -#define CAR_mmCRTC_VBI_END 0x1b86 -#define CAR_mmCRTC0_CRTC_VBI_END 0x1b86 -#define CAR_mmCRTC1_CRTC_VBI_END 0x1d86 -#define CAR_mmCRTC2_CRTC_VBI_END 0x1f86 -#define CAR_mmCRTC3_CRTC_VBI_END 0x4186 -#define CAR_mmCRTC4_CRTC_VBI_END 0x4386 -#define CAR_mmCRTC5_CRTC_VBI_END 0x4586 -#define CAR_mmCRTC_V_TOTAL 0x1b87 -#define CAR_mmCRTC0_CRTC_V_TOTAL 0x1b87 -#define CAR_mmCRTC1_CRTC_V_TOTAL 0x1d87 -#define CAR_mmCRTC2_CRTC_V_TOTAL 0x1f87 -#define CAR_mmCRTC3_CRTC_V_TOTAL 0x4187 -#define CAR_mmCRTC4_CRTC_V_TOTAL 0x4387 -#define CAR_mmCRTC5_CRTC_V_TOTAL 0x4587 -#define CAR_mmCRTC_V_TOTAL_MIN 0x1b88 -#define CAR_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 -#define CAR_mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 -#define CAR_mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 -#define CAR_mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 -#define CAR_mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 -#define CAR_mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 -#define CAR_mmCRTC_V_TOTAL_MAX 0x1b89 -#define CAR_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 -#define CAR_mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 -#define CAR_mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 -#define CAR_mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 -#define CAR_mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 -#define CAR_mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 -#define CAR_mmCRTC_V_TOTAL_CONTROL 0x1b8a -#define CAR_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a -#define CAR_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a -#define CAR_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a -#define CAR_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a -#define CAR_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a -#define CAR_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a -#define CAR_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b -#define CAR_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b -#define CAR_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b -#define CAR_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b -#define CAR_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b -#define CAR_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b -#define CAR_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b -#define CAR_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define CAR_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define CAR_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c -#define CAR_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c -#define CAR_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c -#define CAR_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c -#define CAR_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c -#define CAR_mmCRTC_V_BLANK_START_END 0x1b8d -#define CAR_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d -#define CAR_mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d -#define CAR_mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d -#define CAR_mmCRTC3_CRTC_V_BLANK_START_END 0x418d -#define CAR_mmCRTC4_CRTC_V_BLANK_START_END 0x438d -#define CAR_mmCRTC5_CRTC_V_BLANK_START_END 0x458d -#define CAR_mmCRTC_V_SYNC_A 0x1b8e -#define CAR_mmCRTC0_CRTC_V_SYNC_A 0x1b8e -#define CAR_mmCRTC1_CRTC_V_SYNC_A 0x1d8e -#define CAR_mmCRTC2_CRTC_V_SYNC_A 0x1f8e -#define CAR_mmCRTC3_CRTC_V_SYNC_A 0x418e -#define CAR_mmCRTC4_CRTC_V_SYNC_A 0x438e -#define CAR_mmCRTC5_CRTC_V_SYNC_A 0x458e -#define CAR_mmCRTC_V_SYNC_A_CNTL 0x1b8f -#define CAR_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f -#define CAR_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f -#define CAR_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f -#define CAR_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f -#define CAR_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f -#define CAR_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f -#define CAR_mmCRTC_V_SYNC_B 0x1b90 -#define CAR_mmCRTC0_CRTC_V_SYNC_B 0x1b90 -#define CAR_mmCRTC1_CRTC_V_SYNC_B 0x1d90 -#define CAR_mmCRTC2_CRTC_V_SYNC_B 0x1f90 -#define CAR_mmCRTC3_CRTC_V_SYNC_B 0x4190 -#define CAR_mmCRTC4_CRTC_V_SYNC_B 0x4390 -#define CAR_mmCRTC5_CRTC_V_SYNC_B 0x4590 -#define CAR_mmCRTC_V_SYNC_B_CNTL 0x1b91 -#define CAR_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 -#define CAR_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 -#define CAR_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 -#define CAR_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 -#define CAR_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 -#define CAR_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 -#define CAR_mmCRTC_DTMTEST_CNTL 0x1b92 -#define CAR_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 -#define CAR_mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 -#define CAR_mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 -#define CAR_mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 -#define CAR_mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 -#define CAR_mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 -#define CAR_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define CAR_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define CAR_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 -#define CAR_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 -#define CAR_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 -#define CAR_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 -#define CAR_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 -#define CAR_mmCRTC_TRIGA_CNTL 0x1b94 -#define CAR_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 -#define CAR_mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 -#define CAR_mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 -#define CAR_mmCRTC3_CRTC_TRIGA_CNTL 0x4194 -#define CAR_mmCRTC4_CRTC_TRIGA_CNTL 0x4394 -#define CAR_mmCRTC5_CRTC_TRIGA_CNTL 0x4594 -#define CAR_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define CAR_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define CAR_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 -#define CAR_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 -#define CAR_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 -#define CAR_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 -#define CAR_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 -#define CAR_mmCRTC_TRIGB_CNTL 0x1b96 -#define CAR_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 -#define CAR_mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 -#define CAR_mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 -#define CAR_mmCRTC3_CRTC_TRIGB_CNTL 0x4196 -#define CAR_mmCRTC4_CRTC_TRIGB_CNTL 0x4396 -#define CAR_mmCRTC5_CRTC_TRIGB_CNTL 0x4596 -#define CAR_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define CAR_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define CAR_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 -#define CAR_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 -#define CAR_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 -#define CAR_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 -#define CAR_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 -#define CAR_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define CAR_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define CAR_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 -#define CAR_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 -#define CAR_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 -#define CAR_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 -#define CAR_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 -#define CAR_mmCRTC_FLOW_CONTROL 0x1b99 -#define CAR_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 -#define CAR_mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 -#define CAR_mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 -#define CAR_mmCRTC3_CRTC_FLOW_CONTROL 0x4199 -#define CAR_mmCRTC4_CRTC_FLOW_CONTROL 0x4399 -#define CAR_mmCRTC5_CRTC_FLOW_CONTROL 0x4599 -#define CAR_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a -#define CAR_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a -#define CAR_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a -#define CAR_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a -#define CAR_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a -#define CAR_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a -#define CAR_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a -#define CAR_mmCRTC_AVSYNC_COUNTER 0x1b9b -#define CAR_mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b -#define CAR_mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b -#define CAR_mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b -#define CAR_mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b -#define CAR_mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b -#define CAR_mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b -#define CAR_mmCRTC_CONTROL 0x1b9c -#define CAR_mmCRTC0_CRTC_CONTROL 0x1b9c -#define CAR_mmCRTC1_CRTC_CONTROL 0x1d9c -#define CAR_mmCRTC2_CRTC_CONTROL 0x1f9c -#define CAR_mmCRTC3_CRTC_CONTROL 0x419c -#define CAR_mmCRTC4_CRTC_CONTROL 0x439c -#define CAR_mmCRTC5_CRTC_CONTROL 0x459c -#define CAR_mmCRTC_BLANK_CONTROL 0x1b9d -#define CAR_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d -#define CAR_mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d -#define CAR_mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d -#define CAR_mmCRTC3_CRTC_BLANK_CONTROL 0x419d -#define CAR_mmCRTC4_CRTC_BLANK_CONTROL 0x439d -#define CAR_mmCRTC5_CRTC_BLANK_CONTROL 0x459d -#define CAR_mmCRTC_INTERLACE_CONTROL 0x1b9e -#define CAR_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e -#define CAR_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e -#define CAR_mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e -#define CAR_mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e -#define CAR_mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e -#define CAR_mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e -#define CAR_mmCRTC_INTERLACE_STATUS 0x1b9f -#define CAR_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f -#define CAR_mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f -#define CAR_mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f -#define CAR_mmCRTC3_CRTC_INTERLACE_STATUS 0x419f -#define CAR_mmCRTC4_CRTC_INTERLACE_STATUS 0x439f -#define CAR_mmCRTC5_CRTC_INTERLACE_STATUS 0x459f -#define CAR_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define CAR_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define CAR_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 -#define CAR_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 -#define CAR_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 -#define CAR_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 -#define CAR_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 -#define CAR_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 -#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 -#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 -#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 -#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 -#define CAR_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 -#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 -#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 -#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 -#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 -#define CAR_mmCRTC_STATUS 0x1ba3 -#define CAR_mmCRTC0_CRTC_STATUS 0x1ba3 -#define CAR_mmCRTC1_CRTC_STATUS 0x1da3 -#define CAR_mmCRTC2_CRTC_STATUS 0x1fa3 -#define CAR_mmCRTC3_CRTC_STATUS 0x41a3 -#define CAR_mmCRTC4_CRTC_STATUS 0x43a3 -#define CAR_mmCRTC5_CRTC_STATUS 0x45a3 -#define CAR_mmCRTC_STATUS_POSITION 0x1ba4 -#define CAR_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 -#define CAR_mmCRTC1_CRTC_STATUS_POSITION 0x1da4 -#define CAR_mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 -#define CAR_mmCRTC3_CRTC_STATUS_POSITION 0x41a4 -#define CAR_mmCRTC4_CRTC_STATUS_POSITION 0x43a4 -#define CAR_mmCRTC5_CRTC_STATUS_POSITION 0x45a4 -#define CAR_mmCRTC_NOM_VERT_POSITION 0x1ba5 -#define CAR_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 -#define CAR_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 -#define CAR_mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 -#define CAR_mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 -#define CAR_mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 -#define CAR_mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 -#define CAR_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 -#define CAR_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 -#define CAR_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 -#define CAR_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 -#define CAR_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 -#define CAR_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 -#define CAR_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 -#define CAR_mmCRTC_STATUS_VF_COUNT 0x1ba7 -#define CAR_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 -#define CAR_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 -#define CAR_mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 -#define CAR_mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 -#define CAR_mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 -#define CAR_mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 -#define CAR_mmCRTC_STATUS_HV_COUNT 0x1ba8 -#define CAR_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 -#define CAR_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 -#define CAR_mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 -#define CAR_mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 -#define CAR_mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 -#define CAR_mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 -#define CAR_mmCRTC_COUNT_CONTROL 0x1ba9 -#define CAR_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 -#define CAR_mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 -#define CAR_mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 -#define CAR_mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 -#define CAR_mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 -#define CAR_mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 -#define CAR_mmCRTC_COUNT_RESET 0x1baa -#define CAR_mmCRTC0_CRTC_COUNT_RESET 0x1baa -#define CAR_mmCRTC1_CRTC_COUNT_RESET 0x1daa -#define CAR_mmCRTC2_CRTC_COUNT_RESET 0x1faa -#define CAR_mmCRTC3_CRTC_COUNT_RESET 0x41aa -#define CAR_mmCRTC4_CRTC_COUNT_RESET 0x43aa -#define CAR_mmCRTC5_CRTC_COUNT_RESET 0x45aa -#define CAR_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define CAR_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define CAR_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab -#define CAR_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab -#define CAR_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab -#define CAR_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab -#define CAR_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab -#define CAR_mmCRTC_VERT_SYNC_CONTROL 0x1bac -#define CAR_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac -#define CAR_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac -#define CAR_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac -#define CAR_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac -#define CAR_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac -#define CAR_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac -#define CAR_mmCRTC_STEREO_STATUS 0x1bad -#define CAR_mmCRTC0_CRTC_STEREO_STATUS 0x1bad -#define CAR_mmCRTC1_CRTC_STEREO_STATUS 0x1dad -#define CAR_mmCRTC2_CRTC_STEREO_STATUS 0x1fad -#define CAR_mmCRTC3_CRTC_STEREO_STATUS 0x41ad -#define CAR_mmCRTC4_CRTC_STEREO_STATUS 0x43ad -#define CAR_mmCRTC5_CRTC_STEREO_STATUS 0x45ad -#define CAR_mmCRTC_STEREO_CONTROL 0x1bae -#define CAR_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae -#define CAR_mmCRTC1_CRTC_STEREO_CONTROL 0x1dae -#define CAR_mmCRTC2_CRTC_STEREO_CONTROL 0x1fae -#define CAR_mmCRTC3_CRTC_STEREO_CONTROL 0x41ae -#define CAR_mmCRTC4_CRTC_STEREO_CONTROL 0x43ae -#define CAR_mmCRTC5_CRTC_STEREO_CONTROL 0x45ae -#define CAR_mmCRTC_SNAPSHOT_STATUS 0x1baf -#define CAR_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf -#define CAR_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf -#define CAR_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf -#define CAR_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af -#define CAR_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af -#define CAR_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af -#define CAR_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 -#define CAR_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 -#define CAR_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 -#define CAR_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 -#define CAR_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 -#define CAR_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 -#define CAR_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 -#define CAR_mmCRTC_SNAPSHOT_POSITION 0x1bb1 -#define CAR_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 -#define CAR_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 -#define CAR_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 -#define CAR_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 -#define CAR_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 -#define CAR_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 -#define CAR_mmCRTC_SNAPSHOT_FRAME 0x1bb2 -#define CAR_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 -#define CAR_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 -#define CAR_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 -#define CAR_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 -#define CAR_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 -#define CAR_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 -#define CAR_mmCRTC_START_LINE_CONTROL 0x1bb3 -#define CAR_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 -#define CAR_mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 -#define CAR_mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 -#define CAR_mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 -#define CAR_mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 -#define CAR_mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 -#define CAR_mmCRTC_INTERRUPT_CONTROL 0x1bb4 -#define CAR_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 -#define CAR_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 -#define CAR_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 -#define CAR_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 -#define CAR_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 -#define CAR_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 -#define CAR_mmCRTC_UPDATE_LOCK 0x1bb5 -#define CAR_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 -#define CAR_mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 -#define CAR_mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 -#define CAR_mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 -#define CAR_mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 -#define CAR_mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 -#define CAR_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define CAR_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define CAR_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 -#define CAR_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 -#define CAR_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 -#define CAR_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 -#define CAR_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 -#define CAR_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define CAR_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define CAR_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 -#define CAR_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 -#define CAR_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 -#define CAR_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 -#define CAR_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 -#define CAR_mmCRTC_TEST_PATTERN_CONTROL 0x1bba -#define CAR_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba -#define CAR_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba -#define CAR_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba -#define CAR_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba -#define CAR_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba -#define CAR_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba -#define CAR_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define CAR_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define CAR_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb -#define CAR_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb -#define CAR_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb -#define CAR_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb -#define CAR_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb -#define CAR_mmCRTC_TEST_PATTERN_COLOR 0x1bbc -#define CAR_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc -#define CAR_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc -#define CAR_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc -#define CAR_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc -#define CAR_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc -#define CAR_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc -#define CAR_mmCRTC_MASTER_UPDATE_LOCK 0x1bbd -#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd -#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd -#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd -#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd -#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd -#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd -#define CAR_mmCRTC_MASTER_UPDATE_MODE 0x1bbe -#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe -#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe -#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe -#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be -#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be -#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be -#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf -#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf -#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf -#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf -#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf -#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 -#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 -#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 -#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 -#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 -#define CAR_mmCRTC_MVP_STATUS 0x1bc1 -#define CAR_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 -#define CAR_mmCRTC1_CRTC_MVP_STATUS 0x1dc1 -#define CAR_mmCRTC2_CRTC_MVP_STATUS 0x1fc1 -#define CAR_mmCRTC3_CRTC_MVP_STATUS 0x41c1 -#define CAR_mmCRTC4_CRTC_MVP_STATUS 0x43c1 -#define CAR_mmCRTC5_CRTC_MVP_STATUS 0x45c1 -#define CAR_mmCRTC_MASTER_EN 0x1bc2 -#define CAR_mmCRTC0_CRTC_MASTER_EN 0x1bc2 -#define CAR_mmCRTC1_CRTC_MASTER_EN 0x1dc2 -#define CAR_mmCRTC2_CRTC_MASTER_EN 0x1fc2 -#define CAR_mmCRTC3_CRTC_MASTER_EN 0x41c2 -#define CAR_mmCRTC4_CRTC_MASTER_EN 0x43c2 -#define CAR_mmCRTC5_CRTC_MASTER_EN 0x45c2 -#define CAR_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define CAR_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define CAR_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 -#define CAR_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 -#define CAR_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 -#define CAR_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 -#define CAR_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 -#define CAR_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define CAR_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define CAR_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 -#define CAR_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 -#define CAR_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 -#define CAR_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 -#define CAR_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 -#define CAR_mmCRTC_OVERSCAN_COLOR 0x1bc8 -#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 -#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 -#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 -#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 -#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 -#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 -#define CAR_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 -#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 -#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 -#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 -#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 -#define CAR_mmCRTC_BLANK_DATA_COLOR 0x1bca -#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca -#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca -#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca -#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca -#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca -#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca -#define CAR_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb -#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb -#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb -#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb -#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb -#define CAR_mmCRTC_BLACK_COLOR 0x1bcc -#define CAR_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc -#define CAR_mmCRTC1_CRTC_BLACK_COLOR 0x1dcc -#define CAR_mmCRTC2_CRTC_BLACK_COLOR 0x1fcc -#define CAR_mmCRTC3_CRTC_BLACK_COLOR 0x41cc -#define CAR_mmCRTC4_CRTC_BLACK_COLOR 0x43cc -#define CAR_mmCRTC5_CRTC_BLACK_COLOR 0x45cc -#define CAR_mmCRTC_BLACK_COLOR_EXT 0x1bcd -#define CAR_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd -#define CAR_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd -#define CAR_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd -#define CAR_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd -#define CAR_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd -#define CAR_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd -#define CAR_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce -#define CAR_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf -#define CAR_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 -#define CAR_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 -#define CAR_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 -#define CAR_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 -#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 -#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 -#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 -#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 -#define CAR_mmCRTC_CRC_CNTL 0x1bd4 -#define CAR_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 -#define CAR_mmCRTC1_CRTC_CRC_CNTL 0x1dd4 -#define CAR_mmCRTC2_CRTC_CRC_CNTL 0x1fd4 -#define CAR_mmCRTC3_CRTC_CRC_CNTL 0x41d4 -#define CAR_mmCRTC4_CRTC_CRC_CNTL 0x43d4 -#define CAR_mmCRTC5_CRTC_CRC_CNTL 0x45d4 -#define CAR_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 -#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 -#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 -#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 -#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 -#define CAR_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 -#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 -#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 -#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 -#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 -#define CAR_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 -#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 -#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 -#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 -#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 -#define CAR_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 -#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 -#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 -#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 -#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 -#define CAR_mmCRTC_CRC0_DATA_RG 0x1bd9 -#define CAR_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 -#define CAR_mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 -#define CAR_mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 -#define CAR_mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 -#define CAR_mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 -#define CAR_mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 -#define CAR_mmCRTC_CRC0_DATA_B 0x1bda -#define CAR_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda -#define CAR_mmCRTC1_CRTC_CRC0_DATA_B 0x1dda -#define CAR_mmCRTC2_CRTC_CRC0_DATA_B 0x1fda -#define CAR_mmCRTC3_CRTC_CRC0_DATA_B 0x41da -#define CAR_mmCRTC4_CRTC_CRC0_DATA_B 0x43da -#define CAR_mmCRTC5_CRTC_CRC0_DATA_B 0x45da -#define CAR_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb -#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb -#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db -#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db -#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db -#define CAR_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc -#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc -#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc -#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc -#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc -#define CAR_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd -#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd -#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd -#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd -#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd -#define CAR_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde -#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde -#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de -#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de -#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de -#define CAR_mmCRTC_CRC1_DATA_RG 0x1bdf -#define CAR_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf -#define CAR_mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf -#define CAR_mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf -#define CAR_mmCRTC3_CRTC_CRC1_DATA_RG 0x41df -#define CAR_mmCRTC4_CRTC_CRC1_DATA_RG 0x43df -#define CAR_mmCRTC5_CRTC_CRC1_DATA_RG 0x45df -#define CAR_mmCRTC_CRC1_DATA_B 0x1be0 -#define CAR_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 -#define CAR_mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 -#define CAR_mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 -#define CAR_mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 -#define CAR_mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 -#define CAR_mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 -#define CAR_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define CAR_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define CAR_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 -#define CAR_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 -#define CAR_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 -#define CAR_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 -#define CAR_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 -#define CAR_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define CAR_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define CAR_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 -#define CAR_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 -#define CAR_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 -#define CAR_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 -#define CAR_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 -#define CAR_mmCRTC_GSL_VSYNC_GAP 0x1b79 -#define CAR_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 -#define CAR_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 -#define CAR_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 -#define CAR_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 -#define CAR_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 -#define CAR_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 -#define CAR_mmCRTC_GSL_WINDOW 0x1b7a -#define CAR_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a -#define CAR_mmCRTC1_CRTC_GSL_WINDOW 0x1d7a -#define CAR_mmCRTC2_CRTC_GSL_WINDOW 0x1f7a -#define CAR_mmCRTC3_CRTC_GSL_WINDOW 0x417a -#define CAR_mmCRTC4_CRTC_GSL_WINDOW 0x437a -#define CAR_mmCRTC5_CRTC_GSL_WINDOW 0x457a -#define CAR_mmCRTC_GSL_CONTROL 0x1b7b -#define CAR_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b -#define CAR_mmCRTC1_CRTC_GSL_CONTROL 0x1d7b -#define CAR_mmCRTC2_CRTC_GSL_CONTROL 0x1f7b -#define CAR_mmCRTC3_CRTC_GSL_CONTROL 0x417b -#define CAR_mmCRTC4_CRTC_GSL_CONTROL 0x437b -#define CAR_mmCRTC5_CRTC_GSL_CONTROL 0x457b -#define CAR_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 -#define CAR_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 -#define CAR_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 -#define CAR_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 -#define CAR_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 -#define CAR_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 -#define CAR_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 -#define CAR_mmCRTC_TEST_DEBUG_DATA 0x1bc7 -#define CAR_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 -#define CAR_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 -#define CAR_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 -#define CAR_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 -#define CAR_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 -#define CAR_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 -#define CAR_mmDAC_ENABLE 0x16aa -#define CAR_mmDAC_SOURCE_SELECT 0x16ab -#define CAR_mmDAC_CRC_EN 0x16ac -#define CAR_mmDAC_CRC_CONTROL 0x16ad -#define CAR_mmDAC_CRC_SIG_RGB_MASK 0x16ae -#define CAR_mmDAC_CRC_SIG_CONTROL_MASK 0x16af -#define CAR_mmDAC_CRC_SIG_RGB 0x16b0 -#define CAR_mmDAC_CRC_SIG_CONTROL 0x16b1 -#define CAR_mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 -#define CAR_mmDAC_STEREOSYNC_SELECT 0x16b3 -#define CAR_mmDAC_AUTODETECT_CONTROL 0x16b4 -#define CAR_mmDAC_AUTODETECT_CONTROL2 0x16b5 -#define CAR_mmDAC_AUTODETECT_CONTROL3 0x16b6 -#define CAR_mmDAC_AUTODETECT_STATUS 0x16b7 -#define CAR_mmDAC_AUTODETECT_INT_CONTROL 0x16b8 -#define CAR_mmDAC_FORCE_OUTPUT_CNTL 0x16b9 -#define CAR_mmDAC_FORCE_DATA 0x16ba -#define CAR_mmDAC_POWERDOWN 0x16bb -#define CAR_mmDAC_CONTROL 0x16bc -#define CAR_mmDAC_COMPARATOR_ENABLE 0x16bd -#define CAR_mmDAC_COMPARATOR_OUTPUT 0x16be -#define CAR_mmDAC_PWR_CNTL 0x16bf -#define CAR_mmDAC_DFT_CONFIG 0x16c0 -#define CAR_mmDAC_FIFO_STATUS 0x16c1 -#define CAR_mmDAC_TEST_DEBUG_INDEX 0x16c2 -#define CAR_mmDAC_TEST_DEBUG_DATA 0x16c3 -#define CAR_mmPERFCOUNTER_CNTL 0x170 -#define CAR_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 -#define CAR_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 -#define CAR_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 -#define CAR_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 -#define CAR_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 -#define CAR_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 -#define CAR_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 -#define CAR_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 -#define CAR_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 -#define CAR_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 -#define CAR_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 -#define CAR_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 -#define CAR_mmPERFCOUNTER_STATE 0x171 -#define CAR_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 -#define CAR_mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 -#define CAR_mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 -#define CAR_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 -#define CAR_mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 -#define CAR_mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 -#define CAR_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 -#define CAR_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 -#define CAR_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 -#define CAR_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 -#define CAR_mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 -#define CAR_mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 -#define CAR_mmPERFMON_CNTL 0x173 -#define CAR_mmDC_PERFMON0_PERFMON_CNTL 0x173 -#define CAR_mmDC_PERFMON1_PERFMON_CNTL 0x367 -#define CAR_mmDC_PERFMON2_PERFMON_CNTL 0x18cb -#define CAR_mmDC_PERFMON3_PERFMON_CNTL 0x1b27 -#define CAR_mmDC_PERFMON4_PERFMON_CNTL 0x1d27 -#define CAR_mmDC_PERFMON5_PERFMON_CNTL 0x1f27 -#define CAR_mmDC_PERFMON6_PERFMON_CNTL 0x4127 -#define CAR_mmDC_PERFMON7_PERFMON_CNTL 0x4327 -#define CAR_mmDC_PERFMON8_PERFMON_CNTL 0x4527 -#define CAR_mmDC_PERFMON9_PERFMON_CNTL 0x4727 -#define CAR_mmDC_PERFMON10_PERFMON_CNTL 0x59a3 -#define CAR_mmDC_PERFMON11_PERFMON_CNTL 0x5f6b -#define CAR_mmPERFMON_CNTL2 0x17a -#define CAR_mmDC_PERFMON0_PERFMON_CNTL2 0x17a -#define CAR_mmDC_PERFMON1_PERFMON_CNTL2 0x36e -#define CAR_mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 -#define CAR_mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e -#define CAR_mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e -#define CAR_mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e -#define CAR_mmDC_PERFMON6_PERFMON_CNTL2 0x412e -#define CAR_mmDC_PERFMON7_PERFMON_CNTL2 0x432e -#define CAR_mmDC_PERFMON8_PERFMON_CNTL2 0x452e -#define CAR_mmDC_PERFMON9_PERFMON_CNTL2 0x472e -#define CAR_mmDC_PERFMON10_PERFMON_CNTL2 0x59aa -#define CAR_mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 -#define CAR_mmPERFMON_CVALUE_INT_MISC 0x172 -#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 -#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 -#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca -#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 -#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 -#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 -#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 -#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 -#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 -#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 -#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 -#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a -#define CAR_mmPERFMON_CVALUE_LOW 0x174 -#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 -#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 -#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc -#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 -#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 -#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 -#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 -#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 -#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 -#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 -#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 -#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c -#define CAR_mmPERFMON_HI 0x175 -#define CAR_mmDC_PERFMON0_PERFMON_HI 0x175 -#define CAR_mmDC_PERFMON1_PERFMON_HI 0x369 -#define CAR_mmDC_PERFMON2_PERFMON_HI 0x18cd -#define CAR_mmDC_PERFMON3_PERFMON_HI 0x1b29 -#define CAR_mmDC_PERFMON4_PERFMON_HI 0x1d29 -#define CAR_mmDC_PERFMON5_PERFMON_HI 0x1f29 -#define CAR_mmDC_PERFMON6_PERFMON_HI 0x4129 -#define CAR_mmDC_PERFMON7_PERFMON_HI 0x4329 -#define CAR_mmDC_PERFMON8_PERFMON_HI 0x4529 -#define CAR_mmDC_PERFMON9_PERFMON_HI 0x4729 -#define CAR_mmDC_PERFMON10_PERFMON_HI 0x59a5 -#define CAR_mmDC_PERFMON11_PERFMON_HI 0x5f6d -#define CAR_mmPERFMON_LOW 0x176 -#define CAR_mmDC_PERFMON0_PERFMON_LOW 0x176 -#define CAR_mmDC_PERFMON1_PERFMON_LOW 0x36a -#define CAR_mmDC_PERFMON2_PERFMON_LOW 0x18ce -#define CAR_mmDC_PERFMON3_PERFMON_LOW 0x1b2a -#define CAR_mmDC_PERFMON4_PERFMON_LOW 0x1d2a -#define CAR_mmDC_PERFMON5_PERFMON_LOW 0x1f2a -#define CAR_mmDC_PERFMON6_PERFMON_LOW 0x412a -#define CAR_mmDC_PERFMON7_PERFMON_LOW 0x432a -#define CAR_mmDC_PERFMON8_PERFMON_LOW 0x452a -#define CAR_mmDC_PERFMON9_PERFMON_LOW 0x472a -#define CAR_mmDC_PERFMON10_PERFMON_LOW 0x59a6 -#define CAR_mmDC_PERFMON11_PERFMON_LOW 0x5f6e -#define CAR_mmPERFMON_TEST_DEBUG_INDEX 0x177 -#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 -#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b -#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf -#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b -#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b -#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b -#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b -#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b -#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b -#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b -#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 -#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f -#define CAR_mmPERFMON_TEST_DEBUG_DATA 0x178 -#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 -#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c -#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 -#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c -#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c -#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c -#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c -#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c -#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c -#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c -#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 -#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 -#define CAR_mmREFCLK_CNTL 0x109 -#define CAR_mmDCCG_CBUS_WRCMD_DELAY 0x110 -#define CAR_mmDPREFCLK_CNTL 0x118 -#define CAR_mmDCE_VERSION 0x11e -#define CAR_mmAVSYNC_COUNTER_WRITE 0x12a -#define CAR_mmAVSYNC_COUNTER_CONTROL 0x12b -#define CAR_mmAVSYNC_COUNTER_READ 0x12f -#define CAR_mmDCCG_GTC_CNTL 0x120 -#define CAR_mmDCCG_GTC_DTO_INCR 0x121 -#define CAR_mmDCCG_GTC_DTO_MODULO 0x122 -#define CAR_mmDCCG_GTC_CURRENT 0x123 -#define CAR_mmDCCG_DS_DTO_INCR 0x113 -#define CAR_mmDCCG_DS_DTO_MODULO 0x114 -#define CAR_mmDCCG_DS_CNTL 0x115 -#define CAR_mmDCCG_DS_HW_CAL_INTERVAL 0x116 -#define CAR_mmDCCG_DS_DEBUG_CNTL 0x112 -#define CAR_mmDMCU_SMU_INTERRUPT_CNTL 0x12c -#define CAR_mmSMU_CONTROL 0x12d -#define CAR_mmSMU_INTERRUPT_CONTROL 0x12e -#define CAR_mmDAC_CLK_ENABLE 0x128 -#define CAR_mmDVO_CLK_ENABLE 0x129 -#define CAR_mmDCCG_GATE_DISABLE_CNTL 0x134 -#define CAR_mmDCCG_GATE_DISABLE_CNTL2 0x13c -#define CAR_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 -#define CAR_mmSCLK_CGTT_BLK_CTRL_REG 0x136 -#define CAR_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 -#define CAR_mmREFCLK_CGTT_BLK_CTRL_REG 0x10b -#define CAR_mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d -#define CAR_mmDCCG_CAC_STATUS 0x137 -#define CAR_mmPIXCLK1_RESYNC_CNTL 0x138 -#define CAR_mmPIXCLK2_RESYNC_CNTL 0x139 -#define CAR_mmPIXCLK0_RESYNC_CNTL 0x13a -#define CAR_mmPHYPLL_PIXCLK_CNTL 0x13e -#define CAR_mmMICROSECOND_TIME_BASE_DIV 0x13b -#define CAR_mmDCCG_DISP_CNTL_REG 0x13f -#define CAR_mmMILLISECOND_TIME_BASE_DIV 0x130 -#define CAR_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 -#define CAR_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 -#define CAR_mmDCCG_PERFMON_CNTL 0x133 -#define CAR_mmDCCG_PERFMON_CNTL2 0x10e -#define CAR_mmCRTC0_PIXEL_RATE_CNTL 0x140 -#define CAR_mmDP_DTO0_PHASE 0x141 -#define CAR_mmDP_DTO0_MODULO 0x142 -#define CAR_mmCRTC1_PIXEL_RATE_CNTL 0x144 -#define CAR_mmDP_DTO1_PHASE 0x145 -#define CAR_mmDP_DTO1_MODULO 0x146 -#define CAR_mmCRTC2_PIXEL_RATE_CNTL 0x148 -#define CAR_mmDP_DTO2_PHASE 0x149 -#define CAR_mmDP_DTO2_MODULO 0x14a -#define CAR_mmCRTC3_PIXEL_RATE_CNTL 0x14c -#define CAR_mmDP_DTO3_PHASE 0x14d -#define CAR_mmDP_DTO3_MODULO 0x14e -#define CAR_mmCRTC4_PIXEL_RATE_CNTL 0x150 -#define CAR_mmDP_DTO4_PHASE 0x151 -#define CAR_mmDP_DTO4_MODULO 0x152 -#define CAR_mmCRTC5_PIXEL_RATE_CNTL 0x154 -#define CAR_mmDP_DTO5_PHASE 0x155 -#define CAR_mmDP_DTO5_MODULO 0x156 -#define CAR_mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104 -#define CAR_mmDCCG_SOFT_RESET 0x15f -#define CAR_mmSYMCLKA_CLOCK_ENABLE 0x160 -#define CAR_mmSYMCLKB_CLOCK_ENABLE 0x161 -#define CAR_mmSYMCLKC_CLOCK_ENABLE 0x162 -#define CAR_mmSYMCLKD_CLOCK_ENABLE 0x163 -#define CAR_mmSYMCLKE_CLOCK_ENABLE 0x164 -#define CAR_mmSYMCLKF_CLOCK_ENABLE 0x165 -#define CAR_mmSYMCLKG_CLOCK_ENABLE 0x117 -#define CAR_mmDPDBG_CLK_FORCE_CONTROL 0x10d -#define CAR_mmDCCG_AUDIO_DTO_SOURCE 0x16b -#define CAR_mmDCCG_AUDIO_DTO0_PHASE 0x16c -#define CAR_mmDCCG_AUDIO_DTO0_MODULE 0x16d -#define CAR_mmDCCG_AUDIO_DTO1_PHASE 0x16e -#define CAR_mmDCCG_AUDIO_DTO1_MODULE 0x16f -#define CAR_mmDCCG_TEST_DEBUG_INDEX 0x17c -#define CAR_mmDCCG_TEST_DEBUG_DATA 0x17d -#define CAR_mmDCCG_TEST_CLK_SEL 0x17e -#define CAR_mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 -#define CAR_mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa -#define CAR_mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb -#define CAR_mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc -#define CAR_mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd -#define CAR_mmCPLL_MACRO_CNTL_RESERVED10 0x5fda -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe -#define CAR_mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb -#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb -#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 -#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 -#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff -#define CAR_mmPLL_MACRO_CNTL_RESERVED0 0x1700 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 -#define CAR_mmPLL_MACRO_CNTL_RESERVED1 0x1701 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 -#define CAR_mmPLL_MACRO_CNTL_RESERVED2 0x1702 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 -#define CAR_mmPLL_MACRO_CNTL_RESERVED3 0x1703 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 -#define CAR_mmPLL_MACRO_CNTL_RESERVED4 0x1704 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 -#define CAR_mmPLL_MACRO_CNTL_RESERVED5 0x1705 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 -#define CAR_mmPLL_MACRO_CNTL_RESERVED6 0x1706 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a -#define CAR_mmPLL_MACRO_CNTL_RESERVED7 0x1707 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b -#define CAR_mmPLL_MACRO_CNTL_RESERVED8 0x1708 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c -#define CAR_mmPLL_MACRO_CNTL_RESERVED9 0x1709 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d -#define CAR_mmPLL_MACRO_CNTL_RESERVED10 0x170a -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e -#define CAR_mmPLL_MACRO_CNTL_RESERVED11 0x170b -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f -#define CAR_mmPLL_MACRO_CNTL_RESERVED12 0x170c -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 -#define CAR_mmPLL_MACRO_CNTL_RESERVED13 0x170d -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 -#define CAR_mmPLL_MACRO_CNTL_RESERVED14 0x170e -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 -#define CAR_mmPLL_MACRO_CNTL_RESERVED15 0x170f -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 -#define CAR_mmPLL_MACRO_CNTL_RESERVED16 0x1710 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 -#define CAR_mmPLL_MACRO_CNTL_RESERVED17 0x1711 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 -#define CAR_mmPLL_MACRO_CNTL_RESERVED18 0x1712 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 -#define CAR_mmPLL_MACRO_CNTL_RESERVED19 0x1713 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 -#define CAR_mmPLL_MACRO_CNTL_RESERVED20 0x1714 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 -#define CAR_mmPLL_MACRO_CNTL_RESERVED21 0x1715 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 -#define CAR_mmPLL_MACRO_CNTL_RESERVED22 0x1716 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a -#define CAR_mmPLL_MACRO_CNTL_RESERVED23 0x1717 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b -#define CAR_mmPLL_MACRO_CNTL_RESERVED24 0x1718 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c -#define CAR_mmPLL_MACRO_CNTL_RESERVED25 0x1719 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d -#define CAR_mmPLL_MACRO_CNTL_RESERVED26 0x171a -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e -#define CAR_mmPLL_MACRO_CNTL_RESERVED27 0x171b -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f -#define CAR_mmPLL_MACRO_CNTL_RESERVED28 0x171c -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 -#define CAR_mmPLL_MACRO_CNTL_RESERVED29 0x171d -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 -#define CAR_mmPLL_MACRO_CNTL_RESERVED30 0x171e -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 -#define CAR_mmPLL_MACRO_CNTL_RESERVED31 0x171f -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 -#define CAR_mmPLL_MACRO_CNTL_RESERVED32 0x1720 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 -#define CAR_mmPLL_MACRO_CNTL_RESERVED33 0x1721 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 -#define CAR_mmPLL_MACRO_CNTL_RESERVED34 0x1722 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 -#define CAR_mmPLL_MACRO_CNTL_RESERVED35 0x1723 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 -#define CAR_mmPLL_MACRO_CNTL_RESERVED36 0x1724 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 -#define CAR_mmPLL_MACRO_CNTL_RESERVED37 0x1725 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 -#define CAR_mmPLL_MACRO_CNTL_RESERVED38 0x1726 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a -#define CAR_mmPLL_MACRO_CNTL_RESERVED39 0x1727 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b -#define CAR_mmPLL_MACRO_CNTL_RESERVED40 0x1728 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c -#define CAR_mmPLL_MACRO_CNTL_RESERVED41 0x1729 -#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 -#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 -#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d -#define CAR_mmDENTIST_DISPCLK_CNTL 0x124 -#define CAR_mmDCDEBUG_BUS_CLK1_SEL 0x16c4 -#define CAR_mmDCDEBUG_BUS_CLK2_SEL 0x16c5 -#define CAR_mmDCDEBUG_BUS_CLK3_SEL 0x16c6 -#define CAR_mmDCDEBUG_BUS_CLK4_SEL 0x16c7 -#define CAR_mmDCDEBUG_BUS_CLK5_SEL 0x16c8 -#define CAR_mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 -#define CAR_mmDCDEBUG_OUT_CNTL 0x16ca -#define CAR_mmDCDEBUG_OUT_DATA 0x16cb -#define CAR_mmDMIF_ADDR_CONFIG 0x2f5 -#define CAR_mmDMIF_CONTROL 0x2f6 -#define CAR_mmDMIF_STATUS 0x2f7 -#define CAR_mmDMIF_HW_DEBUG 0x2f8 -#define CAR_mmDMIF_ARBITRATION_CONTROL 0x2f9 -#define CAR_mmPIPE0_ARBITRATION_CONTROL3 0x2fa -#define CAR_mmPIPE1_ARBITRATION_CONTROL3 0x2fb -#define CAR_mmPIPE2_ARBITRATION_CONTROL3 0x2fc -#define CAR_mmPIPE3_ARBITRATION_CONTROL3 0x2fd -#define CAR_mmPIPE4_ARBITRATION_CONTROL3 0x2fe -#define CAR_mmPIPE5_ARBITRATION_CONTROL3 0x2ff -#define CAR_mmPIPE6_ARBITRATION_CONTROL3 0x32a -#define CAR_mmPIPE7_ARBITRATION_CONTROL3 0x32b -#define CAR_mmDMIF_P_VMID 0x300 -#define CAR_mmDMIF_URG_OVERRIDE 0x329 -#define CAR_mmDMIF_TEST_DEBUG_INDEX 0x301 -#define CAR_mmDMIF_TEST_DEBUG_DATA 0x302 -#define CAR_ixDMIF_DEBUG02_CORE0 0x2 -#define CAR_ixDMIF_DEBUG02_CORE1 0xa -#define CAR_mmDMIF_ADDR_CALC 0x303 -#define CAR_mmDMIF_STATUS2 0x304 -#define CAR_mmPIPE0_MAX_REQUESTS 0x305 -#define CAR_mmPIPE1_MAX_REQUESTS 0x306 -#define CAR_mmPIPE2_MAX_REQUESTS 0x307 -#define CAR_mmPIPE3_MAX_REQUESTS 0x308 -#define CAR_mmPIPE4_MAX_REQUESTS 0x309 -#define CAR_mmPIPE5_MAX_REQUESTS 0x30a -#define CAR_mmPIPE6_MAX_REQUESTS 0x32c -#define CAR_mmPIPE7_MAX_REQUESTS 0x32d -#define CAR_mmDVMM_REG_RD_STATUS 0x32e -#define CAR_mmDVMM_REG_RD_DATA 0x32f -#define CAR_mmDVMM_PTE_REQ 0x330 -#define CAR_mmDVMM_CNTL 0x331 -#define CAR_mmDVMM_FAULT_STATUS 0x332 -#define CAR_mmDVMM_FAULT_ADDR 0x333 -#define CAR_mmLOW_POWER_TILING_CONTROL 0x30b -#define CAR_mmMCIF_CONTROL 0x30c -#define CAR_mmMCIF_WRITE_COMBINE_CONTROL 0x30d -#define CAR_mmMCIF_TEST_DEBUG_INDEX 0x30e -#define CAR_mmMCIF_TEST_DEBUG_DATA 0x30f -#define CAR_ixIDDCCIF02_DBG_DCCIF_C 0x9 -#define CAR_ixIDDCCIF04_DBG_DCCIF_E 0xb -#define CAR_ixIDDCCIF05_DBG_DCCIF_F 0xc -#define CAR_mmMCIF_VMID 0x310 -#define CAR_mmMCIF_MEM_CONTROL 0x311 -#define CAR_mmCC_DC_PIPE_DIS 0x312 -#define CAR_mmMC_DC_INTERFACE_NACK_STATUS 0x313 -#define CAR_mmRBBMIF_TIMEOUT 0x314 -#define CAR_mmRBBMIF_STATUS 0x315 -#define CAR_mmRBBMIF_TIMEOUT_DIS 0x316 -#define CAR_mmRBBMIF_STATUS_FLAG 0x327 -#define CAR_mmDCI_MEM_PWR_STATUS 0x317 -#define CAR_mmDCI_MEM_PWR_STATUS2 0x318 -#define CAR_mmDCI_CLK_CNTL 0x319 -#define CAR_mmDCI_CLK_RAMP_CNTL 0x31a -#define CAR_mmDCI_MEM_PWR_CNTL 0x31b -#define CAR_mmDCI_MEM_PWR_CNTL2 0x31c -#define CAR_mmDCI_MEM_PWR_CNTL3 0x31d -#define CAR_mmDVMM_PTE_PGMEM_CONTROL 0x335 -#define CAR_mmDVMM_PTE_PGMEM_STATE 0x336 -#define CAR_mmDCI_SOFT_RESET 0x328 -#define CAR_mmDCI_MISC 0x334 -#define CAR_mmDCI_TEST_DEBUG_INDEX 0x31e -#define CAR_mmDCI_TEST_DEBUG_DATA 0x31f -#define CAR_mmDCI_DEBUG_CONFIG 0x320 -#define CAR_mmPIPE0_DMIF_BUFFER_CONTROL 0x321 -#define CAR_mmPIPE1_DMIF_BUFFER_CONTROL 0x322 -#define CAR_mmPIPE2_DMIF_BUFFER_CONTROL 0x323 -#define CAR_mmPIPE3_DMIF_BUFFER_CONTROL 0x324 -#define CAR_mmPIPE4_DMIF_BUFFER_CONTROL 0x325 -#define CAR_mmPIPE5_DMIF_BUFFER_CONTROL 0x326 -#define CAR_mmDC_GENERICA 0x4800 -#define CAR_mmDC_GENERICB 0x4801 -#define CAR_mmDC_PAD_EXTERN_SIG 0x4802 -#define CAR_mmDC_REF_CLK_CNTL 0x4803 -#define CAR_mmDC_GPIO_DEBUG 0x4804 -#define CAR_mmUNIPHYA_LINK_CNTL 0x4805 -#define CAR_mmUNIPHYB_LINK_CNTL 0x4807 -#define CAR_mmUNIPHYC_LINK_CNTL 0x4809 -#define CAR_mmUNIPHYD_LINK_CNTL 0x480b -#define CAR_mmUNIPHYE_LINK_CNTL 0x480d -#define CAR_mmUNIPHYF_LINK_CNTL 0x480f -#define CAR_mmUNIPHYG_LINK_CNTL 0x4811 -#define CAR_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 -#define CAR_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 -#define CAR_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a -#define CAR_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c -#define CAR_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e -#define CAR_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 -#define CAR_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 -#define CAR_mmUNIPHYLPA_LINK_CNTL 0x4847 -#define CAR_mmUNIPHYLPB_LINK_CNTL 0x4848 -#define CAR_mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 -#define CAR_mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a -#define CAR_mmUNIPHY_IMPCAL_LINKA 0x4838 -#define CAR_mmUNIPHY_IMPCAL_LINKB 0x4839 -#define CAR_mmUNIPHY_IMPCAL_LINKC 0x483f -#define CAR_mmUNIPHY_IMPCAL_LINKD 0x4840 -#define CAR_mmUNIPHY_IMPCAL_LINKE 0x4843 -#define CAR_mmUNIPHY_IMPCAL_LINKF 0x4844 -#define CAR_mmUNIPHY_IMPCAL_PERIOD 0x483a -#define CAR_mmAUXP_IMPCAL 0x483b -#define CAR_mmAUXN_IMPCAL 0x483c -#define CAR_mmDCIO_IMPCAL_CNTL 0x483d -#define CAR_mmUNIPHY_IMPCAL_PSW_AB 0x483e -#define CAR_mmDCIO_IMPCAL_CNTL_CD 0x4841 -#define CAR_mmUNIPHY_IMPCAL_PSW_CD 0x4842 -#define CAR_mmDCIO_IMPCAL_CNTL_EF 0x4845 -#define CAR_mmUNIPHY_IMPCAL_PSW_EF 0x4846 -#define CAR_mmDCIO_WRCMD_DELAY 0x4816 -#define CAR_mmDC_PINSTRAPS 0x4818 -#define CAR_mmDC_DVODATA_CONFIG 0x481a -#define CAR_mmLVTMA_PWRSEQ_CNTL 0x481b -#define CAR_mmLVTMA_PWRSEQ_STATE 0x481c -#define CAR_mmLVTMA_PWRSEQ_REF_DIV 0x481d -#define CAR_mmLVTMA_PWRSEQ_DELAY1 0x481e -#define CAR_mmLVTMA_PWRSEQ_DELAY2 0x481f -#define CAR_mmBL_PWM_CNTL 0x4820 -#define CAR_mmBL_PWM_CNTL2 0x4821 -#define CAR_mmBL_PWM_PERIOD_CNTL 0x4822 -#define CAR_mmBL_PWM_GRP1_REG_LOCK 0x4823 -#define CAR_mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 -#define CAR_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 -#define CAR_mmDCIO_GSL0_CNTL 0x4826 -#define CAR_mmDCIO_GSL1_CNTL 0x4827 -#define CAR_mmDCIO_GSL2_CNTL 0x4828 -#define CAR_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 -#define CAR_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a -#define CAR_mmDC_GPU_TIMER_READ 0x482b -#define CAR_mmDC_GPU_TIMER_READ_CNTL 0x482c -#define CAR_mmDCIO_CLOCK_CNTL 0x482d -#define CAR_mmDCIO_DEBUG 0x482f -#define CAR_mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 -#define CAR_mmDBG_OUT_CNTL 0x4834 -#define CAR_mmDCIO_DEBUG_CONFIG 0x4835 -#define CAR_mmDCIO_SOFT_RESET 0x4836 -#define CAR_mmDCIO_DPHY_SEL 0x4837 -#define CAR_mmDCIO_TEST_DEBUG_INDEX 0x4831 -#define CAR_mmDCIO_TEST_DEBUG_DATA 0x4832 -#define CAR_ixDCIO_DEBUG1 0x1 -#define CAR_ixDCIO_DEBUG2 0x2 -#define CAR_ixDCIO_DEBUG3 0x3 -#define CAR_ixDCIO_DEBUG4 0x4 -#define CAR_ixDCIO_DEBUG5 0x5 -#define CAR_ixDCIO_DEBUG6 0x6 -#define CAR_ixDCIO_DEBUG7 0x7 -#define CAR_ixDCIO_DEBUG8 0x8 -#define CAR_ixDCIO_DEBUG9 0x9 -#define CAR_ixDCIO_DEBUGA 0xa -#define CAR_ixDCIO_DEBUGB 0xb -#define CAR_ixDCIO_DEBUGC 0xc -#define CAR_ixDCIO_DEBUGD 0xd -#define CAR_ixDCIO_DEBUGE 0xe -#define CAR_ixDCIO_DEBUGF 0xf -#define CAR_ixDCIO_DEBUG10 0x10 -#define CAR_ixDCIO_DEBUG11 0x11 -#define CAR_ixDCIO_DEBUG12 0x12 -#define CAR_ixDCIO_DEBUG13 0x13 -#define CAR_ixDCIO_DEBUG14 0x14 -#define CAR_ixDCIO_DEBUG15 0x15 -#define CAR_ixDCIO_DEBUG16 0x16 -#define CAR_ixDCIO_DEBUG17 0x17 -#define CAR_ixDCIO_DEBUG18 0x18 -#define CAR_ixDCIO_DEBUG19 0x19 -#define CAR_ixDCIO_DEBUG1A 0x1a -#define CAR_ixDCIO_DEBUG1B 0x1b -#define CAR_ixDCIO_DEBUG_ID 0x0 -#define CAR_mmDC_GPIO_GENERIC_MASK 0x4860 -#define CAR_mmDC_GPIO_GENERIC_A 0x4861 -#define CAR_mmDC_GPIO_GENERIC_EN 0x4862 -#define CAR_mmDC_GPIO_GENERIC_Y 0x4863 -#define CAR_mmDC_GPIO_DVODATA_MASK 0x4864 -#define CAR_mmDC_GPIO_DVODATA_A 0x4865 -#define CAR_mmDC_GPIO_DVODATA_EN 0x4866 -#define CAR_mmDC_GPIO_DVODATA_Y 0x4867 -#define CAR_mmDC_GPIO_DDC1_MASK 0x4868 -#define CAR_mmDC_GPIO_DDC1_A 0x4869 -#define CAR_mmDC_GPIO_DDC1_EN 0x486a -#define CAR_mmDC_GPIO_DDC1_Y 0x486b -#define CAR_mmDC_GPIO_DDC2_MASK 0x486c -#define CAR_mmDC_GPIO_DDC2_A 0x486d -#define CAR_mmDC_GPIO_DDC2_EN 0x486e -#define CAR_mmDC_GPIO_DDC2_Y 0x486f -#define CAR_mmDC_GPIO_DDC3_MASK 0x4870 -#define CAR_mmDC_GPIO_DDC3_A 0x4871 -#define CAR_mmDC_GPIO_DDC3_EN 0x4872 -#define CAR_mmDC_GPIO_DDC3_Y 0x4873 -#define CAR_mmDC_GPIO_DDC4_MASK 0x4874 -#define CAR_mmDC_GPIO_DDC4_A 0x4875 -#define CAR_mmDC_GPIO_DDC4_EN 0x4876 -#define CAR_mmDC_GPIO_DDC4_Y 0x4877 -#define CAR_mmDC_GPIO_DDC5_MASK 0x4878 -#define CAR_mmDC_GPIO_DDC5_A 0x4879 -#define CAR_mmDC_GPIO_DDC5_EN 0x487a -#define CAR_mmDC_GPIO_DDC5_Y 0x487b -#define CAR_mmDC_GPIO_DDC6_MASK 0x487c -#define CAR_mmDC_GPIO_DDC6_A 0x487d -#define CAR_mmDC_GPIO_DDC6_EN 0x487e -#define CAR_mmDC_GPIO_DDC6_Y 0x487f -#define CAR_mmDC_GPIO_DDCVGA_MASK 0x4880 -#define CAR_mmDC_GPIO_DDCVGA_A 0x4881 -#define CAR_mmDC_GPIO_DDCVGA_EN 0x4882 -#define CAR_mmDC_GPIO_DDCVGA_Y 0x4883 -#define CAR_mmDC_GPIO_SYNCA_MASK 0x4884 -#define CAR_mmDC_GPIO_SYNCA_A 0x4885 -#define CAR_mmDC_GPIO_SYNCA_EN 0x4886 -#define CAR_mmDC_GPIO_SYNCA_Y 0x4887 -#define CAR_mmDC_GPIO_GENLK_MASK 0x4888 -#define CAR_mmDC_GPIO_GENLK_A 0x4889 -#define CAR_mmDC_GPIO_GENLK_EN 0x488a -#define CAR_mmDC_GPIO_GENLK_Y 0x488b -#define CAR_mmDC_GPIO_HPD_MASK 0x488c #define CAR_mmDC_GPIO_HPD_A 0x488d -#define CAR_mmDC_GPIO_HPD_EN 0x488e -#define CAR_mmDC_GPIO_HPD_Y 0x488f -#define CAR_mmDC_GPIO_PWRSEQ_MASK 0x4890 -#define CAR_mmDC_GPIO_PWRSEQ_A 0x4891 -#define CAR_mmDC_GPIO_PWRSEQ_EN 0x4892 -#define CAR_mmDC_GPIO_PWRSEQ_Y 0x4893 -#define CAR_mmDC_GPIO_PAD_STRENGTH_1 0x4894 -#define CAR_mmDC_GPIO_PAD_STRENGTH_2 0x4895 -#define CAR_mmPHY_AUX_CNTL 0x4897 -#define CAR_mmDC_GPIO_I2CPAD_MASK 0x4898 -#define CAR_mmDC_GPIO_I2CPAD_A 0x4899 -#define CAR_mmDC_GPIO_I2CPAD_EN 0x489a -#define CAR_mmDC_GPIO_I2CPAD_Y 0x489b -#define CAR_mmDC_GPIO_I2CPAD_STRENGTH 0x489c -#define CAR_mmDVO_VREF_CONTROL 0x489e -#define CAR_mmDVO_SKEW_ADJUST 0x489f -#define CAR_mmDAC_MACRO_CNTL_RESERVED0 0x48b8 -#define CAR_mmDAC_MACRO_CNTL_RESERVED1 0x48b9 -#define CAR_mmDAC_MACRO_CNTL_RESERVED2 0x48ba -#define CAR_mmDAC_MACRO_CNTL_RESERVED3 0x48bb -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9 -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9 -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe -#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df -#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df -#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff -#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f -#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f -#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f -#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f -#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f -#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df -#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe -#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff -#define CAR_mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a -#define CAR_mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b -#define CAR_mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c -#define CAR_mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d -#define CAR_mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e -#define CAR_mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f -#define CAR_mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED18 0x5daa -#define CAR_mmDPHY_MACRO_CNTL_RESERVED19 0x5dab -#define CAR_mmDPHY_MACRO_CNTL_RESERVED20 0x5dac -#define CAR_mmDPHY_MACRO_CNTL_RESERVED21 0x5dad -#define CAR_mmDPHY_MACRO_CNTL_RESERVED22 0x5dae -#define CAR_mmDPHY_MACRO_CNTL_RESERVED23 0x5daf -#define CAR_mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED34 0x5dba -#define CAR_mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb -#define CAR_mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc -#define CAR_mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd -#define CAR_mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe -#define CAR_mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf -#define CAR_mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED50 0x5dca -#define CAR_mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb -#define CAR_mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc -#define CAR_mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd -#define CAR_mmDPHY_MACRO_CNTL_RESERVED54 0x5dce -#define CAR_mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf -#define CAR_mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 -#define CAR_mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 -#define CAR_mmGRPH_ENABLE 0x1a00 -#define CAR_mmDCP0_GRPH_ENABLE 0x1a00 -#define CAR_mmDCP1_GRPH_ENABLE 0x1c00 -#define CAR_mmDCP2_GRPH_ENABLE 0x1e00 -#define CAR_mmDCP3_GRPH_ENABLE 0x4000 -#define CAR_mmDCP4_GRPH_ENABLE 0x4200 -#define CAR_mmDCP5_GRPH_ENABLE 0x4400 -#define CAR_mmGRPH_CONTROL 0x1a01 -#define CAR_mmDCP0_GRPH_CONTROL 0x1a01 -#define CAR_mmDCP1_GRPH_CONTROL 0x1c01 -#define CAR_mmDCP2_GRPH_CONTROL 0x1e01 -#define CAR_mmDCP3_GRPH_CONTROL 0x4001 -#define CAR_mmDCP4_GRPH_CONTROL 0x4201 -#define CAR_mmDCP5_GRPH_CONTROL 0x4401 -#define CAR_mmGRPH_LUT_10BIT_BYPASS 0x1a02 -#define CAR_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 -#define CAR_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 -#define CAR_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 -#define CAR_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 -#define CAR_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 -#define CAR_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 -#define CAR_mmGRPH_SWAP_CNTL 0x1a03 -#define CAR_mmDCP0_GRPH_SWAP_CNTL 0x1a03 -#define CAR_mmDCP1_GRPH_SWAP_CNTL 0x1c03 -#define CAR_mmDCP2_GRPH_SWAP_CNTL 0x1e03 -#define CAR_mmDCP3_GRPH_SWAP_CNTL 0x4003 -#define CAR_mmDCP4_GRPH_SWAP_CNTL 0x4203 -#define CAR_mmDCP5_GRPH_SWAP_CNTL 0x4403 -#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 -#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 -#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 -#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 -#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 -#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 -#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 -#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 -#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 -#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 -#define CAR_mmGRPH_PITCH 0x1a06 -#define CAR_mmDCP0_GRPH_PITCH 0x1a06 -#define CAR_mmDCP1_GRPH_PITCH 0x1c06 -#define CAR_mmDCP2_GRPH_PITCH 0x1e06 -#define CAR_mmDCP3_GRPH_PITCH 0x4006 -#define CAR_mmDCP4_GRPH_PITCH 0x4206 -#define CAR_mmDCP5_GRPH_PITCH 0x4406 -#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 -#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 -#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 -#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 -#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 -#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 -#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 -#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 -#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 -#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 -#define CAR_mmGRPH_SURFACE_OFFSET_X 0x1a09 -#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 -#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 -#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 -#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 -#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 -#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 -#define CAR_mmGRPH_SURFACE_OFFSET_Y 0x1a0a -#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a -#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a -#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a -#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a -#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a -#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a -#define CAR_mmGRPH_X_START 0x1a0b -#define CAR_mmDCP0_GRPH_X_START 0x1a0b -#define CAR_mmDCP1_GRPH_X_START 0x1c0b -#define CAR_mmDCP2_GRPH_X_START 0x1e0b -#define CAR_mmDCP3_GRPH_X_START 0x400b -#define CAR_mmDCP4_GRPH_X_START 0x420b -#define CAR_mmDCP5_GRPH_X_START 0x440b -#define CAR_mmGRPH_Y_START 0x1a0c -#define CAR_mmDCP0_GRPH_Y_START 0x1a0c -#define CAR_mmDCP1_GRPH_Y_START 0x1c0c -#define CAR_mmDCP2_GRPH_Y_START 0x1e0c -#define CAR_mmDCP3_GRPH_Y_START 0x400c -#define CAR_mmDCP4_GRPH_Y_START 0x420c -#define CAR_mmDCP5_GRPH_Y_START 0x440c -#define CAR_mmGRPH_X_END 0x1a0d -#define CAR_mmDCP0_GRPH_X_END 0x1a0d -#define CAR_mmDCP1_GRPH_X_END 0x1c0d -#define CAR_mmDCP2_GRPH_X_END 0x1e0d -#define CAR_mmDCP3_GRPH_X_END 0x400d -#define CAR_mmDCP4_GRPH_X_END 0x420d -#define CAR_mmDCP5_GRPH_X_END 0x440d -#define CAR_mmGRPH_Y_END 0x1a0e -#define CAR_mmDCP0_GRPH_Y_END 0x1a0e -#define CAR_mmDCP1_GRPH_Y_END 0x1c0e -#define CAR_mmDCP2_GRPH_Y_END 0x1e0e -#define CAR_mmDCP3_GRPH_Y_END 0x400e -#define CAR_mmDCP4_GRPH_Y_END 0x420e -#define CAR_mmDCP5_GRPH_Y_END 0x440e -#define CAR_mmINPUT_GAMMA_CONTROL 0x1a10 -#define CAR_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 -#define CAR_mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 -#define CAR_mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 -#define CAR_mmDCP3_INPUT_GAMMA_CONTROL 0x4010 -#define CAR_mmDCP4_INPUT_GAMMA_CONTROL 0x4210 -#define CAR_mmDCP5_INPUT_GAMMA_CONTROL 0x4410 -#define CAR_mmGRPH_UPDATE 0x1a11 -#define CAR_mmDCP0_GRPH_UPDATE 0x1a11 -#define CAR_mmDCP1_GRPH_UPDATE 0x1c11 -#define CAR_mmDCP2_GRPH_UPDATE 0x1e11 -#define CAR_mmDCP3_GRPH_UPDATE 0x4011 -#define CAR_mmDCP4_GRPH_UPDATE 0x4211 -#define CAR_mmDCP5_GRPH_UPDATE 0x4411 -#define CAR_mmGRPH_FLIP_CONTROL 0x1a12 -#define CAR_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 -#define CAR_mmDCP1_GRPH_FLIP_CONTROL 0x1c12 -#define CAR_mmDCP2_GRPH_FLIP_CONTROL 0x1e12 -#define CAR_mmDCP3_GRPH_FLIP_CONTROL 0x4012 -#define CAR_mmDCP4_GRPH_FLIP_CONTROL 0x4212 -#define CAR_mmDCP5_GRPH_FLIP_CONTROL 0x4412 -#define CAR_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 -#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 -#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 -#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 -#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 -#define CAR_mmGRPH_DFQ_CONTROL 0x1a14 -#define CAR_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 -#define CAR_mmDCP1_GRPH_DFQ_CONTROL 0x1c14 -#define CAR_mmDCP2_GRPH_DFQ_CONTROL 0x1e14 -#define CAR_mmDCP3_GRPH_DFQ_CONTROL 0x4014 -#define CAR_mmDCP4_GRPH_DFQ_CONTROL 0x4214 -#define CAR_mmDCP5_GRPH_DFQ_CONTROL 0x4414 -#define CAR_mmGRPH_DFQ_STATUS 0x1a15 -#define CAR_mmDCP0_GRPH_DFQ_STATUS 0x1a15 -#define CAR_mmDCP1_GRPH_DFQ_STATUS 0x1c15 -#define CAR_mmDCP2_GRPH_DFQ_STATUS 0x1e15 -#define CAR_mmDCP3_GRPH_DFQ_STATUS 0x4015 -#define CAR_mmDCP4_GRPH_DFQ_STATUS 0x4215 -#define CAR_mmDCP5_GRPH_DFQ_STATUS 0x4415 -#define CAR_mmGRPH_INTERRUPT_STATUS 0x1a16 -#define CAR_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 -#define CAR_mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 -#define CAR_mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 -#define CAR_mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 -#define CAR_mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 -#define CAR_mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 -#define CAR_mmGRPH_INTERRUPT_CONTROL 0x1a17 -#define CAR_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 -#define CAR_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 -#define CAR_mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 -#define CAR_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 -#define CAR_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 -#define CAR_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 -#define CAR_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 -#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 -#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 -#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 -#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 -#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 -#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 -#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 -#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 -#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 -#define CAR_mmGRPH_COMPRESS_PITCH 0x1a1a -#define CAR_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a -#define CAR_mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a -#define CAR_mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a -#define CAR_mmDCP3_GRPH_COMPRESS_PITCH 0x401a -#define CAR_mmDCP4_GRPH_COMPRESS_PITCH 0x421a -#define CAR_mmDCP5_GRPH_COMPRESS_PITCH 0x441a -#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b -#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b -#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b -#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b -#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b -#define CAR_mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c -#define CAR_mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c -#define CAR_mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c -#define CAR_mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c -#define CAR_mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c -#define CAR_mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c -#define CAR_mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c -#define CAR_mmPRESCALE_GRPH_CONTROL 0x1a2d -#define CAR_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d -#define CAR_mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d -#define CAR_mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d -#define CAR_mmDCP3_PRESCALE_GRPH_CONTROL 0x402d -#define CAR_mmDCP4_PRESCALE_GRPH_CONTROL 0x422d -#define CAR_mmDCP5_PRESCALE_GRPH_CONTROL 0x442d -#define CAR_mmPRESCALE_VALUES_GRPH_R 0x1a2e -#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e -#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e -#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e -#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e -#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e -#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e -#define CAR_mmPRESCALE_VALUES_GRPH_G 0x1a2f -#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f -#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f -#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f -#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f -#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f -#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f -#define CAR_mmPRESCALE_VALUES_GRPH_B 0x1a30 -#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 -#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 -#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 -#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 -#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 -#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 -#define CAR_mmINPUT_CSC_CONTROL 0x1a35 -#define CAR_mmDCP0_INPUT_CSC_CONTROL 0x1a35 -#define CAR_mmDCP1_INPUT_CSC_CONTROL 0x1c35 -#define CAR_mmDCP2_INPUT_CSC_CONTROL 0x1e35 -#define CAR_mmDCP3_INPUT_CSC_CONTROL 0x4035 -#define CAR_mmDCP4_INPUT_CSC_CONTROL 0x4235 -#define CAR_mmDCP5_INPUT_CSC_CONTROL 0x4435 -#define CAR_mmINPUT_CSC_C11_C12 0x1a36 -#define CAR_mmDCP0_INPUT_CSC_C11_C12 0x1a36 -#define CAR_mmDCP1_INPUT_CSC_C11_C12 0x1c36 -#define CAR_mmDCP2_INPUT_CSC_C11_C12 0x1e36 -#define CAR_mmDCP3_INPUT_CSC_C11_C12 0x4036 -#define CAR_mmDCP4_INPUT_CSC_C11_C12 0x4236 -#define CAR_mmDCP5_INPUT_CSC_C11_C12 0x4436 -#define CAR_mmINPUT_CSC_C13_C14 0x1a37 -#define CAR_mmDCP0_INPUT_CSC_C13_C14 0x1a37 -#define CAR_mmDCP1_INPUT_CSC_C13_C14 0x1c37 -#define CAR_mmDCP2_INPUT_CSC_C13_C14 0x1e37 -#define CAR_mmDCP3_INPUT_CSC_C13_C14 0x4037 -#define CAR_mmDCP4_INPUT_CSC_C13_C14 0x4237 -#define CAR_mmDCP5_INPUT_CSC_C13_C14 0x4437 -#define CAR_mmINPUT_CSC_C21_C22 0x1a38 -#define CAR_mmDCP0_INPUT_CSC_C21_C22 0x1a38 -#define CAR_mmDCP1_INPUT_CSC_C21_C22 0x1c38 -#define CAR_mmDCP2_INPUT_CSC_C21_C22 0x1e38 -#define CAR_mmDCP3_INPUT_CSC_C21_C22 0x4038 -#define CAR_mmDCP4_INPUT_CSC_C21_C22 0x4238 -#define CAR_mmDCP5_INPUT_CSC_C21_C22 0x4438 -#define CAR_mmINPUT_CSC_C23_C24 0x1a39 -#define CAR_mmDCP0_INPUT_CSC_C23_C24 0x1a39 -#define CAR_mmDCP1_INPUT_CSC_C23_C24 0x1c39 -#define CAR_mmDCP2_INPUT_CSC_C23_C24 0x1e39 -#define CAR_mmDCP3_INPUT_CSC_C23_C24 0x4039 -#define CAR_mmDCP4_INPUT_CSC_C23_C24 0x4239 -#define CAR_mmDCP5_INPUT_CSC_C23_C24 0x4439 -#define CAR_mmINPUT_CSC_C31_C32 0x1a3a -#define CAR_mmDCP0_INPUT_CSC_C31_C32 0x1a3a -#define CAR_mmDCP1_INPUT_CSC_C31_C32 0x1c3a -#define CAR_mmDCP2_INPUT_CSC_C31_C32 0x1e3a -#define CAR_mmDCP3_INPUT_CSC_C31_C32 0x403a -#define CAR_mmDCP4_INPUT_CSC_C31_C32 0x423a -#define CAR_mmDCP5_INPUT_CSC_C31_C32 0x443a -#define CAR_mmINPUT_CSC_C33_C34 0x1a3b -#define CAR_mmDCP0_INPUT_CSC_C33_C34 0x1a3b -#define CAR_mmDCP1_INPUT_CSC_C33_C34 0x1c3b -#define CAR_mmDCP2_INPUT_CSC_C33_C34 0x1e3b -#define CAR_mmDCP3_INPUT_CSC_C33_C34 0x403b -#define CAR_mmDCP4_INPUT_CSC_C33_C34 0x423b -#define CAR_mmDCP5_INPUT_CSC_C33_C34 0x443b -#define CAR_mmOUTPUT_CSC_CONTROL 0x1a3c -#define CAR_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c -#define CAR_mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c -#define CAR_mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c -#define CAR_mmDCP3_OUTPUT_CSC_CONTROL 0x403c -#define CAR_mmDCP4_OUTPUT_CSC_CONTROL 0x423c -#define CAR_mmDCP5_OUTPUT_CSC_CONTROL 0x443c -#define CAR_mmOUTPUT_CSC_C11_C12 0x1a3d -#define CAR_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d -#define CAR_mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d -#define CAR_mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d -#define CAR_mmDCP3_OUTPUT_CSC_C11_C12 0x403d -#define CAR_mmDCP4_OUTPUT_CSC_C11_C12 0x423d -#define CAR_mmDCP5_OUTPUT_CSC_C11_C12 0x443d -#define CAR_mmOUTPUT_CSC_C13_C14 0x1a3e -#define CAR_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e -#define CAR_mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e -#define CAR_mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e -#define CAR_mmDCP3_OUTPUT_CSC_C13_C14 0x403e -#define CAR_mmDCP4_OUTPUT_CSC_C13_C14 0x423e -#define CAR_mmDCP5_OUTPUT_CSC_C13_C14 0x443e -#define CAR_mmOUTPUT_CSC_C21_C22 0x1a3f -#define CAR_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f -#define CAR_mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f -#define CAR_mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f -#define CAR_mmDCP3_OUTPUT_CSC_C21_C22 0x403f -#define CAR_mmDCP4_OUTPUT_CSC_C21_C22 0x423f -#define CAR_mmDCP5_OUTPUT_CSC_C21_C22 0x443f -#define CAR_mmOUTPUT_CSC_C23_C24 0x1a40 -#define CAR_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 -#define CAR_mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 -#define CAR_mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 -#define CAR_mmDCP3_OUTPUT_CSC_C23_C24 0x4040 -#define CAR_mmDCP4_OUTPUT_CSC_C23_C24 0x4240 -#define CAR_mmDCP5_OUTPUT_CSC_C23_C24 0x4440 -#define CAR_mmOUTPUT_CSC_C31_C32 0x1a41 -#define CAR_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 -#define CAR_mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 -#define CAR_mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 -#define CAR_mmDCP3_OUTPUT_CSC_C31_C32 0x4041 -#define CAR_mmDCP4_OUTPUT_CSC_C31_C32 0x4241 -#define CAR_mmDCP5_OUTPUT_CSC_C31_C32 0x4441 -#define CAR_mmOUTPUT_CSC_C33_C34 0x1a42 -#define CAR_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 -#define CAR_mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 -#define CAR_mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 -#define CAR_mmDCP3_OUTPUT_CSC_C33_C34 0x4042 -#define CAR_mmDCP4_OUTPUT_CSC_C33_C34 0x4242 -#define CAR_mmDCP5_OUTPUT_CSC_C33_C34 0x4442 -#define CAR_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 -#define CAR_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 -#define CAR_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 -#define CAR_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 -#define CAR_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 -#define CAR_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 -#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 -#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 -#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 -#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 -#define CAR_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 -#define CAR_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a -#define CAR_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b -#define CAR_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c -#define CAR_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d -#define CAR_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e -#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e -#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e -#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e -#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e -#define CAR_mmDENORM_CONTROL 0x1a50 -#define CAR_mmDCP0_DENORM_CONTROL 0x1a50 -#define CAR_mmDCP1_DENORM_CONTROL 0x1c50 -#define CAR_mmDCP2_DENORM_CONTROL 0x1e50 -#define CAR_mmDCP3_DENORM_CONTROL 0x4050 -#define CAR_mmDCP4_DENORM_CONTROL 0x4250 -#define CAR_mmDCP5_DENORM_CONTROL 0x4450 -#define CAR_mmOUT_ROUND_CONTROL 0x1a51 -#define CAR_mmDCP0_OUT_ROUND_CONTROL 0x1a51 -#define CAR_mmDCP1_OUT_ROUND_CONTROL 0x1c51 -#define CAR_mmDCP2_OUT_ROUND_CONTROL 0x1e51 -#define CAR_mmDCP3_OUT_ROUND_CONTROL 0x4051 -#define CAR_mmDCP4_OUT_ROUND_CONTROL 0x4251 -#define CAR_mmDCP5_OUT_ROUND_CONTROL 0x4451 -#define CAR_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 -#define CAR_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 -#define CAR_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 -#define CAR_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 -#define CAR_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 -#define CAR_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 -#define CAR_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 -#define CAR_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c -#define CAR_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c -#define CAR_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c -#define CAR_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c -#define CAR_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c -#define CAR_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c -#define CAR_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c -#define CAR_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d -#define CAR_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d -#define CAR_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d -#define CAR_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d -#define CAR_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d -#define CAR_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d -#define CAR_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d -#define CAR_mmKEY_CONTROL 0x1a53 -#define CAR_mmDCP0_KEY_CONTROL 0x1a53 -#define CAR_mmDCP1_KEY_CONTROL 0x1c53 -#define CAR_mmDCP2_KEY_CONTROL 0x1e53 -#define CAR_mmDCP3_KEY_CONTROL 0x4053 -#define CAR_mmDCP4_KEY_CONTROL 0x4253 -#define CAR_mmDCP5_KEY_CONTROL 0x4453 -#define CAR_mmKEY_RANGE_ALPHA 0x1a54 -#define CAR_mmDCP0_KEY_RANGE_ALPHA 0x1a54 -#define CAR_mmDCP1_KEY_RANGE_ALPHA 0x1c54 -#define CAR_mmDCP2_KEY_RANGE_ALPHA 0x1e54 -#define CAR_mmDCP3_KEY_RANGE_ALPHA 0x4054 -#define CAR_mmDCP4_KEY_RANGE_ALPHA 0x4254 -#define CAR_mmDCP5_KEY_RANGE_ALPHA 0x4454 -#define CAR_mmKEY_RANGE_RED 0x1a55 -#define CAR_mmDCP0_KEY_RANGE_RED 0x1a55 -#define CAR_mmDCP1_KEY_RANGE_RED 0x1c55 -#define CAR_mmDCP2_KEY_RANGE_RED 0x1e55 -#define CAR_mmDCP3_KEY_RANGE_RED 0x4055 -#define CAR_mmDCP4_KEY_RANGE_RED 0x4255 -#define CAR_mmDCP5_KEY_RANGE_RED 0x4455 -#define CAR_mmKEY_RANGE_GREEN 0x1a56 -#define CAR_mmDCP0_KEY_RANGE_GREEN 0x1a56 -#define CAR_mmDCP1_KEY_RANGE_GREEN 0x1c56 -#define CAR_mmDCP2_KEY_RANGE_GREEN 0x1e56 -#define CAR_mmDCP3_KEY_RANGE_GREEN 0x4056 -#define CAR_mmDCP4_KEY_RANGE_GREEN 0x4256 -#define CAR_mmDCP5_KEY_RANGE_GREEN 0x4456 -#define CAR_mmKEY_RANGE_BLUE 0x1a57 -#define CAR_mmDCP0_KEY_RANGE_BLUE 0x1a57 -#define CAR_mmDCP1_KEY_RANGE_BLUE 0x1c57 -#define CAR_mmDCP2_KEY_RANGE_BLUE 0x1e57 -#define CAR_mmDCP3_KEY_RANGE_BLUE 0x4057 -#define CAR_mmDCP4_KEY_RANGE_BLUE 0x4257 -#define CAR_mmDCP5_KEY_RANGE_BLUE 0x4457 -#define CAR_mmDEGAMMA_CONTROL 0x1a58 -#define CAR_mmDCP0_DEGAMMA_CONTROL 0x1a58 -#define CAR_mmDCP1_DEGAMMA_CONTROL 0x1c58 -#define CAR_mmDCP2_DEGAMMA_CONTROL 0x1e58 -#define CAR_mmDCP3_DEGAMMA_CONTROL 0x4058 -#define CAR_mmDCP4_DEGAMMA_CONTROL 0x4258 -#define CAR_mmDCP5_DEGAMMA_CONTROL 0x4458 -#define CAR_mmGAMUT_REMAP_CONTROL 0x1a59 -#define CAR_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 -#define CAR_mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 -#define CAR_mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 -#define CAR_mmDCP3_GAMUT_REMAP_CONTROL 0x4059 -#define CAR_mmDCP4_GAMUT_REMAP_CONTROL 0x4259 -#define CAR_mmDCP5_GAMUT_REMAP_CONTROL 0x4459 -#define CAR_mmGAMUT_REMAP_C11_C12 0x1a5a -#define CAR_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a -#define CAR_mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a -#define CAR_mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a -#define CAR_mmDCP3_GAMUT_REMAP_C11_C12 0x405a -#define CAR_mmDCP4_GAMUT_REMAP_C11_C12 0x425a -#define CAR_mmDCP5_GAMUT_REMAP_C11_C12 0x445a -#define CAR_mmGAMUT_REMAP_C13_C14 0x1a5b -#define CAR_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b -#define CAR_mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b -#define CAR_mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b -#define CAR_mmDCP3_GAMUT_REMAP_C13_C14 0x405b -#define CAR_mmDCP4_GAMUT_REMAP_C13_C14 0x425b -#define CAR_mmDCP5_GAMUT_REMAP_C13_C14 0x445b -#define CAR_mmGAMUT_REMAP_C21_C22 0x1a5c -#define CAR_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c -#define CAR_mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c -#define CAR_mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c -#define CAR_mmDCP3_GAMUT_REMAP_C21_C22 0x405c -#define CAR_mmDCP4_GAMUT_REMAP_C21_C22 0x425c -#define CAR_mmDCP5_GAMUT_REMAP_C21_C22 0x445c -#define CAR_mmGAMUT_REMAP_C23_C24 0x1a5d -#define CAR_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d -#define CAR_mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d -#define CAR_mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d -#define CAR_mmDCP3_GAMUT_REMAP_C23_C24 0x405d -#define CAR_mmDCP4_GAMUT_REMAP_C23_C24 0x425d -#define CAR_mmDCP5_GAMUT_REMAP_C23_C24 0x445d -#define CAR_mmGAMUT_REMAP_C31_C32 0x1a5e -#define CAR_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e -#define CAR_mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e -#define CAR_mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e -#define CAR_mmDCP3_GAMUT_REMAP_C31_C32 0x405e -#define CAR_mmDCP4_GAMUT_REMAP_C31_C32 0x425e -#define CAR_mmDCP5_GAMUT_REMAP_C31_C32 0x445e -#define CAR_mmGAMUT_REMAP_C33_C34 0x1a5f -#define CAR_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f -#define CAR_mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f -#define CAR_mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f -#define CAR_mmDCP3_GAMUT_REMAP_C33_C34 0x405f -#define CAR_mmDCP4_GAMUT_REMAP_C33_C34 0x425f -#define CAR_mmDCP5_GAMUT_REMAP_C33_C34 0x445f -#define CAR_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 -#define CAR_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 -#define CAR_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 -#define CAR_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 -#define CAR_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 -#define CAR_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 -#define CAR_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 -#define CAR_mmDCP_FP_CONVERTED_FIELD 0x1a65 -#define CAR_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 -#define CAR_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 -#define CAR_mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 -#define CAR_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 -#define CAR_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 -#define CAR_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 -#define CAR_mmCUR_CONTROL 0x1a66 -#define CAR_mmDCP0_CUR_CONTROL 0x1a66 -#define CAR_mmDCP1_CUR_CONTROL 0x1c66 -#define CAR_mmDCP2_CUR_CONTROL 0x1e66 -#define CAR_mmDCP3_CUR_CONTROL 0x4066 -#define CAR_mmDCP4_CUR_CONTROL 0x4266 -#define CAR_mmDCP5_CUR_CONTROL 0x4466 -#define CAR_mmCUR_SURFACE_ADDRESS 0x1a67 -#define CAR_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 -#define CAR_mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 -#define CAR_mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 -#define CAR_mmDCP3_CUR_SURFACE_ADDRESS 0x4067 -#define CAR_mmDCP4_CUR_SURFACE_ADDRESS 0x4267 -#define CAR_mmDCP5_CUR_SURFACE_ADDRESS 0x4467 -#define CAR_mmCUR_SIZE 0x1a68 -#define CAR_mmDCP0_CUR_SIZE 0x1a68 -#define CAR_mmDCP1_CUR_SIZE 0x1c68 -#define CAR_mmDCP2_CUR_SIZE 0x1e68 -#define CAR_mmDCP3_CUR_SIZE 0x4068 -#define CAR_mmDCP4_CUR_SIZE 0x4268 -#define CAR_mmDCP5_CUR_SIZE 0x4468 -#define CAR_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define CAR_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define CAR_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 -#define CAR_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 -#define CAR_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 -#define CAR_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 -#define CAR_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 -#define CAR_mmCUR_POSITION 0x1a6a -#define CAR_mmDCP0_CUR_POSITION 0x1a6a -#define CAR_mmDCP1_CUR_POSITION 0x1c6a -#define CAR_mmDCP2_CUR_POSITION 0x1e6a -#define CAR_mmDCP3_CUR_POSITION 0x406a -#define CAR_mmDCP4_CUR_POSITION 0x426a -#define CAR_mmDCP5_CUR_POSITION 0x446a -#define CAR_mmCUR_HOT_SPOT 0x1a6b -#define CAR_mmDCP0_CUR_HOT_SPOT 0x1a6b -#define CAR_mmDCP1_CUR_HOT_SPOT 0x1c6b -#define CAR_mmDCP2_CUR_HOT_SPOT 0x1e6b -#define CAR_mmDCP3_CUR_HOT_SPOT 0x406b -#define CAR_mmDCP4_CUR_HOT_SPOT 0x426b -#define CAR_mmDCP5_CUR_HOT_SPOT 0x446b -#define CAR_mmCUR_COLOR1 0x1a6c -#define CAR_mmDCP0_CUR_COLOR1 0x1a6c -#define CAR_mmDCP1_CUR_COLOR1 0x1c6c -#define CAR_mmDCP2_CUR_COLOR1 0x1e6c -#define CAR_mmDCP3_CUR_COLOR1 0x406c -#define CAR_mmDCP4_CUR_COLOR1 0x426c -#define CAR_mmDCP5_CUR_COLOR1 0x446c -#define CAR_mmCUR_COLOR2 0x1a6d -#define CAR_mmDCP0_CUR_COLOR2 0x1a6d -#define CAR_mmDCP1_CUR_COLOR2 0x1c6d -#define CAR_mmDCP2_CUR_COLOR2 0x1e6d -#define CAR_mmDCP3_CUR_COLOR2 0x406d -#define CAR_mmDCP4_CUR_COLOR2 0x426d -#define CAR_mmDCP5_CUR_COLOR2 0x446d -#define CAR_mmCUR_UPDATE 0x1a6e -#define CAR_mmDCP0_CUR_UPDATE 0x1a6e -#define CAR_mmDCP1_CUR_UPDATE 0x1c6e -#define CAR_mmDCP2_CUR_UPDATE 0x1e6e -#define CAR_mmDCP3_CUR_UPDATE 0x406e -#define CAR_mmDCP4_CUR_UPDATE 0x426e -#define CAR_mmDCP5_CUR_UPDATE 0x446e -#define CAR_mmCUR_REQUEST_FILTER_CNTL 0x1a99 -#define CAR_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 -#define CAR_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 -#define CAR_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 -#define CAR_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 -#define CAR_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 -#define CAR_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 -#define CAR_mmCUR_STEREO_CONTROL 0x1a9a -#define CAR_mmDCP0_CUR_STEREO_CONTROL 0x1a9a -#define CAR_mmDCP1_CUR_STEREO_CONTROL 0x1c9a -#define CAR_mmDCP2_CUR_STEREO_CONTROL 0x1e9a -#define CAR_mmDCP3_CUR_STEREO_CONTROL 0x409a -#define CAR_mmDCP4_CUR_STEREO_CONTROL 0x429a -#define CAR_mmDCP5_CUR_STEREO_CONTROL 0x449a -#define CAR_mmDC_LUT_RW_MODE 0x1a78 -#define CAR_mmDCP0_DC_LUT_RW_MODE 0x1a78 -#define CAR_mmDCP1_DC_LUT_RW_MODE 0x1c78 -#define CAR_mmDCP2_DC_LUT_RW_MODE 0x1e78 -#define CAR_mmDCP3_DC_LUT_RW_MODE 0x4078 -#define CAR_mmDCP4_DC_LUT_RW_MODE 0x4278 -#define CAR_mmDCP5_DC_LUT_RW_MODE 0x4478 -#define CAR_mmDC_LUT_RW_INDEX 0x1a79 -#define CAR_mmDCP0_DC_LUT_RW_INDEX 0x1a79 -#define CAR_mmDCP1_DC_LUT_RW_INDEX 0x1c79 -#define CAR_mmDCP2_DC_LUT_RW_INDEX 0x1e79 -#define CAR_mmDCP3_DC_LUT_RW_INDEX 0x4079 -#define CAR_mmDCP4_DC_LUT_RW_INDEX 0x4279 -#define CAR_mmDCP5_DC_LUT_RW_INDEX 0x4479 -#define CAR_mmDC_LUT_SEQ_COLOR 0x1a7a -#define CAR_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a -#define CAR_mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a -#define CAR_mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a -#define CAR_mmDCP3_DC_LUT_SEQ_COLOR 0x407a -#define CAR_mmDCP4_DC_LUT_SEQ_COLOR 0x427a -#define CAR_mmDCP5_DC_LUT_SEQ_COLOR 0x447a -#define CAR_mmDC_LUT_PWL_DATA 0x1a7b -#define CAR_mmDCP0_DC_LUT_PWL_DATA 0x1a7b -#define CAR_mmDCP1_DC_LUT_PWL_DATA 0x1c7b -#define CAR_mmDCP2_DC_LUT_PWL_DATA 0x1e7b -#define CAR_mmDCP3_DC_LUT_PWL_DATA 0x407b -#define CAR_mmDCP4_DC_LUT_PWL_DATA 0x427b -#define CAR_mmDCP5_DC_LUT_PWL_DATA 0x447b -#define CAR_mmDC_LUT_30_COLOR 0x1a7c -#define CAR_mmDCP0_DC_LUT_30_COLOR 0x1a7c -#define CAR_mmDCP1_DC_LUT_30_COLOR 0x1c7c -#define CAR_mmDCP2_DC_LUT_30_COLOR 0x1e7c -#define CAR_mmDCP3_DC_LUT_30_COLOR 0x407c -#define CAR_mmDCP4_DC_LUT_30_COLOR 0x427c -#define CAR_mmDCP5_DC_LUT_30_COLOR 0x447c -#define CAR_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define CAR_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define CAR_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d -#define CAR_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d -#define CAR_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d -#define CAR_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d -#define CAR_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d -#define CAR_mmDC_LUT_WRITE_EN_MASK 0x1a7e -#define CAR_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e -#define CAR_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e -#define CAR_mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e -#define CAR_mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e -#define CAR_mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e -#define CAR_mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e -#define CAR_mmDC_LUT_AUTOFILL 0x1a7f -#define CAR_mmDCP0_DC_LUT_AUTOFILL 0x1a7f -#define CAR_mmDCP1_DC_LUT_AUTOFILL 0x1c7f -#define CAR_mmDCP2_DC_LUT_AUTOFILL 0x1e7f -#define CAR_mmDCP3_DC_LUT_AUTOFILL 0x407f -#define CAR_mmDCP4_DC_LUT_AUTOFILL 0x427f -#define CAR_mmDCP5_DC_LUT_AUTOFILL 0x447f -#define CAR_mmDC_LUT_CONTROL 0x1a80 -#define CAR_mmDCP0_DC_LUT_CONTROL 0x1a80 -#define CAR_mmDCP1_DC_LUT_CONTROL 0x1c80 -#define CAR_mmDCP2_DC_LUT_CONTROL 0x1e80 -#define CAR_mmDCP3_DC_LUT_CONTROL 0x4080 -#define CAR_mmDCP4_DC_LUT_CONTROL 0x4280 -#define CAR_mmDCP5_DC_LUT_CONTROL 0x4480 -#define CAR_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 -#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 -#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 -#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 -#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 -#define CAR_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 -#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 -#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 -#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 -#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 -#define CAR_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 -#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 -#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 -#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 -#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 -#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 -#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 -#define CAR_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 -#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 -#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 -#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 -#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 -#define CAR_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 -#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 -#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 -#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 -#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 -#define CAR_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 -#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 -#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 -#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 -#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 -#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 -#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 -#define CAR_mmDCP_CRC_CONTROL 0x1a87 -#define CAR_mmDCP0_DCP_CRC_CONTROL 0x1a87 -#define CAR_mmDCP1_DCP_CRC_CONTROL 0x1c87 -#define CAR_mmDCP2_DCP_CRC_CONTROL 0x1e87 -#define CAR_mmDCP3_DCP_CRC_CONTROL 0x4087 -#define CAR_mmDCP4_DCP_CRC_CONTROL 0x4287 -#define CAR_mmDCP5_DCP_CRC_CONTROL 0x4487 -#define CAR_mmDCP_CRC_MASK 0x1a88 -#define CAR_mmDCP0_DCP_CRC_MASK 0x1a88 -#define CAR_mmDCP1_DCP_CRC_MASK 0x1c88 -#define CAR_mmDCP2_DCP_CRC_MASK 0x1e88 -#define CAR_mmDCP3_DCP_CRC_MASK 0x4088 -#define CAR_mmDCP4_DCP_CRC_MASK 0x4288 -#define CAR_mmDCP5_DCP_CRC_MASK 0x4488 -#define CAR_mmDCP_CRC_CURRENT 0x1a89 -#define CAR_mmDCP0_DCP_CRC_CURRENT 0x1a89 -#define CAR_mmDCP1_DCP_CRC_CURRENT 0x1c89 -#define CAR_mmDCP2_DCP_CRC_CURRENT 0x1e89 -#define CAR_mmDCP3_DCP_CRC_CURRENT 0x4089 -#define CAR_mmDCP4_DCP_CRC_CURRENT 0x4289 -#define CAR_mmDCP5_DCP_CRC_CURRENT 0x4489 -#define CAR_mmDVMM_PTE_CONTROL 0x1a8a -#define CAR_mmDCP0_DVMM_PTE_CONTROL 0x1a8a -#define CAR_mmDCP1_DVMM_PTE_CONTROL 0x1c8a -#define CAR_mmDCP2_DVMM_PTE_CONTROL 0x1e8a -#define CAR_mmDCP3_DVMM_PTE_CONTROL 0x408a -#define CAR_mmDCP4_DVMM_PTE_CONTROL 0x428a -#define CAR_mmDCP5_DVMM_PTE_CONTROL 0x448a -#define CAR_mmDCP_CRC_LAST 0x1a8b -#define CAR_mmDCP0_DCP_CRC_LAST 0x1a8b -#define CAR_mmDCP1_DCP_CRC_LAST 0x1c8b -#define CAR_mmDCP2_DCP_CRC_LAST 0x1e8b -#define CAR_mmDCP3_DCP_CRC_LAST 0x408b -#define CAR_mmDCP4_DCP_CRC_LAST 0x428b -#define CAR_mmDCP5_DCP_CRC_LAST 0x448b -#define CAR_mmDVMM_PTE_ARB_CONTROL 0x1a8c -#define CAR_mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c -#define CAR_mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c -#define CAR_mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c -#define CAR_mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c -#define CAR_mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c -#define CAR_mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c -#define CAR_mmDCP_DEBUG 0x1a8d -#define CAR_mmDCP0_DCP_DEBUG 0x1a8d -#define CAR_mmDCP1_DCP_DEBUG 0x1c8d -#define CAR_mmDCP2_DCP_DEBUG 0x1e8d -#define CAR_mmDCP3_DCP_DEBUG 0x408d -#define CAR_mmDCP4_DCP_DEBUG 0x428d -#define CAR_mmDCP5_DCP_DEBUG 0x448d -#define CAR_mmGRPH_FLIP_RATE_CNTL 0x1a8e -#define CAR_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e -#define CAR_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e -#define CAR_mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e -#define CAR_mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e -#define CAR_mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e -#define CAR_mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e -#define CAR_mmDCP_GSL_CONTROL 0x1a90 -#define CAR_mmDCP0_DCP_GSL_CONTROL 0x1a90 -#define CAR_mmDCP1_DCP_GSL_CONTROL 0x1c90 -#define CAR_mmDCP2_DCP_GSL_CONTROL 0x1e90 -#define CAR_mmDCP3_DCP_GSL_CONTROL 0x4090 -#define CAR_mmDCP4_DCP_GSL_CONTROL 0x4290 -#define CAR_mmDCP5_DCP_GSL_CONTROL 0x4490 -#define CAR_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define CAR_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define CAR_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 -#define CAR_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 -#define CAR_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 -#define CAR_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 -#define CAR_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 -#define CAR_mmDCP_DEBUG_SG 0x1a92 -#define CAR_mmDCP0_DCP_DEBUG_SG 0x1a92 -#define CAR_mmDCP1_DCP_DEBUG_SG 0x1c92 -#define CAR_mmDCP2_DCP_DEBUG_SG 0x1e92 -#define CAR_mmDCP3_DCP_DEBUG_SG 0x4092 -#define CAR_mmDCP4_DCP_DEBUG_SG 0x4292 -#define CAR_mmDCP5_DCP_DEBUG_SG 0x4492 -#define CAR_mmDCP_DEBUG_SG2 0x1a94 -#define CAR_mmDCP0_DCP_DEBUG_SG2 0x1a94 -#define CAR_mmDCP1_DCP_DEBUG_SG2 0x1c94 -#define CAR_mmDCP2_DCP_DEBUG_SG2 0x1e94 -#define CAR_mmDCP3_DCP_DEBUG_SG2 0x4094 -#define CAR_mmDCP4_DCP_DEBUG_SG2 0x4294 -#define CAR_mmDCP5_DCP_DEBUG_SG2 0x4494 -#define CAR_mmDCP_DVMM_DEBUG 0x1a93 -#define CAR_mmDCP0_DCP_DVMM_DEBUG 0x1a93 -#define CAR_mmDCP1_DCP_DVMM_DEBUG 0x1c93 -#define CAR_mmDCP2_DCP_DVMM_DEBUG 0x1e93 -#define CAR_mmDCP3_DCP_DVMM_DEBUG 0x4093 -#define CAR_mmDCP4_DCP_DVMM_DEBUG 0x4293 -#define CAR_mmDCP5_DCP_DVMM_DEBUG 0x4493 -#define CAR_mmDCP_TEST_DEBUG_INDEX 0x1a95 -#define CAR_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 -#define CAR_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 -#define CAR_mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 -#define CAR_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 -#define CAR_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 -#define CAR_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 -#define CAR_mmDCP_TEST_DEBUG_DATA 0x1a96 -#define CAR_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 -#define CAR_mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 -#define CAR_mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 -#define CAR_mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 -#define CAR_mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 -#define CAR_mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 -#define CAR_mmGRPH_STEREOSYNC_FLIP 0x1a97 -#define CAR_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 -#define CAR_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 -#define CAR_mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 -#define CAR_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 -#define CAR_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 -#define CAR_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 -#define CAR_mmDCP_DEBUG2 0x1a98 -#define CAR_mmDCP0_DCP_DEBUG2 0x1a98 -#define CAR_mmDCP1_DCP_DEBUG2 0x1c98 -#define CAR_mmDCP2_DCP_DEBUG2 0x1e98 -#define CAR_mmDCP3_DCP_DEBUG2 0x4098 -#define CAR_mmDCP4_DCP_DEBUG2 0x4298 -#define CAR_mmDCP5_DCP_DEBUG2 0x4498 -#define CAR_mmHW_ROTATION 0x1a9e -#define CAR_mmDCP0_HW_ROTATION 0x1a9e -#define CAR_mmDCP1_HW_ROTATION 0x1c9e -#define CAR_mmDCP2_HW_ROTATION 0x1e9e -#define CAR_mmDCP3_HW_ROTATION 0x409e -#define CAR_mmDCP4_HW_ROTATION 0x429e -#define CAR_mmDCP5_HW_ROTATION 0x449e -#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f -#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f -#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f -#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f -#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f -#define CAR_mmREGAMMA_CONTROL 0x1aa0 -#define CAR_mmDCP0_REGAMMA_CONTROL 0x1aa0 -#define CAR_mmDCP1_REGAMMA_CONTROL 0x1ca0 -#define CAR_mmDCP2_REGAMMA_CONTROL 0x1ea0 -#define CAR_mmDCP3_REGAMMA_CONTROL 0x40a0 -#define CAR_mmDCP4_REGAMMA_CONTROL 0x42a0 -#define CAR_mmDCP5_REGAMMA_CONTROL 0x44a0 -#define CAR_mmREGAMMA_LUT_INDEX 0x1aa1 -#define CAR_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 -#define CAR_mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 -#define CAR_mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 -#define CAR_mmDCP3_REGAMMA_LUT_INDEX 0x40a1 -#define CAR_mmDCP4_REGAMMA_LUT_INDEX 0x42a1 -#define CAR_mmDCP5_REGAMMA_LUT_INDEX 0x44a1 -#define CAR_mmREGAMMA_LUT_DATA 0x1aa2 -#define CAR_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 -#define CAR_mmDCP1_REGAMMA_LUT_DATA 0x1ca2 -#define CAR_mmDCP2_REGAMMA_LUT_DATA 0x1ea2 -#define CAR_mmDCP3_REGAMMA_LUT_DATA 0x40a2 -#define CAR_mmDCP4_REGAMMA_LUT_DATA 0x42a2 -#define CAR_mmDCP5_REGAMMA_LUT_DATA 0x44a2 -#define CAR_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define CAR_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define CAR_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 -#define CAR_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 -#define CAR_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 -#define CAR_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 -#define CAR_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 -#define CAR_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 -#define CAR_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 -#define CAR_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 -#define CAR_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 -#define CAR_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 -#define CAR_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 -#define CAR_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 -#define CAR_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define CAR_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define CAR_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 -#define CAR_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 -#define CAR_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 -#define CAR_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 -#define CAR_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 -#define CAR_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 -#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 -#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 -#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 -#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 -#define CAR_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 -#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 -#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 -#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 -#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 -#define CAR_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 -#define CAR_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 -#define CAR_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa -#define CAR_mmREGAMMA_CNTLA_REGION_6_7 0x1aab -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab -#define CAR_mmREGAMMA_CNTLA_REGION_8_9 0x1aac -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac -#define CAR_mmREGAMMA_CNTLA_REGION_10_11 0x1aad -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad -#define CAR_mmREGAMMA_CNTLA_REGION_12_13 0x1aae -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae -#define CAR_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf -#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf -#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf -#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf -#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af -#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af -#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af -#define CAR_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 -#define CAR_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 -#define CAR_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 -#define CAR_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 -#define CAR_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 -#define CAR_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 -#define CAR_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 -#define CAR_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define CAR_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define CAR_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 -#define CAR_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 -#define CAR_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 -#define CAR_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 -#define CAR_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 -#define CAR_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 -#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 -#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 -#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 -#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 -#define CAR_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 -#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 -#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 -#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 -#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 -#define CAR_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 -#define CAR_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 -#define CAR_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 -#define CAR_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 -#define CAR_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 -#define CAR_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 -#define CAR_mmREGAMMA_CNTLB_REGION_12_13 0x1aba -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba -#define CAR_mmREGAMMA_CNTLB_REGION_14_15 0x1abb -#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb -#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb -#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb -#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb -#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb -#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb -#define CAR_mmALPHA_CONTROL 0x1abc -#define CAR_mmDCP0_ALPHA_CONTROL 0x1abc -#define CAR_mmDCP1_ALPHA_CONTROL 0x1cbc -#define CAR_mmDCP2_ALPHA_CONTROL 0x1ebc -#define CAR_mmDCP3_ALPHA_CONTROL 0x40bc -#define CAR_mmDCP4_ALPHA_CONTROL 0x42bc -#define CAR_mmDCP5_ALPHA_CONTROL 0x44bc -#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd -#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd -#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd -#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd -#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd -#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe -#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe -#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be -#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be -#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be -#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf -#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf -#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf -#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf -#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf -#define CAR_mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f -#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f -#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f -#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f -#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f -#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f -#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f -#define CAR_mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d -#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d -#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d -#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d -#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d -#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d -#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d -#define CAR_mmDIG_FE_CNTL 0x4a00 -#define CAR_mmDIG0_DIG_FE_CNTL 0x4a00 -#define CAR_mmDIG1_DIG_FE_CNTL 0x4b00 -#define CAR_mmDIG2_DIG_FE_CNTL 0x4c00 -#define CAR_mmDIG3_DIG_FE_CNTL 0x4d00 -#define CAR_mmDIG4_DIG_FE_CNTL 0x4e00 -#define CAR_mmDIG5_DIG_FE_CNTL 0x4f00 -#define CAR_mmDIG6_DIG_FE_CNTL 0x5400 -#define CAR_mmDIG7_DIG_FE_CNTL 0x5600 -#define CAR_mmDIG8_DIG_FE_CNTL 0x5700 -#define CAR_mmDIG_OUTPUT_CRC_CNTL 0x4a01 -#define CAR_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 -#define CAR_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 -#define CAR_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 -#define CAR_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 -#define CAR_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 -#define CAR_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 -#define CAR_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 -#define CAR_mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 -#define CAR_mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 -#define CAR_mmDIG_OUTPUT_CRC_RESULT 0x4a02 -#define CAR_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 -#define CAR_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 -#define CAR_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 -#define CAR_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 -#define CAR_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 -#define CAR_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 -#define CAR_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 -#define CAR_mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 -#define CAR_mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 -#define CAR_mmDIG_CLOCK_PATTERN 0x4a03 -#define CAR_mmDIG0_DIG_CLOCK_PATTERN 0x4a03 -#define CAR_mmDIG1_DIG_CLOCK_PATTERN 0x4b03 -#define CAR_mmDIG2_DIG_CLOCK_PATTERN 0x4c03 -#define CAR_mmDIG3_DIG_CLOCK_PATTERN 0x4d03 -#define CAR_mmDIG4_DIG_CLOCK_PATTERN 0x4e03 -#define CAR_mmDIG5_DIG_CLOCK_PATTERN 0x4f03 -#define CAR_mmDIG6_DIG_CLOCK_PATTERN 0x5403 -#define CAR_mmDIG7_DIG_CLOCK_PATTERN 0x5603 -#define CAR_mmDIG8_DIG_CLOCK_PATTERN 0x5703 -#define CAR_mmDIG_TEST_PATTERN 0x4a04 -#define CAR_mmDIG0_DIG_TEST_PATTERN 0x4a04 -#define CAR_mmDIG1_DIG_TEST_PATTERN 0x4b04 -#define CAR_mmDIG2_DIG_TEST_PATTERN 0x4c04 -#define CAR_mmDIG3_DIG_TEST_PATTERN 0x4d04 -#define CAR_mmDIG4_DIG_TEST_PATTERN 0x4e04 -#define CAR_mmDIG5_DIG_TEST_PATTERN 0x4f04 -#define CAR_mmDIG6_DIG_TEST_PATTERN 0x5404 -#define CAR_mmDIG7_DIG_TEST_PATTERN 0x5604 -#define CAR_mmDIG8_DIG_TEST_PATTERN 0x5704 -#define CAR_mmDIG_RANDOM_PATTERN_SEED 0x4a05 -#define CAR_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 -#define CAR_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 -#define CAR_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 -#define CAR_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 -#define CAR_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 -#define CAR_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 -#define CAR_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 -#define CAR_mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 -#define CAR_mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 -#define CAR_mmDIG_FIFO_STATUS 0x4a06 -#define CAR_mmDIG0_DIG_FIFO_STATUS 0x4a06 -#define CAR_mmDIG1_DIG_FIFO_STATUS 0x4b06 -#define CAR_mmDIG2_DIG_FIFO_STATUS 0x4c06 -#define CAR_mmDIG3_DIG_FIFO_STATUS 0x4d06 -#define CAR_mmDIG4_DIG_FIFO_STATUS 0x4e06 -#define CAR_mmDIG5_DIG_FIFO_STATUS 0x4f06 -#define CAR_mmDIG6_DIG_FIFO_STATUS 0x5406 -#define CAR_mmDIG7_DIG_FIFO_STATUS 0x5606 -#define CAR_mmDIG8_DIG_FIFO_STATUS 0x5706 -#define CAR_mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 -#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 -#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 -#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 -#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 -#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 -#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 -#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 -#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 -#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 -#define CAR_mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 -#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 -#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 -#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 -#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 -#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 -#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 -#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 -#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 -#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 -#define CAR_mmHDMI_CONTROL 0x4a09 -#define CAR_mmDIG0_HDMI_CONTROL 0x4a09 -#define CAR_mmDIG1_HDMI_CONTROL 0x4b09 -#define CAR_mmDIG2_HDMI_CONTROL 0x4c09 -#define CAR_mmDIG3_HDMI_CONTROL 0x4d09 -#define CAR_mmDIG4_HDMI_CONTROL 0x4e09 -#define CAR_mmDIG5_HDMI_CONTROL 0x4f09 -#define CAR_mmDIG6_HDMI_CONTROL 0x5409 -#define CAR_mmDIG7_HDMI_CONTROL 0x5609 -#define CAR_mmDIG8_HDMI_CONTROL 0x5709 -#define CAR_mmHDMI_STATUS 0x4a0a -#define CAR_mmDIG0_HDMI_STATUS 0x4a0a -#define CAR_mmDIG1_HDMI_STATUS 0x4b0a -#define CAR_mmDIG2_HDMI_STATUS 0x4c0a -#define CAR_mmDIG3_HDMI_STATUS 0x4d0a -#define CAR_mmDIG4_HDMI_STATUS 0x4e0a -#define CAR_mmDIG5_HDMI_STATUS 0x4f0a -#define CAR_mmDIG6_HDMI_STATUS 0x540a -#define CAR_mmDIG7_HDMI_STATUS 0x560a -#define CAR_mmDIG8_HDMI_STATUS 0x570a -#define CAR_mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b -#define CAR_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b -#define CAR_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b -#define CAR_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b -#define CAR_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b -#define CAR_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b -#define CAR_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b -#define CAR_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b -#define CAR_mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b -#define CAR_mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b -#define CAR_mmHDMI_ACR_PACKET_CONTROL 0x4a0c -#define CAR_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c -#define CAR_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c -#define CAR_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c -#define CAR_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c -#define CAR_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c -#define CAR_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c -#define CAR_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c -#define CAR_mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c -#define CAR_mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c -#define CAR_mmHDMI_VBI_PACKET_CONTROL 0x4a0d -#define CAR_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d -#define CAR_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d -#define CAR_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d -#define CAR_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d -#define CAR_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d -#define CAR_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d -#define CAR_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d -#define CAR_mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d -#define CAR_mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d -#define CAR_mmHDMI_INFOFRAME_CONTROL0 0x4a0e -#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e -#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e -#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e -#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e -#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e -#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e -#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e -#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e -#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e -#define CAR_mmHDMI_INFOFRAME_CONTROL1 0x4a0f -#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f -#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f -#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f -#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f -#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f -#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f -#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f -#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f -#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f -#define CAR_mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 -#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 -#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 -#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 -#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 -#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 -#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 -#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 -#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 -#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 -#define CAR_mmAFMT_INTERRUPT_STATUS 0x4a11 -#define CAR_mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 -#define CAR_mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 -#define CAR_mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 -#define CAR_mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 -#define CAR_mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 -#define CAR_mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 -#define CAR_mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 -#define CAR_mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 -#define CAR_mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 -#define CAR_mmHDMI_GC 0x4a13 -#define CAR_mmDIG0_HDMI_GC 0x4a13 -#define CAR_mmDIG1_HDMI_GC 0x4b13 -#define CAR_mmDIG2_HDMI_GC 0x4c13 -#define CAR_mmDIG3_HDMI_GC 0x4d13 -#define CAR_mmDIG4_HDMI_GC 0x4e13 -#define CAR_mmDIG5_HDMI_GC 0x4f13 -#define CAR_mmDIG6_HDMI_GC 0x5413 -#define CAR_mmDIG7_HDMI_GC 0x5613 -#define CAR_mmDIG8_HDMI_GC 0x5713 -#define CAR_mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 -#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 -#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 -#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 -#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 -#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 -#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 -#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 -#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 -#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 -#define CAR_mmAFMT_ISRC1_0 0x4a15 -#define CAR_mmDIG0_AFMT_ISRC1_0 0x4a15 -#define CAR_mmDIG1_AFMT_ISRC1_0 0x4b15 -#define CAR_mmDIG2_AFMT_ISRC1_0 0x4c15 -#define CAR_mmDIG3_AFMT_ISRC1_0 0x4d15 -#define CAR_mmDIG4_AFMT_ISRC1_0 0x4e15 -#define CAR_mmDIG5_AFMT_ISRC1_0 0x4f15 -#define CAR_mmDIG6_AFMT_ISRC1_0 0x5415 -#define CAR_mmDIG7_AFMT_ISRC1_0 0x5615 -#define CAR_mmDIG8_AFMT_ISRC1_0 0x5715 -#define CAR_mmAFMT_ISRC1_1 0x4a16 -#define CAR_mmDIG0_AFMT_ISRC1_1 0x4a16 -#define CAR_mmDIG1_AFMT_ISRC1_1 0x4b16 -#define CAR_mmDIG2_AFMT_ISRC1_1 0x4c16 -#define CAR_mmDIG3_AFMT_ISRC1_1 0x4d16 -#define CAR_mmDIG4_AFMT_ISRC1_1 0x4e16 -#define CAR_mmDIG5_AFMT_ISRC1_1 0x4f16 -#define CAR_mmDIG6_AFMT_ISRC1_1 0x5416 -#define CAR_mmDIG7_AFMT_ISRC1_1 0x5616 -#define CAR_mmDIG8_AFMT_ISRC1_1 0x5716 -#define CAR_mmAFMT_ISRC1_2 0x4a17 -#define CAR_mmDIG0_AFMT_ISRC1_2 0x4a17 -#define CAR_mmDIG1_AFMT_ISRC1_2 0x4b17 -#define CAR_mmDIG2_AFMT_ISRC1_2 0x4c17 -#define CAR_mmDIG3_AFMT_ISRC1_2 0x4d17 -#define CAR_mmDIG4_AFMT_ISRC1_2 0x4e17 -#define CAR_mmDIG5_AFMT_ISRC1_2 0x4f17 -#define CAR_mmDIG6_AFMT_ISRC1_2 0x5417 -#define CAR_mmDIG7_AFMT_ISRC1_2 0x5617 -#define CAR_mmDIG8_AFMT_ISRC1_2 0x5717 -#define CAR_mmAFMT_ISRC1_3 0x4a18 -#define CAR_mmDIG0_AFMT_ISRC1_3 0x4a18 -#define CAR_mmDIG1_AFMT_ISRC1_3 0x4b18 -#define CAR_mmDIG2_AFMT_ISRC1_3 0x4c18 -#define CAR_mmDIG3_AFMT_ISRC1_3 0x4d18 -#define CAR_mmDIG4_AFMT_ISRC1_3 0x4e18 -#define CAR_mmDIG5_AFMT_ISRC1_3 0x4f18 -#define CAR_mmDIG6_AFMT_ISRC1_3 0x5418 -#define CAR_mmDIG7_AFMT_ISRC1_3 0x5618 -#define CAR_mmDIG8_AFMT_ISRC1_3 0x5718 -#define CAR_mmAFMT_ISRC1_4 0x4a19 -#define CAR_mmDIG0_AFMT_ISRC1_4 0x4a19 -#define CAR_mmDIG1_AFMT_ISRC1_4 0x4b19 -#define CAR_mmDIG2_AFMT_ISRC1_4 0x4c19 -#define CAR_mmDIG3_AFMT_ISRC1_4 0x4d19 -#define CAR_mmDIG4_AFMT_ISRC1_4 0x4e19 -#define CAR_mmDIG5_AFMT_ISRC1_4 0x4f19 -#define CAR_mmDIG6_AFMT_ISRC1_4 0x5419 -#define CAR_mmDIG7_AFMT_ISRC1_4 0x5619 -#define CAR_mmDIG8_AFMT_ISRC1_4 0x5719 -#define CAR_mmAFMT_ISRC2_0 0x4a1a -#define CAR_mmDIG0_AFMT_ISRC2_0 0x4a1a -#define CAR_mmDIG1_AFMT_ISRC2_0 0x4b1a -#define CAR_mmDIG2_AFMT_ISRC2_0 0x4c1a -#define CAR_mmDIG3_AFMT_ISRC2_0 0x4d1a -#define CAR_mmDIG4_AFMT_ISRC2_0 0x4e1a -#define CAR_mmDIG5_AFMT_ISRC2_0 0x4f1a -#define CAR_mmDIG6_AFMT_ISRC2_0 0x541a -#define CAR_mmDIG7_AFMT_ISRC2_0 0x561a -#define CAR_mmDIG8_AFMT_ISRC2_0 0x571a -#define CAR_mmAFMT_ISRC2_1 0x4a1b -#define CAR_mmDIG0_AFMT_ISRC2_1 0x4a1b -#define CAR_mmDIG1_AFMT_ISRC2_1 0x4b1b -#define CAR_mmDIG2_AFMT_ISRC2_1 0x4c1b -#define CAR_mmDIG3_AFMT_ISRC2_1 0x4d1b -#define CAR_mmDIG4_AFMT_ISRC2_1 0x4e1b -#define CAR_mmDIG5_AFMT_ISRC2_1 0x4f1b -#define CAR_mmDIG6_AFMT_ISRC2_1 0x541b -#define CAR_mmDIG7_AFMT_ISRC2_1 0x561b -#define CAR_mmDIG8_AFMT_ISRC2_1 0x571b -#define CAR_mmAFMT_ISRC2_2 0x4a1c -#define CAR_mmDIG0_AFMT_ISRC2_2 0x4a1c -#define CAR_mmDIG1_AFMT_ISRC2_2 0x4b1c -#define CAR_mmDIG2_AFMT_ISRC2_2 0x4c1c -#define CAR_mmDIG3_AFMT_ISRC2_2 0x4d1c -#define CAR_mmDIG4_AFMT_ISRC2_2 0x4e1c -#define CAR_mmDIG5_AFMT_ISRC2_2 0x4f1c -#define CAR_mmDIG6_AFMT_ISRC2_2 0x541c -#define CAR_mmDIG7_AFMT_ISRC2_2 0x561c -#define CAR_mmDIG8_AFMT_ISRC2_2 0x571c -#define CAR_mmAFMT_ISRC2_3 0x4a1d -#define CAR_mmDIG0_AFMT_ISRC2_3 0x4a1d -#define CAR_mmDIG1_AFMT_ISRC2_3 0x4b1d -#define CAR_mmDIG2_AFMT_ISRC2_3 0x4c1d -#define CAR_mmDIG3_AFMT_ISRC2_3 0x4d1d -#define CAR_mmDIG4_AFMT_ISRC2_3 0x4e1d -#define CAR_mmDIG5_AFMT_ISRC2_3 0x4f1d -#define CAR_mmDIG6_AFMT_ISRC2_3 0x541d -#define CAR_mmDIG7_AFMT_ISRC2_3 0x561d -#define CAR_mmDIG8_AFMT_ISRC2_3 0x571d -#define CAR_mmAFMT_AVI_INFO0 0x4a1e -#define CAR_mmDIG0_AFMT_AVI_INFO0 0x4a1e -#define CAR_mmDIG1_AFMT_AVI_INFO0 0x4b1e -#define CAR_mmDIG2_AFMT_AVI_INFO0 0x4c1e -#define CAR_mmDIG3_AFMT_AVI_INFO0 0x4d1e -#define CAR_mmDIG4_AFMT_AVI_INFO0 0x4e1e -#define CAR_mmDIG5_AFMT_AVI_INFO0 0x4f1e -#define CAR_mmDIG6_AFMT_AVI_INFO0 0x541e -#define CAR_mmDIG7_AFMT_AVI_INFO0 0x561e -#define CAR_mmDIG8_AFMT_AVI_INFO0 0x571e -#define CAR_mmAFMT_AVI_INFO1 0x4a1f -#define CAR_mmDIG0_AFMT_AVI_INFO1 0x4a1f -#define CAR_mmDIG1_AFMT_AVI_INFO1 0x4b1f -#define CAR_mmDIG2_AFMT_AVI_INFO1 0x4c1f -#define CAR_mmDIG3_AFMT_AVI_INFO1 0x4d1f -#define CAR_mmDIG4_AFMT_AVI_INFO1 0x4e1f -#define CAR_mmDIG5_AFMT_AVI_INFO1 0x4f1f -#define CAR_mmDIG6_AFMT_AVI_INFO1 0x541f -#define CAR_mmDIG7_AFMT_AVI_INFO1 0x561f -#define CAR_mmDIG8_AFMT_AVI_INFO1 0x571f -#define CAR_mmAFMT_AVI_INFO2 0x4a20 -#define CAR_mmDIG0_AFMT_AVI_INFO2 0x4a20 -#define CAR_mmDIG1_AFMT_AVI_INFO2 0x4b20 -#define CAR_mmDIG2_AFMT_AVI_INFO2 0x4c20 -#define CAR_mmDIG3_AFMT_AVI_INFO2 0x4d20 -#define CAR_mmDIG4_AFMT_AVI_INFO2 0x4e20 -#define CAR_mmDIG5_AFMT_AVI_INFO2 0x4f20 -#define CAR_mmDIG6_AFMT_AVI_INFO2 0x5420 -#define CAR_mmDIG7_AFMT_AVI_INFO2 0x5620 -#define CAR_mmDIG8_AFMT_AVI_INFO2 0x5720 -#define CAR_mmAFMT_AVI_INFO3 0x4a21 -#define CAR_mmDIG0_AFMT_AVI_INFO3 0x4a21 -#define CAR_mmDIG1_AFMT_AVI_INFO3 0x4b21 -#define CAR_mmDIG2_AFMT_AVI_INFO3 0x4c21 -#define CAR_mmDIG3_AFMT_AVI_INFO3 0x4d21 -#define CAR_mmDIG4_AFMT_AVI_INFO3 0x4e21 -#define CAR_mmDIG5_AFMT_AVI_INFO3 0x4f21 -#define CAR_mmDIG6_AFMT_AVI_INFO3 0x5421 -#define CAR_mmDIG7_AFMT_AVI_INFO3 0x5621 -#define CAR_mmDIG8_AFMT_AVI_INFO3 0x5721 -#define CAR_mmAFMT_MPEG_INFO0 0x4a22 -#define CAR_mmDIG0_AFMT_MPEG_INFO0 0x4a22 -#define CAR_mmDIG1_AFMT_MPEG_INFO0 0x4b22 -#define CAR_mmDIG2_AFMT_MPEG_INFO0 0x4c22 -#define CAR_mmDIG3_AFMT_MPEG_INFO0 0x4d22 -#define CAR_mmDIG4_AFMT_MPEG_INFO0 0x4e22 -#define CAR_mmDIG5_AFMT_MPEG_INFO0 0x4f22 -#define CAR_mmDIG6_AFMT_MPEG_INFO0 0x5422 -#define CAR_mmDIG7_AFMT_MPEG_INFO0 0x5622 -#define CAR_mmDIG8_AFMT_MPEG_INFO0 0x5722 -#define CAR_mmAFMT_MPEG_INFO1 0x4a23 -#define CAR_mmDIG0_AFMT_MPEG_INFO1 0x4a23 -#define CAR_mmDIG1_AFMT_MPEG_INFO1 0x4b23 -#define CAR_mmDIG2_AFMT_MPEG_INFO1 0x4c23 -#define CAR_mmDIG3_AFMT_MPEG_INFO1 0x4d23 -#define CAR_mmDIG4_AFMT_MPEG_INFO1 0x4e23 -#define CAR_mmDIG5_AFMT_MPEG_INFO1 0x4f23 -#define CAR_mmDIG6_AFMT_MPEG_INFO1 0x5423 -#define CAR_mmDIG7_AFMT_MPEG_INFO1 0x5623 -#define CAR_mmDIG8_AFMT_MPEG_INFO1 0x5723 -#define CAR_mmAFMT_GENERIC_HDR 0x4a24 -#define CAR_mmDIG0_AFMT_GENERIC_HDR 0x4a24 -#define CAR_mmDIG1_AFMT_GENERIC_HDR 0x4b24 -#define CAR_mmDIG2_AFMT_GENERIC_HDR 0x4c24 -#define CAR_mmDIG3_AFMT_GENERIC_HDR 0x4d24 -#define CAR_mmDIG4_AFMT_GENERIC_HDR 0x4e24 -#define CAR_mmDIG5_AFMT_GENERIC_HDR 0x4f24 -#define CAR_mmDIG6_AFMT_GENERIC_HDR 0x5424 -#define CAR_mmDIG7_AFMT_GENERIC_HDR 0x5624 -#define CAR_mmDIG8_AFMT_GENERIC_HDR 0x5724 -#define CAR_mmAFMT_GENERIC_0 0x4a25 -#define CAR_mmDIG0_AFMT_GENERIC_0 0x4a25 -#define CAR_mmDIG1_AFMT_GENERIC_0 0x4b25 -#define CAR_mmDIG2_AFMT_GENERIC_0 0x4c25 -#define CAR_mmDIG3_AFMT_GENERIC_0 0x4d25 -#define CAR_mmDIG4_AFMT_GENERIC_0 0x4e25 -#define CAR_mmDIG5_AFMT_GENERIC_0 0x4f25 -#define CAR_mmDIG6_AFMT_GENERIC_0 0x5425 -#define CAR_mmDIG7_AFMT_GENERIC_0 0x5625 -#define CAR_mmDIG8_AFMT_GENERIC_0 0x5725 -#define CAR_mmAFMT_GENERIC_1 0x4a26 -#define CAR_mmDIG0_AFMT_GENERIC_1 0x4a26 -#define CAR_mmDIG1_AFMT_GENERIC_1 0x4b26 -#define CAR_mmDIG2_AFMT_GENERIC_1 0x4c26 -#define CAR_mmDIG3_AFMT_GENERIC_1 0x4d26 -#define CAR_mmDIG4_AFMT_GENERIC_1 0x4e26 -#define CAR_mmDIG5_AFMT_GENERIC_1 0x4f26 -#define CAR_mmDIG6_AFMT_GENERIC_1 0x5426 -#define CAR_mmDIG7_AFMT_GENERIC_1 0x5626 -#define CAR_mmDIG8_AFMT_GENERIC_1 0x5726 -#define CAR_mmAFMT_GENERIC_2 0x4a27 -#define CAR_mmDIG0_AFMT_GENERIC_2 0x4a27 -#define CAR_mmDIG1_AFMT_GENERIC_2 0x4b27 -#define CAR_mmDIG2_AFMT_GENERIC_2 0x4c27 -#define CAR_mmDIG3_AFMT_GENERIC_2 0x4d27 -#define CAR_mmDIG4_AFMT_GENERIC_2 0x4e27 -#define CAR_mmDIG5_AFMT_GENERIC_2 0x4f27 -#define CAR_mmDIG6_AFMT_GENERIC_2 0x5427 -#define CAR_mmDIG7_AFMT_GENERIC_2 0x5627 -#define CAR_mmDIG8_AFMT_GENERIC_2 0x5727 -#define CAR_mmAFMT_GENERIC_3 0x4a28 -#define CAR_mmDIG0_AFMT_GENERIC_3 0x4a28 -#define CAR_mmDIG1_AFMT_GENERIC_3 0x4b28 -#define CAR_mmDIG2_AFMT_GENERIC_3 0x4c28 -#define CAR_mmDIG3_AFMT_GENERIC_3 0x4d28 -#define CAR_mmDIG4_AFMT_GENERIC_3 0x4e28 -#define CAR_mmDIG5_AFMT_GENERIC_3 0x4f28 -#define CAR_mmDIG6_AFMT_GENERIC_3 0x5428 -#define CAR_mmDIG7_AFMT_GENERIC_3 0x5628 -#define CAR_mmDIG8_AFMT_GENERIC_3 0x5728 -#define CAR_mmAFMT_GENERIC_4 0x4a29 -#define CAR_mmDIG0_AFMT_GENERIC_4 0x4a29 -#define CAR_mmDIG1_AFMT_GENERIC_4 0x4b29 -#define CAR_mmDIG2_AFMT_GENERIC_4 0x4c29 -#define CAR_mmDIG3_AFMT_GENERIC_4 0x4d29 -#define CAR_mmDIG4_AFMT_GENERIC_4 0x4e29 -#define CAR_mmDIG5_AFMT_GENERIC_4 0x4f29 -#define CAR_mmDIG6_AFMT_GENERIC_4 0x5429 -#define CAR_mmDIG7_AFMT_GENERIC_4 0x5629 -#define CAR_mmDIG8_AFMT_GENERIC_4 0x5729 -#define CAR_mmAFMT_GENERIC_5 0x4a2a -#define CAR_mmDIG0_AFMT_GENERIC_5 0x4a2a -#define CAR_mmDIG1_AFMT_GENERIC_5 0x4b2a -#define CAR_mmDIG2_AFMT_GENERIC_5 0x4c2a -#define CAR_mmDIG3_AFMT_GENERIC_5 0x4d2a -#define CAR_mmDIG4_AFMT_GENERIC_5 0x4e2a -#define CAR_mmDIG5_AFMT_GENERIC_5 0x4f2a -#define CAR_mmDIG6_AFMT_GENERIC_5 0x542a -#define CAR_mmDIG7_AFMT_GENERIC_5 0x562a -#define CAR_mmDIG8_AFMT_GENERIC_5 0x572a -#define CAR_mmAFMT_GENERIC_6 0x4a2b -#define CAR_mmDIG0_AFMT_GENERIC_6 0x4a2b -#define CAR_mmDIG1_AFMT_GENERIC_6 0x4b2b -#define CAR_mmDIG2_AFMT_GENERIC_6 0x4c2b -#define CAR_mmDIG3_AFMT_GENERIC_6 0x4d2b -#define CAR_mmDIG4_AFMT_GENERIC_6 0x4e2b -#define CAR_mmDIG5_AFMT_GENERIC_6 0x4f2b -#define CAR_mmDIG6_AFMT_GENERIC_6 0x542b -#define CAR_mmDIG7_AFMT_GENERIC_6 0x562b -#define CAR_mmDIG8_AFMT_GENERIC_6 0x572b -#define CAR_mmAFMT_GENERIC_7 0x4a2c -#define CAR_mmDIG0_AFMT_GENERIC_7 0x4a2c -#define CAR_mmDIG1_AFMT_GENERIC_7 0x4b2c -#define CAR_mmDIG2_AFMT_GENERIC_7 0x4c2c -#define CAR_mmDIG3_AFMT_GENERIC_7 0x4d2c -#define CAR_mmDIG4_AFMT_GENERIC_7 0x4e2c -#define CAR_mmDIG5_AFMT_GENERIC_7 0x4f2c -#define CAR_mmDIG6_AFMT_GENERIC_7 0x542c -#define CAR_mmDIG7_AFMT_GENERIC_7 0x562c -#define CAR_mmDIG8_AFMT_GENERIC_7 0x572c -#define CAR_mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d -#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d -#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d -#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d -#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d -#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d -#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d -#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d -#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d -#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d -#define CAR_mmHDMI_ACR_32_0 0x4a2e -#define CAR_mmDIG0_HDMI_ACR_32_0 0x4a2e -#define CAR_mmDIG1_HDMI_ACR_32_0 0x4b2e -#define CAR_mmDIG2_HDMI_ACR_32_0 0x4c2e -#define CAR_mmDIG3_HDMI_ACR_32_0 0x4d2e -#define CAR_mmDIG4_HDMI_ACR_32_0 0x4e2e -#define CAR_mmDIG5_HDMI_ACR_32_0 0x4f2e -#define CAR_mmDIG6_HDMI_ACR_32_0 0x542e -#define CAR_mmDIG7_HDMI_ACR_32_0 0x562e -#define CAR_mmDIG8_HDMI_ACR_32_0 0x572e -#define CAR_mmHDMI_ACR_32_1 0x4a2f -#define CAR_mmDIG0_HDMI_ACR_32_1 0x4a2f -#define CAR_mmDIG1_HDMI_ACR_32_1 0x4b2f -#define CAR_mmDIG2_HDMI_ACR_32_1 0x4c2f -#define CAR_mmDIG3_HDMI_ACR_32_1 0x4d2f -#define CAR_mmDIG4_HDMI_ACR_32_1 0x4e2f -#define CAR_mmDIG5_HDMI_ACR_32_1 0x4f2f -#define CAR_mmDIG6_HDMI_ACR_32_1 0x542f -#define CAR_mmDIG7_HDMI_ACR_32_1 0x562f -#define CAR_mmDIG8_HDMI_ACR_32_1 0x572f -#define CAR_mmHDMI_ACR_44_0 0x4a30 -#define CAR_mmDIG0_HDMI_ACR_44_0 0x4a30 -#define CAR_mmDIG1_HDMI_ACR_44_0 0x4b30 -#define CAR_mmDIG2_HDMI_ACR_44_0 0x4c30 -#define CAR_mmDIG3_HDMI_ACR_44_0 0x4d30 -#define CAR_mmDIG4_HDMI_ACR_44_0 0x4e30 -#define CAR_mmDIG5_HDMI_ACR_44_0 0x4f30 -#define CAR_mmDIG6_HDMI_ACR_44_0 0x5430 -#define CAR_mmDIG7_HDMI_ACR_44_0 0x5630 -#define CAR_mmDIG8_HDMI_ACR_44_0 0x5730 -#define CAR_mmHDMI_ACR_44_1 0x4a31 -#define CAR_mmDIG0_HDMI_ACR_44_1 0x4a31 -#define CAR_mmDIG1_HDMI_ACR_44_1 0x4b31 -#define CAR_mmDIG2_HDMI_ACR_44_1 0x4c31 -#define CAR_mmDIG3_HDMI_ACR_44_1 0x4d31 -#define CAR_mmDIG4_HDMI_ACR_44_1 0x4e31 -#define CAR_mmDIG5_HDMI_ACR_44_1 0x4f31 -#define CAR_mmDIG6_HDMI_ACR_44_1 0x5431 -#define CAR_mmDIG7_HDMI_ACR_44_1 0x5631 -#define CAR_mmDIG8_HDMI_ACR_44_1 0x5731 -#define CAR_mmHDMI_ACR_48_0 0x4a32 -#define CAR_mmDIG0_HDMI_ACR_48_0 0x4a32 -#define CAR_mmDIG1_HDMI_ACR_48_0 0x4b32 -#define CAR_mmDIG2_HDMI_ACR_48_0 0x4c32 -#define CAR_mmDIG3_HDMI_ACR_48_0 0x4d32 -#define CAR_mmDIG4_HDMI_ACR_48_0 0x4e32 -#define CAR_mmDIG5_HDMI_ACR_48_0 0x4f32 -#define CAR_mmDIG6_HDMI_ACR_48_0 0x5432 -#define CAR_mmDIG7_HDMI_ACR_48_0 0x5632 -#define CAR_mmDIG8_HDMI_ACR_48_0 0x5732 -#define CAR_mmHDMI_ACR_48_1 0x4a33 -#define CAR_mmDIG0_HDMI_ACR_48_1 0x4a33 -#define CAR_mmDIG1_HDMI_ACR_48_1 0x4b33 -#define CAR_mmDIG2_HDMI_ACR_48_1 0x4c33 -#define CAR_mmDIG3_HDMI_ACR_48_1 0x4d33 -#define CAR_mmDIG4_HDMI_ACR_48_1 0x4e33 -#define CAR_mmDIG5_HDMI_ACR_48_1 0x4f33 -#define CAR_mmDIG6_HDMI_ACR_48_1 0x5433 -#define CAR_mmDIG7_HDMI_ACR_48_1 0x5633 -#define CAR_mmDIG8_HDMI_ACR_48_1 0x5733 -#define CAR_mmHDMI_ACR_STATUS_0 0x4a34 -#define CAR_mmDIG0_HDMI_ACR_STATUS_0 0x4a34 -#define CAR_mmDIG1_HDMI_ACR_STATUS_0 0x4b34 -#define CAR_mmDIG2_HDMI_ACR_STATUS_0 0x4c34 -#define CAR_mmDIG3_HDMI_ACR_STATUS_0 0x4d34 -#define CAR_mmDIG4_HDMI_ACR_STATUS_0 0x4e34 -#define CAR_mmDIG5_HDMI_ACR_STATUS_0 0x4f34 -#define CAR_mmDIG6_HDMI_ACR_STATUS_0 0x5434 -#define CAR_mmDIG7_HDMI_ACR_STATUS_0 0x5634 -#define CAR_mmDIG8_HDMI_ACR_STATUS_0 0x5734 -#define CAR_mmHDMI_ACR_STATUS_1 0x4a35 -#define CAR_mmDIG0_HDMI_ACR_STATUS_1 0x4a35 -#define CAR_mmDIG1_HDMI_ACR_STATUS_1 0x4b35 -#define CAR_mmDIG2_HDMI_ACR_STATUS_1 0x4c35 -#define CAR_mmDIG3_HDMI_ACR_STATUS_1 0x4d35 -#define CAR_mmDIG4_HDMI_ACR_STATUS_1 0x4e35 -#define CAR_mmDIG5_HDMI_ACR_STATUS_1 0x4f35 -#define CAR_mmDIG6_HDMI_ACR_STATUS_1 0x5435 -#define CAR_mmDIG7_HDMI_ACR_STATUS_1 0x5635 -#define CAR_mmDIG8_HDMI_ACR_STATUS_1 0x5735 -#define CAR_mmAFMT_AUDIO_INFO0 0x4a36 -#define CAR_mmDIG0_AFMT_AUDIO_INFO0 0x4a36 -#define CAR_mmDIG1_AFMT_AUDIO_INFO0 0x4b36 -#define CAR_mmDIG2_AFMT_AUDIO_INFO0 0x4c36 -#define CAR_mmDIG3_AFMT_AUDIO_INFO0 0x4d36 -#define CAR_mmDIG4_AFMT_AUDIO_INFO0 0x4e36 -#define CAR_mmDIG5_AFMT_AUDIO_INFO0 0x4f36 -#define CAR_mmDIG6_AFMT_AUDIO_INFO0 0x5436 -#define CAR_mmDIG7_AFMT_AUDIO_INFO0 0x5636 -#define CAR_mmDIG8_AFMT_AUDIO_INFO0 0x5736 -#define CAR_mmAFMT_AUDIO_INFO1 0x4a37 -#define CAR_mmDIG0_AFMT_AUDIO_INFO1 0x4a37 -#define CAR_mmDIG1_AFMT_AUDIO_INFO1 0x4b37 -#define CAR_mmDIG2_AFMT_AUDIO_INFO1 0x4c37 -#define CAR_mmDIG3_AFMT_AUDIO_INFO1 0x4d37 -#define CAR_mmDIG4_AFMT_AUDIO_INFO1 0x4e37 -#define CAR_mmDIG5_AFMT_AUDIO_INFO1 0x4f37 -#define CAR_mmDIG6_AFMT_AUDIO_INFO1 0x5437 -#define CAR_mmDIG7_AFMT_AUDIO_INFO1 0x5637 -#define CAR_mmDIG8_AFMT_AUDIO_INFO1 0x5737 -#define CAR_mmAFMT_60958_0 0x4a38 -#define CAR_mmDIG0_AFMT_60958_0 0x4a38 -#define CAR_mmDIG1_AFMT_60958_0 0x4b38 -#define CAR_mmDIG2_AFMT_60958_0 0x4c38 -#define CAR_mmDIG3_AFMT_60958_0 0x4d38 -#define CAR_mmDIG4_AFMT_60958_0 0x4e38 -#define CAR_mmDIG5_AFMT_60958_0 0x4f38 -#define CAR_mmDIG6_AFMT_60958_0 0x5438 -#define CAR_mmDIG7_AFMT_60958_0 0x5638 -#define CAR_mmDIG8_AFMT_60958_0 0x5738 -#define CAR_mmAFMT_60958_1 0x4a39 -#define CAR_mmDIG0_AFMT_60958_1 0x4a39 -#define CAR_mmDIG1_AFMT_60958_1 0x4b39 -#define CAR_mmDIG2_AFMT_60958_1 0x4c39 -#define CAR_mmDIG3_AFMT_60958_1 0x4d39 -#define CAR_mmDIG4_AFMT_60958_1 0x4e39 -#define CAR_mmDIG5_AFMT_60958_1 0x4f39 -#define CAR_mmDIG6_AFMT_60958_1 0x5439 -#define CAR_mmDIG7_AFMT_60958_1 0x5639 -#define CAR_mmDIG8_AFMT_60958_1 0x5739 -#define CAR_mmAFMT_AUDIO_CRC_CONTROL 0x4a3a -#define CAR_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a -#define CAR_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a -#define CAR_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a -#define CAR_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a -#define CAR_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a -#define CAR_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a -#define CAR_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a -#define CAR_mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a -#define CAR_mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a -#define CAR_mmAFMT_RAMP_CONTROL0 0x4a3b -#define CAR_mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b -#define CAR_mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b -#define CAR_mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b -#define CAR_mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b -#define CAR_mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b -#define CAR_mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b -#define CAR_mmDIG6_AFMT_RAMP_CONTROL0 0x543b -#define CAR_mmDIG7_AFMT_RAMP_CONTROL0 0x563b -#define CAR_mmDIG8_AFMT_RAMP_CONTROL0 0x573b -#define CAR_mmAFMT_RAMP_CONTROL1 0x4a3c -#define CAR_mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c -#define CAR_mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c -#define CAR_mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c -#define CAR_mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c -#define CAR_mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c -#define CAR_mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c -#define CAR_mmDIG6_AFMT_RAMP_CONTROL1 0x543c -#define CAR_mmDIG7_AFMT_RAMP_CONTROL1 0x563c -#define CAR_mmDIG8_AFMT_RAMP_CONTROL1 0x573c -#define CAR_mmAFMT_RAMP_CONTROL2 0x4a3d -#define CAR_mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d -#define CAR_mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d -#define CAR_mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d -#define CAR_mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d -#define CAR_mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d -#define CAR_mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d -#define CAR_mmDIG6_AFMT_RAMP_CONTROL2 0x543d -#define CAR_mmDIG7_AFMT_RAMP_CONTROL2 0x563d -#define CAR_mmDIG8_AFMT_RAMP_CONTROL2 0x573d -#define CAR_mmAFMT_RAMP_CONTROL3 0x4a3e -#define CAR_mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e -#define CAR_mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e -#define CAR_mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e -#define CAR_mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e -#define CAR_mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e -#define CAR_mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e -#define CAR_mmDIG6_AFMT_RAMP_CONTROL3 0x543e -#define CAR_mmDIG7_AFMT_RAMP_CONTROL3 0x563e -#define CAR_mmDIG8_AFMT_RAMP_CONTROL3 0x573e -#define CAR_mmAFMT_60958_2 0x4a3f -#define CAR_mmDIG0_AFMT_60958_2 0x4a3f -#define CAR_mmDIG1_AFMT_60958_2 0x4b3f -#define CAR_mmDIG2_AFMT_60958_2 0x4c3f -#define CAR_mmDIG3_AFMT_60958_2 0x4d3f -#define CAR_mmDIG4_AFMT_60958_2 0x4e3f -#define CAR_mmDIG5_AFMT_60958_2 0x4f3f -#define CAR_mmDIG6_AFMT_60958_2 0x543f -#define CAR_mmDIG7_AFMT_60958_2 0x563f -#define CAR_mmDIG8_AFMT_60958_2 0x573f -#define CAR_mmAFMT_AUDIO_CRC_RESULT 0x4a40 -#define CAR_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 -#define CAR_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 -#define CAR_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 -#define CAR_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 -#define CAR_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 -#define CAR_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 -#define CAR_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 -#define CAR_mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 -#define CAR_mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 -#define CAR_mmAFMT_STATUS 0x4a41 -#define CAR_mmDIG0_AFMT_STATUS 0x4a41 -#define CAR_mmDIG1_AFMT_STATUS 0x4b41 -#define CAR_mmDIG2_AFMT_STATUS 0x4c41 -#define CAR_mmDIG3_AFMT_STATUS 0x4d41 -#define CAR_mmDIG4_AFMT_STATUS 0x4e41 -#define CAR_mmDIG5_AFMT_STATUS 0x4f41 -#define CAR_mmDIG6_AFMT_STATUS 0x5441 -#define CAR_mmDIG7_AFMT_STATUS 0x5641 -#define CAR_mmDIG8_AFMT_STATUS 0x5741 -#define CAR_mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 -#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 -#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 -#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 -#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 -#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 -#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 -#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 -#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 -#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 -#define CAR_mmAFMT_VBI_PACKET_CONTROL 0x4a43 -#define CAR_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 -#define CAR_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 -#define CAR_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 -#define CAR_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 -#define CAR_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 -#define CAR_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 -#define CAR_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 -#define CAR_mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 -#define CAR_mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 -#define CAR_mmAFMT_INFOFRAME_CONTROL0 0x4a44 -#define CAR_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 -#define CAR_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 -#define CAR_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 -#define CAR_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 -#define CAR_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 -#define CAR_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 -#define CAR_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 -#define CAR_mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 -#define CAR_mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 -#define CAR_mmAFMT_AUDIO_SRC_CONTROL 0x4a45 -#define CAR_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 -#define CAR_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 -#define CAR_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 -#define CAR_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 -#define CAR_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 -#define CAR_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 -#define CAR_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 -#define CAR_mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 -#define CAR_mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 -#define CAR_mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 -#define CAR_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 -#define CAR_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 -#define CAR_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 -#define CAR_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 -#define CAR_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 -#define CAR_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 -#define CAR_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 -#define CAR_mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 -#define CAR_mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 -#define CAR_mmAFMT_CNTL 0x4a7e -#define CAR_mmDIG0_AFMT_CNTL 0x4a7e -#define CAR_mmDIG1_AFMT_CNTL 0x4b7e -#define CAR_mmDIG2_AFMT_CNTL 0x4c7e -#define CAR_mmDIG3_AFMT_CNTL 0x4d7e -#define CAR_mmDIG4_AFMT_CNTL 0x4e7e -#define CAR_mmDIG5_AFMT_CNTL 0x4f7e -#define CAR_mmDIG6_AFMT_CNTL 0x547e -#define CAR_mmDIG7_AFMT_CNTL 0x567e -#define CAR_mmDIG8_AFMT_CNTL 0x577e -#define CAR_mmDIG_BE_CNTL 0x4a47 -#define CAR_mmDIG0_DIG_BE_CNTL 0x4a47 -#define CAR_mmDIG1_DIG_BE_CNTL 0x4b47 -#define CAR_mmDIG2_DIG_BE_CNTL 0x4c47 -#define CAR_mmDIG3_DIG_BE_CNTL 0x4d47 -#define CAR_mmDIG4_DIG_BE_CNTL 0x4e47 -#define CAR_mmDIG5_DIG_BE_CNTL 0x4f47 -#define CAR_mmDIG6_DIG_BE_CNTL 0x5447 -#define CAR_mmDIG7_DIG_BE_CNTL 0x5647 -#define CAR_mmDIG8_DIG_BE_CNTL 0x5747 -#define CAR_mmDIG_BE_EN_CNTL 0x4a48 -#define CAR_mmDIG0_DIG_BE_EN_CNTL 0x4a48 -#define CAR_mmDIG1_DIG_BE_EN_CNTL 0x4b48 -#define CAR_mmDIG2_DIG_BE_EN_CNTL 0x4c48 -#define CAR_mmDIG3_DIG_BE_EN_CNTL 0x4d48 -#define CAR_mmDIG4_DIG_BE_EN_CNTL 0x4e48 -#define CAR_mmDIG5_DIG_BE_EN_CNTL 0x4f48 -#define CAR_mmDIG6_DIG_BE_EN_CNTL 0x5448 -#define CAR_mmDIG7_DIG_BE_EN_CNTL 0x5648 -#define CAR_mmDIG8_DIG_BE_EN_CNTL 0x5748 -#define CAR_mmTMDS_CNTL 0x4a6b -#define CAR_mmDIG0_TMDS_CNTL 0x4a6b -#define CAR_mmDIG1_TMDS_CNTL 0x4b6b -#define CAR_mmDIG2_TMDS_CNTL 0x4c6b -#define CAR_mmDIG3_TMDS_CNTL 0x4d6b -#define CAR_mmDIG4_TMDS_CNTL 0x4e6b -#define CAR_mmDIG5_TMDS_CNTL 0x4f6b -#define CAR_mmDIG6_TMDS_CNTL 0x546b -#define CAR_mmDIG7_TMDS_CNTL 0x566b -#define CAR_mmDIG8_TMDS_CNTL 0x576b -#define CAR_mmTMDS_CONTROL_CHAR 0x4a6c -#define CAR_mmDIG0_TMDS_CONTROL_CHAR 0x4a6c -#define CAR_mmDIG1_TMDS_CONTROL_CHAR 0x4b6c -#define CAR_mmDIG2_TMDS_CONTROL_CHAR 0x4c6c -#define CAR_mmDIG3_TMDS_CONTROL_CHAR 0x4d6c -#define CAR_mmDIG4_TMDS_CONTROL_CHAR 0x4e6c -#define CAR_mmDIG5_TMDS_CONTROL_CHAR 0x4f6c -#define CAR_mmDIG6_TMDS_CONTROL_CHAR 0x546c -#define CAR_mmDIG7_TMDS_CONTROL_CHAR 0x566c -#define CAR_mmDIG8_TMDS_CONTROL_CHAR 0x576c -#define CAR_mmTMDS_CONTROL0_FEEDBACK 0x4a6d -#define CAR_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d -#define CAR_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d -#define CAR_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d -#define CAR_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d -#define CAR_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d -#define CAR_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d -#define CAR_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d -#define CAR_mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d -#define CAR_mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d -#define CAR_mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e -#define CAR_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e -#define CAR_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e -#define CAR_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e -#define CAR_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e -#define CAR_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e -#define CAR_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e -#define CAR_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e -#define CAR_mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e -#define CAR_mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e -#define CAR_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f -#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f -#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f -#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f -#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f -#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f -#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f -#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f -#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f -#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f -#define CAR_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 -#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 -#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 -#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 -#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 -#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 -#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 -#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 -#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 -#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 -#define CAR_mmTMDS_DEBUG 0x4a71 -#define CAR_mmDIG0_TMDS_DEBUG 0x4a71 -#define CAR_mmDIG1_TMDS_DEBUG 0x4b71 -#define CAR_mmDIG2_TMDS_DEBUG 0x4c71 -#define CAR_mmDIG3_TMDS_DEBUG 0x4d71 -#define CAR_mmDIG4_TMDS_DEBUG 0x4e71 -#define CAR_mmDIG5_TMDS_DEBUG 0x4f71 -#define CAR_mmDIG6_TMDS_DEBUG 0x5471 -#define CAR_mmDIG7_TMDS_DEBUG 0x5671 -#define CAR_mmDIG8_TMDS_DEBUG 0x5771 -#define CAR_mmTMDS_CTL_BITS 0x4a72 -#define CAR_mmDIG0_TMDS_CTL_BITS 0x4a72 -#define CAR_mmDIG1_TMDS_CTL_BITS 0x4b72 -#define CAR_mmDIG2_TMDS_CTL_BITS 0x4c72 -#define CAR_mmDIG3_TMDS_CTL_BITS 0x4d72 -#define CAR_mmDIG4_TMDS_CTL_BITS 0x4e72 -#define CAR_mmDIG5_TMDS_CTL_BITS 0x4f72 -#define CAR_mmDIG6_TMDS_CTL_BITS 0x5472 -#define CAR_mmDIG7_TMDS_CTL_BITS 0x5672 -#define CAR_mmDIG8_TMDS_CTL_BITS 0x5772 -#define CAR_mmTMDS_DCBALANCER_CONTROL 0x4a73 -#define CAR_mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 -#define CAR_mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 -#define CAR_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 -#define CAR_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 -#define CAR_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 -#define CAR_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 -#define CAR_mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 -#define CAR_mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 -#define CAR_mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 -#define CAR_mmTMDS_CTL0_1_GEN_CNTL 0x4a75 -#define CAR_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 -#define CAR_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 -#define CAR_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 -#define CAR_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 -#define CAR_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 -#define CAR_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 -#define CAR_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 -#define CAR_mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 -#define CAR_mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 -#define CAR_mmTMDS_CTL2_3_GEN_CNTL 0x4a76 -#define CAR_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 -#define CAR_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 -#define CAR_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 -#define CAR_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 -#define CAR_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 -#define CAR_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 -#define CAR_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 -#define CAR_mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 -#define CAR_mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 -#define CAR_mmDIG_VERSION 0x4a78 -#define CAR_mmDIG0_DIG_VERSION 0x4a78 -#define CAR_mmDIG1_DIG_VERSION 0x4b78 -#define CAR_mmDIG2_DIG_VERSION 0x4c78 -#define CAR_mmDIG3_DIG_VERSION 0x4d78 -#define CAR_mmDIG4_DIG_VERSION 0x4e78 -#define CAR_mmDIG5_DIG_VERSION 0x4f78 -#define CAR_mmDIG6_DIG_VERSION 0x5478 -#define CAR_mmDIG7_DIG_VERSION 0x5678 -#define CAR_mmDIG8_DIG_VERSION 0x5778 -#define CAR_mmDIG_LANE_ENABLE 0x4a79 -#define CAR_mmDIG0_DIG_LANE_ENABLE 0x4a79 -#define CAR_mmDIG1_DIG_LANE_ENABLE 0x4b79 -#define CAR_mmDIG2_DIG_LANE_ENABLE 0x4c79 -#define CAR_mmDIG3_DIG_LANE_ENABLE 0x4d79 -#define CAR_mmDIG4_DIG_LANE_ENABLE 0x4e79 -#define CAR_mmDIG5_DIG_LANE_ENABLE 0x4f79 -#define CAR_mmDIG6_DIG_LANE_ENABLE 0x5479 -#define CAR_mmDIG7_DIG_LANE_ENABLE 0x5679 -#define CAR_mmDIG8_DIG_LANE_ENABLE 0x5779 -#define CAR_mmDIG_TEST_DEBUG_INDEX 0x4a7a -#define CAR_mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a -#define CAR_mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a -#define CAR_mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a -#define CAR_mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a -#define CAR_mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a -#define CAR_mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a -#define CAR_mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a -#define CAR_mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a -#define CAR_mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a -#define CAR_mmDIG_TEST_DEBUG_DATA 0x4a7b -#define CAR_mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b -#define CAR_mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b -#define CAR_mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b -#define CAR_mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b -#define CAR_mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b -#define CAR_mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b -#define CAR_mmDIG6_DIG_TEST_DEBUG_DATA 0x547b -#define CAR_mmDIG7_DIG_TEST_DEBUG_DATA 0x567b -#define CAR_mmDIG8_DIG_TEST_DEBUG_DATA 0x577b -#define CAR_mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c -#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c -#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c -#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c -#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c -#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c -#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c -#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c -#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c -#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c -#define CAR_mmDIG_FE_TEST_DEBUG_DATA 0x4a7d -#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d -#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d -#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d -#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d -#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d -#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d -#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d -#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d -#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d -#define CAR_mmDMCU_CTRL 0x1600 -#define CAR_mmDMCU_STATUS 0x1601 -#define CAR_mmDMCU_PC_START_ADDR 0x1602 -#define CAR_mmDMCU_FW_START_ADDR 0x1603 -#define CAR_mmDMCU_FW_END_ADDR 0x1604 -#define CAR_mmDMCU_FW_ISR_START_ADDR 0x1605 -#define CAR_mmDMCU_FW_CS_HI 0x1606 -#define CAR_mmDMCU_FW_CS_LO 0x1607 -#define CAR_mmDMCU_RAM_ACCESS_CTRL 0x1608 -#define CAR_mmDMCU_ERAM_WR_CTRL 0x1609 -#define CAR_mmDMCU_ERAM_WR_DATA 0x160a -#define CAR_mmDMCU_ERAM_RD_CTRL 0x160b -#define CAR_mmDMCU_ERAM_RD_DATA 0x160c -#define CAR_mmDMCU_IRAM_WR_CTRL 0x160d -#define CAR_mmDMCU_IRAM_WR_DATA 0x160e -#define CAR_mmDMCU_IRAM_RD_CTRL 0x160f -#define CAR_mmDMCU_IRAM_RD_DATA 0x1610 -#define CAR_mmDMCU_EVENT_TRIGGER 0x1611 -#define CAR_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 -#define CAR_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 -#define CAR_mmDMCU_INTERRUPT_STATUS 0x1614 -#define CAR_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 -#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 -#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 -#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 -#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 -#define CAR_mmDC_DMCU_SCRATCH 0x1618 -#define CAR_mmDMCU_INT_CNT 0x1619 -#define CAR_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a -#define CAR_mmDMCU_UC_CLK_GATING_CNTL 0x161b -#define CAR_mmMASTER_COMM_DATA_REG1 0x161c -#define CAR_mmMASTER_COMM_DATA_REG2 0x161d -#define CAR_mmMASTER_COMM_DATA_REG3 0x161e -#define CAR_mmMASTER_COMM_CMD_REG 0x161f -#define CAR_mmMASTER_COMM_CNTL_REG 0x1620 -#define CAR_mmSLAVE_COMM_DATA_REG1 0x1621 -#define CAR_mmSLAVE_COMM_DATA_REG2 0x1622 -#define CAR_mmSLAVE_COMM_DATA_REG3 0x1623 -#define CAR_mmSLAVE_COMM_CMD_REG 0x1624 -#define CAR_mmSLAVE_COMM_CNTL_REG 0x1625 -#define CAR_mmDMCU_TEST_DEBUG_INDEX 0x1626 -#define CAR_mmDMCU_TEST_DEBUG_DATA 0x1627 -#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 -#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 -#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 -#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 -#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b -#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 -#define CAR_mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 -#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 -#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 -#define CAR_mmDP_LINK_CNTL 0x4aa0 -#define CAR_mmDP0_DP_LINK_CNTL 0x4aa0 -#define CAR_mmDP1_DP_LINK_CNTL 0x4ba0 -#define CAR_mmDP2_DP_LINK_CNTL 0x4ca0 -#define CAR_mmDP3_DP_LINK_CNTL 0x4da0 -#define CAR_mmDP4_DP_LINK_CNTL 0x4ea0 -#define CAR_mmDP5_DP_LINK_CNTL 0x4fa0 -#define CAR_mmDP6_DP_LINK_CNTL 0x54a0 -#define CAR_mmDP7_DP_LINK_CNTL 0x56a0 -#define CAR_mmDP8_DP_LINK_CNTL 0x57a0 -#define CAR_mmDP_PIXEL_FORMAT 0x4aa1 -#define CAR_mmDP0_DP_PIXEL_FORMAT 0x4aa1 -#define CAR_mmDP1_DP_PIXEL_FORMAT 0x4ba1 -#define CAR_mmDP2_DP_PIXEL_FORMAT 0x4ca1 -#define CAR_mmDP3_DP_PIXEL_FORMAT 0x4da1 -#define CAR_mmDP4_DP_PIXEL_FORMAT 0x4ea1 -#define CAR_mmDP5_DP_PIXEL_FORMAT 0x4fa1 -#define CAR_mmDP6_DP_PIXEL_FORMAT 0x54a1 -#define CAR_mmDP7_DP_PIXEL_FORMAT 0x56a1 -#define CAR_mmDP8_DP_PIXEL_FORMAT 0x57a1 -#define CAR_mmDP_MSA_COLORIMETRY 0x4aa2 -#define CAR_mmDP0_DP_MSA_COLORIMETRY 0x4aa2 -#define CAR_mmDP1_DP_MSA_COLORIMETRY 0x4ba2 -#define CAR_mmDP2_DP_MSA_COLORIMETRY 0x4ca2 -#define CAR_mmDP3_DP_MSA_COLORIMETRY 0x4da2 -#define CAR_mmDP4_DP_MSA_COLORIMETRY 0x4ea2 -#define CAR_mmDP5_DP_MSA_COLORIMETRY 0x4fa2 -#define CAR_mmDP6_DP_MSA_COLORIMETRY 0x54a2 -#define CAR_mmDP7_DP_MSA_COLORIMETRY 0x56a2 -#define CAR_mmDP8_DP_MSA_COLORIMETRY 0x57a2 -#define CAR_mmDP_CONFIG 0x4aa3 -#define CAR_mmDP0_DP_CONFIG 0x4aa3 -#define CAR_mmDP1_DP_CONFIG 0x4ba3 -#define CAR_mmDP2_DP_CONFIG 0x4ca3 -#define CAR_mmDP3_DP_CONFIG 0x4da3 -#define CAR_mmDP4_DP_CONFIG 0x4ea3 -#define CAR_mmDP5_DP_CONFIG 0x4fa3 -#define CAR_mmDP6_DP_CONFIG 0x54a3 -#define CAR_mmDP7_DP_CONFIG 0x56a3 -#define CAR_mmDP8_DP_CONFIG 0x57a3 -#define CAR_mmDP_VID_STREAM_CNTL 0x4aa4 -#define CAR_mmDP0_DP_VID_STREAM_CNTL 0x4aa4 -#define CAR_mmDP1_DP_VID_STREAM_CNTL 0x4ba4 -#define CAR_mmDP2_DP_VID_STREAM_CNTL 0x4ca4 -#define CAR_mmDP3_DP_VID_STREAM_CNTL 0x4da4 -#define CAR_mmDP4_DP_VID_STREAM_CNTL 0x4ea4 -#define CAR_mmDP5_DP_VID_STREAM_CNTL 0x4fa4 -#define CAR_mmDP6_DP_VID_STREAM_CNTL 0x54a4 -#define CAR_mmDP7_DP_VID_STREAM_CNTL 0x56a4 -#define CAR_mmDP8_DP_VID_STREAM_CNTL 0x57a4 -#define CAR_mmDP_STEER_FIFO 0x4aa5 -#define CAR_mmDP0_DP_STEER_FIFO 0x4aa5 -#define CAR_mmDP1_DP_STEER_FIFO 0x4ba5 -#define CAR_mmDP2_DP_STEER_FIFO 0x4ca5 -#define CAR_mmDP3_DP_STEER_FIFO 0x4da5 -#define CAR_mmDP4_DP_STEER_FIFO 0x4ea5 -#define CAR_mmDP5_DP_STEER_FIFO 0x4fa5 -#define CAR_mmDP6_DP_STEER_FIFO 0x54a5 -#define CAR_mmDP7_DP_STEER_FIFO 0x56a5 -#define CAR_mmDP8_DP_STEER_FIFO 0x57a5 -#define CAR_mmDP_MSA_MISC 0x4aa6 -#define CAR_mmDP0_DP_MSA_MISC 0x4aa6 -#define CAR_mmDP1_DP_MSA_MISC 0x4ba6 -#define CAR_mmDP2_DP_MSA_MISC 0x4ca6 -#define CAR_mmDP3_DP_MSA_MISC 0x4da6 -#define CAR_mmDP4_DP_MSA_MISC 0x4ea6 -#define CAR_mmDP5_DP_MSA_MISC 0x4fa6 -#define CAR_mmDP6_DP_MSA_MISC 0x54a6 -#define CAR_mmDP7_DP_MSA_MISC 0x56a6 -#define CAR_mmDP8_DP_MSA_MISC 0x57a6 -#define CAR_mmDP_VID_TIMING 0x4aa8 -#define CAR_mmDP0_DP_VID_TIMING 0x4aa8 -#define CAR_mmDP1_DP_VID_TIMING 0x4ba8 -#define CAR_mmDP2_DP_VID_TIMING 0x4ca8 -#define CAR_mmDP3_DP_VID_TIMING 0x4da8 -#define CAR_mmDP4_DP_VID_TIMING 0x4ea8 -#define CAR_mmDP5_DP_VID_TIMING 0x4fa8 -#define CAR_mmDP6_DP_VID_TIMING 0x54a8 -#define CAR_mmDP7_DP_VID_TIMING 0x56a8 -#define CAR_mmDP8_DP_VID_TIMING 0x57a8 -#define CAR_mmDP_VID_N 0x4aa9 -#define CAR_mmDP0_DP_VID_N 0x4aa9 -#define CAR_mmDP1_DP_VID_N 0x4ba9 -#define CAR_mmDP2_DP_VID_N 0x4ca9 -#define CAR_mmDP3_DP_VID_N 0x4da9 -#define CAR_mmDP4_DP_VID_N 0x4ea9 -#define CAR_mmDP5_DP_VID_N 0x4fa9 -#define CAR_mmDP6_DP_VID_N 0x54a9 -#define CAR_mmDP7_DP_VID_N 0x56a9 -#define CAR_mmDP8_DP_VID_N 0x57a9 -#define CAR_mmDP_VID_M 0x4aaa -#define CAR_mmDP0_DP_VID_M 0x4aaa -#define CAR_mmDP1_DP_VID_M 0x4baa -#define CAR_mmDP2_DP_VID_M 0x4caa -#define CAR_mmDP3_DP_VID_M 0x4daa -#define CAR_mmDP4_DP_VID_M 0x4eaa -#define CAR_mmDP5_DP_VID_M 0x4faa -#define CAR_mmDP6_DP_VID_M 0x54aa -#define CAR_mmDP7_DP_VID_M 0x56aa -#define CAR_mmDP8_DP_VID_M 0x57aa -#define CAR_mmDP_LINK_FRAMING_CNTL 0x4aab -#define CAR_mmDP0_DP_LINK_FRAMING_CNTL 0x4aab -#define CAR_mmDP1_DP_LINK_FRAMING_CNTL 0x4bab -#define CAR_mmDP2_DP_LINK_FRAMING_CNTL 0x4cab -#define CAR_mmDP3_DP_LINK_FRAMING_CNTL 0x4dab -#define CAR_mmDP4_DP_LINK_FRAMING_CNTL 0x4eab -#define CAR_mmDP5_DP_LINK_FRAMING_CNTL 0x4fab -#define CAR_mmDP6_DP_LINK_FRAMING_CNTL 0x54ab -#define CAR_mmDP7_DP_LINK_FRAMING_CNTL 0x56ab -#define CAR_mmDP8_DP_LINK_FRAMING_CNTL 0x57ab -#define CAR_mmDP_HBR2_EYE_PATTERN 0x4aac -#define CAR_mmDP0_DP_HBR2_EYE_PATTERN 0x4aac -#define CAR_mmDP1_DP_HBR2_EYE_PATTERN 0x4bac -#define CAR_mmDP2_DP_HBR2_EYE_PATTERN 0x4cac -#define CAR_mmDP3_DP_HBR2_EYE_PATTERN 0x4dac -#define CAR_mmDP4_DP_HBR2_EYE_PATTERN 0x4eac -#define CAR_mmDP5_DP_HBR2_EYE_PATTERN 0x4fac -#define CAR_mmDP6_DP_HBR2_EYE_PATTERN 0x54ac -#define CAR_mmDP7_DP_HBR2_EYE_PATTERN 0x56ac -#define CAR_mmDP8_DP_HBR2_EYE_PATTERN 0x57ac -#define CAR_mmDP_VID_MSA_VBID 0x4aad -#define CAR_mmDP0_DP_VID_MSA_VBID 0x4aad -#define CAR_mmDP1_DP_VID_MSA_VBID 0x4bad -#define CAR_mmDP2_DP_VID_MSA_VBID 0x4cad -#define CAR_mmDP3_DP_VID_MSA_VBID 0x4dad -#define CAR_mmDP4_DP_VID_MSA_VBID 0x4ead -#define CAR_mmDP5_DP_VID_MSA_VBID 0x4fad -#define CAR_mmDP6_DP_VID_MSA_VBID 0x54ad -#define CAR_mmDP7_DP_VID_MSA_VBID 0x56ad -#define CAR_mmDP8_DP_VID_MSA_VBID 0x57ad -#define CAR_mmDP_VID_INTERRUPT_CNTL 0x4aae -#define CAR_mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae -#define CAR_mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae -#define CAR_mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae -#define CAR_mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae -#define CAR_mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae -#define CAR_mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae -#define CAR_mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae -#define CAR_mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae -#define CAR_mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae -#define CAR_mmDP_DPHY_CNTL 0x4aaf -#define CAR_mmDP0_DP_DPHY_CNTL 0x4aaf -#define CAR_mmDP1_DP_DPHY_CNTL 0x4baf -#define CAR_mmDP2_DP_DPHY_CNTL 0x4caf -#define CAR_mmDP3_DP_DPHY_CNTL 0x4daf -#define CAR_mmDP4_DP_DPHY_CNTL 0x4eaf -#define CAR_mmDP5_DP_DPHY_CNTL 0x4faf -#define CAR_mmDP6_DP_DPHY_CNTL 0x54af -#define CAR_mmDP7_DP_DPHY_CNTL 0x56af -#define CAR_mmDP8_DP_DPHY_CNTL 0x57af -#define CAR_mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 -#define CAR_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 -#define CAR_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 -#define CAR_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 -#define CAR_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 -#define CAR_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 -#define CAR_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 -#define CAR_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 -#define CAR_mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 -#define CAR_mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 -#define CAR_mmDP_DPHY_SYM0 0x4ab1 -#define CAR_mmDP0_DP_DPHY_SYM0 0x4ab1 -#define CAR_mmDP1_DP_DPHY_SYM0 0x4bb1 -#define CAR_mmDP2_DP_DPHY_SYM0 0x4cb1 -#define CAR_mmDP3_DP_DPHY_SYM0 0x4db1 -#define CAR_mmDP4_DP_DPHY_SYM0 0x4eb1 -#define CAR_mmDP5_DP_DPHY_SYM0 0x4fb1 -#define CAR_mmDP6_DP_DPHY_SYM0 0x54b1 -#define CAR_mmDP7_DP_DPHY_SYM0 0x56b1 -#define CAR_mmDP8_DP_DPHY_SYM0 0x57b1 -#define CAR_mmDP_DPHY_SYM1 0x4ab2 -#define CAR_mmDP0_DP_DPHY_SYM1 0x4ab2 -#define CAR_mmDP1_DP_DPHY_SYM1 0x4bb2 -#define CAR_mmDP2_DP_DPHY_SYM1 0x4cb2 -#define CAR_mmDP3_DP_DPHY_SYM1 0x4db2 -#define CAR_mmDP4_DP_DPHY_SYM1 0x4eb2 -#define CAR_mmDP5_DP_DPHY_SYM1 0x4fb2 -#define CAR_mmDP6_DP_DPHY_SYM1 0x54b2 -#define CAR_mmDP7_DP_DPHY_SYM1 0x56b2 -#define CAR_mmDP8_DP_DPHY_SYM1 0x57b2 -#define CAR_mmDP_DPHY_SYM2 0x4ab3 -#define CAR_mmDP0_DP_DPHY_SYM2 0x4ab3 -#define CAR_mmDP1_DP_DPHY_SYM2 0x4bb3 -#define CAR_mmDP2_DP_DPHY_SYM2 0x4cb3 -#define CAR_mmDP3_DP_DPHY_SYM2 0x4db3 -#define CAR_mmDP4_DP_DPHY_SYM2 0x4eb3 -#define CAR_mmDP5_DP_DPHY_SYM2 0x4fb3 -#define CAR_mmDP6_DP_DPHY_SYM2 0x54b3 -#define CAR_mmDP7_DP_DPHY_SYM2 0x56b3 -#define CAR_mmDP8_DP_DPHY_SYM2 0x57b3 -#define CAR_mmDP_DPHY_8B10B_CNTL 0x4ab4 -#define CAR_mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 -#define CAR_mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 -#define CAR_mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 -#define CAR_mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 -#define CAR_mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 -#define CAR_mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 -#define CAR_mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 -#define CAR_mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 -#define CAR_mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 -#define CAR_mmDP_DPHY_PRBS_CNTL 0x4ab5 -#define CAR_mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 -#define CAR_mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 -#define CAR_mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 -#define CAR_mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 -#define CAR_mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 -#define CAR_mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 -#define CAR_mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 -#define CAR_mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 -#define CAR_mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 -#define CAR_mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc -#define CAR_mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc -#define CAR_mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc -#define CAR_mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc -#define CAR_mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc -#define CAR_mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc -#define CAR_mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc -#define CAR_mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc -#define CAR_mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc -#define CAR_mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc -#define CAR_mmDP_DPHY_CRC_EN 0x4ab7 -#define CAR_mmDP0_DP_DPHY_CRC_EN 0x4ab7 -#define CAR_mmDP1_DP_DPHY_CRC_EN 0x4bb7 -#define CAR_mmDP2_DP_DPHY_CRC_EN 0x4cb7 -#define CAR_mmDP3_DP_DPHY_CRC_EN 0x4db7 -#define CAR_mmDP4_DP_DPHY_CRC_EN 0x4eb7 -#define CAR_mmDP5_DP_DPHY_CRC_EN 0x4fb7 -#define CAR_mmDP6_DP_DPHY_CRC_EN 0x54b7 -#define CAR_mmDP7_DP_DPHY_CRC_EN 0x56b7 -#define CAR_mmDP8_DP_DPHY_CRC_EN 0x57b7 -#define CAR_mmDP_DPHY_CRC_CNTL 0x4ab8 -#define CAR_mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 -#define CAR_mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 -#define CAR_mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 -#define CAR_mmDP3_DP_DPHY_CRC_CNTL 0x4db8 -#define CAR_mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 -#define CAR_mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 -#define CAR_mmDP6_DP_DPHY_CRC_CNTL 0x54b8 -#define CAR_mmDP7_DP_DPHY_CRC_CNTL 0x56b8 -#define CAR_mmDP8_DP_DPHY_CRC_CNTL 0x57b8 -#define CAR_mmDP_DPHY_CRC_RESULT 0x4ab9 -#define CAR_mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 -#define CAR_mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 -#define CAR_mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 -#define CAR_mmDP3_DP_DPHY_CRC_RESULT 0x4db9 -#define CAR_mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 -#define CAR_mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 -#define CAR_mmDP6_DP_DPHY_CRC_RESULT 0x54b9 -#define CAR_mmDP7_DP_DPHY_CRC_RESULT 0x56b9 -#define CAR_mmDP8_DP_DPHY_CRC_RESULT 0x57b9 -#define CAR_mmDP_DPHY_CRC_MST_CNTL 0x4aba -#define CAR_mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba -#define CAR_mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba -#define CAR_mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba -#define CAR_mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba -#define CAR_mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba -#define CAR_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba -#define CAR_mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba -#define CAR_mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba -#define CAR_mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba -#define CAR_mmDP_DPHY_CRC_MST_STATUS 0x4abb -#define CAR_mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb -#define CAR_mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb -#define CAR_mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb -#define CAR_mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb -#define CAR_mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb -#define CAR_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb -#define CAR_mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb -#define CAR_mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb -#define CAR_mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb -#define CAR_mmDP_DPHY_FAST_TRAINING 0x4abc -#define CAR_mmDP0_DP_DPHY_FAST_TRAINING 0x4abc -#define CAR_mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc -#define CAR_mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc -#define CAR_mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc -#define CAR_mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc -#define CAR_mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc -#define CAR_mmDP6_DP_DPHY_FAST_TRAINING 0x54bc -#define CAR_mmDP7_DP_DPHY_FAST_TRAINING 0x56bc -#define CAR_mmDP8_DP_DPHY_FAST_TRAINING 0x57bc -#define CAR_mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd -#define CAR_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd -#define CAR_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd -#define CAR_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd -#define CAR_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd -#define CAR_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd -#define CAR_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd -#define CAR_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd -#define CAR_mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd -#define CAR_mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd -#define CAR_mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add -#define CAR_mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add -#define CAR_mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd -#define CAR_mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd -#define CAR_mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd -#define CAR_mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd -#define CAR_mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd -#define CAR_mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd -#define CAR_mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd -#define CAR_mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd -#define CAR_mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe -#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe -#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe -#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe -#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe -#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe -#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe -#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be -#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be -#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be -#define CAR_mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf -#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf -#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf -#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf -#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf -#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf -#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf -#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf -#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf -#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf -#define CAR_mmDP_SEC_CNTL 0x4ac3 -#define CAR_mmDP0_DP_SEC_CNTL 0x4ac3 -#define CAR_mmDP1_DP_SEC_CNTL 0x4bc3 -#define CAR_mmDP2_DP_SEC_CNTL 0x4cc3 -#define CAR_mmDP3_DP_SEC_CNTL 0x4dc3 -#define CAR_mmDP4_DP_SEC_CNTL 0x4ec3 -#define CAR_mmDP5_DP_SEC_CNTL 0x4fc3 -#define CAR_mmDP6_DP_SEC_CNTL 0x54c3 -#define CAR_mmDP7_DP_SEC_CNTL 0x56c3 -#define CAR_mmDP8_DP_SEC_CNTL 0x57c3 -#define CAR_mmDP_SEC_CNTL1 0x4ac4 -#define CAR_mmDP0_DP_SEC_CNTL1 0x4ac4 -#define CAR_mmDP1_DP_SEC_CNTL1 0x4bc4 -#define CAR_mmDP2_DP_SEC_CNTL1 0x4cc4 -#define CAR_mmDP3_DP_SEC_CNTL1 0x4dc4 -#define CAR_mmDP4_DP_SEC_CNTL1 0x4ec4 -#define CAR_mmDP5_DP_SEC_CNTL1 0x4fc4 -#define CAR_mmDP6_DP_SEC_CNTL1 0x54c4 -#define CAR_mmDP7_DP_SEC_CNTL1 0x56c4 -#define CAR_mmDP8_DP_SEC_CNTL1 0x57c4 -#define CAR_mmDP_SEC_FRAMING1 0x4ac5 -#define CAR_mmDP0_DP_SEC_FRAMING1 0x4ac5 -#define CAR_mmDP1_DP_SEC_FRAMING1 0x4bc5 -#define CAR_mmDP2_DP_SEC_FRAMING1 0x4cc5 -#define CAR_mmDP3_DP_SEC_FRAMING1 0x4dc5 -#define CAR_mmDP4_DP_SEC_FRAMING1 0x4ec5 -#define CAR_mmDP5_DP_SEC_FRAMING1 0x4fc5 -#define CAR_mmDP6_DP_SEC_FRAMING1 0x54c5 -#define CAR_mmDP7_DP_SEC_FRAMING1 0x56c5 -#define CAR_mmDP8_DP_SEC_FRAMING1 0x57c5 -#define CAR_mmDP_SEC_FRAMING2 0x4ac6 -#define CAR_mmDP0_DP_SEC_FRAMING2 0x4ac6 -#define CAR_mmDP1_DP_SEC_FRAMING2 0x4bc6 -#define CAR_mmDP2_DP_SEC_FRAMING2 0x4cc6 -#define CAR_mmDP3_DP_SEC_FRAMING2 0x4dc6 -#define CAR_mmDP4_DP_SEC_FRAMING2 0x4ec6 -#define CAR_mmDP5_DP_SEC_FRAMING2 0x4fc6 -#define CAR_mmDP6_DP_SEC_FRAMING2 0x54c6 -#define CAR_mmDP7_DP_SEC_FRAMING2 0x56c6 -#define CAR_mmDP8_DP_SEC_FRAMING2 0x57c6 -#define CAR_mmDP_SEC_FRAMING3 0x4ac7 -#define CAR_mmDP0_DP_SEC_FRAMING3 0x4ac7 -#define CAR_mmDP1_DP_SEC_FRAMING3 0x4bc7 -#define CAR_mmDP2_DP_SEC_FRAMING3 0x4cc7 -#define CAR_mmDP3_DP_SEC_FRAMING3 0x4dc7 -#define CAR_mmDP4_DP_SEC_FRAMING3 0x4ec7 -#define CAR_mmDP5_DP_SEC_FRAMING3 0x4fc7 -#define CAR_mmDP6_DP_SEC_FRAMING3 0x54c7 -#define CAR_mmDP7_DP_SEC_FRAMING3 0x56c7 -#define CAR_mmDP8_DP_SEC_FRAMING3 0x57c7 -#define CAR_mmDP_SEC_FRAMING4 0x4ac8 -#define CAR_mmDP0_DP_SEC_FRAMING4 0x4ac8 -#define CAR_mmDP1_DP_SEC_FRAMING4 0x4bc8 -#define CAR_mmDP2_DP_SEC_FRAMING4 0x4cc8 -#define CAR_mmDP3_DP_SEC_FRAMING4 0x4dc8 -#define CAR_mmDP4_DP_SEC_FRAMING4 0x4ec8 -#define CAR_mmDP5_DP_SEC_FRAMING4 0x4fc8 -#define CAR_mmDP6_DP_SEC_FRAMING4 0x54c8 -#define CAR_mmDP7_DP_SEC_FRAMING4 0x56c8 -#define CAR_mmDP8_DP_SEC_FRAMING4 0x57c8 -#define CAR_mmDP_SEC_AUD_N 0x4ac9 -#define CAR_mmDP0_DP_SEC_AUD_N 0x4ac9 -#define CAR_mmDP1_DP_SEC_AUD_N 0x4bc9 -#define CAR_mmDP2_DP_SEC_AUD_N 0x4cc9 -#define CAR_mmDP3_DP_SEC_AUD_N 0x4dc9 -#define CAR_mmDP4_DP_SEC_AUD_N 0x4ec9 -#define CAR_mmDP5_DP_SEC_AUD_N 0x4fc9 -#define CAR_mmDP6_DP_SEC_AUD_N 0x54c9 -#define CAR_mmDP7_DP_SEC_AUD_N 0x56c9 -#define CAR_mmDP8_DP_SEC_AUD_N 0x57c9 -#define CAR_mmDP_SEC_AUD_N_READBACK 0x4aca -#define CAR_mmDP0_DP_SEC_AUD_N_READBACK 0x4aca -#define CAR_mmDP1_DP_SEC_AUD_N_READBACK 0x4bca -#define CAR_mmDP2_DP_SEC_AUD_N_READBACK 0x4cca -#define CAR_mmDP3_DP_SEC_AUD_N_READBACK 0x4dca -#define CAR_mmDP4_DP_SEC_AUD_N_READBACK 0x4eca -#define CAR_mmDP5_DP_SEC_AUD_N_READBACK 0x4fca -#define CAR_mmDP6_DP_SEC_AUD_N_READBACK 0x54ca -#define CAR_mmDP7_DP_SEC_AUD_N_READBACK 0x56ca -#define CAR_mmDP8_DP_SEC_AUD_N_READBACK 0x57ca -#define CAR_mmDP_SEC_AUD_M 0x4acb -#define CAR_mmDP0_DP_SEC_AUD_M 0x4acb -#define CAR_mmDP1_DP_SEC_AUD_M 0x4bcb -#define CAR_mmDP2_DP_SEC_AUD_M 0x4ccb -#define CAR_mmDP3_DP_SEC_AUD_M 0x4dcb -#define CAR_mmDP4_DP_SEC_AUD_M 0x4ecb -#define CAR_mmDP5_DP_SEC_AUD_M 0x4fcb -#define CAR_mmDP6_DP_SEC_AUD_M 0x54cb -#define CAR_mmDP7_DP_SEC_AUD_M 0x56cb -#define CAR_mmDP8_DP_SEC_AUD_M 0x57cb -#define CAR_mmDP_SEC_AUD_M_READBACK 0x4acc -#define CAR_mmDP0_DP_SEC_AUD_M_READBACK 0x4acc -#define CAR_mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc -#define CAR_mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc -#define CAR_mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc -#define CAR_mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc -#define CAR_mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc -#define CAR_mmDP6_DP_SEC_AUD_M_READBACK 0x54cc -#define CAR_mmDP7_DP_SEC_AUD_M_READBACK 0x56cc -#define CAR_mmDP8_DP_SEC_AUD_M_READBACK 0x57cc -#define CAR_mmDP_SEC_TIMESTAMP 0x4acd -#define CAR_mmDP0_DP_SEC_TIMESTAMP 0x4acd -#define CAR_mmDP1_DP_SEC_TIMESTAMP 0x4bcd -#define CAR_mmDP2_DP_SEC_TIMESTAMP 0x4ccd -#define CAR_mmDP3_DP_SEC_TIMESTAMP 0x4dcd -#define CAR_mmDP4_DP_SEC_TIMESTAMP 0x4ecd -#define CAR_mmDP5_DP_SEC_TIMESTAMP 0x4fcd -#define CAR_mmDP6_DP_SEC_TIMESTAMP 0x54cd -#define CAR_mmDP7_DP_SEC_TIMESTAMP 0x56cd -#define CAR_mmDP8_DP_SEC_TIMESTAMP 0x57cd -#define CAR_mmDP_SEC_PACKET_CNTL 0x4ace -#define CAR_mmDP0_DP_SEC_PACKET_CNTL 0x4ace -#define CAR_mmDP1_DP_SEC_PACKET_CNTL 0x4bce -#define CAR_mmDP2_DP_SEC_PACKET_CNTL 0x4cce -#define CAR_mmDP3_DP_SEC_PACKET_CNTL 0x4dce -#define CAR_mmDP4_DP_SEC_PACKET_CNTL 0x4ece -#define CAR_mmDP5_DP_SEC_PACKET_CNTL 0x4fce -#define CAR_mmDP6_DP_SEC_PACKET_CNTL 0x54ce -#define CAR_mmDP7_DP_SEC_PACKET_CNTL 0x56ce -#define CAR_mmDP8_DP_SEC_PACKET_CNTL 0x57ce -#define CAR_mmDP_MSE_RATE_CNTL 0x4acf -#define CAR_mmDP0_DP_MSE_RATE_CNTL 0x4acf -#define CAR_mmDP1_DP_MSE_RATE_CNTL 0x4bcf -#define CAR_mmDP2_DP_MSE_RATE_CNTL 0x4ccf -#define CAR_mmDP3_DP_MSE_RATE_CNTL 0x4dcf -#define CAR_mmDP4_DP_MSE_RATE_CNTL 0x4ecf -#define CAR_mmDP5_DP_MSE_RATE_CNTL 0x4fcf -#define CAR_mmDP6_DP_MSE_RATE_CNTL 0x54cf -#define CAR_mmDP7_DP_MSE_RATE_CNTL 0x56cf -#define CAR_mmDP8_DP_MSE_RATE_CNTL 0x57cf -#define CAR_mmDP_MSE_RATE_UPDATE 0x4ad1 -#define CAR_mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 -#define CAR_mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 -#define CAR_mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 -#define CAR_mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 -#define CAR_mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 -#define CAR_mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 -#define CAR_mmDP6_DP_MSE_RATE_UPDATE 0x54d1 -#define CAR_mmDP7_DP_MSE_RATE_UPDATE 0x56d1 -#define CAR_mmDP8_DP_MSE_RATE_UPDATE 0x57d1 -#define CAR_mmDP_MSE_SAT0 0x4ad2 -#define CAR_mmDP0_DP_MSE_SAT0 0x4ad2 -#define CAR_mmDP1_DP_MSE_SAT0 0x4bd2 -#define CAR_mmDP2_DP_MSE_SAT0 0x4cd2 -#define CAR_mmDP3_DP_MSE_SAT0 0x4dd2 -#define CAR_mmDP4_DP_MSE_SAT0 0x4ed2 -#define CAR_mmDP5_DP_MSE_SAT0 0x4fd2 -#define CAR_mmDP6_DP_MSE_SAT0 0x54d2 -#define CAR_mmDP7_DP_MSE_SAT0 0x56d2 -#define CAR_mmDP8_DP_MSE_SAT0 0x57d2 -#define CAR_mmDP_MSE_SAT1 0x4ad3 -#define CAR_mmDP0_DP_MSE_SAT1 0x4ad3 -#define CAR_mmDP1_DP_MSE_SAT1 0x4bd3 -#define CAR_mmDP2_DP_MSE_SAT1 0x4cd3 -#define CAR_mmDP3_DP_MSE_SAT1 0x4dd3 -#define CAR_mmDP4_DP_MSE_SAT1 0x4ed3 -#define CAR_mmDP5_DP_MSE_SAT1 0x4fd3 -#define CAR_mmDP6_DP_MSE_SAT1 0x54d3 -#define CAR_mmDP7_DP_MSE_SAT1 0x56d3 -#define CAR_mmDP8_DP_MSE_SAT1 0x57d3 -#define CAR_mmDP_MSE_SAT2 0x4ad4 -#define CAR_mmDP0_DP_MSE_SAT2 0x4ad4 -#define CAR_mmDP1_DP_MSE_SAT2 0x4bd4 -#define CAR_mmDP2_DP_MSE_SAT2 0x4cd4 -#define CAR_mmDP3_DP_MSE_SAT2 0x4dd4 -#define CAR_mmDP4_DP_MSE_SAT2 0x4ed4 -#define CAR_mmDP5_DP_MSE_SAT2 0x4fd4 -#define CAR_mmDP6_DP_MSE_SAT2 0x54d4 -#define CAR_mmDP7_DP_MSE_SAT2 0x56d4 -#define CAR_mmDP8_DP_MSE_SAT2 0x57d4 -#define CAR_mmDP_MSE_SAT_UPDATE 0x4ad5 -#define CAR_mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 -#define CAR_mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 -#define CAR_mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 -#define CAR_mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 -#define CAR_mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 -#define CAR_mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 -#define CAR_mmDP6_DP_MSE_SAT_UPDATE 0x54d5 -#define CAR_mmDP7_DP_MSE_SAT_UPDATE 0x56d5 -#define CAR_mmDP8_DP_MSE_SAT_UPDATE 0x57d5 -#define CAR_mmDP_MSE_LINK_TIMING 0x4ad6 -#define CAR_mmDP0_DP_MSE_LINK_TIMING 0x4ad6 -#define CAR_mmDP1_DP_MSE_LINK_TIMING 0x4bd6 -#define CAR_mmDP2_DP_MSE_LINK_TIMING 0x4cd6 -#define CAR_mmDP3_DP_MSE_LINK_TIMING 0x4dd6 -#define CAR_mmDP4_DP_MSE_LINK_TIMING 0x4ed6 -#define CAR_mmDP5_DP_MSE_LINK_TIMING 0x4fd6 -#define CAR_mmDP6_DP_MSE_LINK_TIMING 0x54d6 -#define CAR_mmDP7_DP_MSE_LINK_TIMING 0x56d6 -#define CAR_mmDP8_DP_MSE_LINK_TIMING 0x57d6 -#define CAR_mmDP_MSE_MISC_CNTL 0x4ad7 -#define CAR_mmDP0_DP_MSE_MISC_CNTL 0x4ad7 -#define CAR_mmDP1_DP_MSE_MISC_CNTL 0x4bd7 -#define CAR_mmDP2_DP_MSE_MISC_CNTL 0x4cd7 -#define CAR_mmDP3_DP_MSE_MISC_CNTL 0x4dd7 -#define CAR_mmDP4_DP_MSE_MISC_CNTL 0x4ed7 -#define CAR_mmDP5_DP_MSE_MISC_CNTL 0x4fd7 -#define CAR_mmDP6_DP_MSE_MISC_CNTL 0x54d7 -#define CAR_mmDP7_DP_MSE_MISC_CNTL 0x56d7 -#define CAR_mmDP8_DP_MSE_MISC_CNTL 0x57d7 -#define CAR_mmDP_TEST_DEBUG_INDEX 0x4ad8 -#define CAR_mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 -#define CAR_mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 -#define CAR_mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 -#define CAR_mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 -#define CAR_mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 -#define CAR_mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 -#define CAR_mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 -#define CAR_mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 -#define CAR_mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 -#define CAR_mmDP_TEST_DEBUG_DATA 0x4ad9 -#define CAR_mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 -#define CAR_mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 -#define CAR_mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 -#define CAR_mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 -#define CAR_mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 -#define CAR_mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 -#define CAR_mmDP6_DP_TEST_DEBUG_DATA 0x54d9 -#define CAR_mmDP7_DP_TEST_DEBUG_DATA 0x56d9 -#define CAR_mmDP8_DP_TEST_DEBUG_DATA 0x57d9 -#define CAR_mmDP_FE_TEST_DEBUG_INDEX 0x4ada -#define CAR_mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada -#define CAR_mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda -#define CAR_mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda -#define CAR_mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda -#define CAR_mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda -#define CAR_mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda -#define CAR_mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da -#define CAR_mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da -#define CAR_mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da -#define CAR_mmDP_FE_TEST_DEBUG_DATA 0x4adb -#define CAR_mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb -#define CAR_mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb -#define CAR_mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb -#define CAR_mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb -#define CAR_mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb -#define CAR_mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb -#define CAR_mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db -#define CAR_mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db -#define CAR_mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db -#define CAR_mmAUX_CONTROL 0x5c00 -#define CAR_mmDP_AUX0_AUX_CONTROL 0x5c00 -#define CAR_mmDP_AUX1_AUX_CONTROL 0x5c1c -#define CAR_mmDP_AUX2_AUX_CONTROL 0x5c38 -#define CAR_mmDP_AUX3_AUX_CONTROL 0x5c54 -#define CAR_mmDP_AUX4_AUX_CONTROL 0x5c70 -#define CAR_mmDP_AUX5_AUX_CONTROL 0x5c8c -#define CAR_mmAUX_SW_CONTROL 0x5c01 -#define CAR_mmDP_AUX0_AUX_SW_CONTROL 0x5c01 -#define CAR_mmDP_AUX1_AUX_SW_CONTROL 0x5c1d -#define CAR_mmDP_AUX2_AUX_SW_CONTROL 0x5c39 -#define CAR_mmDP_AUX3_AUX_SW_CONTROL 0x5c55 -#define CAR_mmDP_AUX4_AUX_SW_CONTROL 0x5c71 -#define CAR_mmDP_AUX5_AUX_SW_CONTROL 0x5c8d -#define CAR_mmAUX_ARB_CONTROL 0x5c02 -#define CAR_mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 -#define CAR_mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e -#define CAR_mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a -#define CAR_mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 -#define CAR_mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 -#define CAR_mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e -#define CAR_mmAUX_INTERRUPT_CONTROL 0x5c03 -#define CAR_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 -#define CAR_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f -#define CAR_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b -#define CAR_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 -#define CAR_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 -#define CAR_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f -#define CAR_mmAUX_SW_STATUS 0x5c04 -#define CAR_mmDP_AUX0_AUX_SW_STATUS 0x5c04 -#define CAR_mmDP_AUX1_AUX_SW_STATUS 0x5c20 -#define CAR_mmDP_AUX2_AUX_SW_STATUS 0x5c3c -#define CAR_mmDP_AUX3_AUX_SW_STATUS 0x5c58 -#define CAR_mmDP_AUX4_AUX_SW_STATUS 0x5c74 -#define CAR_mmDP_AUX5_AUX_SW_STATUS 0x5c90 -#define CAR_mmAUX_LS_STATUS 0x5c05 -#define CAR_mmDP_AUX0_AUX_LS_STATUS 0x5c05 -#define CAR_mmDP_AUX1_AUX_LS_STATUS 0x5c21 -#define CAR_mmDP_AUX2_AUX_LS_STATUS 0x5c3d -#define CAR_mmDP_AUX3_AUX_LS_STATUS 0x5c59 -#define CAR_mmDP_AUX4_AUX_LS_STATUS 0x5c75 -#define CAR_mmDP_AUX5_AUX_LS_STATUS 0x5c91 -#define CAR_mmAUX_SW_DATA 0x5c06 -#define CAR_mmDP_AUX0_AUX_SW_DATA 0x5c06 -#define CAR_mmDP_AUX1_AUX_SW_DATA 0x5c22 -#define CAR_mmDP_AUX2_AUX_SW_DATA 0x5c3e -#define CAR_mmDP_AUX3_AUX_SW_DATA 0x5c5a -#define CAR_mmDP_AUX4_AUX_SW_DATA 0x5c76 -#define CAR_mmDP_AUX5_AUX_SW_DATA 0x5c92 -#define CAR_mmAUX_LS_DATA 0x5c07 -#define CAR_mmDP_AUX0_AUX_LS_DATA 0x5c07 -#define CAR_mmDP_AUX1_AUX_LS_DATA 0x5c23 -#define CAR_mmDP_AUX2_AUX_LS_DATA 0x5c3f -#define CAR_mmDP_AUX3_AUX_LS_DATA 0x5c5b -#define CAR_mmDP_AUX4_AUX_LS_DATA 0x5c77 -#define CAR_mmDP_AUX5_AUX_LS_DATA 0x5c93 -#define CAR_mmAUX_DPHY_TX_REF_CONTROL 0x5c08 -#define CAR_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 -#define CAR_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 -#define CAR_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 -#define CAR_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c -#define CAR_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 -#define CAR_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 -#define CAR_mmAUX_DPHY_TX_CONTROL 0x5c09 -#define CAR_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 -#define CAR_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 -#define CAR_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 -#define CAR_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d -#define CAR_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 -#define CAR_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 -#define CAR_mmAUX_DPHY_RX_CONTROL0 0x5c0a -#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a -#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 -#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 -#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e -#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a -#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 -#define CAR_mmAUX_DPHY_RX_CONTROL1 0x5c0b -#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b -#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 -#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 -#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f -#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b -#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 -#define CAR_mmAUX_DPHY_TX_STATUS 0x5c0c -#define CAR_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c -#define CAR_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 -#define CAR_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 -#define CAR_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 -#define CAR_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c -#define CAR_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 -#define CAR_mmAUX_DPHY_RX_STATUS 0x5c0d -#define CAR_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d -#define CAR_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 -#define CAR_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 -#define CAR_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 -#define CAR_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d -#define CAR_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 -#define CAR_mmAUX_GTC_SYNC_CONTROL 0x5c0e -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a -#define CAR_mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b -#define CAR_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c -#define CAR_mmAUX_GTC_SYNC_STATUS 0x5c11 -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d -#define CAR_mmAUX_GTC_SYNC_DATA 0x5c12 -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e -#define CAR_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 -#define CAR_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 -#define CAR_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f -#define CAR_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b -#define CAR_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 -#define CAR_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 -#define CAR_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f -#define CAR_mmAUX_TEST_DEBUG_INDEX 0x5c14 -#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 -#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 -#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c -#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 -#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 -#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 -#define CAR_mmAUX_TEST_DEBUG_DATA 0x5c15 -#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 -#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 -#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d -#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 -#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 -#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 -#define CAR_ixDP_AUX_DEBUG_A 0x10 -#define CAR_ixDP_AUX_DEBUG_B 0x11 -#define CAR_ixDP_AUX_DEBUG_C 0x12 -#define CAR_ixDP_AUX_DEBUG_D 0x13 -#define CAR_ixDP_AUX_DEBUG_E 0x14 -#define CAR_ixDP_AUX_DEBUG_F 0x15 -#define CAR_ixDP_AUX_DEBUG_G 0x16 -#define CAR_ixDP_AUX_DEBUG_H 0x17 -#define CAR_ixDP_AUX_DEBUG_I 0x18 -#define CAR_ixDP_AUX_DEBUG_J 0x19 -#define CAR_ixDP_AUX_DEBUG_K 0x1a -#define CAR_ixDP_AUX_DEBUG_L 0x1b -#define CAR_ixDP_AUX_DEBUG_M 0x1c -#define CAR_ixDP_AUX_DEBUG_N 0x1d -#define CAR_ixDP_AUX_DEBUG_O 0x1e -#define CAR_ixDP_AUX_DEBUG_P 0x1f -#define CAR_ixDP_AUX_DEBUG_Q 0x20 -#define CAR_mmDVO_ENABLE 0x16a0 -#define CAR_mmDVO_SOURCE_SELECT 0x16a1 -#define CAR_mmDVO_OUTPUT 0x16a2 -#define CAR_mmDVO_CONTROL 0x16a3 -#define CAR_mmDVO_CRC_EN 0x16a4 -#define CAR_mmDVO_CRC2_SIG_MASK 0x16a5 -#define CAR_mmDVO_CRC2_SIG_RESULT 0x16a6 -#define CAR_mmDVO_FIFO_ERROR_STATUS 0x16a7 -#define CAR_mmDVO_TEST_DEBUG_INDEX 0x16a8 -#define CAR_mmDVO_TEST_DEBUG_DATA 0x16a9 -#define CAR_mmFBC_CNTL 0x280 -#define CAR_mmFBC_IDLE_MASK 0x281 -#define CAR_mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 -#define CAR_mmFBC_START_STOP_DELAY 0x283 -#define CAR_mmFBC_COMP_CNTL 0x284 -#define CAR_mmFBC_COMP_MODE 0x285 -#define CAR_mmFBC_DEBUG0 0x286 -#define CAR_mmFBC_DEBUG1 0x287 -#define CAR_mmFBC_DEBUG2 0x288 -#define CAR_mmFBC_IND_LUT0 0x289 -#define CAR_mmFBC_IND_LUT1 0x28a -#define CAR_mmFBC_IND_LUT2 0x28b -#define CAR_mmFBC_IND_LUT3 0x28c -#define CAR_mmFBC_IND_LUT4 0x28d -#define CAR_mmFBC_IND_LUT5 0x28e -#define CAR_mmFBC_IND_LUT6 0x28f -#define CAR_mmFBC_IND_LUT7 0x290 -#define CAR_mmFBC_IND_LUT8 0x291 -#define CAR_mmFBC_IND_LUT9 0x292 -#define CAR_mmFBC_IND_LUT10 0x293 -#define CAR_mmFBC_IND_LUT11 0x294 -#define CAR_mmFBC_IND_LUT12 0x295 -#define CAR_mmFBC_IND_LUT13 0x296 -#define CAR_mmFBC_IND_LUT14 0x297 -#define CAR_mmFBC_IND_LUT15 0x298 -#define CAR_mmFBC_CSM_REGION_OFFSET_01 0x299 -#define CAR_mmFBC_CSM_REGION_OFFSET_23 0x29a -#define CAR_mmFBC_CLIENT_REGION_MASK 0x29b -#define CAR_mmFBC_DEBUG_COMP 0x29c -#define CAR_mmFBC_DEBUG_CSR 0x29d -#define CAR_mmFBC_DEBUG_CSR_RDATA 0x29e -#define CAR_mmFBC_DEBUG_CSR_WDATA 0x29f -#define CAR_mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 -#define CAR_mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 -#define CAR_mmFBC_MISC 0x2a2 -#define CAR_mmFBC_STATUS 0x2a3 -#define CAR_mmFBC_TEST_DEBUG_INDEX 0x2a4 -#define CAR_mmFBC_TEST_DEBUG_DATA 0x2a5 -#define CAR_mmFMT_CLAMP_COMPONENT_R 0x1be8 -#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 -#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 -#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 -#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 -#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 -#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 -#define CAR_mmFMT_CLAMP_COMPONENT_G 0x1be9 -#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 -#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 -#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 -#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 -#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 -#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 -#define CAR_mmFMT_CLAMP_COMPONENT_B 0x1bea -#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea -#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea -#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea -#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea -#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea -#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea -#define CAR_mmFMT_DYNAMIC_EXP_CNTL 0x1bed -#define CAR_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed -#define CAR_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded -#define CAR_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed -#define CAR_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed -#define CAR_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed -#define CAR_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed -#define CAR_mmFMT_CONTROL 0x1bee -#define CAR_mmFMT0_FMT_CONTROL 0x1bee -#define CAR_mmFMT1_FMT_CONTROL 0x1dee -#define CAR_mmFMT2_FMT_CONTROL 0x1fee -#define CAR_mmFMT3_FMT_CONTROL 0x41ee -#define CAR_mmFMT4_FMT_CONTROL 0x43ee -#define CAR_mmFMT5_FMT_CONTROL 0x45ee -#define CAR_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 -#define CAR_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 -#define CAR_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 -#define CAR_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 -#define CAR_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 -#define CAR_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 -#define CAR_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 -#define CAR_mmFMT_DITHER_RAND_R_SEED 0x1bf3 -#define CAR_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 -#define CAR_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 -#define CAR_mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 -#define CAR_mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 -#define CAR_mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 -#define CAR_mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 -#define CAR_mmFMT_DITHER_RAND_G_SEED 0x1bf4 -#define CAR_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 -#define CAR_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 -#define CAR_mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 -#define CAR_mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 -#define CAR_mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 -#define CAR_mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 -#define CAR_mmFMT_DITHER_RAND_B_SEED 0x1bf5 -#define CAR_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 -#define CAR_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 -#define CAR_mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 -#define CAR_mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 -#define CAR_mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 -#define CAR_mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 -#define CAR_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 -#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 -#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 -#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 -#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 -#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 -#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 -#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 -#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 -#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 -#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 -#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 -#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 -#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 -#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 -#define CAR_mmFMT_CLAMP_CNTL 0x1bf9 -#define CAR_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 -#define CAR_mmFMT1_FMT_CLAMP_CNTL 0x1df9 -#define CAR_mmFMT2_FMT_CLAMP_CNTL 0x1ff9 -#define CAR_mmFMT3_FMT_CLAMP_CNTL 0x41f9 -#define CAR_mmFMT4_FMT_CLAMP_CNTL 0x43f9 -#define CAR_mmFMT5_FMT_CLAMP_CNTL 0x45f9 -#define CAR_mmFMT_CRC_CNTL 0x1bfa -#define CAR_mmFMT0_FMT_CRC_CNTL 0x1bfa -#define CAR_mmFMT1_FMT_CRC_CNTL 0x1dfa -#define CAR_mmFMT2_FMT_CRC_CNTL 0x1ffa -#define CAR_mmFMT3_FMT_CRC_CNTL 0x41fa -#define CAR_mmFMT4_FMT_CRC_CNTL 0x43fa -#define CAR_mmFMT5_FMT_CRC_CNTL 0x45fa -#define CAR_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb -#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb -#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb -#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb -#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb -#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc -#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc -#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc -#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc -#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc -#define CAR_mmFMT_CRC_SIG_RED_GREEN 0x1bfd -#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd -#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd -#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd -#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd -#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd -#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd -#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe -#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe -#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe -#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe -#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe -#define CAR_mmFMT_DEBUG_CNTL 0x1bff -#define CAR_mmFMT0_FMT_DEBUG_CNTL 0x1bff -#define CAR_mmFMT1_FMT_DEBUG_CNTL 0x1dff -#define CAR_mmFMT2_FMT_DEBUG_CNTL 0x1fff -#define CAR_mmFMT3_FMT_DEBUG_CNTL 0x41ff -#define CAR_mmFMT4_FMT_DEBUG_CNTL 0x43ff -#define CAR_mmFMT5_FMT_DEBUG_CNTL 0x45ff -#define CAR_mmFMT_TEST_DEBUG_INDEX 0x1beb -#define CAR_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb -#define CAR_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb -#define CAR_mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb -#define CAR_mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb -#define CAR_mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb -#define CAR_mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb -#define CAR_mmFMT_TEST_DEBUG_DATA 0x1bec -#define CAR_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec -#define CAR_mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec -#define CAR_mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec -#define CAR_mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec -#define CAR_mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec -#define CAR_mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec -#define CAR_ixFMT_DEBUG0 0x1 -#define CAR_ixFMT_DEBUG1 0x2 -#define CAR_ixFMT_DEBUG2 0x3 -#define CAR_ixFMT_DEBUG_ID 0x0 -#define CAR_mmLB_DATA_FORMAT 0x1ac0 -#define CAR_mmLB0_LB_DATA_FORMAT 0x1ac0 -#define CAR_mmLB1_LB_DATA_FORMAT 0x1cc0 -#define CAR_mmLB2_LB_DATA_FORMAT 0x1ec0 -#define CAR_mmLB3_LB_DATA_FORMAT 0x40c0 -#define CAR_mmLB4_LB_DATA_FORMAT 0x42c0 -#define CAR_mmLB5_LB_DATA_FORMAT 0x44c0 -#define CAR_mmLB_MEMORY_CTRL 0x1ac1 -#define CAR_mmLB0_LB_MEMORY_CTRL 0x1ac1 -#define CAR_mmLB1_LB_MEMORY_CTRL 0x1cc1 -#define CAR_mmLB2_LB_MEMORY_CTRL 0x1ec1 -#define CAR_mmLB3_LB_MEMORY_CTRL 0x40c1 -#define CAR_mmLB4_LB_MEMORY_CTRL 0x42c1 -#define CAR_mmLB5_LB_MEMORY_CTRL 0x44c1 -#define CAR_mmLB_MEMORY_SIZE_STATUS 0x1ac2 -#define CAR_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 -#define CAR_mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 -#define CAR_mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 -#define CAR_mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 -#define CAR_mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 -#define CAR_mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 -#define CAR_mmLB_DESKTOP_HEIGHT 0x1ac3 -#define CAR_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 -#define CAR_mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 -#define CAR_mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 -#define CAR_mmLB3_LB_DESKTOP_HEIGHT 0x40c3 -#define CAR_mmLB4_LB_DESKTOP_HEIGHT 0x42c3 -#define CAR_mmLB5_LB_DESKTOP_HEIGHT 0x44c3 -#define CAR_mmLB_VLINE_START_END 0x1ac4 -#define CAR_mmLB0_LB_VLINE_START_END 0x1ac4 -#define CAR_mmLB1_LB_VLINE_START_END 0x1cc4 -#define CAR_mmLB2_LB_VLINE_START_END 0x1ec4 -#define CAR_mmLB3_LB_VLINE_START_END 0x40c4 -#define CAR_mmLB4_LB_VLINE_START_END 0x42c4 -#define CAR_mmLB5_LB_VLINE_START_END 0x44c4 -#define CAR_mmLB_VLINE2_START_END 0x1ac5 -#define CAR_mmLB0_LB_VLINE2_START_END 0x1ac5 -#define CAR_mmLB1_LB_VLINE2_START_END 0x1cc5 -#define CAR_mmLB2_LB_VLINE2_START_END 0x1ec5 -#define CAR_mmLB3_LB_VLINE2_START_END 0x40c5 -#define CAR_mmLB4_LB_VLINE2_START_END 0x42c5 -#define CAR_mmLB5_LB_VLINE2_START_END 0x44c5 -#define CAR_mmLB_V_COUNTER 0x1ac6 -#define CAR_mmLB0_LB_V_COUNTER 0x1ac6 -#define CAR_mmLB1_LB_V_COUNTER 0x1cc6 -#define CAR_mmLB2_LB_V_COUNTER 0x1ec6 -#define CAR_mmLB3_LB_V_COUNTER 0x40c6 -#define CAR_mmLB4_LB_V_COUNTER 0x42c6 -#define CAR_mmLB5_LB_V_COUNTER 0x44c6 -#define CAR_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 -#define CAR_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 -#define CAR_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 -#define CAR_mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 -#define CAR_mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 -#define CAR_mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 -#define CAR_mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 -#define CAR_mmLB_INTERRUPT_MASK 0x1ac8 -#define CAR_mmLB0_LB_INTERRUPT_MASK 0x1ac8 -#define CAR_mmLB1_LB_INTERRUPT_MASK 0x1cc8 -#define CAR_mmLB2_LB_INTERRUPT_MASK 0x1ec8 -#define CAR_mmLB3_LB_INTERRUPT_MASK 0x40c8 -#define CAR_mmLB4_LB_INTERRUPT_MASK 0x42c8 -#define CAR_mmLB5_LB_INTERRUPT_MASK 0x44c8 -#define CAR_mmLB_VLINE_STATUS 0x1ac9 -#define CAR_mmLB0_LB_VLINE_STATUS 0x1ac9 -#define CAR_mmLB1_LB_VLINE_STATUS 0x1cc9 -#define CAR_mmLB2_LB_VLINE_STATUS 0x1ec9 -#define CAR_mmLB3_LB_VLINE_STATUS 0x40c9 -#define CAR_mmLB4_LB_VLINE_STATUS 0x42c9 -#define CAR_mmLB5_LB_VLINE_STATUS 0x44c9 -#define CAR_mmLB_VLINE2_STATUS 0x1aca -#define CAR_mmLB0_LB_VLINE2_STATUS 0x1aca -#define CAR_mmLB1_LB_VLINE2_STATUS 0x1cca -#define CAR_mmLB2_LB_VLINE2_STATUS 0x1eca -#define CAR_mmLB3_LB_VLINE2_STATUS 0x40ca -#define CAR_mmLB4_LB_VLINE2_STATUS 0x42ca -#define CAR_mmLB5_LB_VLINE2_STATUS 0x44ca -#define CAR_mmLB_VBLANK_STATUS 0x1acb -#define CAR_mmLB0_LB_VBLANK_STATUS 0x1acb -#define CAR_mmLB1_LB_VBLANK_STATUS 0x1ccb -#define CAR_mmLB2_LB_VBLANK_STATUS 0x1ecb -#define CAR_mmLB3_LB_VBLANK_STATUS 0x40cb -#define CAR_mmLB4_LB_VBLANK_STATUS 0x42cb -#define CAR_mmLB5_LB_VBLANK_STATUS 0x44cb -#define CAR_mmLB_SYNC_RESET_SEL 0x1acc -#define CAR_mmLB0_LB_SYNC_RESET_SEL 0x1acc -#define CAR_mmLB1_LB_SYNC_RESET_SEL 0x1ccc -#define CAR_mmLB2_LB_SYNC_RESET_SEL 0x1ecc -#define CAR_mmLB3_LB_SYNC_RESET_SEL 0x40cc -#define CAR_mmLB4_LB_SYNC_RESET_SEL 0x42cc -#define CAR_mmLB5_LB_SYNC_RESET_SEL 0x44cc -#define CAR_mmLB_BLACK_KEYER_R_CR 0x1acd -#define CAR_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd -#define CAR_mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd -#define CAR_mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd -#define CAR_mmLB3_LB_BLACK_KEYER_R_CR 0x40cd -#define CAR_mmLB4_LB_BLACK_KEYER_R_CR 0x42cd -#define CAR_mmLB5_LB_BLACK_KEYER_R_CR 0x44cd -#define CAR_mmLB_BLACK_KEYER_G_Y 0x1ace -#define CAR_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace -#define CAR_mmLB1_LB_BLACK_KEYER_G_Y 0x1cce -#define CAR_mmLB2_LB_BLACK_KEYER_G_Y 0x1ece -#define CAR_mmLB3_LB_BLACK_KEYER_G_Y 0x40ce -#define CAR_mmLB4_LB_BLACK_KEYER_G_Y 0x42ce -#define CAR_mmLB5_LB_BLACK_KEYER_G_Y 0x44ce -#define CAR_mmLB_BLACK_KEYER_B_CB 0x1acf -#define CAR_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf -#define CAR_mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf -#define CAR_mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf -#define CAR_mmLB3_LB_BLACK_KEYER_B_CB 0x40cf -#define CAR_mmLB4_LB_BLACK_KEYER_B_CB 0x42cf -#define CAR_mmLB5_LB_BLACK_KEYER_B_CB 0x44cf -#define CAR_mmLB_KEYER_COLOR_CTRL 0x1ad0 -#define CAR_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 -#define CAR_mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 -#define CAR_mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 -#define CAR_mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 -#define CAR_mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 -#define CAR_mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 -#define CAR_mmLB_KEYER_COLOR_R_CR 0x1ad1 -#define CAR_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 -#define CAR_mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 -#define CAR_mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 -#define CAR_mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 -#define CAR_mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 -#define CAR_mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 -#define CAR_mmLB_KEYER_COLOR_G_Y 0x1ad2 -#define CAR_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 -#define CAR_mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 -#define CAR_mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 -#define CAR_mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 -#define CAR_mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 -#define CAR_mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 -#define CAR_mmLB_KEYER_COLOR_B_CB 0x1ad3 -#define CAR_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 -#define CAR_mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 -#define CAR_mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 -#define CAR_mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 -#define CAR_mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 -#define CAR_mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 -#define CAR_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define CAR_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define CAR_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 -#define CAR_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 -#define CAR_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 -#define CAR_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 -#define CAR_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 -#define CAR_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define CAR_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define CAR_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 -#define CAR_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 -#define CAR_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 -#define CAR_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 -#define CAR_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 -#define CAR_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define CAR_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define CAR_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 -#define CAR_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 -#define CAR_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 -#define CAR_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 -#define CAR_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 -#define CAR_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 -#define CAR_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 -#define CAR_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 -#define CAR_mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 -#define CAR_mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 -#define CAR_mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 -#define CAR_mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 -#define CAR_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 -#define CAR_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 -#define CAR_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 -#define CAR_mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 -#define CAR_mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 -#define CAR_mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 -#define CAR_mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 -#define CAR_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 -#define CAR_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 -#define CAR_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 -#define CAR_mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 -#define CAR_mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 -#define CAR_mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 -#define CAR_mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 -#define CAR_mmLB_BUFFER_STATUS 0x1ada -#define CAR_mmLB0_LB_BUFFER_STATUS 0x1ada -#define CAR_mmLB1_LB_BUFFER_STATUS 0x1cda -#define CAR_mmLB2_LB_BUFFER_STATUS 0x1eda -#define CAR_mmLB3_LB_BUFFER_STATUS 0x40da -#define CAR_mmLB4_LB_BUFFER_STATUS 0x42da -#define CAR_mmLB5_LB_BUFFER_STATUS 0x44da -#define CAR_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define CAR_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define CAR_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc -#define CAR_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc -#define CAR_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc -#define CAR_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc -#define CAR_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc -#define CAR_mmMVP_AFR_FLIP_MODE 0x1ae0 -#define CAR_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 -#define CAR_mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 -#define CAR_mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 -#define CAR_mmLB3_MVP_AFR_FLIP_MODE 0x40e0 -#define CAR_mmLB4_MVP_AFR_FLIP_MODE 0x42e0 -#define CAR_mmLB5_MVP_AFR_FLIP_MODE 0x44e0 -#define CAR_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define CAR_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define CAR_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 -#define CAR_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 -#define CAR_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 -#define CAR_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 -#define CAR_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 -#define CAR_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define CAR_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define CAR_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 -#define CAR_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 -#define CAR_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 -#define CAR_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 -#define CAR_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 -#define CAR_mmDC_MVP_LB_CONTROL 0x1ae3 -#define CAR_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 -#define CAR_mmLB1_DC_MVP_LB_CONTROL 0x1ce3 -#define CAR_mmLB2_DC_MVP_LB_CONTROL 0x1ee3 -#define CAR_mmLB3_DC_MVP_LB_CONTROL 0x40e3 -#define CAR_mmLB4_DC_MVP_LB_CONTROL 0x42e3 -#define CAR_mmLB5_DC_MVP_LB_CONTROL 0x44e3 -#define CAR_mmLB_DEBUG 0x1ae4 -#define CAR_mmLB0_LB_DEBUG 0x1ae4 -#define CAR_mmLB1_LB_DEBUG 0x1ce4 -#define CAR_mmLB2_LB_DEBUG 0x1ee4 -#define CAR_mmLB3_LB_DEBUG 0x40e4 -#define CAR_mmLB4_LB_DEBUG 0x42e4 -#define CAR_mmLB5_LB_DEBUG 0x44e4 -#define CAR_mmLB_DEBUG2 0x1ae5 -#define CAR_mmLB0_LB_DEBUG2 0x1ae5 -#define CAR_mmLB1_LB_DEBUG2 0x1ce5 -#define CAR_mmLB2_LB_DEBUG2 0x1ee5 -#define CAR_mmLB3_LB_DEBUG2 0x40e5 -#define CAR_mmLB4_LB_DEBUG2 0x42e5 -#define CAR_mmLB5_LB_DEBUG2 0x44e5 -#define CAR_mmLB_DEBUG3 0x1ae6 -#define CAR_mmLB0_LB_DEBUG3 0x1ae6 -#define CAR_mmLB1_LB_DEBUG3 0x1ce6 -#define CAR_mmLB2_LB_DEBUG3 0x1ee6 -#define CAR_mmLB3_LB_DEBUG3 0x40e6 -#define CAR_mmLB4_LB_DEBUG3 0x42e6 -#define CAR_mmLB5_LB_DEBUG3 0x44e6 -#define CAR_mmLB_TEST_DEBUG_INDEX 0x1afe -#define CAR_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe -#define CAR_mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe -#define CAR_mmLB2_LB_TEST_DEBUG_INDEX 0x1efe -#define CAR_mmLB3_LB_TEST_DEBUG_INDEX 0x40fe -#define CAR_mmLB4_LB_TEST_DEBUG_INDEX 0x42fe -#define CAR_mmLB5_LB_TEST_DEBUG_INDEX 0x44fe -#define CAR_mmLB_TEST_DEBUG_DATA 0x1aff -#define CAR_mmLB0_LB_TEST_DEBUG_DATA 0x1aff -#define CAR_mmLB1_LB_TEST_DEBUG_DATA 0x1cff -#define CAR_mmLB2_LB_TEST_DEBUG_DATA 0x1eff -#define CAR_mmLB3_LB_TEST_DEBUG_DATA 0x40ff -#define CAR_mmLB4_LB_TEST_DEBUG_DATA 0x42ff -#define CAR_mmLB5_LB_TEST_DEBUG_DATA 0x44ff -#define CAR_mmLBV_DATA_FORMAT 0x463c -#define CAR_mmLBV_MEMORY_CTRL 0x463d -#define CAR_mmLBV_MEMORY_SIZE_STATUS 0x463e -#define CAR_mmLBV_DESKTOP_HEIGHT 0x463f -#define CAR_mmLBV_VLINE_START_END 0x4640 -#define CAR_mmLBV_VLINE2_START_END 0x4641 -#define CAR_mmLBV_V_COUNTER 0x4642 -#define CAR_mmLBV_SNAPSHOT_V_COUNTER 0x4643 -#define CAR_mmLBV_V_COUNTER_CHROMA 0x4644 -#define CAR_mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 -#define CAR_mmLBV_INTERRUPT_MASK 0x4646 -#define CAR_mmLBV_VLINE_STATUS 0x4647 -#define CAR_mmLBV_VLINE2_STATUS 0x4648 -#define CAR_mmLBV_VBLANK_STATUS 0x4649 -#define CAR_mmLBV_SYNC_RESET_SEL 0x464a -#define CAR_mmLBV_BLACK_KEYER_R_CR 0x464b -#define CAR_mmLBV_BLACK_KEYER_G_Y 0x464c -#define CAR_mmLBV_BLACK_KEYER_B_CB 0x464d -#define CAR_mmLBV_KEYER_COLOR_CTRL 0x464e -#define CAR_mmLBV_KEYER_COLOR_R_CR 0x464f -#define CAR_mmLBV_KEYER_COLOR_G_Y 0x4650 -#define CAR_mmLBV_KEYER_COLOR_B_CB 0x4651 -#define CAR_mmLBV_KEYER_COLOR_REP_R_CR 0x4652 -#define CAR_mmLBV_KEYER_COLOR_REP_G_Y 0x4653 -#define CAR_mmLBV_KEYER_COLOR_REP_B_CB 0x4654 -#define CAR_mmLBV_BUFFER_LEVEL_STATUS 0x4655 -#define CAR_mmLBV_BUFFER_URGENCY_CTRL 0x4656 -#define CAR_mmLBV_BUFFER_URGENCY_STATUS 0x4657 -#define CAR_mmLBV_BUFFER_STATUS 0x4658 -#define CAR_mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 -#define CAR_mmLBV_DEBUG 0x465a -#define CAR_mmLBV_DEBUG2 0x465b -#define CAR_mmLBV_DEBUG3 0x465c -#define CAR_mmLBV_TEST_DEBUG_INDEX 0x4666 -#define CAR_mmLBV_TEST_DEBUG_DATA 0x4667 -#define CAR_mmMVP_CONTROL1 0x2ac -#define CAR_mmMVP_CONTROL2 0x2ad -#define CAR_mmMVP_FIFO_CONTROL 0x2ae -#define CAR_mmMVP_FIFO_STATUS 0x2af -#define CAR_mmMVP_SLAVE_STATUS 0x2b0 -#define CAR_mmMVP_INBAND_CNTL_CAP 0x2b1 -#define CAR_mmMVP_BLACK_KEYER 0x2b2 -#define CAR_mmMVP_CRC_CNTL 0x2b3 -#define CAR_mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 -#define CAR_mmMVP_CRC_RESULT_RED 0x2b5 -#define CAR_mmMVP_CONTROL3 0x2b6 -#define CAR_mmMVP_RECEIVE_CNT_CNTL1 0x2b7 -#define CAR_mmMVP_RECEIVE_CNT_CNTL2 0x2b8 -#define CAR_mmMVP_DEBUG 0x2bb -#define CAR_mmMVP_TEST_DEBUG_INDEX 0x2b9 -#define CAR_mmMVP_TEST_DEBUG_DATA 0x2ba -#define CAR_ixMVP_DEBUG_12 0xc -#define CAR_ixMVP_DEBUG_13 0xd -#define CAR_ixMVP_DEBUG_14 0xe -#define CAR_ixMVP_DEBUG_15 0xf -#define CAR_ixMVP_DEBUG_16 0x10 -#define CAR_ixMVP_DEBUG_17 0x11 -#define CAR_mmSCL_COEF_RAM_SELECT 0x1b40 -#define CAR_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 -#define CAR_mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 -#define CAR_mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 -#define CAR_mmSCL3_SCL_COEF_RAM_SELECT 0x4140 -#define CAR_mmSCL4_SCL_COEF_RAM_SELECT 0x4340 -#define CAR_mmSCL5_SCL_COEF_RAM_SELECT 0x4540 -#define CAR_mmSCL_COEF_RAM_TAP_DATA 0x1b41 -#define CAR_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 -#define CAR_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 -#define CAR_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 -#define CAR_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 -#define CAR_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 -#define CAR_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 -#define CAR_mmSCL_MODE 0x1b42 -#define CAR_mmSCL0_SCL_MODE 0x1b42 -#define CAR_mmSCL1_SCL_MODE 0x1d42 -#define CAR_mmSCL2_SCL_MODE 0x1f42 -#define CAR_mmSCL3_SCL_MODE 0x4142 -#define CAR_mmSCL4_SCL_MODE 0x4342 -#define CAR_mmSCL5_SCL_MODE 0x4542 -#define CAR_mmSCL_TAP_CONTROL 0x1b43 -#define CAR_mmSCL0_SCL_TAP_CONTROL 0x1b43 -#define CAR_mmSCL1_SCL_TAP_CONTROL 0x1d43 -#define CAR_mmSCL2_SCL_TAP_CONTROL 0x1f43 -#define CAR_mmSCL3_SCL_TAP_CONTROL 0x4143 -#define CAR_mmSCL4_SCL_TAP_CONTROL 0x4343 -#define CAR_mmSCL5_SCL_TAP_CONTROL 0x4543 -#define CAR_mmSCL_CONTROL 0x1b44 -#define CAR_mmSCL0_SCL_CONTROL 0x1b44 -#define CAR_mmSCL1_SCL_CONTROL 0x1d44 -#define CAR_mmSCL2_SCL_CONTROL 0x1f44 -#define CAR_mmSCL3_SCL_CONTROL 0x4144 -#define CAR_mmSCL4_SCL_CONTROL 0x4344 -#define CAR_mmSCL5_SCL_CONTROL 0x4544 -#define CAR_mmSCL_BYPASS_CONTROL 0x1b45 -#define CAR_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 -#define CAR_mmSCL1_SCL_BYPASS_CONTROL 0x1d45 -#define CAR_mmSCL2_SCL_BYPASS_CONTROL 0x1f45 -#define CAR_mmSCL3_SCL_BYPASS_CONTROL 0x4145 -#define CAR_mmSCL4_SCL_BYPASS_CONTROL 0x4345 -#define CAR_mmSCL5_SCL_BYPASS_CONTROL 0x4545 -#define CAR_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define CAR_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define CAR_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 -#define CAR_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 -#define CAR_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 -#define CAR_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 -#define CAR_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 -#define CAR_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define CAR_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define CAR_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 -#define CAR_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 -#define CAR_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 -#define CAR_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 -#define CAR_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 -#define CAR_mmSCL_HORZ_FILTER_CONTROL 0x1b48 -#define CAR_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 -#define CAR_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 -#define CAR_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 -#define CAR_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 -#define CAR_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 -#define CAR_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 -#define CAR_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define CAR_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define CAR_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 -#define CAR_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 -#define CAR_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 -#define CAR_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 -#define CAR_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 -#define CAR_mmSCL_HORZ_FILTER_INIT 0x1b4a -#define CAR_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a -#define CAR_mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a -#define CAR_mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a -#define CAR_mmSCL3_SCL_HORZ_FILTER_INIT 0x414a -#define CAR_mmSCL4_SCL_HORZ_FILTER_INIT 0x434a -#define CAR_mmSCL5_SCL_HORZ_FILTER_INIT 0x454a -#define CAR_mmSCL_VERT_FILTER_CONTROL 0x1b4b -#define CAR_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b -#define CAR_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b -#define CAR_mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b -#define CAR_mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b -#define CAR_mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b -#define CAR_mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b -#define CAR_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define CAR_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define CAR_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c -#define CAR_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c -#define CAR_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c -#define CAR_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c -#define CAR_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c -#define CAR_mmSCL_VERT_FILTER_INIT 0x1b4d -#define CAR_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d -#define CAR_mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d -#define CAR_mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d -#define CAR_mmSCL3_SCL_VERT_FILTER_INIT 0x414d -#define CAR_mmSCL4_SCL_VERT_FILTER_INIT 0x434d -#define CAR_mmSCL5_SCL_VERT_FILTER_INIT 0x454d -#define CAR_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e -#define CAR_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e -#define CAR_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e -#define CAR_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e -#define CAR_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e -#define CAR_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e -#define CAR_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e -#define CAR_mmSCL_ROUND_OFFSET 0x1b4f -#define CAR_mmSCL0_SCL_ROUND_OFFSET 0x1b4f -#define CAR_mmSCL1_SCL_ROUND_OFFSET 0x1d4f -#define CAR_mmSCL2_SCL_ROUND_OFFSET 0x1f4f -#define CAR_mmSCL3_SCL_ROUND_OFFSET 0x414f -#define CAR_mmSCL4_SCL_ROUND_OFFSET 0x434f -#define CAR_mmSCL5_SCL_ROUND_OFFSET 0x454f -#define CAR_mmSCL_UPDATE 0x1b51 -#define CAR_mmSCL0_SCL_UPDATE 0x1b51 -#define CAR_mmSCL1_SCL_UPDATE 0x1d51 -#define CAR_mmSCL2_SCL_UPDATE 0x1f51 -#define CAR_mmSCL3_SCL_UPDATE 0x4151 -#define CAR_mmSCL4_SCL_UPDATE 0x4351 -#define CAR_mmSCL5_SCL_UPDATE 0x4551 -#define CAR_mmSCL_F_SHARP_CONTROL 0x1b53 -#define CAR_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 -#define CAR_mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 -#define CAR_mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 -#define CAR_mmSCL3_SCL_F_SHARP_CONTROL 0x4153 -#define CAR_mmSCL4_SCL_F_SHARP_CONTROL 0x4353 -#define CAR_mmSCL5_SCL_F_SHARP_CONTROL 0x4553 -#define CAR_mmSCL_ALU_CONTROL 0x1b54 -#define CAR_mmSCL0_SCL_ALU_CONTROL 0x1b54 -#define CAR_mmSCL1_SCL_ALU_CONTROL 0x1d54 -#define CAR_mmSCL2_SCL_ALU_CONTROL 0x1f54 -#define CAR_mmSCL3_SCL_ALU_CONTROL 0x4154 -#define CAR_mmSCL4_SCL_ALU_CONTROL 0x4354 -#define CAR_mmSCL5_SCL_ALU_CONTROL 0x4554 -#define CAR_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define CAR_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define CAR_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 -#define CAR_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 -#define CAR_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 -#define CAR_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 -#define CAR_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 -#define CAR_mmVIEWPORT_START_SECONDARY 0x1b5b -#define CAR_mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b -#define CAR_mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b -#define CAR_mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b -#define CAR_mmSCL3_VIEWPORT_START_SECONDARY 0x415b -#define CAR_mmSCL4_VIEWPORT_START_SECONDARY 0x435b -#define CAR_mmSCL5_VIEWPORT_START_SECONDARY 0x455b -#define CAR_mmVIEWPORT_START 0x1b5c -#define CAR_mmSCL0_VIEWPORT_START 0x1b5c -#define CAR_mmSCL1_VIEWPORT_START 0x1d5c -#define CAR_mmSCL2_VIEWPORT_START 0x1f5c -#define CAR_mmSCL3_VIEWPORT_START 0x415c -#define CAR_mmSCL4_VIEWPORT_START 0x435c -#define CAR_mmSCL5_VIEWPORT_START 0x455c -#define CAR_mmVIEWPORT_SIZE 0x1b5d -#define CAR_mmSCL0_VIEWPORT_SIZE 0x1b5d -#define CAR_mmSCL1_VIEWPORT_SIZE 0x1d5d -#define CAR_mmSCL2_VIEWPORT_SIZE 0x1f5d -#define CAR_mmSCL3_VIEWPORT_SIZE 0x415d -#define CAR_mmSCL4_VIEWPORT_SIZE 0x435d -#define CAR_mmSCL5_VIEWPORT_SIZE 0x455d -#define CAR_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define CAR_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define CAR_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e -#define CAR_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e -#define CAR_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e -#define CAR_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e -#define CAR_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e -#define CAR_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define CAR_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define CAR_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f -#define CAR_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f -#define CAR_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f -#define CAR_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f -#define CAR_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f -#define CAR_mmSCL_MODE_CHANGE_DET1 0x1b60 -#define CAR_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 -#define CAR_mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 -#define CAR_mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 -#define CAR_mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 -#define CAR_mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 -#define CAR_mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 -#define CAR_mmSCL_MODE_CHANGE_DET2 0x1b61 -#define CAR_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 -#define CAR_mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 -#define CAR_mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 -#define CAR_mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 -#define CAR_mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 -#define CAR_mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 -#define CAR_mmSCL_MODE_CHANGE_DET3 0x1b62 -#define CAR_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 -#define CAR_mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 -#define CAR_mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 -#define CAR_mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 -#define CAR_mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 -#define CAR_mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 -#define CAR_mmSCL_MODE_CHANGE_MASK 0x1b63 -#define CAR_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 -#define CAR_mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 -#define CAR_mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 -#define CAR_mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 -#define CAR_mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 -#define CAR_mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 -#define CAR_mmSCL_DEBUG2 0x1b69 -#define CAR_mmSCL0_SCL_DEBUG2 0x1b69 -#define CAR_mmSCL1_SCL_DEBUG2 0x1d69 -#define CAR_mmSCL2_SCL_DEBUG2 0x1f69 -#define CAR_mmSCL3_SCL_DEBUG2 0x4169 -#define CAR_mmSCL4_SCL_DEBUG2 0x4369 -#define CAR_mmSCL5_SCL_DEBUG2 0x4569 -#define CAR_mmSCL_DEBUG 0x1b6a -#define CAR_mmSCL0_SCL_DEBUG 0x1b6a -#define CAR_mmSCL1_SCL_DEBUG 0x1d6a -#define CAR_mmSCL2_SCL_DEBUG 0x1f6a -#define CAR_mmSCL3_SCL_DEBUG 0x416a -#define CAR_mmSCL4_SCL_DEBUG 0x436a -#define CAR_mmSCL5_SCL_DEBUG 0x456a -#define CAR_mmSCL_TEST_DEBUG_INDEX 0x1b6b -#define CAR_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b -#define CAR_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b -#define CAR_mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b -#define CAR_mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b -#define CAR_mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b -#define CAR_mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b -#define CAR_mmSCL_TEST_DEBUG_DATA 0x1b6c -#define CAR_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c -#define CAR_mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c -#define CAR_mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c -#define CAR_mmSCL3_SCL_TEST_DEBUG_DATA 0x416c -#define CAR_mmSCL4_SCL_TEST_DEBUG_DATA 0x436c -#define CAR_mmSCL5_SCL_TEST_DEBUG_DATA 0x456c -#define CAR_mmSCLV_COEF_RAM_SELECT 0x4670 -#define CAR_mmSCLV_COEF_RAM_TAP_DATA 0x4671 -#define CAR_mmSCLV_MODE 0x4672 -#define CAR_mmSCLV_TAP_CONTROL 0x4673 -#define CAR_mmSCLV_CONTROL 0x4674 -#define CAR_mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 -#define CAR_mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 -#define CAR_mmSCLV_HORZ_FILTER_CONTROL 0x4677 -#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 -#define CAR_mmSCLV_HORZ_FILTER_INIT 0x4679 -#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a -#define CAR_mmSCLV_HORZ_FILTER_INIT_C 0x467b -#define CAR_mmSCLV_VERT_FILTER_CONTROL 0x467c -#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d -#define CAR_mmSCLV_VERT_FILTER_INIT 0x467e -#define CAR_mmSCLV_VERT_FILTER_INIT_BOT 0x467f -#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 -#define CAR_mmSCLV_VERT_FILTER_INIT_C 0x4681 -#define CAR_mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 -#define CAR_mmSCLV_ROUND_OFFSET 0x4683 -#define CAR_mmSCLV_UPDATE 0x4684 -#define CAR_mmSCLV_ALU_CONTROL 0x4685 -#define CAR_mmSCLV_VIEWPORT_START 0x4686 -#define CAR_mmSCLV_VIEWPORT_START_SECONDARY 0x4687 -#define CAR_mmSCLV_VIEWPORT_SIZE 0x4688 -#define CAR_mmSCLV_VIEWPORT_START_C 0x4689 -#define CAR_mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a -#define CAR_mmSCLV_VIEWPORT_SIZE_C 0x468b -#define CAR_mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c -#define CAR_mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d -#define CAR_mmSCLV_MODE_CHANGE_DET1 0x468e -#define CAR_mmSCLV_MODE_CHANGE_DET2 0x468f -#define CAR_mmSCLV_MODE_CHANGE_DET3 0x4690 -#define CAR_mmSCLV_MODE_CHANGE_MASK 0x4691 -#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 -#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 -#define CAR_mmSCLV_DEBUG2 0x4694 -#define CAR_mmSCLV_DEBUG 0x4695 -#define CAR_mmSCLV_TEST_DEBUG_INDEX 0x4696 -#define CAR_mmSCLV_TEST_DEBUG_DATA 0x4697 -#define CAR_mmCOL_MAN_UPDATE 0x46a4 -#define CAR_mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 -#define CAR_mmINPUT_CSC_C11_C12_A 0x46a6 -#define CAR_mmINPUT_CSC_C13_C14_A 0x46a7 -#define CAR_mmINPUT_CSC_C21_C22_A 0x46a8 -#define CAR_mmINPUT_CSC_C23_C24_A 0x46a9 -#define CAR_mmINPUT_CSC_C31_C32_A 0x46aa -#define CAR_mmINPUT_CSC_C33_C34_A 0x46ab -#define CAR_mmINPUT_CSC_C11_C12_B 0x46ac -#define CAR_mmINPUT_CSC_C13_C14_B 0x46ad -#define CAR_mmINPUT_CSC_C21_C22_B 0x46ae -#define CAR_mmINPUT_CSC_C23_C24_B 0x46af -#define CAR_mmINPUT_CSC_C31_C32_B 0x46b0 -#define CAR_mmINPUT_CSC_C33_C34_B 0x46b1 -#define CAR_mmPRESCALE_CONTROL 0x46b2 -#define CAR_mmPRESCALE_VALUES_R 0x46b3 -#define CAR_mmPRESCALE_VALUES_G 0x46b4 -#define CAR_mmPRESCALE_VALUES_B 0x46b5 -#define CAR_mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 -#define CAR_mmOUTPUT_CSC_C11_C12_A 0x46b7 -#define CAR_mmOUTPUT_CSC_C13_C14_A 0x46b8 -#define CAR_mmOUTPUT_CSC_C21_C22_A 0x46b9 -#define CAR_mmOUTPUT_CSC_C23_C24_A 0x46ba -#define CAR_mmOUTPUT_CSC_C31_C32_A 0x46bb -#define CAR_mmOUTPUT_CSC_C33_C34_A 0x46bc -#define CAR_mmOUTPUT_CSC_C11_C12_B 0x46bd -#define CAR_mmOUTPUT_CSC_C13_C14_B 0x46be -#define CAR_mmOUTPUT_CSC_C21_C22_B 0x46bf -#define CAR_mmOUTPUT_CSC_C23_C24_B 0x46c0 -#define CAR_mmOUTPUT_CSC_C31_C32_B 0x46c1 -#define CAR_mmOUTPUT_CSC_C33_C34_B 0x46c2 -#define CAR_mmDENORM_CLAMP_CONTROL 0x46c3 -#define CAR_mmDENORM_CLAMP_RANGE_R_CR 0x46c4 -#define CAR_mmDENORM_CLAMP_RANGE_G_Y 0x46c5 -#define CAR_mmDENORM_CLAMP_RANGE_B_CB 0x46c6 -#define CAR_mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 -#define CAR_mmGAMMA_CORR_CONTROL 0x46c8 -#define CAR_mmGAMMA_CORR_LUT_INDEX 0x46c9 -#define CAR_mmGAMMA_CORR_LUT_DATA 0x46ca -#define CAR_mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb -#define CAR_mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc -#define CAR_mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd -#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce -#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf -#define CAR_mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 -#define CAR_mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 -#define CAR_mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 -#define CAR_mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 -#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da -#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db -#define CAR_mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc -#define CAR_mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd -#define CAR_mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de -#define CAR_mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df -#define CAR_mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 -#define CAR_mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 -#define CAR_mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 -#define CAR_mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 -#define CAR_mmPACK_FIFO_ERROR 0x46e4 -#define CAR_mmOUTPUT_FIFO_ERROR 0x46e5 -#define CAR_mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 -#define CAR_mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 -#define CAR_mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 -#define CAR_mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 -#define CAR_mmINPUT_GAMMA_LUT_30_COLOR 0x46ea -#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb -#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec -#define CAR_mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed -#define CAR_mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee -#define CAR_mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef -#define CAR_mmCOL_MAN_DEBUG_CONTROL 0x46f0 -#define CAR_mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 -#define CAR_mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 -#define CAR_mmUNP_GRPH_ENABLE 0x4600 -#define CAR_mmUNP_GRPH_CONTROL 0x4601 -#define CAR_mmUNP_GRPH_CONTROL_C 0x4602 -#define CAR_mmUNP_GRPH_CONTROL_EXP 0x4603 -#define CAR_mmUNP_GRPH_SWAP_CNTL 0x4605 -#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 -#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 -#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 -#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 -#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a -#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b -#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c -#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d -#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e -#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f -#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 -#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 -#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 -#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 -#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 -#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 -#define CAR_mmUNP_GRPH_PITCH_L 0x4616 -#define CAR_mmUNP_GRPH_PITCH_C 0x4617 -#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 -#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 -#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a -#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b -#define CAR_mmUNP_GRPH_X_START_L 0x461c -#define CAR_mmUNP_GRPH_X_START_C 0x461d -#define CAR_mmUNP_GRPH_Y_START_L 0x461e -#define CAR_mmUNP_GRPH_Y_START_C 0x461f -#define CAR_mmUNP_GRPH_X_END_L 0x4620 -#define CAR_mmUNP_GRPH_X_END_C 0x4621 -#define CAR_mmUNP_GRPH_Y_END_L 0x4622 -#define CAR_mmUNP_GRPH_Y_END_C 0x4623 -#define CAR_mmUNP_GRPH_UPDATE 0x4624 -#define CAR_mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a -#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 -#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 -#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 -#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 -#define CAR_mmUNP_DVMM_PTE_CONTROL 0x4629 -#define CAR_mmUNP_DVMM_PTE_CONTROL_C 0x4604 -#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL 0x462a -#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d -#define CAR_mmUNP_GRPH_INTERRUPT_STATUS 0x462b -#define CAR_mmUNP_GRPH_INTERRUPT_CONTROL 0x462c -#define CAR_mmUNP_GRPH_STEREOSYNC_FLIP 0x462e -#define CAR_mmUNP_FLIP_CONTROL 0x462f -#define CAR_mmUNP_CRC_CONTROL 0x4630 -#define CAR_mmUNP_CRC_MASK 0x4631 -#define CAR_mmUNP_CRC_CURRENT 0x4632 -#define CAR_mmUNP_CRC_LAST 0x4633 -#define CAR_mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 -#define CAR_mmUNP_HW_ROTATION 0x4635 -#define CAR_mmUNP_DEBUG 0x4636 -#define CAR_mmUNP_DEBUG2 0x4637 -#define CAR_mmUNP_DVMM_DEBUG 0x463b -#define CAR_mmUNP_TEST_DEBUG_INDEX 0x4638 -#define CAR_mmUNP_TEST_DEBUG_DATA 0x4639 -#define CAR_mmGENMO_WT 0xf0 -#define CAR_mmGENMO_RD 0xf3 -#define CAR_mmGENENB 0xf0 -#define CAR_mmGENFC_WT 0xee -#define CAR_mmVGA0_GENFC_WT 0xee -#define CAR_mmVGA1_GENFC_WT 0xf6 -#define CAR_mmGENFC_RD 0xf2 -#define CAR_mmGENS0 0xf0 -#define CAR_mmGENS1 0xee -#define CAR_mmVGA0_GENS1 0xee -#define CAR_mmVGA1_GENS1 0xf6 -#define CAR_mmDAC_DATA 0xf2 -#define CAR_mmDAC_MASK 0xf1 -#define CAR_mmDAC_R_INDEX 0xf1 -#define CAR_mmDAC_W_INDEX 0xf2 -#define CAR_mmSEQ8_IDX 0xf1 -#define CAR_mmSEQ8_DATA 0xf1 -#define CAR_ixSEQ00 0x0 -#define CAR_ixSEQ01 0x1 -#define CAR_ixSEQ02 0x2 -#define CAR_ixSEQ03 0x3 -#define CAR_ixSEQ04 0x4 -#define CAR_mmCRTC8_IDX 0xed -#define CAR_mmVGA0_CRTC8_IDX 0xed -#define CAR_mmVGA1_CRTC8_IDX 0xf5 -#define CAR_mmCRTC8_DATA 0xed -#define CAR_mmVGA0_CRTC8_DATA 0xed -#define CAR_mmVGA1_CRTC8_DATA 0xf5 -#define CAR_ixCRT00 0x0 -#define CAR_ixCRT01 0x1 -#define CAR_ixCRT02 0x2 -#define CAR_ixCRT03 0x3 -#define CAR_ixCRT04 0x4 -#define CAR_ixCRT05 0x5 -#define CAR_ixCRT06 0x6 -#define CAR_ixCRT07 0x7 -#define CAR_ixCRT08 0x8 -#define CAR_ixCRT09 0x9 -#define CAR_ixCRT0A 0xa -#define CAR_ixCRT0B 0xb -#define CAR_ixCRT0C 0xc -#define CAR_ixCRT0D 0xd -#define CAR_ixCRT0E 0xe -#define CAR_ixCRT0F 0xf -#define CAR_ixCRT10 0x10 -#define CAR_ixCRT11 0x11 -#define CAR_ixCRT12 0x12 -#define CAR_ixCRT13 0x13 -#define CAR_ixCRT14 0x14 -#define CAR_ixCRT15 0x15 -#define CAR_ixCRT16 0x16 -#define CAR_ixCRT17 0x17 -#define CAR_ixCRT18 0x18 -#define CAR_ixCRT1E 0x1e -#define CAR_ixCRT1F 0x1f -#define CAR_ixCRT22 0x22 -#define CAR_mmGRPH8_IDX 0xf3 -#define CAR_mmGRPH8_DATA 0xf3 -#define CAR_ixGRA00 0x0 -#define CAR_ixGRA01 0x1 -#define CAR_ixGRA02 0x2 -#define CAR_ixGRA03 0x3 -#define CAR_ixGRA04 0x4 -#define CAR_ixGRA05 0x5 -#define CAR_ixGRA06 0x6 -#define CAR_ixGRA07 0x7 -#define CAR_ixGRA08 0x8 -#define CAR_mmATTRX 0xf0 -#define CAR_mmATTRDW 0xf0 -#define CAR_mmATTRDR 0xf0 -#define CAR_ixATTR00 0x0 -#define CAR_ixATTR01 0x1 -#define CAR_ixATTR02 0x2 -#define CAR_ixATTR03 0x3 -#define CAR_ixATTR04 0x4 -#define CAR_ixATTR05 0x5 -#define CAR_ixATTR06 0x6 -#define CAR_ixATTR07 0x7 -#define CAR_ixATTR08 0x8 -#define CAR_ixATTR09 0x9 -#define CAR_ixATTR0A 0xa -#define CAR_ixATTR0B 0xb -#define CAR_ixATTR0C 0xc -#define CAR_ixATTR0D 0xd -#define CAR_ixATTR0E 0xe -#define CAR_ixATTR0F 0xf -#define CAR_ixATTR10 0x10 -#define CAR_ixATTR11 0x11 -#define CAR_ixATTR12 0x12 -#define CAR_ixATTR13 0x13 -#define CAR_ixATTR14 0x14 -#define CAR_mmVGA_RENDER_CONTROL 0xc0 -#define CAR_mmVGA_SOURCE_SELECT 0xfc -#define CAR_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 -#define CAR_mmVGA_MODE_CONTROL 0xc2 -#define CAR_mmVGA_SURFACE_PITCH_SELECT 0xc3 -#define CAR_mmVGA_MEMORY_BASE_ADDRESS 0xc4 -#define CAR_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 -#define CAR_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 -#define CAR_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 -#define CAR_mmVGA_HDP_CONTROL 0xca -#define CAR_mmVGA_CACHE_CONTROL 0xcb -#define CAR_mmD1VGA_CONTROL 0xcc -#define CAR_mmD2VGA_CONTROL 0xce -#define CAR_mmD3VGA_CONTROL 0xf8 -#define CAR_mmD4VGA_CONTROL 0xf9 -#define CAR_mmD5VGA_CONTROL 0xfa -#define CAR_mmD6VGA_CONTROL 0xfb -#define CAR_mmVGA_HW_DEBUG 0xcf -#define CAR_mmVGA_STATUS 0xd0 -#define CAR_mmVGA_INTERRUPT_CONTROL 0xd1 -#define CAR_mmVGA_STATUS_CLEAR 0xd2 -#define CAR_mmVGA_INTERRUPT_STATUS 0xd3 -#define CAR_mmVGA_MAIN_CONTROL 0xd4 -#define CAR_mmVGA_TEST_CONTROL 0xd5 -#define CAR_mmVGA_DEBUG_READBACK_INDEX 0xd6 -#define CAR_mmVGA_DEBUG_READBACK_DATA 0xd7 -#define CAR_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 -#define CAR_mmVGA_MEM_READ_PAGE_ADDR 0x13 -#define CAR_mmVGA_TEST_DEBUG_INDEX 0xc5 -#define CAR_mmVGA_TEST_DEBUG_DATA 0xc7 -#define CAR_ixVGADCC_DBG_DCCIF_C 0x7e -#define CAR_mmBPHYC_DAC_MACRO_CNTL 0x48b9 -#define CAR_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba -#define CAR_mmPLL_REF_DIV 0x1700 -#define CAR_mmBPHYC_PLL0_PLL_REF_DIV 0x1700 -#define CAR_mmBPHYC_PLL1_PLL_REF_DIV 0x172a -#define CAR_mmBPHYC_PLL2_PLL_REF_DIV 0x1754 -#define CAR_mmPLL_FB_DIV 0x1701 -#define CAR_mmBPHYC_PLL0_PLL_FB_DIV 0x1701 -#define CAR_mmBPHYC_PLL1_PLL_FB_DIV 0x172b -#define CAR_mmBPHYC_PLL2_PLL_FB_DIV 0x1755 -#define CAR_mmPLL_POST_DIV 0x1702 -#define CAR_mmBPHYC_PLL0_PLL_POST_DIV 0x1702 -#define CAR_mmBPHYC_PLL1_PLL_POST_DIV 0x172c -#define CAR_mmBPHYC_PLL2_PLL_POST_DIV 0x1756 -#define CAR_mmPLL_SS_AMOUNT_DSFRAC 0x1703 -#define CAR_mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 -#define CAR_mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d -#define CAR_mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 -#define CAR_mmPLL_SS_CNTL 0x1704 -#define CAR_mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 -#define CAR_mmBPHYC_PLL1_PLL_SS_CNTL 0x172e -#define CAR_mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 -#define CAR_mmPLL_DS_CNTL 0x1705 -#define CAR_mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 -#define CAR_mmBPHYC_PLL1_PLL_DS_CNTL 0x172f -#define CAR_mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 -#define CAR_mmPLL_IDCLK_CNTL 0x1706 -#define CAR_mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 -#define CAR_mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 -#define CAR_mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a -#define CAR_mmPLL_CNTL 0x1707 -#define CAR_mmBPHYC_PLL0_PLL_CNTL 0x1707 -#define CAR_mmBPHYC_PLL1_PLL_CNTL 0x1731 -#define CAR_mmBPHYC_PLL2_PLL_CNTL 0x175b -#define CAR_mmPLL_ANALOG 0x1708 -#define CAR_mmBPHYC_PLL0_PLL_ANALOG 0x1708 -#define CAR_mmBPHYC_PLL1_PLL_ANALOG 0x1732 -#define CAR_mmBPHYC_PLL2_PLL_ANALOG 0x175c -#define CAR_mmPLL_VREG_CNTL 0x1709 -#define CAR_mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 -#define CAR_mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 -#define CAR_mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d -#define CAR_mmPLL_UNLOCK_DETECT_CNTL 0x170a -#define CAR_mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a -#define CAR_mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 -#define CAR_mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e -#define CAR_mmPLL_DEBUG_CNTL 0x170b -#define CAR_mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b -#define CAR_mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 -#define CAR_mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f -#define CAR_mmPLL_UPDATE_LOCK 0x170c -#define CAR_mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c -#define CAR_mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 -#define CAR_mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 -#define CAR_mmPLL_UPDATE_CNTL 0x170d -#define CAR_mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d -#define CAR_mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 -#define CAR_mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 -#define CAR_mmPLL_XOR_LOCK 0x1710 -#define CAR_mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 -#define CAR_mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a -#define CAR_mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 -#define CAR_mmPLL_ANALOG_CNTL 0x1711 -#define CAR_mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 -#define CAR_mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b -#define CAR_mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 -#define CAR_mmVGA25_PPLL_REF_DIV 0x1712 -#define CAR_mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 -#define CAR_mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c -#define CAR_mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 -#define CAR_mmVGA28_PPLL_REF_DIV 0x1713 -#define CAR_mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 -#define CAR_mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d -#define CAR_mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 -#define CAR_mmVGA41_PPLL_REF_DIV 0x1714 -#define CAR_mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 -#define CAR_mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e -#define CAR_mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 -#define CAR_mmVGA25_PPLL_FB_DIV 0x1715 -#define CAR_mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 -#define CAR_mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f -#define CAR_mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 -#define CAR_mmVGA28_PPLL_FB_DIV 0x1716 -#define CAR_mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 -#define CAR_mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 -#define CAR_mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a -#define CAR_mmVGA41_PPLL_FB_DIV 0x1717 -#define CAR_mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 -#define CAR_mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 -#define CAR_mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b -#define CAR_mmVGA25_PPLL_POST_DIV 0x1718 -#define CAR_mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 -#define CAR_mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 -#define CAR_mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c -#define CAR_mmVGA28_PPLL_POST_DIV 0x1719 -#define CAR_mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 -#define CAR_mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 -#define CAR_mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d -#define CAR_mmVGA41_PPLL_POST_DIV 0x171a -#define CAR_mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a -#define CAR_mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 -#define CAR_mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e -#define CAR_mmVGA25_PPLL_ANALOG 0x171b -#define CAR_mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b -#define CAR_mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 -#define CAR_mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f -#define CAR_mmVGA28_PPLL_ANALOG 0x171c -#define CAR_mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c -#define CAR_mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 -#define CAR_mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 -#define CAR_mmVGA41_PPLL_ANALOG 0x171d -#define CAR_mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d -#define CAR_mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 -#define CAR_mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 -#define CAR_mmDISPPLL_BG_CNTL 0x171e -#define CAR_mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e -#define CAR_mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 -#define CAR_mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 -#define CAR_mmPPLL_DIV_UPDATE_DEBUG 0x171f -#define CAR_mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f -#define CAR_mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 -#define CAR_mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 -#define CAR_mmPPLL_STATUS_DEBUG 0x1720 -#define CAR_mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 -#define CAR_mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a -#define CAR_mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 -#define CAR_mmPPLL_DEBUG_MUX_CNTL 0x1721 -#define CAR_mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 -#define CAR_mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b -#define CAR_mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 -#define CAR_mmPPLL_SPARE0 0x1722 -#define CAR_mmBPHYC_PLL0_PPLL_SPARE0 0x1722 -#define CAR_mmBPHYC_PLL1_PPLL_SPARE0 0x174c -#define CAR_mmBPHYC_PLL2_PPLL_SPARE0 0x1776 -#define CAR_mmPPLL_SPARE1 0x1723 -#define CAR_mmBPHYC_PLL0_PPLL_SPARE1 0x1723 -#define CAR_mmBPHYC_PLL1_PPLL_SPARE1 0x174d -#define CAR_mmBPHYC_PLL2_PPLL_SPARE1 0x1777 -#define CAR_mmUNIPHY_TX_CONTROL1 0x48c0 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0 -#define CAR_mmUNIPHY_TX_CONTROL2 0x48c1 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1 -#define CAR_mmUNIPHY_TX_CONTROL3 0x48c2 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2 -#define CAR_mmUNIPHY_TX_CONTROL4 0x48c3 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3 -#define CAR_mmUNIPHY_POWER_CONTROL 0x48c4 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4 -#define CAR_mmUNIPHY_PLL_FBDIV 0x48c5 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5 -#define CAR_mmUNIPHY_PLL_CONTROL1 0x48c6 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6 -#define CAR_mmUNIPHY_PLL_CONTROL2 0x48c7 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7 -#define CAR_mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8 -#define CAR_mmUNIPHY_PLL_SS_CNTL 0x48c9 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9 -#define CAR_mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea -#define CAR_mmUNIPHY_REG_TEST_OUTPUT 0x48cb -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb -#define CAR_mmUNIPHY_ANG_BIST_CNTL 0x48cc -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec -#define CAR_mmUNIPHY_REG_TEST_OUTPUT2 0x48cd -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed -#define CAR_mmUNIPHY_TMDP_REG0 0x48ce -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee -#define CAR_mmUNIPHY_TMDP_REG1 0x48cf -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef -#define CAR_mmUNIPHY_TMDP_REG2 0x48d0 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0 -#define CAR_mmUNIPHY_TMDP_REG3 0x48d1 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1 -#define CAR_mmUNIPHY_TMDP_REG4 0x48d2 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2 -#define CAR_mmUNIPHY_TMDP_REG5 0x48d3 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3 -#define CAR_mmUNIPHY_TMDP_REG6 0x48d4 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4 -#define CAR_mmUNIPHY_TPG_CONTROL 0x48d5 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5 -#define CAR_mmUNIPHY_TPG_SEED 0x48d6 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6 -#define CAR_mmUNIPHY_DEBUG 0x48d7 -#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 -#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 -#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 -#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 -#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 -#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 -#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 -#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7 -#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7 -#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 -#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 -#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 -#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 -#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 -#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 -#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 -#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 -#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 -#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 -#define CAR_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 -#define CAR_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 -#define CAR_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 -#define CAR_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 -#define CAR_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 -#define CAR_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 -#define CAR_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 -#define CAR_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 -#define CAR_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 -#define CAR_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 -#define CAR_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 -#define CAR_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 -#define CAR_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 -#define CAR_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 -#define CAR_mmDPG_PIPE_DPM_CONTROL 0x1b34 -#define CAR_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 -#define CAR_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 -#define CAR_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 -#define CAR_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 -#define CAR_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 -#define CAR_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 -#define CAR_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 -#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 -#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 -#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 -#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 -#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 -#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 -#define CAR_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define CAR_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define CAR_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 -#define CAR_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 -#define CAR_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 -#define CAR_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 -#define CAR_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 -#define CAR_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 -#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 -#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 -#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 -#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 -#define CAR_mmDPG_REPEATER_PROGRAM 0x1b3a -#define CAR_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a -#define CAR_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a -#define CAR_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a -#define CAR_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a -#define CAR_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a -#define CAR_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a -#define CAR_mmDPG_HW_DEBUG_A 0x1b3b -#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b -#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b -#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b -#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b -#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b -#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b -#define CAR_mmDPG_HW_DEBUG_B 0x1b3c -#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c -#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c -#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c -#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c -#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c -#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c -#define CAR_mmDPG_HW_DEBUG_11 0x1b3d -#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d -#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d -#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d -#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d -#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d -#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d -#define CAR_mmDPG_CHK_PRE_PROC_CNTL 0x1b3e -#define CAR_mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e -#define CAR_mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e -#define CAR_mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e -#define CAR_mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e -#define CAR_mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e -#define CAR_mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e -#define CAR_mmDPG_TEST_DEBUG_INDEX 0x1b38 -#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 -#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 -#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 -#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 -#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 -#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 -#define CAR_mmDPG_TEST_DEBUG_DATA 0x1b39 -#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 -#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 -#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 -#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 -#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 -#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 -#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 -#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d -#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 -#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e -#define CAR_mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 -#define CAR_mmDPGV1_WATERMARK_MASK_CONTROL 0x473f -#define CAR_mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 -#define CAR_mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 -#define CAR_mmDPGV0_PIPE_DPM_CONTROL 0x4734 -#define CAR_mmDPGV1_PIPE_DPM_CONTROL 0x4741 -#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 -#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 -#define CAR_mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 -#define CAR_mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 -#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 -#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 -#define CAR_mmDPGV0_REPEATER_PROGRAM 0x4738 -#define CAR_mmDPGV1_REPEATER_PROGRAM 0x4745 -#define CAR_mmDPGV0_HW_DEBUG_A 0x4739 -#define CAR_mmDPGV1_HW_DEBUG_A 0x4746 -#define CAR_mmDPGV0_HW_DEBUG_B 0x473a -#define CAR_mmDPGV1_HW_DEBUG_B 0x4747 -#define CAR_mmDPGV0_HW_DEBUG_11 0x473b -#define CAR_mmDPGV1_HW_DEBUG_11 0x4748 -#define CAR_mmDPGV0_CHK_PRE_PROC_CNTL 0x473c -#define CAR_mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 -#define CAR_mmDPGV_TEST_DEBUG_INDEX 0x474e -#define CAR_mmDPGV_TEST_DEBUG_DATA 0x474f -#define CAR_ixDPGV0_DEBUG00_DMIFARB 0x1 -#define CAR_ixDPGV1_DEBUG00_DMIFARB 0x6a -#define CAR_ixDPGV0_DEBUG01_DMIFARB 0x2 -#define CAR_ixDPGV1_DEBUG01_DMIFARB 0x6b -#define CAR_ixDPGV0_DEBUG02_DMIFARB 0x3 -#define CAR_ixDPGV1_DEBUG02_DMIFARB 0x6c -#define CAR_ixDPGV0_DEBUG03_DMIFARB 0x4 -#define CAR_ixDPGV1_DEBUG03_DMIFARB 0x6d -#define CAR_ixDPGV0_DEBUG04_DMIFARB 0x5 -#define CAR_ixDPGV1_DEBUG04_DMIFARB 0x6e -#define CAR_ixDPGV0_DEBUG00 0x6 -#define CAR_ixDPGV1_DEBUG00 0x6f -#define CAR_ixDPGV0_DEBUG01 0x7 -#define CAR_ixDPGV1_DEBUG01 0x70 -#define CAR_ixDPGV0_DEBUG02 0x8 -#define CAR_ixDPGV1_DEBUG02 0x71 -#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 -#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 -#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 -#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 -#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 -#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 -#define CAR_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a -#define CAR_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 -#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 -#define CAR_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 -#define CAR_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 -#define CAR_mmAZALIA_F0_CODEC_DEBUG 0x1836 -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c -#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d -#define CAR_mmGLOBAL_CAPABILITIES 0x0 -#define CAR_mmMINOR_VERSION 0x0 -#define CAR_mmMAJOR_VERSION 0x0 -#define CAR_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 -#define CAR_mmINPUT_PAYLOAD_CAPABILITY 0x1 -#define CAR_mmGLOBAL_CONTROL 0x2 -#define CAR_mmWAKE_ENABLE 0x3 -#define CAR_mmSTATE_CHANGE_STATUS 0x3 -#define CAR_mmGLOBAL_STATUS 0x4 -#define CAR_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -#define CAR_mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -#define CAR_mmINTERRUPT_CONTROL 0x8 -#define CAR_mmINTERRUPT_STATUS 0x9 -#define CAR_mmWALL_CLOCK_COUNTER 0xc -#define CAR_mmSTREAM_SYNCHRONIZATION 0xe -#define CAR_mmCORB_LOWER_BASE_ADDRESS 0x10 -#define CAR_mmCORB_UPPER_BASE_ADDRESS 0x11 -#define CAR_mmCORB_WRITE_POINTER 0x12 -#define CAR_mmCORB_READ_POINTER 0x12 -#define CAR_mmCORB_CONTROL 0x13 -#define CAR_mmCORB_STATUS 0x13 -#define CAR_mmCORB_SIZE 0x13 -#define CAR_mmRIRB_LOWER_BASE_ADDRESS 0x14 -#define CAR_mmRIRB_UPPER_BASE_ADDRESS 0x15 -#define CAR_mmRIRB_WRITE_POINTER 0x16 -#define CAR_mmRESPONSE_INTERRUPT_COUNT 0x16 -#define CAR_mmRIRB_CONTROL 0x17 -#define CAR_mmRIRB_STATUS 0x17 -#define CAR_mmRIRB_SIZE 0x17 -#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 -#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define CAR_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 -#define CAR_mmIMMEDIATE_COMMAND_STATUS 0x1a -#define CAR_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c -#define CAR_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d -#define CAR_mmWALL_CLOCK_COUNTER_ALIAS 0x80c -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 -#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 -#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 -#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 -#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 -#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c -#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 -#define CAR_ixAUDIO_DESCRIPTOR0 0x1 -#define CAR_ixAUDIO_DESCRIPTOR1 0x2 -#define CAR_ixAUDIO_DESCRIPTOR2 0x3 -#define CAR_ixAUDIO_DESCRIPTOR3 0x4 -#define CAR_ixAUDIO_DESCRIPTOR4 0x5 -#define CAR_ixAUDIO_DESCRIPTOR5 0x6 -#define CAR_ixAUDIO_DESCRIPTOR6 0x7 -#define CAR_ixAUDIO_DESCRIPTOR7 0x8 -#define CAR_ixAUDIO_DESCRIPTOR8 0x9 -#define CAR_ixAUDIO_DESCRIPTOR9 0xa -#define CAR_ixAUDIO_DESCRIPTOR10 0xb -#define CAR_ixAUDIO_DESCRIPTOR11 0xc -#define CAR_ixAUDIO_DESCRIPTOR12 0xd -#define CAR_ixAUDIO_DESCRIPTOR13 0xe -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 -#define CAR_ixSINK_DESCRIPTION0 0x5 -#define CAR_ixSINK_DESCRIPTION1 0x6 -#define CAR_ixSINK_DESCRIPTION2 0x7 -#define CAR_ixSINK_DESCRIPTION3 0x8 -#define CAR_ixSINK_DESCRIPTION4 0x9 -#define CAR_ixSINK_DESCRIPTION5 0xa -#define CAR_ixSINK_DESCRIPTION6 0xb -#define CAR_ixSINK_DESCRIPTION7 0xc -#define CAR_ixSINK_DESCRIPTION8 0xd -#define CAR_ixSINK_DESCRIPTION9 0xe -#define CAR_ixSINK_DESCRIPTION10 0xf -#define CAR_ixSINK_DESCRIPTION11 0x10 -#define CAR_ixSINK_DESCRIPTION12 0x11 -#define CAR_ixSINK_DESCRIPTION13 0x12 -#define CAR_ixSINK_DESCRIPTION14 0x13 -#define CAR_ixSINK_DESCRIPTION15 0x14 -#define CAR_ixSINK_DESCRIPTION16 0x15 -#define CAR_ixSINK_DESCRIPTION17 0x16 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 -#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 -#define CAR_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d -#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e -#define CAR_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 -#define CAR_mmAZALIA_AUDIO_DTO 0x17e5 -#define CAR_mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 -#define CAR_mmAZALIA_SCLK_CONTROL 0x17e7 -#define CAR_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 -#define CAR_mmAZALIA_DATA_DMA_CONTROL 0x17e9 -#define CAR_mmAZALIA_BDL_DMA_CONTROL 0x17ea -#define CAR_mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb -#define CAR_mmAZALIA_CORB_DMA_CONTROL 0x17ec -#define CAR_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 -#define CAR_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 -#define CAR_mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 -#define CAR_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 -#define CAR_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 -#define CAR_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 -#define CAR_mmAZALIA_CONTROLLER_DEBUG 0x17f9 -#define CAR_mmAZALIA_MEM_PWR_CTRL 0x1810 -#define CAR_mmAZALIA_MEM_PWR_STATUS 0x1811 -#define CAR_mmDCI_PG_DEBUG_CONFIG 0x1812 -#define CAR_mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb -#define CAR_mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc -#define CAR_mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd -#define CAR_mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe -#define CAR_mmAZALIA_INPUT_CRC0_RESULT 0x17ff -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 -#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 -#define CAR_mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 -#define CAR_mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 -#define CAR_mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 -#define CAR_mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 -#define CAR_mmAZALIA_INPUT_CRC1_RESULT 0x1804 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 -#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 -#define CAR_mmAZALIA_CRC0_CONTROL0 0x1805 -#define CAR_mmAZALIA_CRC0_CONTROL1 0x1806 -#define CAR_mmAZALIA_CRC0_CONTROL2 0x1807 -#define CAR_mmAZALIA_CRC0_CONTROL3 0x1808 -#define CAR_mmAZALIA_CRC0_RESULT 0x1809 -#define CAR_ixAZALIA_CRC0_CHANNEL0 0x0 -#define CAR_ixAZALIA_CRC0_CHANNEL1 0x1 -#define CAR_ixAZALIA_CRC0_CHANNEL2 0x2 -#define CAR_ixAZALIA_CRC0_CHANNEL3 0x3 -#define CAR_ixAZALIA_CRC0_CHANNEL4 0x4 -#define CAR_ixAZALIA_CRC0_CHANNEL5 0x5 -#define CAR_ixAZALIA_CRC0_CHANNEL6 0x6 -#define CAR_ixAZALIA_CRC0_CHANNEL7 0x7 -#define CAR_mmAZALIA_CRC1_CONTROL0 0x180a -#define CAR_mmAZALIA_CRC1_CONTROL1 0x180b -#define CAR_mmAZALIA_CRC1_CONTROL2 0x180c -#define CAR_mmAZALIA_CRC1_CONTROL3 0x180d -#define CAR_mmAZALIA_CRC1_RESULT 0x180e -#define CAR_ixAZALIA_CRC1_CHANNEL0 0x0 -#define CAR_ixAZALIA_CRC1_CHANNEL1 0x1 -#define CAR_ixAZALIA_CRC1_CHANNEL2 0x2 -#define CAR_ixAZALIA_CRC1_CHANNEL3 0x3 -#define CAR_ixAZALIA_CRC1_CHANNEL4 0x4 -#define CAR_ixAZALIA_CRC1_CHANNEL5 0x5 -#define CAR_ixAZALIA_CRC1_CHANNEL6 0x6 -#define CAR_ixAZALIA_CRC1_CHANNEL7 0x7 -#define CAR_mmAZ_TEST_DEBUG_INDEX 0x181f -#define CAR_mmAZ_TEST_DEBUG_DATA 0x1820 -#define CAR_mmAZALIA_STREAM_INDEX 0x1780 -#define CAR_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 -#define CAR_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 -#define CAR_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 -#define CAR_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 -#define CAR_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 -#define CAR_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a -#define CAR_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c -#define CAR_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e -#define CAR_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 -#define CAR_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 -#define CAR_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 -#define CAR_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 -#define CAR_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 -#define CAR_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca -#define CAR_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc -#define CAR_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce -#define CAR_mmAZALIA_STREAM_DATA 0x1781 -#define CAR_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 -#define CAR_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 -#define CAR_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 -#define CAR_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 -#define CAR_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 -#define CAR_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b -#define CAR_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d -#define CAR_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f -#define CAR_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 -#define CAR_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 -#define CAR_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 -#define CAR_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 -#define CAR_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 -#define CAR_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb -#define CAR_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd -#define CAR_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf -#define CAR_ixAZALIA_FIFO_SIZE_CONTROL 0x0 -#define CAR_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 -#define CAR_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 -#define CAR_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 -#define CAR_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 -#define CAR_ixAZALIA_STREAM_DEBUG 0x5 -#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 -#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 -#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac -#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 -#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 -#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 -#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc -#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 -#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 -#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 -#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 -#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad -#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 -#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 -#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 -#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd -#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 -#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd -#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe -#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 -#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 -#define CAR_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 -#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a -#define CAR_ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b -#define CAR_ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c -#define CAR_ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d -#define CAR_ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e -#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 -#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 -#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 -#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc -#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 -#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 -#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 -#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec -#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 -#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 -#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 -#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 -#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd -#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 -#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 -#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 -#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed -#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 -#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 -#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 -#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 -#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 -#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a -#define CAR_mmBLND_CONTROL 0x1b6d -#define CAR_mmBLND0_BLND_CONTROL 0x1b6d -#define CAR_mmBLND1_BLND_CONTROL 0x1d6d -#define CAR_mmBLND2_BLND_CONTROL 0x1f6d -#define CAR_mmBLND3_BLND_CONTROL 0x416d -#define CAR_mmBLND4_BLND_CONTROL 0x436d -#define CAR_mmBLND5_BLND_CONTROL 0x456d -#define CAR_mmBLND_SM_CONTROL2 0x1b6e -#define CAR_mmBLND0_BLND_SM_CONTROL2 0x1b6e -#define CAR_mmBLND1_BLND_SM_CONTROL2 0x1d6e -#define CAR_mmBLND2_BLND_SM_CONTROL2 0x1f6e -#define CAR_mmBLND3_BLND_SM_CONTROL2 0x416e -#define CAR_mmBLND4_BLND_SM_CONTROL2 0x436e -#define CAR_mmBLND5_BLND_SM_CONTROL2 0x456e -#define CAR_mmBLND_CONTROL2 0x1b6f -#define CAR_mmBLND0_BLND_CONTROL2 0x1b6f -#define CAR_mmBLND1_BLND_CONTROL2 0x1d6f -#define CAR_mmBLND2_BLND_CONTROL2 0x1f6f -#define CAR_mmBLND3_BLND_CONTROL2 0x416f -#define CAR_mmBLND4_BLND_CONTROL2 0x436f -#define CAR_mmBLND5_BLND_CONTROL2 0x456f -#define CAR_mmBLND_UPDATE 0x1b70 -#define CAR_mmBLND0_BLND_UPDATE 0x1b70 -#define CAR_mmBLND1_BLND_UPDATE 0x1d70 -#define CAR_mmBLND2_BLND_UPDATE 0x1f70 -#define CAR_mmBLND3_BLND_UPDATE 0x4170 -#define CAR_mmBLND4_BLND_UPDATE 0x4370 -#define CAR_mmBLND5_BLND_UPDATE 0x4570 -#define CAR_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 -#define CAR_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 -#define CAR_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 -#define CAR_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 -#define CAR_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 -#define CAR_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 -#define CAR_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 -#define CAR_mmBLND_V_UPDATE_LOCK 0x1b73 -#define CAR_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 -#define CAR_mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 -#define CAR_mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 -#define CAR_mmBLND3_BLND_V_UPDATE_LOCK 0x4173 -#define CAR_mmBLND4_BLND_V_UPDATE_LOCK 0x4373 -#define CAR_mmBLND5_BLND_V_UPDATE_LOCK 0x4573 -#define CAR_mmBLND_REG_UPDATE_STATUS 0x1b77 -#define CAR_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 -#define CAR_mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 -#define CAR_mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 -#define CAR_mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 -#define CAR_mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 -#define CAR_mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 -#define CAR_mmBLND_DEBUG 0x1b74 -#define CAR_mmBLND0_BLND_DEBUG 0x1b74 -#define CAR_mmBLND1_BLND_DEBUG 0x1d74 -#define CAR_mmBLND2_BLND_DEBUG 0x1f74 -#define CAR_mmBLND3_BLND_DEBUG 0x4174 -#define CAR_mmBLND4_BLND_DEBUG 0x4374 -#define CAR_mmBLND5_BLND_DEBUG 0x4574 -#define CAR_mmBLND_TEST_DEBUG_INDEX 0x1b75 -#define CAR_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 -#define CAR_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 -#define CAR_mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 -#define CAR_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 -#define CAR_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 -#define CAR_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 -#define CAR_mmBLND_TEST_DEBUG_DATA 0x1b76 -#define CAR_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 -#define CAR_mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 -#define CAR_mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 -#define CAR_mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 -#define CAR_mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 -#define CAR_mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 -#define CAR_mmWB_ENABLE 0x5e18 -#define CAR_mmWB_EC_CONFIG 0x5e19 -#define CAR_mmCNV_MODE 0x5e1a -#define CAR_mmCNV_WINDOW_START 0x5e1b -#define CAR_mmCNV_WINDOW_SIZE 0x5e1c -#define CAR_mmCNV_UPDATE 0x5e1d -#define CAR_mmCNV_SOURCE_SIZE 0x5e1e -#define CAR_mmCNV_CSC_CONTROL 0x5e1f -#define CAR_mmCNV_CSC_C11_C12 0x5e20 -#define CAR_mmCNV_CSC_C13_C14 0x5e21 -#define CAR_mmCNV_CSC_C21_C22 0x5e22 -#define CAR_mmCNV_CSC_C23_C24 0x5e23 -#define CAR_mmCNV_CSC_C31_C32 0x5e24 -#define CAR_mmCNV_CSC_C33_C34 0x5e25 -#define CAR_mmCNV_CSC_ROUND_OFFSET_R 0x5e26 -#define CAR_mmCNV_CSC_ROUND_OFFSET_G 0x5e27 -#define CAR_mmCNV_CSC_ROUND_OFFSET_B 0x5e28 -#define CAR_mmCNV_CSC_CLAMP_R 0x5e29 -#define CAR_mmCNV_CSC_CLAMP_G 0x5e2a -#define CAR_mmCNV_CSC_CLAMP_B 0x5e2b -#define CAR_mmCNV_TEST_CNTL 0x5e2c -#define CAR_mmCNV_TEST_CRC_RED 0x5e2d -#define CAR_mmCNV_TEST_CRC_GREEN 0x5e2e -#define CAR_mmCNV_TEST_CRC_BLUE 0x5e2f -#define CAR_mmWB_DEBUG_CTRL 0x5e30 -#define CAR_mmWB_DBG_MODE 0x5e31 -#define CAR_mmWB_HW_DEBUG 0x5e32 -#define CAR_mmCNV_INPUT_SELECT 0x5e33 -#define CAR_mmWB_SOFT_RESET 0x5e36 -#define CAR_mmCNV_TEST_DEBUG_INDEX 0x5e34 -#define CAR_mmCNV_TEST_DEBUG_DATA 0x5e35 -#define CAR_mmDCFE_CLOCK_CONTROL 0x1b00 -#define CAR_mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 -#define CAR_mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 -#define CAR_mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 -#define CAR_mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 -#define CAR_mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 -#define CAR_mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 -#define CAR_mmDCFE_SOFT_RESET 0x1b01 -#define CAR_mmDCFE0_DCFE_SOFT_RESET 0x1b01 -#define CAR_mmDCFE1_DCFE_SOFT_RESET 0x1d01 -#define CAR_mmDCFE2_DCFE_SOFT_RESET 0x1f01 -#define CAR_mmDCFE3_DCFE_SOFT_RESET 0x4101 -#define CAR_mmDCFE4_DCFE_SOFT_RESET 0x4301 -#define CAR_mmDCFE5_DCFE_SOFT_RESET 0x4501 -#define CAR_mmDCFE_DBG_CONFIG 0x1b02 -#define CAR_mmDCFE0_DCFE_DBG_CONFIG 0x1b02 -#define CAR_mmDCFE1_DCFE_DBG_CONFIG 0x1d02 -#define CAR_mmDCFE2_DCFE_DBG_CONFIG 0x1f02 -#define CAR_mmDCFE3_DCFE_DBG_CONFIG 0x4102 -#define CAR_mmDCFE4_DCFE_DBG_CONFIG 0x4302 -#define CAR_mmDCFE5_DCFE_DBG_CONFIG 0x4502 -#define CAR_mmDCFE_MEM_PWR_CTRL 0x1b03 -#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 -#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 -#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 -#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 -#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 -#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 -#define CAR_mmDCFE_MEM_PWR_CTRL2 0x1b04 -#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 -#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 -#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 -#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 -#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 -#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 -#define CAR_mmDCFE_MEM_PWR_STATUS 0x1b05 -#define CAR_mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 -#define CAR_mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 -#define CAR_mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 -#define CAR_mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 -#define CAR_mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 -#define CAR_mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 -#define CAR_mmDCFE_MISC 0x1b06 -#define CAR_mmDCFE0_DCFE_MISC 0x1b06 -#define CAR_mmDCFE1_DCFE_MISC 0x1d06 -#define CAR_mmDCFE2_DCFE_MISC 0x1f06 -#define CAR_mmDCFE3_DCFE_MISC 0x4106 -#define CAR_mmDCFE4_DCFE_MISC 0x4306 -#define CAR_mmDCFE5_DCFE_MISC 0x4506 -#define CAR_mmDCFEV_CLOCK_CONTROL 0x46f4 -#define CAR_mmDCFEV_SOFT_RESET 0x46f5 -#define CAR_mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 -#define CAR_mmDCFEV_DBG_CONFIG 0x46f7 -#define CAR_mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 -#define CAR_mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 -#define CAR_mmDCFEV_MEM_PWR_CTRL 0x46fa -#define CAR_mmDCFEV_MEM_PWR_CTRL2 0x46fb -#define CAR_mmDCFEV_MEM_PWR_STATUS 0x46fc -#define CAR_mmDCFEV_DMIFV_DEBUG 0x46fd -#define CAR_mmDCFEV_MISC 0x46fe -#define CAR_mmDC_HPD_INT_STATUS 0x1898 -#define CAR_mmHPD0_DC_HPD_INT_STATUS 0x1898 -#define CAR_mmHPD1_DC_HPD_INT_STATUS 0x18a0 -#define CAR_mmHPD2_DC_HPD_INT_STATUS 0x18a8 -#define CAR_mmHPD3_DC_HPD_INT_STATUS 0x18b0 -#define CAR_mmHPD4_DC_HPD_INT_STATUS 0x18b8 -#define CAR_mmHPD5_DC_HPD_INT_STATUS 0x18c0 -#define CAR_mmDC_HPD_INT_CONTROL 0x1899 -#define CAR_mmHPD0_DC_HPD_INT_CONTROL 0x1899 -#define CAR_mmHPD1_DC_HPD_INT_CONTROL 0x18a1 -#define CAR_mmHPD2_DC_HPD_INT_CONTROL 0x18a9 -#define CAR_mmHPD3_DC_HPD_INT_CONTROL 0x18b1 -#define CAR_mmHPD4_DC_HPD_INT_CONTROL 0x18b9 -#define CAR_mmHPD5_DC_HPD_INT_CONTROL 0x18c1 -#define CAR_mmDC_HPD_CONTROL 0x189a -#define CAR_mmHPD0_DC_HPD_CONTROL 0x189a -#define CAR_mmHPD1_DC_HPD_CONTROL 0x18a2 -#define CAR_mmHPD2_DC_HPD_CONTROL 0x18aa -#define CAR_mmHPD3_DC_HPD_CONTROL 0x18b2 -#define CAR_mmHPD4_DC_HPD_CONTROL 0x18ba -#define CAR_mmHPD5_DC_HPD_CONTROL 0x18c2 -#define CAR_mmDC_HPD_FAST_TRAIN_CNTL 0x189b -#define CAR_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b -#define CAR_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 -#define CAR_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab -#define CAR_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 -#define CAR_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb -#define CAR_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 -#define CAR_mmDC_HPD_TOGGLE_FILT_CNTL 0x189c -#define CAR_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c -#define CAR_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 -#define CAR_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac -#define CAR_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 -#define CAR_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc -#define CAR_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 -#define CAR_mmDCO_SCRATCH0 0x184e -#define CAR_mmDCO_SCRATCH1 0x184f -#define CAR_mmDCO_SCRATCH2 0x1850 -#define CAR_mmDCO_SCRATCH3 0x1851 -#define CAR_mmDCO_SCRATCH4 0x1852 -#define CAR_mmDCO_SCRATCH5 0x1853 -#define CAR_mmDCO_SCRATCH6 0x1854 -#define CAR_mmDCO_SCRATCH7 0x1855 -#define CAR_mmDCE_VCE_CONTROL 0x1856 -#define CAR_mmDISP_INTERRUPT_STATUS 0x1857 -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 -#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 -#define CAR_mmDCO_MEM_PWR_STATUS 0x1861 -#define CAR_mmDCO_MEM_PWR_STATUS1 0x1874 -#define CAR_mmDCO_MEM_PWR_CTRL 0x1862 -#define CAR_mmDCO_MEM_PWR_CTRL2 0x1863 -#define CAR_mmDCO_CLK_CNTL 0x1864 -#define CAR_mmDCO_CLK_CNTL2 0x1876 -#define CAR_mmDCO_CLK_CNTL3 0x1877 -#define CAR_mmDPDBG_CNTL 0x1866 -#define CAR_mmDPDBG_INTERRUPT 0x1867 -#define CAR_mmDCO_POWER_MANAGEMENT_CNTL 0x1868 -#define CAR_mmDCO_SOFT_RESET 0x1871 -#define CAR_mmDIG_SOFT_RESET 0x1872 -#define CAR_mmDIG_SOFT_RESET_2 0x186a -#define CAR_mmDCO_STEREOSYNC_SEL 0x186e -#define CAR_mmDCO_TEST_DEBUG_INDEX 0x186f -#define CAR_mmDCO_TEST_DEBUG_DATA 0x1870 -#define CAR_mmDC_I2C_CONTROL 0x16d4 -#define CAR_mmDC_I2C_ARBITRATION 0x16d5 -#define CAR_mmDC_I2C_INTERRUPT_CONTROL 0x16d6 -#define CAR_mmDC_I2C_SW_STATUS 0x16d7 -#define CAR_mmDC_I2C_DDC1_HW_STATUS 0x16d8 -#define CAR_mmDC_I2C_DDC2_HW_STATUS 0x16d9 -#define CAR_mmDC_I2C_DDC3_HW_STATUS 0x16da -#define CAR_mmDC_I2C_DDC4_HW_STATUS 0x16db -#define CAR_mmDC_I2C_DDC5_HW_STATUS 0x16dc -#define CAR_mmDC_I2C_DDC6_HW_STATUS 0x16dd -#define CAR_mmDC_I2C_DDC1_SPEED 0x16de -#define CAR_mmDC_I2C_DDC1_SETUP 0x16df -#define CAR_mmDC_I2C_DDC2_SPEED 0x16e0 -#define CAR_mmDC_I2C_DDC2_SETUP 0x16e1 -#define CAR_mmDC_I2C_DDC3_SPEED 0x16e2 -#define CAR_mmDC_I2C_DDC3_SETUP 0x16e3 -#define CAR_mmDC_I2C_DDC4_SPEED 0x16e4 -#define CAR_mmDC_I2C_DDC4_SETUP 0x16e5 -#define CAR_mmDC_I2C_DDC5_SPEED 0x16e6 -#define CAR_mmDC_I2C_DDC5_SETUP 0x16e7 -#define CAR_mmDC_I2C_DDC6_SPEED 0x16e8 -#define CAR_mmDC_I2C_DDC6_SETUP 0x16e9 -#define CAR_mmDC_I2C_TRANSACTION0 0x16ea -#define CAR_mmDC_I2C_TRANSACTION1 0x16eb -#define CAR_mmDC_I2C_TRANSACTION2 0x16ec -#define CAR_mmDC_I2C_TRANSACTION3 0x16ed -#define CAR_mmDC_I2C_DATA 0x16ee -#define CAR_mmDC_I2C_DDCVGA_HW_STATUS 0x16ef -#define CAR_mmDC_I2C_DDCVGA_SPEED 0x16f0 -#define CAR_mmDC_I2C_DDCVGA_SETUP 0x16f1 -#define CAR_mmDC_I2C_EDID_DETECT_CTRL 0x16f2 -#define CAR_mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 -#define CAR_mmGENERIC_I2C_CONTROL 0x16f4 -#define CAR_mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 -#define CAR_mmGENERIC_I2C_STATUS 0x16f6 -#define CAR_mmGENERIC_I2C_SPEED 0x16f7 -#define CAR_mmGENERIC_I2C_SETUP 0x16f8 -#define CAR_mmGENERIC_I2C_TRANSACTION 0x16f9 -#define CAR_mmGENERIC_I2C_DATA 0x16fa -#define CAR_mmGENERIC_I2C_PIN_SELECTION 0x16fb -#define CAR_mmGENERIC_I2C_PIN_DEBUG 0x16fc -#define CAR_mmBLNDV_CONTROL 0x476d -#define CAR_mmBLNDV_SM_CONTROL2 0x476e -#define CAR_mmBLNDV_CONTROL2 0x476f -#define CAR_mmBLNDV_UPDATE 0x4770 -#define CAR_mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 -#define CAR_mmBLNDV_V_UPDATE_LOCK 0x4773 -#define CAR_mmBLNDV_REG_UPDATE_STATUS 0x4777 -#define CAR_mmBLNDV_DEBUG 0x4774 -#define CAR_mmBLNDV_TEST_DEBUG_INDEX 0x4775 -#define CAR_mmBLNDV_TEST_DEBUG_DATA 0x4776 -#define CAR_mmCRTCV_H_BLANK_EARLY_NUM 0x477d -#define CAR_mmCRTCV_H_TOTAL 0x4780 -#define CAR_mmCRTCV_H_BLANK_START_END 0x4781 -#define CAR_mmCRTCV_H_SYNC_A 0x4782 -#define CAR_mmCRTCV_H_SYNC_A_CNTL 0x4783 -#define CAR_mmCRTCV_H_SYNC_B 0x4784 -#define CAR_mmCRTCV_H_SYNC_B_CNTL 0x4785 -#define CAR_mmCRTCV_VBI_END 0x4786 -#define CAR_mmCRTCV_V_TOTAL 0x4787 -#define CAR_mmCRTCV_V_TOTAL_MIN 0x4788 -#define CAR_mmCRTCV_V_TOTAL_MAX 0x4789 -#define CAR_mmCRTCV_V_TOTAL_CONTROL 0x478a -#define CAR_mmCRTCV_V_TOTAL_INT_STATUS 0x478b -#define CAR_mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c -#define CAR_mmCRTCV_V_BLANK_START_END 0x478d -#define CAR_mmCRTCV_V_SYNC_A 0x478e -#define CAR_mmCRTCV_V_SYNC_A_CNTL 0x478f -#define CAR_mmCRTCV_V_SYNC_B 0x4790 -#define CAR_mmCRTCV_V_SYNC_B_CNTL 0x4791 -#define CAR_mmCRTCV_DTMTEST_CNTL 0x4792 -#define CAR_mmCRTCV_DTMTEST_STATUS_POSITION 0x4793 -#define CAR_mmCRTCV_TRIGA_CNTL 0x4794 -#define CAR_mmCRTCV_TRIGA_MANUAL_TRIG 0x4795 -#define CAR_mmCRTCV_TRIGB_CNTL 0x4796 -#define CAR_mmCRTCV_TRIGB_MANUAL_TRIG 0x4797 -#define CAR_mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798 -#define CAR_mmCRTCV_FLOW_CONTROL 0x4799 -#define CAR_mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a -#define CAR_mmCRTCV_AVSYNC_COUNTER 0x479b -#define CAR_mmCRTCV_CONTROL 0x479c -#define CAR_mmCRTCV_BLANK_CONTROL 0x479d -#define CAR_mmCRTCV_INTERLACE_CONTROL 0x479e -#define CAR_mmCRTCV_INTERLACE_STATUS 0x479f -#define CAR_mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0 -#define CAR_mmCRTCV_PIXEL_DATA_READBACK0 0x47a1 -#define CAR_mmCRTCV_PIXEL_DATA_READBACK1 0x47a2 -#define CAR_mmCRTCV_STATUS 0x47a3 -#define CAR_mmCRTCV_STATUS_POSITION 0x47a4 -#define CAR_mmCRTCV_NOM_VERT_POSITION 0x47a5 -#define CAR_mmCRTCV_STATUS_FRAME_COUNT 0x47a6 -#define CAR_mmCRTCV_STATUS_VF_COUNT 0x47a7 -#define CAR_mmCRTCV_STATUS_HV_COUNT 0x47a8 -#define CAR_mmCRTCV_COUNT_CONTROL 0x47a9 -#define CAR_mmCRTCV_COUNT_RESET 0x47aa -#define CAR_mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab -#define CAR_mmCRTCV_VERT_SYNC_CONTROL 0x47ac -#define CAR_mmCRTCV_STEREO_STATUS 0x47ad -#define CAR_mmCRTCV_STEREO_CONTROL 0x47ae -#define CAR_mmCRTCV_SNAPSHOT_STATUS 0x47af -#define CAR_mmCRTCV_SNAPSHOT_CONTROL 0x47b0 -#define CAR_mmCRTCV_SNAPSHOT_POSITION 0x47b1 -#define CAR_mmCRTCV_SNAPSHOT_FRAME 0x47b2 -#define CAR_mmCRTCV_START_LINE_CONTROL 0x47b3 -#define CAR_mmCRTCV_INTERRUPT_CONTROL 0x47b4 -#define CAR_mmCRTCV_UPDATE_LOCK 0x47b5 -#define CAR_mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6 -#define CAR_mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7 -#define CAR_mmCRTCV_TEST_PATTERN_CONTROL 0x47ba -#define CAR_mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb -#define CAR_mmCRTCV_TEST_PATTERN_COLOR 0x47bc -#define CAR_mmCRTCV_MASTER_UPDATE_LOCK 0x47bd -#define CAR_mmCRTCV_MASTER_UPDATE_MODE 0x47be -#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf -#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 -#define CAR_mmCRTCV_MVP_STATUS 0x47c1 -#define CAR_mmCRTCV_MASTER_EN 0x47c2 -#define CAR_mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3 -#define CAR_mmCRTCV_V_UPDATE_INT_STATUS 0x47c4 -#define CAR_mmCRTCV_OVERSCAN_COLOR 0x47c8 -#define CAR_mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 -#define CAR_mmCRTCV_BLANK_DATA_COLOR 0x47ca -#define CAR_mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb -#define CAR_mmCRTCV_BLACK_COLOR 0x47cc -#define CAR_mmCRTCV_BLACK_COLOR_EXT 0x47cd -#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce -#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf -#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0 -#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1 -#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2 -#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3 -#define CAR_mmCRTCV_CRC_CNTL 0x47d4 -#define CAR_mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 -#define CAR_mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 -#define CAR_mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 -#define CAR_mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 -#define CAR_mmCRTCV_CRC0_DATA_RG 0x47d9 -#define CAR_mmCRTCV_CRC0_DATA_B 0x47da -#define CAR_mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db -#define CAR_mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc -#define CAR_mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd -#define CAR_mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de -#define CAR_mmCRTCV_CRC1_DATA_RG 0x47df -#define CAR_mmCRTCV_CRC1_DATA_B 0x47e0 -#define CAR_mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7 -#define CAR_mmCRTCV_3D_STRUCTURE_CONTROL 0x4778 -#define CAR_mmCRTCV_GSL_VSYNC_GAP 0x4779 -#define CAR_mmCRTCV_GSL_WINDOW 0x477a -#define CAR_mmCRTCV_GSL_CONTROL 0x477b -#define CAR_mmCRTCV_TEST_DEBUG_INDEX 0x47c6 -#define CAR_mmCRTCV_TEST_DEBUG_DATA 0x47c7 -#define CAR_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 -#define CAR_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 -#define CAR_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 -#define CAR_mmXDMA_INTERRUPT 0x3e3 -#define CAR_mmXDMA_CLOCK_GATING_CNTL 0x3e4 -#define CAR_mmXDMA_MEM_POWER_CNTL 0x3e6 -#define CAR_mmXDMA_IF_BIF_STATUS 0x3e7 -#define CAR_mmXDMA_PERF_MEAS_STATUS 0x3e8 -#define CAR_mmXDMA_IF_STATUS 0x3e9 -#define CAR_mmXDMA_TEST_DEBUG_INDEX 0x3ea -#define CAR_mmXDMA_TEST_DEBUG_DATA 0x3eb -#define CAR_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 -#define CAR_mmXDMA_PG_CONTROL 0x3f9 -#define CAR_mmXDMA_PG_WDATA 0x3fa -#define CAR_mmXDMA_PG_STATUS 0x3fb -#define CAR_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc -#define CAR_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd -#define CAR_mmXDMA_MSTR_CNTL 0x3ec -#define CAR_mmXDMA_MSTR_STATUS 0x3ed -#define CAR_mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee -#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef -#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 -#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 -#define CAR_mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 -#define CAR_mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 -#define CAR_mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 -#define CAR_mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 -#define CAR_mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 -#define CAR_mmXDMA_MSTR_PIPE_CNTL 0x400 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 -#define CAR_mmXDMA_MSTR_READ_COMMAND 0x401 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 -#define CAR_mmXDMA_MSTR_CHANNEL_DIM 0x402 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 -#define CAR_mmXDMA_MSTR_HEIGHT 0x403 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 -#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 -#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 -#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 -#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 -#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 -#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 -#define CAR_mmXDMA_MSTR_CACHE 0x40a -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a -#define CAR_mmXDMA_MSTR_CHANNEL_START 0x40b -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b -#define CAR_mmXDMA_MSTR_PERFMEAS_STATUS 0x40e -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e -#define CAR_mmXDMA_MSTR_PERFMEAS_CNTL 0x40f -#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f -#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f -#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f -#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f -#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f -#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f -#define CAR_mmXDMA_SLV_CNTL 0x460 -#define CAR_mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 -#define CAR_mmXDMA_SLV_SLS_PITCH 0x462 -#define CAR_mmXDMA_SLV_READ_URGENT_CNTL 0x463 -#define CAR_mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 -#define CAR_mmXDMA_SLV_WB_RATE_CNTL 0x465 -#define CAR_mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 -#define CAR_mmXDMA_SLV_READ_LATENCY_AVE 0x467 -#define CAR_mmXDMA_SLV_PCIE_NACK_STATUS 0x468 -#define CAR_mmXDMA_SLV_MEM_NACK_STATUS 0x469 -#define CAR_mmXDMA_SLV_RDRET_BUF_STATUS 0x46a -#define CAR_mmXDMA_SLV_READ_LATENCY_TIMER 0x46b -#define CAR_mmXDMA_SLV_FLIP_PENDING 0x46c -#define CAR_mmXDMA_SLV_CHANNEL_CNTL 0x470 -#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 -#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 -#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 -#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 -#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 -#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 -#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 -#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 -#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 -#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 -#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 -#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 -#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 -#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 -#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 -#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a -#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 -#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a -#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 -#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a #endif /* DCE_11_0_D_H */ diff --git a/headers/private/graphics/radeon_hd/pol_reg.h b/headers/private/graphics/radeon_hd/pol_reg.h index 9562f080d2..9c1919e7fc 100644 --- a/headers/private/graphics/radeon_hd/pol_reg.h +++ b/headers/private/graphics/radeon_hd/pol_reg.h @@ -18,18191 +18,13 @@ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* This header has been modified from its original version: + * it has been formatted to contain only what Haiku needs. */ + #ifndef _dce_12_0_OFFSET_HEADER #define _dce_12_0_OFFSET_HEADER - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR -// base address: 0x48 -#define POL_mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012 -#define POL_mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR -// base address: 0x4c -#define POL_mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014 -#define POL_mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 - - -// addressBlock: dce_dc_dc_perfmon0_dispdec -// base address: 0x0 -#define POL_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020 -#define POL_mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021 -#define POL_mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022 -#define POL_mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_CNTL 0x0023 -#define POL_mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_CNTL2 0x0024 -#define POL_mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025 -#define POL_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026 -#define POL_mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_HI 0x0027 -#define POL_mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON0_PERFMON_LOW 0x0028 -#define POL_mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon13_dispdec -// base address: 0x30 -#define POL_mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c -#define POL_mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d -#define POL_mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e -#define POL_mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_CNTL 0x002f -#define POL_mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_CNTL2 0x0030 -#define POL_mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031 -#define POL_mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032 -#define POL_mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_HI 0x0033 -#define POL_mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON13_PERFMON_LOW 0x0034 -#define POL_mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_displaypllregs_dispdec -// base address: 0x0 -#define POL_mmPPLL_VREG_CFG 0x0038 -#define POL_mmPPLL_VREG_CFG_BASE_IDX 2 -#define POL_mmPPLL_MODE_CNTL 0x0039 -#define POL_mmPPLL_MODE_CNTL_BASE_IDX 2 -#define POL_mmPPLL_FREQ_CTRL0 0x003a -#define POL_mmPPLL_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmPPLL_FREQ_CTRL1 0x003b -#define POL_mmPPLL_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmPPLL_FREQ_CTRL2 0x003c -#define POL_mmPPLL_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmPPLL_FREQ_CTRL3 0x003d -#define POL_mmPPLL_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmPPLL_BW_CTRL_COARSE 0x003e -#define POL_mmPPLL_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmPPLL_BW_CTRL_FINE 0x0040 -#define POL_mmPPLL_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmPPLL_CAL_CTRL 0x0041 -#define POL_mmPPLL_CAL_CTRL_BASE_IDX 2 -#define POL_mmPPLL_LOOP_CTRL 0x0042 -#define POL_mmPPLL_LOOP_CTRL_BASE_IDX 2 -#define POL_mmPPLL_REFCLK_CNTL 0x0050 -#define POL_mmPPLL_REFCLK_CNTL_BASE_IDX 2 -#define POL_mmPPLL_CLKOUT_CNTL 0x0051 -#define POL_mmPPLL_CLKOUT_CNTL_BASE_IDX 2 -#define POL_mmPPLL_DFT_CNTL 0x0052 -#define POL_mmPPLL_DFT_CNTL_BASE_IDX 2 -#define POL_mmPPLL_ANALOG_CNTL 0x0053 -#define POL_mmPPLL_ANALOG_CNTL_BASE_IDX 2 -#define POL_mmPPLL_POSTDIV 0x0054 -#define POL_mmPPLL_POSTDIV_BASE_IDX 2 -#define POL_mmPPLL_OBSERVE0 0x0059 -#define POL_mmPPLL_OBSERVE0_BASE_IDX 2 -#define POL_mmPPLL_OBSERVE1 0x005a -#define POL_mmPPLL_OBSERVE1_BASE_IDX 2 -#define POL_mmPPLL_UPDATE_CNTL 0x005c -#define POL_mmPPLL_UPDATE_CNTL_BASE_IDX 2 -#define POL_mmPPLL_OBSERVE0_OUT 0x005d -#define POL_mmPPLL_OBSERVE0_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dccg_pll0_dispdec -// base address: 0x0 -#define POL_mmPLL_MACRO_CNTL_RESERVED0 0x0038 -#define POL_mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED1 0x0039 -#define POL_mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED2 0x003a -#define POL_mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED3 0x003b -#define POL_mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED4 0x003c -#define POL_mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED5 0x003d -#define POL_mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED6 0x003e -#define POL_mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED7 0x003f -#define POL_mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED8 0x0040 -#define POL_mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED9 0x0041 -#define POL_mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED10 0x0042 -#define POL_mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED11 0x0043 -#define POL_mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED12 0x0044 -#define POL_mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED13 0x0045 -#define POL_mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED14 0x0046 -#define POL_mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED15 0x0047 -#define POL_mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED16 0x0048 -#define POL_mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED17 0x0049 -#define POL_mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED18 0x004a -#define POL_mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED19 0x004b -#define POL_mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED20 0x004c -#define POL_mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED21 0x004d -#define POL_mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED22 0x004e -#define POL_mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED23 0x004f -#define POL_mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED24 0x0050 -#define POL_mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED25 0x0051 -#define POL_mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED26 0x0052 -#define POL_mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED27 0x0053 -#define POL_mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED28 0x0054 -#define POL_mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED29 0x0055 -#define POL_mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED30 0x0056 -#define POL_mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED31 0x0057 -#define POL_mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED32 0x0058 -#define POL_mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED33 0x0059 -#define POL_mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED34 0x005a -#define POL_mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED35 0x005b -#define POL_mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED36 0x005c -#define POL_mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED37 0x005d -#define POL_mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED38 0x005e -#define POL_mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED39 0x005f -#define POL_mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED40 0x0060 -#define POL_mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmPLL_MACRO_CNTL_RESERVED41 0x0061 -#define POL_mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon1_dispdec -// base address: 0x598 -#define POL_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186 -#define POL_mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187 -#define POL_mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188 -#define POL_mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_CNTL 0x0189 -#define POL_mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_CNTL2 0x018a -#define POL_mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b -#define POL_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c -#define POL_mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_HI 0x018d -#define POL_mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON1_PERFMON_LOW 0x018e -#define POL_mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_mcif_wb0_dispdec -// base address: 0x0 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e -#define POL_mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f -#define POL_mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d -#define POL_mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292 -#define POL_mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293 -#define POL_mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294 -#define POL_mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295 -#define POL_mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296 -#define POL_mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297 -#define POL_mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298 -#define POL_mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299 -#define POL_mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b -#define POL_mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 -#define POL_mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c -#define POL_mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 - - -// addressBlock: dce_dc_mcif_wb1_dispdec -// base address: 0x100 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be -#define POL_mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf -#define POL_mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd -#define POL_mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 -#define POL_mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 -#define POL_mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 -#define POL_mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5 -#define POL_mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 -#define POL_mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7 -#define POL_mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 -#define POL_mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9 -#define POL_mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db -#define POL_mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 -#define POL_mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc -#define POL_mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 - - -// addressBlock: dce_dc_mcif_wb2_dispdec -// base address: 0x200 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe -#define POL_mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff -#define POL_mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d -#define POL_mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 -#define POL_mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 -#define POL_mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314 -#define POL_mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315 -#define POL_mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 -#define POL_mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317 -#define POL_mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 -#define POL_mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319 -#define POL_mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b -#define POL_mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 -#define POL_mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c -#define POL_mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 - - -// addressBlock: dce_dc_cwb0_dispdec -// base address: 0x0 -#define POL_mmCWB0_CWB_CTRL 0x0332 -#define POL_mmCWB0_CWB_CTRL_BASE_IDX 2 -#define POL_mmCWB0_CWB_FENCE_PAR0 0x0334 -#define POL_mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2 -#define POL_mmCWB0_CWB_FENCE_PAR1 0x0335 -#define POL_mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2 -#define POL_mmCWB0_CWB_CRC_CTRL 0x0339 -#define POL_mmCWB0_CWB_CRC_CTRL_BASE_IDX 2 -#define POL_mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a -#define POL_mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmCWB0_CWB_CRC_BLUE_MASK 0x033b -#define POL_mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2 -#define POL_mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c -#define POL_mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2 -#define POL_mmCWB0_CWB_CRC_BLUE_RESULT 0x033d -#define POL_mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2 - - -// addressBlock: dce_dc_cwb1_dispdec -// base address: 0x60 -#define POL_mmCWB1_CWB_CTRL 0x034a -#define POL_mmCWB1_CWB_CTRL_BASE_IDX 2 -#define POL_mmCWB1_CWB_FENCE_PAR0 0x034c -#define POL_mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2 -#define POL_mmCWB1_CWB_FENCE_PAR1 0x034d -#define POL_mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2 -#define POL_mmCWB1_CWB_CRC_CTRL 0x0351 -#define POL_mmCWB1_CWB_CRC_CTRL_BASE_IDX 2 -#define POL_mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352 -#define POL_mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmCWB1_CWB_CRC_BLUE_MASK 0x0353 -#define POL_mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2 -#define POL_mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354 -#define POL_mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2 -#define POL_mmCWB1_CWB_CRC_BLUE_RESULT 0x0355 -#define POL_mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon9_dispdec -// base address: 0xd08 -#define POL_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362 -#define POL_mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363 -#define POL_mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364 -#define POL_mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_CNTL 0x0365 -#define POL_mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_CNTL2 0x0366 -#define POL_mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367 -#define POL_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368 -#define POL_mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_HI 0x0369 -#define POL_mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON9_PERFMON_LOW 0x036a -#define POL_mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dispdec -// base address: 0x0 -#define POL_mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 -#define POL_mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 -#define POL_mmVGA_MEM_READ_PAGE_ADDR 0x0001 -#define POL_mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 -#define POL_mmVGA_RENDER_CONTROL 0x0000 -#define POL_mmVGA_RENDER_CONTROL_BASE_IDX 1 -#define POL_mmVGA_SEQUENCER_RESET_CONTROL 0x0001 -#define POL_mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 -#define POL_mmVGA_MODE_CONTROL 0x0002 -#define POL_mmVGA_MODE_CONTROL_BASE_IDX 1 -#define POL_mmVGA_SURFACE_PITCH_SELECT 0x0003 -#define POL_mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 -#define POL_mmVGA_MEMORY_BASE_ADDRESS 0x0004 -#define POL_mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 -#define POL_mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 -#define POL_mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 -#define POL_mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 -#define POL_mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 -#define POL_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 -#define POL_mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 -#define POL_mmVGA_HDP_CONTROL 0x000a -#define POL_mmVGA_HDP_CONTROL_BASE_IDX 1 -#define POL_mmVGA_CACHE_CONTROL 0x000b -#define POL_mmVGA_CACHE_CONTROL_BASE_IDX 1 -#define POL_mmD1VGA_CONTROL 0x000c -#define POL_mmD1VGA_CONTROL_BASE_IDX 1 -#define POL_mmD2VGA_CONTROL 0x000e -#define POL_mmD2VGA_CONTROL_BASE_IDX 1 -#define POL_mmVGA_STATUS 0x0010 -#define POL_mmVGA_STATUS_BASE_IDX 1 -#define POL_mmVGA_INTERRUPT_CONTROL 0x0011 -#define POL_mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 -#define POL_mmVGA_STATUS_CLEAR 0x0012 -#define POL_mmVGA_STATUS_CLEAR_BASE_IDX 1 -#define POL_mmVGA_INTERRUPT_STATUS 0x0013 -#define POL_mmVGA_INTERRUPT_STATUS_BASE_IDX 1 -#define POL_mmVGA_MAIN_CONTROL 0x0014 -#define POL_mmVGA_MAIN_CONTROL_BASE_IDX 1 -#define POL_mmVGA_TEST_CONTROL 0x0015 -#define POL_mmVGA_TEST_CONTROL_BASE_IDX 1 -#define POL_mmVGA_QOS_CTRL 0x0018 -#define POL_mmVGA_QOS_CTRL_BASE_IDX 1 -#define POL_mmCRTC8_IDX 0x002d -#define POL_mmCRTC8_IDX_BASE_IDX 1 -#define POL_mmCRTC8_DATA 0x002d -#define POL_mmCRTC8_DATA_BASE_IDX 1 -#define POL_mmGENFC_WT 0x002e -#define POL_mmGENFC_WT_BASE_IDX 1 -#define POL_mmGENS1 0x002e -#define POL_mmGENS1_BASE_IDX 1 -#define POL_mmATTRDW 0x0030 -#define POL_mmATTRDW_BASE_IDX 1 -#define POL_mmATTRX 0x0030 -#define POL_mmATTRX_BASE_IDX 1 -#define POL_mmATTRDR 0x0030 -#define POL_mmATTRDR_BASE_IDX 1 -#define POL_mmGENMO_WT 0x0030 -#define POL_mmGENMO_WT_BASE_IDX 1 -#define POL_mmGENS0 0x0030 -#define POL_mmGENS0_BASE_IDX 1 -#define POL_mmGENENB 0x0030 -#define POL_mmGENENB_BASE_IDX 1 -#define POL_mmSEQ8_IDX 0x0031 -#define POL_mmSEQ8_IDX_BASE_IDX 1 -#define POL_mmSEQ8_DATA 0x0031 -#define POL_mmSEQ8_DATA_BASE_IDX 1 -#define POL_mmDAC_MASK 0x0031 -#define POL_mmDAC_MASK_BASE_IDX 1 -#define POL_mmDAC_R_INDEX 0x0031 -#define POL_mmDAC_R_INDEX_BASE_IDX 1 -#define POL_mmDAC_W_INDEX 0x0032 -#define POL_mmDAC_W_INDEX_BASE_IDX 1 -#define POL_mmDAC_DATA 0x0032 -#define POL_mmDAC_DATA_BASE_IDX 1 -#define POL_mmGENFC_RD 0x0032 -#define POL_mmGENFC_RD_BASE_IDX 1 -#define POL_mmGENMO_RD 0x0033 -#define POL_mmGENMO_RD_BASE_IDX 1 -#define POL_mmGRPH8_IDX 0x0033 -#define POL_mmGRPH8_IDX_BASE_IDX 1 -#define POL_mmGRPH8_DATA 0x0033 -#define POL_mmGRPH8_DATA_BASE_IDX 1 -#define POL_mmCRTC8_IDX_1 0x0035 -#define POL_mmCRTC8_IDX_1_BASE_IDX 1 -#define POL_mmCRTC8_DATA_1 0x0035 -#define POL_mmCRTC8_DATA_1_BASE_IDX 1 -#define POL_mmGENFC_WT_1 0x0036 -#define POL_mmGENFC_WT_1_BASE_IDX 1 -#define POL_mmGENS1_1 0x0036 -#define POL_mmGENS1_1_BASE_IDX 1 -#define POL_mmD3VGA_CONTROL 0x0038 -#define POL_mmD3VGA_CONTROL_BASE_IDX 1 -#define POL_mmD4VGA_CONTROL 0x0039 -#define POL_mmD4VGA_CONTROL_BASE_IDX 1 -#define POL_mmD5VGA_CONTROL 0x003a -#define POL_mmD5VGA_CONTROL_BASE_IDX 1 -#define POL_mmD6VGA_CONTROL 0x003b -#define POL_mmD6VGA_CONTROL_BASE_IDX 1 -#define POL_mmVGA_SOURCE_SELECT 0x003c -#define POL_mmVGA_SOURCE_SELECT_BASE_IDX 1 -#define POL_mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 -#define POL_mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 -#define POL_mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 -#define POL_mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 -#define POL_mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044 -#define POL_mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045 -#define POL_mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmSYMCLKLPA_CLOCK_ENABLE 0x0046 -#define POL_mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKLPB_CLOCK_ENABLE 0x0047 -#define POL_mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 -#define POL_mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmREFCLK_CNTL 0x0049 -#define POL_mmREFCLK_CNTL_BASE_IDX 1 -#define POL_mmMIPI_CLK_CNTL 0x004a -#define POL_mmMIPI_CLK_CNTL_BASE_IDX 1 -#define POL_mmREFCLK_CGTT_BLK_CTRL_REG 0x004b -#define POL_mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c -#define POL_mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmDCCG_PERFMON_CNTL2 0x004e -#define POL_mmDCCG_PERFMON_CNTL2_BASE_IDX 1 -#define POL_mmDSICLK_CGTT_BLK_CTRL_REG 0x004f -#define POL_mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmDCCG_CBUS_WRCMD_DELAY 0x0050 -#define POL_mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1 -#define POL_mmDCCG_DS_DTO_INCR 0x0053 -#define POL_mmDCCG_DS_DTO_INCR_BASE_IDX 1 -#define POL_mmDCCG_DS_DTO_MODULO 0x0054 -#define POL_mmDCCG_DS_DTO_MODULO_BASE_IDX 1 -#define POL_mmDCCG_DS_CNTL 0x0055 -#define POL_mmDCCG_DS_CNTL_BASE_IDX 1 -#define POL_mmDCCG_DS_HW_CAL_INTERVAL 0x0056 -#define POL_mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 -#define POL_mmSYMCLKG_CLOCK_ENABLE 0x0057 -#define POL_mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmDPREFCLK_CNTL 0x0058 -#define POL_mmDPREFCLK_CNTL_BASE_IDX 1 -#define POL_mmAOMCLK0_CNTL 0x0059 -#define POL_mmAOMCLK0_CNTL_BASE_IDX 1 -#define POL_mmAOMCLK1_CNTL 0x005a -#define POL_mmAOMCLK1_CNTL_BASE_IDX 1 -#define POL_mmAOMCLK2_CNTL 0x005b -#define POL_mmAOMCLK2_CNTL_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO2_PHASE 0x005c -#define POL_mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO2_MODULO 0x005d -#define POL_mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 -#define POL_mmDCE_VERSION 0x005e -#define POL_mmDCE_VERSION_BASE_IDX 1 -#define POL_mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f -#define POL_mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmDCCG_GTC_CNTL 0x0060 -#define POL_mmDCCG_GTC_CNTL_BASE_IDX 1 -#define POL_mmDCCG_GTC_DTO_INCR 0x0061 -#define POL_mmDCCG_GTC_DTO_INCR_BASE_IDX 1 -#define POL_mmDCCG_GTC_DTO_MODULO 0x0062 -#define POL_mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 -#define POL_mmDCCG_GTC_CURRENT 0x0063 -#define POL_mmDCCG_GTC_CURRENT_BASE_IDX 1 -#define POL_mmDENTIST_DISPCLK_CNTL 0x0064 -#define POL_mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 -#define POL_mmMIPI_DTO_CNTL 0x0065 -#define POL_mmMIPI_DTO_CNTL_BASE_IDX 1 -#define POL_mmMIPI_DTO_PHASE 0x0066 -#define POL_mmMIPI_DTO_PHASE_BASE_IDX 1 -#define POL_mmMIPI_DTO_MODULO 0x0067 -#define POL_mmMIPI_DTO_MODULO_BASE_IDX 1 -#define POL_mmDAC_CLK_ENABLE 0x0068 -#define POL_mmDAC_CLK_ENABLE_BASE_IDX 1 -#define POL_mmDVO_CLK_ENABLE 0x0069 -#define POL_mmDVO_CLK_ENABLE_BASE_IDX 1 -#define POL_mmAVSYNC_COUNTER_WRITE 0x006a -#define POL_mmAVSYNC_COUNTER_WRITE_BASE_IDX 1 -#define POL_mmAVSYNC_COUNTER_CONTROL 0x006b -#define POL_mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1 -#define POL_mmDMCU_SMU_INTERRUPT_CNTL 0x006c -#define POL_mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1 -#define POL_mmSMU_CONTROL 0x006d -#define POL_mmSMU_CONTROL_BASE_IDX 1 -#define POL_mmSMU_INTERRUPT_CONTROL 0x006e -#define POL_mmSMU_INTERRUPT_CONTROL_BASE_IDX 1 -#define POL_mmAVSYNC_COUNTER_READ 0x006f -#define POL_mmAVSYNC_COUNTER_READ_BASE_IDX 1 -#define POL_mmMILLISECOND_TIME_BASE_DIV 0x0070 -#define POL_mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 -#define POL_mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 -#define POL_mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 -#define POL_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 -#define POL_mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 -#define POL_mmDCCG_PERFMON_CNTL 0x0073 -#define POL_mmDCCG_PERFMON_CNTL_BASE_IDX 1 -#define POL_mmDCCG_GATE_DISABLE_CNTL 0x0074 -#define POL_mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 -#define POL_mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 -#define POL_mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmSCLK_CGTT_BLK_CTRL_REG 0x0076 -#define POL_mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmDCCG_CAC_STATUS 0x0077 -#define POL_mmDCCG_CAC_STATUS_BASE_IDX 1 -#define POL_mmPIXCLK1_RESYNC_CNTL 0x0078 -#define POL_mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmPIXCLK2_RESYNC_CNTL 0x0079 -#define POL_mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmPIXCLK0_RESYNC_CNTL 0x007a -#define POL_mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmMICROSECOND_TIME_BASE_DIV 0x007b -#define POL_mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 -#define POL_mmDCCG_GATE_DISABLE_CNTL2 0x007c -#define POL_mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 -#define POL_mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d -#define POL_mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 -#define POL_mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e -#define POL_mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 -#define POL_mmDCCG_DISP_CNTL_REG 0x007f -#define POL_mmDCCG_DISP_CNTL_REG_BASE_IDX 1 -#define POL_mmCRTC0_PIXEL_RATE_CNTL 0x0080 -#define POL_mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO0_PHASE 0x0081 -#define POL_mmDP_DTO0_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO0_MODULO 0x0082 -#define POL_mmDP_DTO0_MODULO_BASE_IDX 1 -#define POL_mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083 -#define POL_mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmCRTC1_PIXEL_RATE_CNTL 0x0084 -#define POL_mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO1_PHASE 0x0085 -#define POL_mmDP_DTO1_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO1_MODULO 0x0086 -#define POL_mmDP_DTO1_MODULO_BASE_IDX 1 -#define POL_mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087 -#define POL_mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmCRTC2_PIXEL_RATE_CNTL 0x0088 -#define POL_mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO2_PHASE 0x0089 -#define POL_mmDP_DTO2_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO2_MODULO 0x008a -#define POL_mmDP_DTO2_MODULO_BASE_IDX 1 -#define POL_mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b -#define POL_mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmCRTC3_PIXEL_RATE_CNTL 0x008c -#define POL_mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO3_PHASE 0x008d -#define POL_mmDP_DTO3_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO3_MODULO 0x008e -#define POL_mmDP_DTO3_MODULO_BASE_IDX 1 -#define POL_mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f -#define POL_mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmCRTC4_PIXEL_RATE_CNTL 0x0090 -#define POL_mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO4_PHASE 0x0091 -#define POL_mmDP_DTO4_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO4_MODULO 0x0092 -#define POL_mmDP_DTO4_MODULO_BASE_IDX 1 -#define POL_mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093 -#define POL_mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmCRTC5_PIXEL_RATE_CNTL 0x0094 -#define POL_mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDP_DTO5_PHASE 0x0095 -#define POL_mmDP_DTO5_PHASE_BASE_IDX 1 -#define POL_mmDP_DTO5_MODULO 0x0096 -#define POL_mmDP_DTO5_MODULO_BASE_IDX 1 -#define POL_mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097 -#define POL_mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 -#define POL_mmDCCG_SOFT_RESET 0x009f -#define POL_mmDCCG_SOFT_RESET_BASE_IDX 1 -#define POL_mmSYMCLKA_CLOCK_ENABLE 0x00a0 -#define POL_mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKB_CLOCK_ENABLE 0x00a1 -#define POL_mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKC_CLOCK_ENABLE 0x00a2 -#define POL_mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKD_CLOCK_ENABLE 0x00a3 -#define POL_mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKE_CLOCK_ENABLE 0x00a4 -#define POL_mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmSYMCLKF_CLOCK_ENABLE 0x00a5 -#define POL_mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 -#define POL_mmDVOACLKD_CNTL 0x00a8 -#define POL_mmDVOACLKD_CNTL_BASE_IDX 1 -#define POL_mmDVOACLKC_MVP_CNTL 0x00a9 -#define POL_mmDVOACLKC_MVP_CNTL_BASE_IDX 1 -#define POL_mmDVOACLKC_CNTL 0x00aa -#define POL_mmDVOACLKC_CNTL_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO_SOURCE 0x00ab -#define POL_mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO0_PHASE 0x00ac -#define POL_mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO0_MODULE 0x00ad -#define POL_mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO1_PHASE 0x00ae -#define POL_mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 -#define POL_mmDCCG_AUDIO_DTO1_MODULE 0x00af -#define POL_mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 -#define POL_mmDCCG_TEST_CLK_SEL 0x00be -#define POL_mmDCCG_TEST_CLK_SEL_BASE_IDX 1 -#define POL_mmFBC_CNTL 0x0062 -#define POL_mmFBC_CNTL_BASE_IDX 2 -#define POL_mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064 -#define POL_mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2 -#define POL_mmFBC_START_STOP_DELAY 0x0065 -#define POL_mmFBC_START_STOP_DELAY_BASE_IDX 2 -#define POL_mmFBC_COMP_CNTL 0x0066 -#define POL_mmFBC_COMP_CNTL_BASE_IDX 2 -#define POL_mmFBC_COMP_MODE 0x0067 -#define POL_mmFBC_COMP_MODE_BASE_IDX 2 -#define POL_mmFBC_IND_LUT0 0x006b -#define POL_mmFBC_IND_LUT0_BASE_IDX 2 -#define POL_mmFBC_IND_LUT1 0x006c -#define POL_mmFBC_IND_LUT1_BASE_IDX 2 -#define POL_mmFBC_IND_LUT2 0x006d -#define POL_mmFBC_IND_LUT2_BASE_IDX 2 -#define POL_mmFBC_IND_LUT3 0x006e -#define POL_mmFBC_IND_LUT3_BASE_IDX 2 -#define POL_mmFBC_IND_LUT4 0x006f -#define POL_mmFBC_IND_LUT4_BASE_IDX 2 -#define POL_mmFBC_IND_LUT5 0x0070 -#define POL_mmFBC_IND_LUT5_BASE_IDX 2 -#define POL_mmFBC_IND_LUT6 0x0071 -#define POL_mmFBC_IND_LUT6_BASE_IDX 2 -#define POL_mmFBC_IND_LUT7 0x0072 -#define POL_mmFBC_IND_LUT7_BASE_IDX 2 -#define POL_mmFBC_IND_LUT8 0x0073 -#define POL_mmFBC_IND_LUT8_BASE_IDX 2 -#define POL_mmFBC_IND_LUT9 0x0074 -#define POL_mmFBC_IND_LUT9_BASE_IDX 2 -#define POL_mmFBC_IND_LUT10 0x0075 -#define POL_mmFBC_IND_LUT10_BASE_IDX 2 -#define POL_mmFBC_IND_LUT11 0x0076 -#define POL_mmFBC_IND_LUT11_BASE_IDX 2 -#define POL_mmFBC_IND_LUT12 0x0077 -#define POL_mmFBC_IND_LUT12_BASE_IDX 2 -#define POL_mmFBC_IND_LUT13 0x0078 -#define POL_mmFBC_IND_LUT13_BASE_IDX 2 -#define POL_mmFBC_IND_LUT14 0x0079 -#define POL_mmFBC_IND_LUT14_BASE_IDX 2 -#define POL_mmFBC_IND_LUT15 0x007a -#define POL_mmFBC_IND_LUT15_BASE_IDX 2 -#define POL_mmFBC_CSM_REGION_OFFSET_01 0x007b -#define POL_mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2 -#define POL_mmFBC_CSM_REGION_OFFSET_23 0x007c -#define POL_mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2 -#define POL_mmFBC_CLIENT_REGION_MASK 0x007d -#define POL_mmFBC_CLIENT_REGION_MASK_BASE_IDX 2 -#define POL_mmFBC_DEBUG_COMP 0x007e -#define POL_mmFBC_DEBUG_COMP_BASE_IDX 2 -#define POL_mmFBC_MISC 0x0084 -#define POL_mmFBC_MISC_BASE_IDX 2 -#define POL_mmFBC_STATUS 0x0085 -#define POL_mmFBC_STATUS_BASE_IDX 2 -#define POL_mmFBC_ALPHA_CNTL 0x0088 -#define POL_mmFBC_ALPHA_CNTL_BASE_IDX 2 -#define POL_mmFBC_ALPHA_RGB_OVERRIDE 0x0089 -#define POL_mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2 -#define POL_mmPIPE0_PG_CONFIG 0x008e -#define POL_mmPIPE0_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE0_PG_ENABLE 0x008f -#define POL_mmPIPE0_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE0_PG_STATUS 0x0090 -#define POL_mmPIPE0_PG_STATUS_BASE_IDX 2 -#define POL_mmPIPE1_PG_CONFIG 0x0091 -#define POL_mmPIPE1_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE1_PG_ENABLE 0x0092 -#define POL_mmPIPE1_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE1_PG_STATUS 0x0093 -#define POL_mmPIPE1_PG_STATUS_BASE_IDX 2 -#define POL_mmPIPE2_PG_CONFIG 0x0094 -#define POL_mmPIPE2_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE2_PG_ENABLE 0x0095 -#define POL_mmPIPE2_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE2_PG_STATUS 0x0096 -#define POL_mmPIPE2_PG_STATUS_BASE_IDX 2 -#define POL_mmPIPE3_PG_CONFIG 0x0097 -#define POL_mmPIPE3_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE3_PG_ENABLE 0x0098 -#define POL_mmPIPE3_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE3_PG_STATUS 0x0099 -#define POL_mmPIPE3_PG_STATUS_BASE_IDX 2 -#define POL_mmPIPE4_PG_CONFIG 0x009a -#define POL_mmPIPE4_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE4_PG_ENABLE 0x009b -#define POL_mmPIPE4_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE4_PG_STATUS 0x009c -#define POL_mmPIPE4_PG_STATUS_BASE_IDX 2 -#define POL_mmPIPE5_PG_CONFIG 0x009d -#define POL_mmPIPE5_PG_CONFIG_BASE_IDX 2 -#define POL_mmPIPE5_PG_ENABLE 0x009e -#define POL_mmPIPE5_PG_ENABLE_BASE_IDX 2 -#define POL_mmPIPE5_PG_STATUS 0x009f -#define POL_mmPIPE5_PG_STATUS_BASE_IDX 2 -#define POL_mmDSI_PG_CONFIG 0x00a0 -#define POL_mmDSI_PG_CONFIG_BASE_IDX 2 -#define POL_mmDSI_PG_ENABLE 0x00a1 -#define POL_mmDSI_PG_ENABLE_BASE_IDX 2 -#define POL_mmDSI_PG_STATUS 0x00a2 -#define POL_mmDSI_PG_STATUS_BASE_IDX 2 -#define POL_mmDCFEV0_PG_CONFIG 0x00a3 -#define POL_mmDCFEV0_PG_CONFIG_BASE_IDX 2 -#define POL_mmDCFEV0_PG_ENABLE 0x00a4 -#define POL_mmDCFEV0_PG_ENABLE_BASE_IDX 2 -#define POL_mmDCFEV0_PG_STATUS 0x00a5 -#define POL_mmDCFEV0_PG_STATUS_BASE_IDX 2 -#define POL_mmDCPG_INTERRUPT_STATUS 0x00a6 -#define POL_mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCPG_INTERRUPT_CONTROL 0x00a7 -#define POL_mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCPG_INTERRUPT_CONTROL2 0x00a8 -#define POL_mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2 -#define POL_mmDCFEV1_PG_CONFIG 0x00a9 -#define POL_mmDCFEV1_PG_CONFIG_BASE_IDX 2 -#define POL_mmDCFEV1_PG_ENABLE 0x00aa -#define POL_mmDCFEV1_PG_ENABLE_BASE_IDX 2 -#define POL_mmDCFEV1_PG_STATUS 0x00ab -#define POL_mmDCFEV1_PG_STATUS_BASE_IDX 2 -#define POL_mmDC_IP_REQUEST_CNTL 0x00ac -#define POL_mmDC_IP_REQUEST_CNTL_BASE_IDX 2 -#define POL_mmDC_PGCNTL_STATUS_REG 0x00ad -#define POL_mmDC_PGCNTL_STATUS_REG_BASE_IDX 2 -#define POL_mmDMIFV_STATUS 0x00c3 -#define POL_mmDMIFV_STATUS_BASE_IDX 2 -#define POL_mmDMIF_CONTROL 0x00c4 -#define POL_mmDMIF_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_STATUS 0x00c5 -#define POL_mmDMIF_STATUS_BASE_IDX 2 -#define POL_mmDMIF_ARBITRATION_CONTROL 0x00c7 -#define POL_mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2 -#define POL_mmPIPE0_ARBITRATION_CONTROL3 0x00c8 -#define POL_mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE1_ARBITRATION_CONTROL3 0x00c9 -#define POL_mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE2_ARBITRATION_CONTROL3 0x00ca -#define POL_mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE3_ARBITRATION_CONTROL3 0x00cb -#define POL_mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE4_ARBITRATION_CONTROL3 0x00cc -#define POL_mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE5_ARBITRATION_CONTROL3 0x00cd -#define POL_mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmDMIF_P_VMID 0x00ce -#define POL_mmDMIF_P_VMID_BASE_IDX 2 -#define POL_mmDMIF_ADDR_CALC 0x00d1 -#define POL_mmDMIF_ADDR_CALC_BASE_IDX 2 -#define POL_mmDMIF_STATUS2 0x00d2 -#define POL_mmDMIF_STATUS2_BASE_IDX 2 -#define POL_mmPIPE0_MAX_REQUESTS 0x00d3 -#define POL_mmPIPE0_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE1_MAX_REQUESTS 0x00d4 -#define POL_mmPIPE1_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE2_MAX_REQUESTS 0x00d5 -#define POL_mmPIPE2_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE3_MAX_REQUESTS 0x00d6 -#define POL_mmPIPE3_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE4_MAX_REQUESTS 0x00d7 -#define POL_mmPIPE4_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE5_MAX_REQUESTS 0x00d8 -#define POL_mmPIPE5_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmLOW_POWER_TILING_CONTROL 0x00d9 -#define POL_mmLOW_POWER_TILING_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_CONTROL 0x00da -#define POL_mmMCIF_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_WRITE_COMBINE_CONTROL 0x00db -#define POL_mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 -#define POL_mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de -#define POL_mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 -#define POL_mmCC_DC_PIPE_DIS 0x00e0 -#define POL_mmCC_DC_PIPE_DIS_BASE_IDX 2 -#define POL_mmSMU_WM_CONTROL 0x00e1 -#define POL_mmSMU_WM_CONTROL_BASE_IDX 2 -#define POL_mmRBBMIF_TIMEOUT 0x00e2 -#define POL_mmRBBMIF_TIMEOUT_BASE_IDX 2 -#define POL_mmRBBMIF_STATUS 0x00e3 -#define POL_mmRBBMIF_STATUS_BASE_IDX 2 -#define POL_mmRBBMIF_TIMEOUT_DIS 0x00e4 -#define POL_mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_STATUS 0x00e5 -#define POL_mmDCI_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_STATUS2 0x00e6 -#define POL_mmDCI_MEM_PWR_STATUS2_BASE_IDX 2 -#define POL_mmDCI_CLK_CNTL 0x00e7 -#define POL_mmDCI_CLK_CNTL_BASE_IDX 2 -#define POL_mmDCI_CLK_CNTL2 0x00e8 -#define POL_mmDCI_CLK_CNTL2_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_CNTL 0x00e9 -#define POL_mmDCI_MEM_PWR_CNTL_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_CNTL2 0x00ea -#define POL_mmDCI_MEM_PWR_CNTL2_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_CNTL3 0x00eb -#define POL_mmDCI_MEM_PWR_CNTL3_BASE_IDX 2 -#define POL_mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef -#define POL_mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0 -#define POL_mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1 -#define POL_mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2 -#define POL_mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3 -#define POL_mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4 -#define POL_mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmRBBMIF_STATUS_FLAG 0x00f5 -#define POL_mmRBBMIF_STATUS_FLAG_BASE_IDX 2 -#define POL_mmDCI_SOFT_RESET 0x00f6 -#define POL_mmDCI_SOFT_RESET_BASE_IDX 2 -#define POL_mmDMIF_URG_OVERRIDE 0x00f7 -#define POL_mmDMIF_URG_OVERRIDE_BASE_IDX 2 -#define POL_mmPIPE6_ARBITRATION_CONTROL3 0x00f8 -#define POL_mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE7_ARBITRATION_CONTROL3 0x00f9 -#define POL_mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2 -#define POL_mmPIPE6_MAX_REQUESTS 0x00fa -#define POL_mmPIPE6_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmPIPE7_MAX_REQUESTS 0x00fb -#define POL_mmPIPE7_MAX_REQUESTS_BASE_IDX 2 -#define POL_mmDVMM_REG_RD_STATUS 0x00fc -#define POL_mmDVMM_REG_RD_STATUS_BASE_IDX 2 -#define POL_mmDVMM_REG_RD_DATA 0x00fd -#define POL_mmDVMM_REG_RD_DATA_BASE_IDX 2 -#define POL_mmDVMM_PTE_REQ 0x00fe -#define POL_mmDVMM_PTE_REQ_BASE_IDX 2 -#define POL_mmDVMM_CNTL 0x00ff -#define POL_mmDVMM_CNTL_BASE_IDX 2 -#define POL_mmDVMM_FAULT_STATUS 0x0100 -#define POL_mmDVMM_FAULT_STATUS_BASE_IDX 2 -#define POL_mmDVMM_FAULT_ADDR 0x0101 -#define POL_mmDVMM_FAULT_ADDR_BASE_IDX 2 -#define POL_mmFMON_CTRL 0x0102 -#define POL_mmFMON_CTRL_BASE_IDX 2 -#define POL_mmDVMM_PTE_PGMEM_CONTROL 0x0103 -#define POL_mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2 -#define POL_mmDVMM_PTE_PGMEM_STATE 0x0104 -#define POL_mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2 -#define POL_mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105 -#define POL_mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 -#define POL_mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106 -#define POL_mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 -#define POL_mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107 -#define POL_mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 -#define POL_mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108 -#define POL_mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_CNTL4 0x0109 -#define POL_mmDCI_MEM_PWR_CNTL4_BASE_IDX 2 -#define POL_mmMCIF_WB_MISC_CTRL 0x010a -#define POL_mmMCIF_WB_MISC_CTRL_BASE_IDX 2 -#define POL_mmDCI_MEM_PWR_STATUS3 0x010b -#define POL_mmDCI_MEM_PWR_STATUS3_BASE_IDX 2 -#define POL_mmDMIF_CURSOR_CONTROL 0x010c -#define POL_mmDMIF_CURSOR_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_CURSOR_MEM_CONTROL 0x010d -#define POL_mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2 -#define POL_mmDCHUB_FB_LOCATION 0x0126 -#define POL_mmDCHUB_FB_LOCATION_BASE_IDX 2 -#define POL_mmDCHUB_FB_OFFSET 0x0127 -#define POL_mmDCHUB_FB_OFFSET_BASE_IDX 2 -#define POL_mmDCHUB_AGP_BASE 0x0128 -#define POL_mmDCHUB_AGP_BASE_BASE_IDX 2 -#define POL_mmDCHUB_AGP_BOT 0x0129 -#define POL_mmDCHUB_AGP_BOT_BASE_IDX 2 -#define POL_mmDCHUB_AGP_TOP 0x012a -#define POL_mmDCHUB_AGP_TOP_BASE_IDX 2 -#define POL_mmDCHUB_DRAM_APER_BASE 0x012b -#define POL_mmDCHUB_DRAM_APER_BASE_BASE_IDX 2 -#define POL_mmDCHUB_DRAM_APER_DEF 0x012c -#define POL_mmDCHUB_DRAM_APER_DEF_BASE_IDX 2 -#define POL_mmDCHUB_DRAM_APER_TOP 0x012d -#define POL_mmDCHUB_DRAM_APER_TOP_BASE_IDX 2 -#define POL_mmDCHUB_CONTROL_STATUS 0x012e -#define POL_mmDCHUB_CONTROL_STATUS_BASE_IDX 2 -#define POL_mmWB_ENABLE 0x0212 -#define POL_mmWB_ENABLE_BASE_IDX 2 -#define POL_mmWB_EC_CONFIG 0x0213 -#define POL_mmWB_EC_CONFIG_BASE_IDX 2 -#define POL_mmCNV_MODE 0x0214 -#define POL_mmCNV_MODE_BASE_IDX 2 -#define POL_mmCNV_WINDOW_START 0x0215 -#define POL_mmCNV_WINDOW_START_BASE_IDX 2 -#define POL_mmCNV_WINDOW_SIZE 0x0216 -#define POL_mmCNV_WINDOW_SIZE_BASE_IDX 2 -#define POL_mmCNV_UPDATE 0x0217 -#define POL_mmCNV_UPDATE_BASE_IDX 2 -#define POL_mmCNV_SOURCE_SIZE 0x0218 -#define POL_mmCNV_SOURCE_SIZE_BASE_IDX 2 -#define POL_mmCNV_CSC_CONTROL 0x0219 -#define POL_mmCNV_CSC_CONTROL_BASE_IDX 2 -#define POL_mmCNV_CSC_C11_C12 0x021a -#define POL_mmCNV_CSC_C11_C12_BASE_IDX 2 -#define POL_mmCNV_CSC_C13_C14 0x021b -#define POL_mmCNV_CSC_C13_C14_BASE_IDX 2 -#define POL_mmCNV_CSC_C21_C22 0x021c -#define POL_mmCNV_CSC_C21_C22_BASE_IDX 2 -#define POL_mmCNV_CSC_C23_C24 0x021d -#define POL_mmCNV_CSC_C23_C24_BASE_IDX 2 -#define POL_mmCNV_CSC_C31_C32 0x021e -#define POL_mmCNV_CSC_C31_C32_BASE_IDX 2 -#define POL_mmCNV_CSC_C33_C34 0x021f -#define POL_mmCNV_CSC_C33_C34_BASE_IDX 2 -#define POL_mmCNV_CSC_ROUND_OFFSET_R 0x0220 -#define POL_mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 -#define POL_mmCNV_CSC_ROUND_OFFSET_G 0x0221 -#define POL_mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 -#define POL_mmCNV_CSC_ROUND_OFFSET_B 0x0222 -#define POL_mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 -#define POL_mmCNV_CSC_CLAMP_R 0x0223 -#define POL_mmCNV_CSC_CLAMP_R_BASE_IDX 2 -#define POL_mmCNV_CSC_CLAMP_G 0x0224 -#define POL_mmCNV_CSC_CLAMP_G_BASE_IDX 2 -#define POL_mmCNV_CSC_CLAMP_B 0x0225 -#define POL_mmCNV_CSC_CLAMP_B_BASE_IDX 2 -#define POL_mmCNV_TEST_CNTL 0x0226 -#define POL_mmCNV_TEST_CNTL_BASE_IDX 2 -#define POL_mmCNV_TEST_CRC_RED 0x0227 -#define POL_mmCNV_TEST_CRC_RED_BASE_IDX 2 -#define POL_mmCNV_TEST_CRC_GREEN 0x0228 -#define POL_mmCNV_TEST_CRC_GREEN_BASE_IDX 2 -#define POL_mmCNV_TEST_CRC_BLUE 0x0229 -#define POL_mmCNV_TEST_CRC_BLUE_BASE_IDX 2 -#define POL_mmCNV_INPUT_SELECT 0x022d -#define POL_mmCNV_INPUT_SELECT_BASE_IDX 2 -#define POL_mmWB_SOFT_RESET 0x0230 -#define POL_mmWB_SOFT_RESET_BASE_IDX 2 -#define POL_mmWB_WARM_UP_MODE_CTL1 0x0231 -#define POL_mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2 -#define POL_mmWB_WARM_UP_MODE_CTL2 0x0232 -#define POL_mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2 -#define POL_mmWBSCL_COEF_RAM_SELECT 0x0242 -#define POL_mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmWBSCL_COEF_RAM_TAP_DATA 0x0243 -#define POL_mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmWBSCL_MODE 0x0244 -#define POL_mmWBSCL_MODE_BASE_IDX 2 -#define POL_mmWBSCL_TAP_CONTROL 0x0245 -#define POL_mmWBSCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmWBSCL_DEST_SIZE 0x0246 -#define POL_mmWBSCL_DEST_SIZE_BASE_IDX 2 -#define POL_mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247 -#define POL_mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248 -#define POL_mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 -#define POL_mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249 -#define POL_mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 -#define POL_mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a -#define POL_mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b -#define POL_mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 -#define POL_mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c -#define POL_mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 -#define POL_mmWBSCL_ROUND_OFFSET 0x024d -#define POL_mmWBSCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmWBSCL_CLAMP 0x024e -#define POL_mmWBSCL_CLAMP_BASE_IDX 2 -#define POL_mmWBSCL_OVERFLOW_STATUS 0x024f -#define POL_mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2 -#define POL_mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250 -#define POL_mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251 -#define POL_mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 -#define POL_mmWBSCL_TEST_CNTL 0x0252 -#define POL_mmWBSCL_TEST_CNTL_BASE_IDX 2 -#define POL_mmWBSCL_TEST_CRC_RED 0x0253 -#define POL_mmWBSCL_TEST_CRC_RED_BASE_IDX 2 -#define POL_mmWBSCL_TEST_CRC_GREEN 0x0254 -#define POL_mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2 -#define POL_mmWBSCL_TEST_CRC_BLUE 0x0255 -#define POL_mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2 -#define POL_mmWBSCL_BACKPRESSURE_CNT_EN 0x0256 -#define POL_mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 -#define POL_mmWB_MCIF_BACKPRESSURE_CNT 0x0257 -#define POL_mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 -#define POL_mmWBSCL_RAM_SHUTDOWN 0x025a -#define POL_mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2 -#define POL_mmDMCU_CTRL 0x03b6 -#define POL_mmDMCU_CTRL_BASE_IDX 2 -#define POL_mmDMCU_STATUS 0x03b7 -#define POL_mmDMCU_STATUS_BASE_IDX 2 -#define POL_mmDMCU_PC_START_ADDR 0x03b8 -#define POL_mmDMCU_PC_START_ADDR_BASE_IDX 2 -#define POL_mmDMCU_FW_START_ADDR 0x03b9 -#define POL_mmDMCU_FW_START_ADDR_BASE_IDX 2 -#define POL_mmDMCU_FW_END_ADDR 0x03ba -#define POL_mmDMCU_FW_END_ADDR_BASE_IDX 2 -#define POL_mmDMCU_FW_ISR_START_ADDR 0x03bb -#define POL_mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 -#define POL_mmDMCU_FW_CS_HI 0x03bc -#define POL_mmDMCU_FW_CS_HI_BASE_IDX 2 -#define POL_mmDMCU_FW_CS_LO 0x03bd -#define POL_mmDMCU_FW_CS_LO_BASE_IDX 2 -#define POL_mmDMCU_RAM_ACCESS_CTRL 0x03be -#define POL_mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 -#define POL_mmDMCU_ERAM_WR_CTRL 0x03bf -#define POL_mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 -#define POL_mmDMCU_ERAM_WR_DATA 0x03c0 -#define POL_mmDMCU_ERAM_WR_DATA_BASE_IDX 2 -#define POL_mmDMCU_ERAM_RD_CTRL 0x03c1 -#define POL_mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 -#define POL_mmDMCU_ERAM_RD_DATA 0x03c2 -#define POL_mmDMCU_ERAM_RD_DATA_BASE_IDX 2 -#define POL_mmDMCU_IRAM_WR_CTRL 0x03c3 -#define POL_mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 -#define POL_mmDMCU_IRAM_WR_DATA 0x03c4 -#define POL_mmDMCU_IRAM_WR_DATA_BASE_IDX 2 -#define POL_mmDMCU_IRAM_RD_CTRL 0x03c5 -#define POL_mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 -#define POL_mmDMCU_IRAM_RD_DATA 0x03c6 -#define POL_mmDMCU_IRAM_RD_DATA_BASE_IDX 2 -#define POL_mmDMCU_EVENT_TRIGGER 0x03c7 -#define POL_mmDMCU_EVENT_TRIGGER_BASE_IDX 2 -#define POL_mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8 -#define POL_mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 -#define POL_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9 -#define POL_mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_STATUS 0x03ca -#define POL_mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb -#define POL_mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc -#define POL_mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd -#define POL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 -#define POL_mmDC_DMCU_SCRATCH 0x03ce -#define POL_mmDC_DMCU_SCRATCH_BASE_IDX 2 -#define POL_mmDMCU_INT_CNT 0x03cf -#define POL_mmDMCU_INT_CNT_BASE_IDX 2 -#define POL_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0 -#define POL_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 -#define POL_mmDMCU_UC_CLK_GATING_CNTL 0x03d1 -#define POL_mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 -#define POL_mmMASTER_COMM_DATA_REG1 0x03d2 -#define POL_mmMASTER_COMM_DATA_REG1_BASE_IDX 2 -#define POL_mmMASTER_COMM_DATA_REG2 0x03d3 -#define POL_mmMASTER_COMM_DATA_REG2_BASE_IDX 2 -#define POL_mmMASTER_COMM_DATA_REG3 0x03d4 -#define POL_mmMASTER_COMM_DATA_REG3_BASE_IDX 2 -#define POL_mmMASTER_COMM_CMD_REG 0x03d5 -#define POL_mmMASTER_COMM_CMD_REG_BASE_IDX 2 -#define POL_mmMASTER_COMM_CNTL_REG 0x03d6 -#define POL_mmMASTER_COMM_CNTL_REG_BASE_IDX 2 -#define POL_mmSLAVE_COMM_DATA_REG1 0x03d7 -#define POL_mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 -#define POL_mmSLAVE_COMM_DATA_REG2 0x03d8 -#define POL_mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 -#define POL_mmSLAVE_COMM_DATA_REG3 0x03d9 -#define POL_mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 -#define POL_mmSLAVE_COMM_CMD_REG 0x03da -#define POL_mmSLAVE_COMM_CMD_REG_BASE_IDX 2 -#define POL_mmSLAVE_COMM_CNTL_REG 0x03db -#define POL_mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 -#define POL_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de -#define POL_mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 -#define POL_mmBL1_PWM_USER_LEVEL 0x03df -#define POL_mmBL1_PWM_USER_LEVEL_BASE_IDX 2 -#define POL_mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0 -#define POL_mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 -#define POL_mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1 -#define POL_mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 -#define POL_mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2 -#define POL_mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 -#define POL_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3 -#define POL_mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 -#define POL_mmBL1_PWM_ABM_CNTL 0x03e4 -#define POL_mmBL1_PWM_ABM_CNTL_BASE_IDX 2 -#define POL_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5 -#define POL_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 -#define POL_mmBL1_PWM_GRP2_REG_LOCK 0x03e6 -#define POL_mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7 -#define POL_mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8 -#define POL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 -#define POL_mmDMCU_INTERRUPT_STATUS_1 0x03e9 -#define POL_mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 -#define POL_mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea -#define POL_mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 -#define POL_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb -#define POL_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 -#define POL_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec -#define POL_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 -#define POL_mmDC_ABM1_CNTL 0x03ee -#define POL_mmDC_ABM1_CNTL_BASE_IDX 2 -#define POL_mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef -#define POL_mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4 -#define POL_mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_THRES_12 0x03f5 -#define POL_mmDC_ABM1_ACE_THRES_12_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_THRES_34 0x03f6 -#define POL_mmDC_ABM1_ACE_THRES_34_BASE_IDX 2 -#define POL_mmDC_ABM1_ACE_CNTL_MISC 0x03f7 -#define POL_mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd -#define POL_mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 -#define POL_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400 -#define POL_mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_MISC_CTRL 0x0401 -#define POL_mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_SUM_OF_LUMA 0x0402 -#define POL_mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403 -#define POL_mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404 -#define POL_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_PIXEL_COUNT 0x0405 -#define POL_mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406 -#define POL_mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407 -#define POL_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408 -#define POL_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409 -#define POL_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_SAMPLE_RATE 0x040a -#define POL_mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 -#define POL_mmDC_ABM1_LS_SAMPLE_RATE 0x040b -#define POL_mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c -#define POL_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d -#define POL_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e -#define POL_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f -#define POL_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410 -#define POL_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_1 0x0411 -#define POL_mmDC_ABM1_HG_RESULT_1_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_2 0x0412 -#define POL_mmDC_ABM1_HG_RESULT_2_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_3 0x0413 -#define POL_mmDC_ABM1_HG_RESULT_3_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_4 0x0414 -#define POL_mmDC_ABM1_HG_RESULT_4_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_5 0x0415 -#define POL_mmDC_ABM1_HG_RESULT_5_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_6 0x0416 -#define POL_mmDC_ABM1_HG_RESULT_6_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_7 0x0417 -#define POL_mmDC_ABM1_HG_RESULT_7_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_8 0x0418 -#define POL_mmDC_ABM1_HG_RESULT_8_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_9 0x0419 -#define POL_mmDC_ABM1_HG_RESULT_9_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_10 0x041a -#define POL_mmDC_ABM1_HG_RESULT_10_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_11 0x041b -#define POL_mmDC_ABM1_HG_RESULT_11_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_12 0x041c -#define POL_mmDC_ABM1_HG_RESULT_12_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_13 0x041d -#define POL_mmDC_ABM1_HG_RESULT_13_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_14 0x041e -#define POL_mmDC_ABM1_HG_RESULT_14_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_15 0x041f -#define POL_mmDC_ABM1_HG_RESULT_15_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_16 0x0420 -#define POL_mmDC_ABM1_HG_RESULT_16_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_17 0x0421 -#define POL_mmDC_ABM1_HG_RESULT_17_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_18 0x0422 -#define POL_mmDC_ABM1_HG_RESULT_18_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_19 0x0423 -#define POL_mmDC_ABM1_HG_RESULT_19_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_20 0x0424 -#define POL_mmDC_ABM1_HG_RESULT_20_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_21 0x0425 -#define POL_mmDC_ABM1_HG_RESULT_21_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_22 0x0426 -#define POL_mmDC_ABM1_HG_RESULT_22_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_23 0x0427 -#define POL_mmDC_ABM1_HG_RESULT_23_BASE_IDX 2 -#define POL_mmDC_ABM1_HG_RESULT_24 0x0428 -#define POL_mmDC_ABM1_HG_RESULT_24_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431 -#define POL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 -#define POL_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451 -#define POL_mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2 -#define POL_mmDC_ABM1_BL_MASTER_LOCK 0x0452 -#define POL_mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 -#define POL_mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc -#define POL_mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 -#define POL_mmAZALIA_AUDIO_DTO 0x04bd -#define POL_mmAZALIA_AUDIO_DTO_BASE_IDX 2 -#define POL_mmAZALIA_AUDIO_DTO_CONTROL 0x04be -#define POL_mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_SOCCLK_CONTROL 0x04bf -#define POL_mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0 -#define POL_mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 -#define POL_mmAZALIA_DATA_DMA_CONTROL 0x04c1 -#define POL_mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_BDL_DMA_CONTROL 0x04c2 -#define POL_mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3 -#define POL_mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_CORB_DMA_CONTROL 0x04c4 -#define POL_mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb -#define POL_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 -#define POL_mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc -#define POL_mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 -#define POL_mmAZALIA_GLOBAL_CAPABILITIES 0x04cd -#define POL_mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 -#define POL_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce -#define POL_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 -#define POL_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf -#define POL_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0 -#define POL_mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6 -#define POL_mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC0_RESULT 0x04d7 -#define POL_mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL2 0x04da -#define POL_mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC1_CONTROL3 0x04db -#define POL_mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 -#define POL_mmAZALIA_INPUT_CRC1_RESULT 0x04dc -#define POL_mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 -#define POL_mmAZALIA_CRC0_CONTROL0 0x04dd -#define POL_mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 -#define POL_mmAZALIA_CRC0_CONTROL1 0x04de -#define POL_mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 -#define POL_mmAZALIA_CRC0_CONTROL2 0x04df -#define POL_mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 -#define POL_mmAZALIA_CRC0_CONTROL3 0x04e0 -#define POL_mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 -#define POL_mmAZALIA_CRC0_RESULT 0x04e1 -#define POL_mmAZALIA_CRC0_RESULT_BASE_IDX 2 -#define POL_mmAZALIA_CRC1_CONTROL0 0x04e2 -#define POL_mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 -#define POL_mmAZALIA_CRC1_CONTROL1 0x04e3 -#define POL_mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 -#define POL_mmAZALIA_CRC1_CONTROL2 0x04e4 -#define POL_mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 -#define POL_mmAZALIA_CRC1_CONTROL3 0x04e5 -#define POL_mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 -#define POL_mmAZALIA_CRC1_RESULT 0x04e6 -#define POL_mmAZALIA_CRC1_RESULT_BASE_IDX 2 -#define POL_mmAZALIA_MEM_PWR_CTRL 0x04e8 -#define POL_mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmAZALIA_MEM_PWR_STATUS 0x04e9 -#define POL_mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500 -#define POL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501 -#define POL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502 -#define POL_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503 -#define POL_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b -#define POL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 -#define POL_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c -#define POL_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 -#define POL_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d -#define POL_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515 -#define POL_mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 -#define POL_mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516 -#define POL_mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 -#define POL_mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517 -#define POL_mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 -#define POL_mmDAC_ENABLE 0x155a -#define POL_mmDAC_ENABLE_BASE_IDX 2 -#define POL_mmDAC_SOURCE_SELECT 0x155b -#define POL_mmDAC_SOURCE_SELECT_BASE_IDX 2 -#define POL_mmDAC_CRC_EN 0x155c -#define POL_mmDAC_CRC_EN_BASE_IDX 2 -#define POL_mmDAC_CRC_CONTROL 0x155d -#define POL_mmDAC_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDAC_CRC_SIG_RGB_MASK 0x155e -#define POL_mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2 -#define POL_mmDAC_CRC_SIG_CONTROL_MASK 0x155f -#define POL_mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2 -#define POL_mmDAC_CRC_SIG_RGB 0x1560 -#define POL_mmDAC_CRC_SIG_RGB_BASE_IDX 2 -#define POL_mmDAC_CRC_SIG_CONTROL 0x1561 -#define POL_mmDAC_CRC_SIG_CONTROL_BASE_IDX 2 -#define POL_mmDAC_SYNC_TRISTATE_CONTROL 0x1562 -#define POL_mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2 -#define POL_mmDAC_STEREOSYNC_SELECT 0x1563 -#define POL_mmDAC_STEREOSYNC_SELECT_BASE_IDX 2 -#define POL_mmDAC_AUTODETECT_CONTROL 0x1564 -#define POL_mmDAC_AUTODETECT_CONTROL_BASE_IDX 2 -#define POL_mmDAC_AUTODETECT_CONTROL2 0x1565 -#define POL_mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2 -#define POL_mmDAC_AUTODETECT_CONTROL3 0x1566 -#define POL_mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2 -#define POL_mmDAC_AUTODETECT_STATUS 0x1567 -#define POL_mmDAC_AUTODETECT_STATUS_BASE_IDX 2 -#define POL_mmDAC_AUTODETECT_INT_CONTROL 0x1568 -#define POL_mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2 -#define POL_mmDAC_FORCE_OUTPUT_CNTL 0x1569 -#define POL_mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2 -#define POL_mmDAC_FORCE_DATA 0x156a -#define POL_mmDAC_FORCE_DATA_BASE_IDX 2 -#define POL_mmDAC_POWERDOWN 0x156b -#define POL_mmDAC_POWERDOWN_BASE_IDX 2 -#define POL_mmDAC_CONTROL 0x156c -#define POL_mmDAC_CONTROL_BASE_IDX 2 -#define POL_mmDAC_COMPARATOR_ENABLE 0x156d -#define POL_mmDAC_COMPARATOR_ENABLE_BASE_IDX 2 -#define POL_mmDAC_COMPARATOR_OUTPUT 0x156e -#define POL_mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2 -#define POL_mmDAC_PWR_CNTL 0x156f -#define POL_mmDAC_PWR_CNTL_BASE_IDX 2 -#define POL_mmDAC_DFT_CONFIG 0x1570 -#define POL_mmDAC_DFT_CONFIG_BASE_IDX 2 -#define POL_mmDAC_FIFO_STATUS 0x1571 -#define POL_mmDAC_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_CONTROL 0x1584 -#define POL_mmDC_I2C_CONTROL_BASE_IDX 2 -#define POL_mmDC_I2C_ARBITRATION 0x1585 -#define POL_mmDC_I2C_ARBITRATION_BASE_IDX 2 -#define POL_mmDC_I2C_INTERRUPT_CONTROL 0x1586 -#define POL_mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDC_I2C_SW_STATUS 0x1587 -#define POL_mmDC_I2C_SW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC1_HW_STATUS 0x1588 -#define POL_mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC2_HW_STATUS 0x1589 -#define POL_mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC3_HW_STATUS 0x158a -#define POL_mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC4_HW_STATUS 0x158b -#define POL_mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC5_HW_STATUS 0x158c -#define POL_mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC6_HW_STATUS 0x158d -#define POL_mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDC1_SPEED 0x158e -#define POL_mmDC_I2C_DDC1_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC1_SETUP 0x158f -#define POL_mmDC_I2C_DDC1_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_DDC2_SPEED 0x1590 -#define POL_mmDC_I2C_DDC2_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC2_SETUP 0x1591 -#define POL_mmDC_I2C_DDC2_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_DDC3_SPEED 0x1592 -#define POL_mmDC_I2C_DDC3_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC3_SETUP 0x1593 -#define POL_mmDC_I2C_DDC3_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_DDC4_SPEED 0x1594 -#define POL_mmDC_I2C_DDC4_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC4_SETUP 0x1595 -#define POL_mmDC_I2C_DDC4_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_DDC5_SPEED 0x1596 -#define POL_mmDC_I2C_DDC5_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC5_SETUP 0x1597 -#define POL_mmDC_I2C_DDC5_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_DDC6_SPEED 0x1598 -#define POL_mmDC_I2C_DDC6_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDC6_SETUP 0x1599 -#define POL_mmDC_I2C_DDC6_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_TRANSACTION0 0x159a -#define POL_mmDC_I2C_TRANSACTION0_BASE_IDX 2 -#define POL_mmDC_I2C_TRANSACTION1 0x159b -#define POL_mmDC_I2C_TRANSACTION1_BASE_IDX 2 -#define POL_mmDC_I2C_TRANSACTION2 0x159c -#define POL_mmDC_I2C_TRANSACTION2_BASE_IDX 2 -#define POL_mmDC_I2C_TRANSACTION3 0x159d -#define POL_mmDC_I2C_TRANSACTION3_BASE_IDX 2 -#define POL_mmDC_I2C_DATA 0x159e -#define POL_mmDC_I2C_DATA_BASE_IDX 2 -#define POL_mmDC_I2C_DDCVGA_HW_STATUS 0x159f -#define POL_mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2 -#define POL_mmDC_I2C_DDCVGA_SPEED 0x15a0 -#define POL_mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2 -#define POL_mmDC_I2C_DDCVGA_SETUP 0x15a1 -#define POL_mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2 -#define POL_mmDC_I2C_EDID_DETECT_CTRL 0x15a2 -#define POL_mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 -#define POL_mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3 -#define POL_mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 -#define POL_mmGENERIC_I2C_CONTROL 0x15a4 -#define POL_mmGENERIC_I2C_CONTROL_BASE_IDX 2 -#define POL_mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5 -#define POL_mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmGENERIC_I2C_STATUS 0x15a6 -#define POL_mmGENERIC_I2C_STATUS_BASE_IDX 2 -#define POL_mmGENERIC_I2C_SPEED 0x15a7 -#define POL_mmGENERIC_I2C_SPEED_BASE_IDX 2 -#define POL_mmGENERIC_I2C_SETUP 0x15a8 -#define POL_mmGENERIC_I2C_SETUP_BASE_IDX 2 -#define POL_mmGENERIC_I2C_TRANSACTION 0x15a9 -#define POL_mmGENERIC_I2C_TRANSACTION_BASE_IDX 2 -#define POL_mmGENERIC_I2C_DATA 0x15aa -#define POL_mmGENERIC_I2C_DATA_BASE_IDX 2 -#define POL_mmGENERIC_I2C_PIN_SELECTION 0x15ab -#define POL_mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2 -#define POL_mmDCO_SCRATCH0 0x15b6 -#define POL_mmDCO_SCRATCH0_BASE_IDX 2 -#define POL_mmDCO_SCRATCH1 0x15b7 -#define POL_mmDCO_SCRATCH1_BASE_IDX 2 -#define POL_mmDCO_SCRATCH2 0x15b8 -#define POL_mmDCO_SCRATCH2_BASE_IDX 2 -#define POL_mmDCO_SCRATCH3 0x15b9 -#define POL_mmDCO_SCRATCH3_BASE_IDX 2 -#define POL_mmDCO_SCRATCH4 0x15ba -#define POL_mmDCO_SCRATCH4_BASE_IDX 2 -#define POL_mmDCO_SCRATCH5 0x15bb -#define POL_mmDCO_SCRATCH5_BASE_IDX 2 -#define POL_mmDCO_SCRATCH6 0x15bc -#define POL_mmDCO_SCRATCH6_BASE_IDX 2 -#define POL_mmDCO_SCRATCH7 0x15bd -#define POL_mmDCO_SCRATCH7_BASE_IDX 2 -#define POL_mmDCE_VCE_CONTROL 0x15be -#define POL_mmDCE_VCE_CONTROL_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS 0x15bf -#define POL_mmDISP_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 -#define POL_mmDCO_MEM_PWR_STATUS 0x15c9 -#define POL_mmDCO_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCO_MEM_PWR_CTRL 0x15ca -#define POL_mmDCO_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCO_MEM_PWR_CTRL2 0x15cb -#define POL_mmDCO_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCO_CLK_CNTL 0x15cc -#define POL_mmDCO_CLK_CNTL_BASE_IDX 2 -#define POL_mmDCO_POWER_MANAGEMENT_CNTL 0x15d0 -#define POL_mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 -#define POL_mmDIG_SOFT_RESET_2 0x15d2 -#define POL_mmDIG_SOFT_RESET_2_BASE_IDX 2 -#define POL_mmDCO_STEREOSYNC_SEL 0x15d6 -#define POL_mmDCO_STEREOSYNC_SEL_BASE_IDX 2 -#define POL_mmDCO_SOFT_RESET 0x15d9 -#define POL_mmDCO_SOFT_RESET_BASE_IDX 2 -#define POL_mmDIG_SOFT_RESET 0x15da -#define POL_mmDIG_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCO_MEM_PWR_STATUS1 0x15dc -#define POL_mmDCO_MEM_PWR_STATUS1_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 -#define POL_mmDCO_CLK_CNTL2 0x15de -#define POL_mmDCO_CLK_CNTL2_BASE_IDX 2 -#define POL_mmDCO_CLK_CNTL3 0x15df -#define POL_mmDCO_CLK_CNTL3_BASE_IDX 2 -#define POL_mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb -#define POL_mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 -#define POL_mmDCO_PSP_INTERRUPT_STATUS 0x15ec -#define POL_mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCO_PSP_INTERRUPT_CLEAR 0x15ed -#define POL_mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 -#define POL_mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee -#define POL_mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 -#define POL_mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef -#define POL_mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 -#define POL_mmFMT_MEMORY0_CONTROL 0x15f0 -#define POL_mmFMT_MEMORY0_CONTROL_BASE_IDX 2 -#define POL_mmFMT_MEMORY1_CONTROL 0x15f1 -#define POL_mmFMT_MEMORY1_CONTROL_BASE_IDX 2 -#define POL_mmFMT_MEMORY2_CONTROL 0x15f2 -#define POL_mmFMT_MEMORY2_CONTROL_BASE_IDX 2 -#define POL_mmFMT_MEMORY3_CONTROL 0x15f3 -#define POL_mmFMT_MEMORY3_CONTROL_BASE_IDX 2 -#define POL_mmFMT_MEMORY4_CONTROL 0x15f4 -#define POL_mmFMT_MEMORY4_CONTROL_BASE_IDX 2 -#define POL_mmFMT_MEMORY5_CONTROL 0x15f5 -#define POL_mmFMT_MEMORY5_CONTROL_BASE_IDX 2 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6 -#define POL_mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 -#define POL_mmDC_GENERICA 0x207e -#define POL_mmDC_GENERICA_BASE_IDX 2 -#define POL_mmDC_GENERICB 0x207f -#define POL_mmDC_GENERICB_BASE_IDX 2 -#define POL_mmDC_PAD_EXTERN_SIG 0x2080 -#define POL_mmDC_PAD_EXTERN_SIG_BASE_IDX 2 -#define POL_mmDC_REF_CLK_CNTL 0x2081 -#define POL_mmDC_REF_CLK_CNTL_BASE_IDX 2 -#define POL_mmDC_GPIO_DEBUG 0x2082 -#define POL_mmDC_GPIO_DEBUG_BASE_IDX 2 -#define POL_mmUNIPHYA_LINK_CNTL 0x2083 -#define POL_mmUNIPHYA_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084 -#define POL_mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYB_LINK_CNTL 0x2085 -#define POL_mmUNIPHYB_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086 -#define POL_mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYC_LINK_CNTL 0x2087 -#define POL_mmUNIPHYC_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088 -#define POL_mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYD_LINK_CNTL 0x2089 -#define POL_mmUNIPHYD_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a -#define POL_mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYE_LINK_CNTL 0x208b -#define POL_mmUNIPHYE_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c -#define POL_mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYF_LINK_CNTL 0x208d -#define POL_mmUNIPHYF_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e -#define POL_mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYG_LINK_CNTL 0x208f -#define POL_mmUNIPHYG_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090 -#define POL_mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmDCIO_WRCMD_DELAY 0x2094 -#define POL_mmDCIO_WRCMD_DELAY_BASE_IDX 2 -#define POL_mmDC_PINSTRAPS 0x2096 -#define POL_mmDC_PINSTRAPS_BASE_IDX 2 -#define POL_mmCC_DC_MISC_STRAPS 0x2097 -#define POL_mmCC_DC_MISC_STRAPS_BASE_IDX 2 -#define POL_mmDC_DVODATA_CONFIG 0x2098 -#define POL_mmDC_DVODATA_CONFIG_BASE_IDX 2 -#define POL_mmLVTMA_PWRSEQ_CNTL 0x2099 -#define POL_mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 -#define POL_mmLVTMA_PWRSEQ_STATE 0x209a -#define POL_mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 -#define POL_mmLVTMA_PWRSEQ_REF_DIV 0x209b -#define POL_mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 -#define POL_mmLVTMA_PWRSEQ_DELAY1 0x209c -#define POL_mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 -#define POL_mmLVTMA_PWRSEQ_DELAY2 0x209d -#define POL_mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 -#define POL_mmBL_PWM_CNTL 0x209e -#define POL_mmBL_PWM_CNTL_BASE_IDX 2 -#define POL_mmBL_PWM_CNTL2 0x209f -#define POL_mmBL_PWM_CNTL2_BASE_IDX 2 -#define POL_mmBL_PWM_PERIOD_CNTL 0x20a0 -#define POL_mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 -#define POL_mmBL_PWM_GRP1_REG_LOCK 0x20a1 -#define POL_mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 -#define POL_mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2 -#define POL_mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 -#define POL_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3 -#define POL_mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 -#define POL_mmDCIO_GSL0_CNTL 0x20a4 -#define POL_mmDCIO_GSL0_CNTL_BASE_IDX 2 -#define POL_mmDCIO_GSL1_CNTL 0x20a5 -#define POL_mmDCIO_GSL1_CNTL_BASE_IDX 2 -#define POL_mmDCIO_GSL2_CNTL 0x20a6 -#define POL_mmDCIO_GSL2_CNTL_BASE_IDX 2 -#define POL_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7 -#define POL_mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 -#define POL_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8 -#define POL_mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2 -#define POL_mmDC_GPU_TIMER_READ 0x20a9 -#define POL_mmDC_GPU_TIMER_READ_BASE_IDX 2 -#define POL_mmDC_GPU_TIMER_READ_CNTL 0x20aa -#define POL_mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 -#define POL_mmDCIO_CLOCK_CNTL 0x20ab -#define POL_mmDCIO_CLOCK_CNTL_BASE_IDX 2 -#define POL_mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae -#define POL_mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2 -#define POL_mmDCIO_SOFT_RESET 0x20b4 -#define POL_mmDCIO_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCIO_DPHY_SEL 0x20b5 -#define POL_mmDCIO_DPHY_SEL_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKA 0x20b6 -#define POL_mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKB 0x20b7 -#define POL_mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_PERIOD 0x20b8 -#define POL_mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2 -#define POL_mmAUXP_IMPCAL 0x20b9 -#define POL_mmAUXP_IMPCAL_BASE_IDX 2 -#define POL_mmAUXN_IMPCAL 0x20ba -#define POL_mmAUXN_IMPCAL_BASE_IDX 2 -#define POL_mmDCIO_IMPCAL_CNTL 0x20bb -#define POL_mmDCIO_IMPCAL_CNTL_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_PSW_AB 0x20bc -#define POL_mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKC 0x20bd -#define POL_mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKD 0x20be -#define POL_mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2 -#define POL_mmDCIO_IMPCAL_CNTL_CD 0x20bf -#define POL_mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_PSW_CD 0x20c0 -#define POL_mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKE 0x20c1 -#define POL_mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_LINKF 0x20c2 -#define POL_mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2 -#define POL_mmDCIO_IMPCAL_CNTL_EF 0x20c3 -#define POL_mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2 -#define POL_mmUNIPHY_IMPCAL_PSW_EF 0x20c4 -#define POL_mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2 -#define POL_mmUNIPHYLPA_LINK_CNTL 0x20c5 -#define POL_mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYLPB_LINK_CNTL 0x20c6 -#define POL_mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7 -#define POL_mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8 -#define POL_mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2 -#define POL_mmDCIO_DPCS_TX_INTERRUPT 0x20c9 -#define POL_mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2 -#define POL_mmDCIO_DPCS_RX_INTERRUPT 0x20ca -#define POL_mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE0 0x20cb -#define POL_mmDCIO_SEMAPHORE0_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE1 0x20cc -#define POL_mmDCIO_SEMAPHORE1_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE2 0x20cd -#define POL_mmDCIO_SEMAPHORE2_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE3 0x20ce -#define POL_mmDCIO_SEMAPHORE3_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE4 0x20cf -#define POL_mmDCIO_SEMAPHORE4_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE5 0x20d0 -#define POL_mmDCIO_SEMAPHORE5_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE6 0x20d1 -#define POL_mmDCIO_SEMAPHORE6_BASE_IDX 2 -#define POL_mmDCIO_SEMAPHORE7 0x20d2 -#define POL_mmDCIO_SEMAPHORE7_BASE_IDX 2 -#define POL_mmDC_GPIO_GENERIC_MASK 0x20de -#define POL_mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_GENERIC_A 0x20df -#define POL_mmDC_GPIO_GENERIC_A_BASE_IDX 2 -#define POL_mmDC_GPIO_GENERIC_EN 0x20e0 -#define POL_mmDC_GPIO_GENERIC_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_GENERIC_Y 0x20e1 -#define POL_mmDC_GPIO_GENERIC_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DVODATA_MASK 0x20e2 -#define POL_mmDC_GPIO_DVODATA_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DVODATA_A 0x20e3 -#define POL_mmDC_GPIO_DVODATA_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DVODATA_EN 0x20e4 -#define POL_mmDC_GPIO_DVODATA_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DVODATA_Y 0x20e5 -#define POL_mmDC_GPIO_DVODATA_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC1_MASK 0x20e6 -#define POL_mmDC_GPIO_DDC1_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC1_A 0x20e7 -#define POL_mmDC_GPIO_DDC1_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC1_EN 0x20e8 -#define POL_mmDC_GPIO_DDC1_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC1_Y 0x20e9 -#define POL_mmDC_GPIO_DDC1_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC2_MASK 0x20ea -#define POL_mmDC_GPIO_DDC2_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC2_A 0x20eb -#define POL_mmDC_GPIO_DDC2_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC2_EN 0x20ec -#define POL_mmDC_GPIO_DDC2_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC2_Y 0x20ed -#define POL_mmDC_GPIO_DDC2_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC3_MASK 0x20ee -#define POL_mmDC_GPIO_DDC3_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC3_A 0x20ef -#define POL_mmDC_GPIO_DDC3_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC3_EN 0x20f0 -#define POL_mmDC_GPIO_DDC3_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC3_Y 0x20f1 -#define POL_mmDC_GPIO_DDC3_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC4_MASK 0x20f2 -#define POL_mmDC_GPIO_DDC4_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC4_A 0x20f3 -#define POL_mmDC_GPIO_DDC4_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC4_EN 0x20f4 -#define POL_mmDC_GPIO_DDC4_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC4_Y 0x20f5 -#define POL_mmDC_GPIO_DDC4_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC5_MASK 0x20f6 -#define POL_mmDC_GPIO_DDC5_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC5_A 0x20f7 -#define POL_mmDC_GPIO_DDC5_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC5_EN 0x20f8 -#define POL_mmDC_GPIO_DDC5_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC5_Y 0x20f9 -#define POL_mmDC_GPIO_DDC5_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC6_MASK 0x20fa -#define POL_mmDC_GPIO_DDC6_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC6_A 0x20fb -#define POL_mmDC_GPIO_DDC6_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC6_EN 0x20fc -#define POL_mmDC_GPIO_DDC6_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDC6_Y 0x20fd -#define POL_mmDC_GPIO_DDC6_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_DDCVGA_MASK 0x20fe -#define POL_mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_DDCVGA_A 0x20ff -#define POL_mmDC_GPIO_DDCVGA_A_BASE_IDX 2 -#define POL_mmDC_GPIO_DDCVGA_EN 0x2100 -#define POL_mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_DDCVGA_Y 0x2101 -#define POL_mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_SYNCA_MASK 0x2102 -#define POL_mmDC_GPIO_SYNCA_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_SYNCA_A 0x2103 -#define POL_mmDC_GPIO_SYNCA_A_BASE_IDX 2 -#define POL_mmDC_GPIO_SYNCA_EN 0x2104 -#define POL_mmDC_GPIO_SYNCA_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_SYNCA_Y 0x2105 -#define POL_mmDC_GPIO_SYNCA_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_GENLK_MASK 0x2106 -#define POL_mmDC_GPIO_GENLK_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_GENLK_A 0x2107 -#define POL_mmDC_GPIO_GENLK_A_BASE_IDX 2 -#define POL_mmDC_GPIO_GENLK_EN 0x2108 -#define POL_mmDC_GPIO_GENLK_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_GENLK_Y 0x2109 -#define POL_mmDC_GPIO_GENLK_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_HPD_MASK 0x210a -#define POL_mmDC_GPIO_HPD_MASK_BASE_IDX 2 #define POL_mmDC_GPIO_HPD_A 0x210b -#define POL_mmDC_GPIO_HPD_A_BASE_IDX 2 -#define POL_mmDC_GPIO_HPD_EN 0x210c -#define POL_mmDC_GPIO_HPD_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_HPD_Y 0x210d -#define POL_mmDC_GPIO_HPD_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_PWRSEQ_MASK 0x210e -#define POL_mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_PWRSEQ_A 0x210f -#define POL_mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 -#define POL_mmDC_GPIO_PWRSEQ_EN 0x2110 -#define POL_mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_PWRSEQ_Y 0x2111 -#define POL_mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_PAD_STRENGTH_1 0x2112 -#define POL_mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 -#define POL_mmDC_GPIO_PAD_STRENGTH_2 0x2113 -#define POL_mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 -#define POL_mmPHY_AUX_CNTL 0x2115 -#define POL_mmPHY_AUX_CNTL_BASE_IDX 2 -#define POL_mmDC_GPIO_I2CPAD_MASK 0x2116 -#define POL_mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_I2CPAD_A 0x2117 -#define POL_mmDC_GPIO_I2CPAD_A_BASE_IDX 2 -#define POL_mmDC_GPIO_I2CPAD_EN 0x2118 -#define POL_mmDC_GPIO_I2CPAD_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_I2CPAD_Y 0x2119 -#define POL_mmDC_GPIO_I2CPAD_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_I2CPAD_STRENGTH 0x211a -#define POL_mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2 -#define POL_mmDVO_STRENGTH_CONTROL 0x211b -#define POL_mmDVO_STRENGTH_CONTROL_BASE_IDX 2 -#define POL_mmDVO_VREF_CONTROL 0x211c -#define POL_mmDVO_VREF_CONTROL_BASE_IDX 2 -#define POL_mmDVO_SKEW_ADJUST 0x211d -#define POL_mmDVO_SKEW_ADJUST_BASE_IDX 2 -#define POL_mmDC_GPIO_I2S_SPDIF_MASK 0x2126 -#define POL_mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2 -#define POL_mmDC_GPIO_I2S_SPDIF_A 0x2127 -#define POL_mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2 -#define POL_mmDC_GPIO_I2S_SPDIF_EN 0x2128 -#define POL_mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_I2S_SPDIF_Y 0x2129 -#define POL_mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2 -#define POL_mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a -#define POL_mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2 -#define POL_mmDC_GPIO_TX12_EN 0x212b -#define POL_mmDC_GPIO_TX12_EN_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_0 0x212c -#define POL_mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_1 0x212d -#define POL_mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_2 0x212e -#define POL_mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 -#define POL_mmDC_GPIO_RXEN 0x212f -#define POL_mmDC_GPIO_RXEN_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_3 0x2130 -#define POL_mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_4 0x2131 -#define POL_mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_5 0x2132 -#define POL_mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 -#define POL_mmAUXI2C_PAD_ALL_PWR_OK 0x2133 -#define POL_mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 -#define POL_mmDC_GPIO_PULLUPEN 0x2134 -#define POL_mmDC_GPIO_PULLUPEN_BASE_IDX 2 -#define POL_mmDC_GPIO_AUX_CTRL_6 0x2135 -#define POL_mmDC_GPIO_AUX_CTRL_6_BASE_IDX 2 -#define POL_mmBPHYC_DAC_MACRO_CNTL 0x2136 -#define POL_mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2 -#define POL_mmDAC_MACRO_CNTL_RESERVED0 0x2136 -#define POL_mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137 -#define POL_mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2 -#define POL_mmDAC_MACRO_CNTL_RESERVED1 0x2137 -#define POL_mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDAC_MACRO_CNTL_RESERVED2 0x2138 -#define POL_mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDAC_MACRO_CNTL_RESERVED3 0x2139 -#define POL_mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDISP_DSI_DUAL_CTRL 0x277e -#define POL_mmDISP_DSI_DUAL_CTRL_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED0 0x283e -#define POL_mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED1 0x283f -#define POL_mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED2 0x2840 -#define POL_mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED3 0x2841 -#define POL_mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED4 0x2842 -#define POL_mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED5 0x2843 -#define POL_mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED6 0x2844 -#define POL_mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED7 0x2845 -#define POL_mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED8 0x2846 -#define POL_mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED9 0x2847 -#define POL_mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED10 0x2848 -#define POL_mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED11 0x2849 -#define POL_mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED12 0x284a -#define POL_mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED13 0x284b -#define POL_mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED14 0x284c -#define POL_mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED15 0x284d -#define POL_mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED16 0x284e -#define POL_mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED17 0x284f -#define POL_mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED18 0x2850 -#define POL_mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED19 0x2851 -#define POL_mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED20 0x2852 -#define POL_mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED21 0x2853 -#define POL_mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED22 0x2854 -#define POL_mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED23 0x2855 -#define POL_mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED24 0x2856 -#define POL_mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED25 0x2857 -#define POL_mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED26 0x2858 -#define POL_mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED27 0x2859 -#define POL_mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED28 0x285a -#define POL_mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED29 0x285b -#define POL_mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED30 0x285c -#define POL_mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED31 0x285d -#define POL_mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED32 0x285e -#define POL_mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED33 0x285f -#define POL_mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED34 0x2860 -#define POL_mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED35 0x2861 -#define POL_mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED36 0x2862 -#define POL_mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED37 0x2863 -#define POL_mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED38 0x2864 -#define POL_mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED39 0x2865 -#define POL_mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED40 0x2866 -#define POL_mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED41 0x2867 -#define POL_mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED42 0x2868 -#define POL_mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED43 0x2869 -#define POL_mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED44 0x286a -#define POL_mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED45 0x286b -#define POL_mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED46 0x286c -#define POL_mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED47 0x286d -#define POL_mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED48 0x286e -#define POL_mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED49 0x286f -#define POL_mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED50 0x2870 -#define POL_mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED51 0x2871 -#define POL_mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED52 0x2872 -#define POL_mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED53 0x2873 -#define POL_mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED54 0x2874 -#define POL_mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED55 0x2875 -#define POL_mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED56 0x2876 -#define POL_mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED57 0x2877 -#define POL_mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED58 0x2878 -#define POL_mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED59 0x2879 -#define POL_mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED60 0x287a -#define POL_mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED61 0x287b -#define POL_mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED62 0x287c -#define POL_mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDPHY_MACRO_CNTL_RESERVED63 0x287d -#define POL_mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e -#define POL_mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2 -#define POL_mmDPRX_AUX_CONTROL 0x2a7f -#define POL_mmDPRX_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_AUX_HPD_CONTROL1 0x2a80 -#define POL_mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2 -#define POL_mmDPRX_AUX_HPD_CONTROL2 0x2a81 -#define POL_mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2 -#define POL_mmDPRX_AUX_RX_STATUS 0x2a82 -#define POL_mmDPRX_AUX_RX_STATUS_BASE_IDX 2 -#define POL_mmDPRX_AUX_RX_ERROR_MASK 0x2a83 -#define POL_mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84 -#define POL_mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85 -#define POL_mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86 -#define POL_mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87 -#define POL_mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_TX_STATUS 0x2a88 -#define POL_mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPHY_RX_STATUS 0x2a89 -#define POL_mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a -#define POL_mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2 -#define POL_mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b -#define POL_mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2 -#define POL_mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c -#define POL_mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2 -#define POL_mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d -#define POL_mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2 -#define POL_mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e -#define POL_mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2 -#define POL_mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f -#define POL_mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2 -#define POL_mmDPRX_AUX_AUX_BUF_INDEX 0x2a90 -#define POL_mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2 -#define POL_mmDPRX_AUX_AUX_BUF_DATA 0x2a91 -#define POL_mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2 -#define POL_mmDPRX_AUX_EDID_INDEX 0x2a92 -#define POL_mmDPRX_AUX_EDID_INDEX_BASE_IDX 2 -#define POL_mmDPRX_AUX_EDID_DATA 0x2a93 -#define POL_mmDPRX_AUX_EDID_DATA_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPCD_INDEX1 0x2a94 -#define POL_mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPCD_DATA1 0x2a95 -#define POL_mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPCD_INDEX2 0x2a96 -#define POL_mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2 -#define POL_mmDPRX_AUX_DPCD_DATA2 0x2a97 -#define POL_mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_INDEX1 0x2a98 -#define POL_mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_DATA1 0x2a99 -#define POL_mmDPRX_AUX_MSG_DATA1_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_INDEX2 0x2a9a -#define POL_mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_DATA2 0x2a9b -#define POL_mmDPRX_AUX_MSG_DATA2_BASE_IDX 2 -#define POL_mmDPRX_AUX_KSV_INDEX1 0x2a9c -#define POL_mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2 -#define POL_mmDPRX_AUX_KSV_DATA1 0x2a9d -#define POL_mmDPRX_AUX_KSV_DATA1_BASE_IDX 2 -#define POL_mmDPRX_AUX_KSV_INDEX2 0x2a9e -#define POL_mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2 -#define POL_mmDPRX_AUX_KSV_DATA2 0x2a9f -#define POL_mmDPRX_AUX_KSV_DATA2_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0 -#define POL_mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1 -#define POL_mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2 -#define POL_mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2 -#define POL_mmDPRX_AUX_SCRATCH1 0x2aa3 -#define POL_mmDPRX_AUX_SCRATCH1_BASE_IDX 2 -#define POL_mmDPRX_AUX_SCRATCH2 0x2aa4 -#define POL_mmDPRX_AUX_SCRATCH2_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG1_PENDING 0x2aa5 -#define POL_mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG2_PENDING 0x2aa6 -#define POL_mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG3_PENDING 0x2aa7 -#define POL_mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2 -#define POL_mmDPRX_AUX_MSG4_PENDING 0x2aa8 -#define POL_mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe -#define POL_mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff -#define POL_mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00 -#define POL_mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08 -#define POL_mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_READY 0x2b09 -#define POL_mmDPRX_DPHY_READY_BASE_IDX 2 -#define POL_mmDPRX_DPHY_COMMA_STATUS 0x2b0b -#define POL_mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c -#define POL_mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d -#define POL_mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e -#define POL_mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20 -#define POL_mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21 -#define POL_mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22 -#define POL_mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2 -#define POL_mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24 -#define POL_mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2 -#define POL_mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25 -#define POL_mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2 -#define POL_mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27 -#define POL_mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2 -#define POL_mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28 -#define POL_mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LANESETUP0 0x2b2d -#define POL_mmDPRX_DPHY_LANESETUP0_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LANESETUP1 0x2b2e -#define POL_mmDPRX_DPHY_LANESETUP1_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LFSRADV 0x2b31 -#define POL_mmDPRX_DPHY_LFSRADV_BASE_IDX 2 -#define POL_mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32 -#define POL_mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2 -#define POL_mmDPRX_DPHY_SET_ENABLE 0x2b33 -#define POL_mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ECF_LSB 0x2b34 -#define POL_mmDPRX_DPHY_ECF_LSB_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ECF_MSB 0x2b35 -#define POL_mmDPRX_DPHY_ECF_MSB_BASE_IDX 2 -#define POL_mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36 -#define POL_mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2 -#define POL_mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c -#define POL_mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d -#define POL_mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e -#define POL_mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_DPHY_BYPASS 0x2b3f -#define POL_mmDPRX_DPHY_BYPASS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_INT_RESET 0x2b40 -#define POL_mmDPRX_DPHY_INT_RESET_BASE_IDX 2 -#define POL_mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41 -#define POL_mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43 -#define POL_mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44 -#define POL_mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46 -#define POL_mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48 -#define POL_mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49 -#define POL_mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a -#define POL_mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b -#define POL_mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c -#define POL_mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2 -#define POL_mmDPRX_DPHY_SPARE 0x2b4d -#define POL_mmDPRX_DPHY_SPARE_BASE_IDX 2 -#define POL_mmDCRX_GATE_DISABLE_CNTL 0x2b6e -#define POL_mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2 -#define POL_mmDCRX_SOFT_RESET 0x2b6f -#define POL_mmDCRX_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCRX_LIGHT_SLEEP_CNTL 0x2b70 -#define POL_mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2 -#define POL_mmDCRX_DISPCLK_GATE_CNTL 0x2b73 -#define POL_mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2 -#define POL_mmDCRX_CLK_CNTL 0x2b74 -#define POL_mmDCRX_CLK_CNTL_BASE_IDX 2 -#define POL_mmDCRX_TEST_CLK_CNTL 0x2b75 -#define POL_mmDCRX_TEST_CLK_CNTL_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81 -#define POL_mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2 -#define POL_mmI2S0_CNTL 0x2d82 -#define POL_mmI2S0_CNTL_BASE_IDX 2 -#define POL_mmSPDIF0_CNTL 0x2d83 -#define POL_mmSPDIF0_CNTL_BASE_IDX 2 -#define POL_mmI2S1_CNTL 0x2d84 -#define POL_mmI2S1_CNTL_BASE_IDX 2 -#define POL_mmSPDIF1_CNTL 0x2d85 -#define POL_mmSPDIF1_CNTL_BASE_IDX 2 -#define POL_mmI2S0_STATUS 0x2d86 -#define POL_mmI2S0_STATUS_BASE_IDX 2 -#define POL_mmI2S1_STATUS 0x2d87 -#define POL_mmI2S1_STATUS_BASE_IDX 2 -#define POL_mmI2S0_CRC_TEST_CNTL 0x2d8a -#define POL_mmI2S0_CRC_TEST_CNTL_BASE_IDX 2 -#define POL_mmI2S0_CRC_TEST_DATA_01 0x2d8b -#define POL_mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2 -#define POL_mmI2S0_CRC_TEST_DATA_23 0x2d8c -#define POL_mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2 -#define POL_mmI2S1_CRC_TEST_CNTL 0x2d8d -#define POL_mmI2S1_CRC_TEST_CNTL_BASE_IDX 2 -#define POL_mmI2S1_CRC_TEST_DATA_0 0x2d8e -#define POL_mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2 -#define POL_mmSPDIF0_CRC_TEST_CNTL 0x2d8f -#define POL_mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2 -#define POL_mmSPDIF0_CRC_TEST_DATA_0 0x2d90 -#define POL_mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2 -#define POL_mmSPDIF1_CRC_TEST_CNTL 0x2d91 -#define POL_mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2 -#define POL_mmSPDIF1_CRC_TEST_DATA 0x2d92 -#define POL_mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2 -#define POL_mmCRC_I2S_CONT_REPEAT_NUM 0x2d93 -#define POL_mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2 -#define POL_mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94 -#define POL_mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2 -#define POL_mmZCAL_MACRO_CNTL_RESERVED0 0x2d96 -#define POL_mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmZCAL_MACRO_CNTL_RESERVED1 0x2d97 -#define POL_mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmZCAL_MACRO_CNTL_RESERVED2 0x2d98 -#define POL_mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmZCAL_MACRO_CNTL_RESERVED3 0x2d99 -#define POL_mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a -#define POL_mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream0_dispdec -// base address: 0x0 -#define POL_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458 -#define POL_mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459 -#define POL_mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream1_dispdec -// base address: 0x8 -#define POL_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a -#define POL_mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b -#define POL_mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream2_dispdec -// base address: 0x10 -#define POL_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c -#define POL_mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d -#define POL_mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream3_dispdec -// base address: 0x18 -#define POL_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e -#define POL_mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f -#define POL_mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream4_dispdec -// base address: 0x20 -#define POL_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460 -#define POL_mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461 -#define POL_mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream5_dispdec -// base address: 0x28 -#define POL_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462 -#define POL_mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463 -#define POL_mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream6_dispdec -// base address: 0x30 -#define POL_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464 -#define POL_mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465 -#define POL_mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream7_dispdec -// base address: 0x38 -#define POL_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466 -#define POL_mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467 -#define POL_mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint0_dispdec -// base address: 0x0 -#define POL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480 -#define POL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481 -#define POL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint1_dispdec -// base address: 0x18 -#define POL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486 -#define POL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487 -#define POL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint2_dispdec -// base address: 0x30 -#define POL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c -#define POL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d -#define POL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint3_dispdec -// base address: 0x48 -#define POL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492 -#define POL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493 -#define POL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint4_dispdec -// base address: 0x60 -#define POL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498 -#define POL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499 -#define POL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint5_dispdec -// base address: 0x78 -#define POL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e -#define POL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f -#define POL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint6_dispdec -// base address: 0x90 -#define POL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4 -#define POL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5 -#define POL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0endpoint7_dispdec -// base address: 0xa8 -#define POL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa -#define POL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab -#define POL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream8_dispdec -// base address: 0x320 -#define POL_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520 -#define POL_mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521 -#define POL_mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream9_dispdec -// base address: 0x328 -#define POL_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522 -#define POL_mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523 -#define POL_mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream10_dispdec -// base address: 0x330 -#define POL_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524 -#define POL_mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525 -#define POL_mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream11_dispdec -// base address: 0x338 -#define POL_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526 -#define POL_mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527 -#define POL_mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream12_dispdec -// base address: 0x340 -#define POL_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528 -#define POL_mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529 -#define POL_mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream13_dispdec -// base address: 0x348 -#define POL_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a -#define POL_mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b -#define POL_mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream14_dispdec -// base address: 0x350 -#define POL_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c -#define POL_mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d -#define POL_mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0stream15_dispdec -// base address: 0x358 -#define POL_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e -#define POL_mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 -#define POL_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f -#define POL_mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint0_dispdec -// base address: 0x0 -#define POL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534 -#define POL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535 -#define POL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint1_dispdec -// base address: 0x10 -#define POL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538 -#define POL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539 -#define POL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint2_dispdec -// base address: 0x20 -#define POL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c -#define POL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d -#define POL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint3_dispdec -// base address: 0x30 -#define POL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540 -#define POL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541 -#define POL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint4_dispdec -// base address: 0x40 -#define POL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544 -#define POL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545 -#define POL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint5_dispdec -// base address: 0x50 -#define POL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548 -#define POL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549 -#define POL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint6_dispdec -// base address: 0x60 -#define POL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c -#define POL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d -#define POL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_azf0inputendpoint7_dispdec -// base address: 0x70 -#define POL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550 -#define POL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 -#define POL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551 -#define POL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp0_dispdec -// base address: 0x0 -#define POL_mmDCP0_GRPH_ENABLE 0x055a -#define POL_mmDCP0_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP0_GRPH_CONTROL 0x055b -#define POL_mmDCP0_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c -#define POL_mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SWAP_CNTL 0x055d -#define POL_mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e -#define POL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f -#define POL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_PITCH 0x0560 -#define POL_mmDCP0_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561 -#define POL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562 -#define POL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563 -#define POL_mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564 -#define POL_mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP0_GRPH_X_START 0x0565 -#define POL_mmDCP0_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP0_GRPH_Y_START 0x0566 -#define POL_mmDCP0_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP0_GRPH_X_END 0x0567 -#define POL_mmDCP0_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP0_GRPH_Y_END 0x0568 -#define POL_mmDCP0_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP0_INPUT_GAMMA_CONTROL 0x0569 -#define POL_mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_UPDATE 0x056a -#define POL_mmDCP0_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP0_GRPH_FLIP_CONTROL 0x056b -#define POL_mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c -#define POL_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP0_GRPH_DFQ_CONTROL 0x056d -#define POL_mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_DFQ_STATUS 0x056e -#define POL_mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_INTERRUPT_STATUS 0x056f -#define POL_mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570 -#define POL_mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571 -#define POL_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572 -#define POL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_COMPRESS_PITCH 0x0573 -#define POL_mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574 -#define POL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575 -#define POL_mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP0_PRESCALE_GRPH_CONTROL 0x0576 -#define POL_mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579 -#define POL_mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_CONTROL 0x057a -#define POL_mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C11_C12 0x057b -#define POL_mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C13_C14 0x057c -#define POL_mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C21_C22 0x057d -#define POL_mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C23_C24 0x057e -#define POL_mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C31_C32 0x057f -#define POL_mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP0_INPUT_CSC_C33_C34 0x0580 -#define POL_mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_CONTROL 0x0581 -#define POL_mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C11_C12 0x0582 -#define POL_mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C13_C14 0x0583 -#define POL_mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C21_C22 0x0584 -#define POL_mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C23_C24 0x0585 -#define POL_mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C31_C32 0x0586 -#define POL_mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP0_OUTPUT_CSC_C33_C34 0x0587 -#define POL_mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d -#define POL_mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593 -#define POL_mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP0_DENORM_CONTROL 0x0594 -#define POL_mmDCP0_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_OUT_ROUND_CONTROL 0x0595 -#define POL_mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598 -#define POL_mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP0_KEY_CONTROL 0x0599 -#define POL_mmDCP0_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_KEY_RANGE_ALPHA 0x059a -#define POL_mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP0_KEY_RANGE_RED 0x059b -#define POL_mmDCP0_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP0_KEY_RANGE_GREEN 0x059c -#define POL_mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP0_KEY_RANGE_BLUE 0x059d -#define POL_mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP0_DEGAMMA_CONTROL 0x059e -#define POL_mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_CONTROL 0x059f -#define POL_mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C11_C12 0x05a0 -#define POL_mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C13_C14 0x05a1 -#define POL_mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C21_C22 0x05a2 -#define POL_mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C23_C24 0x05a3 -#define POL_mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C31_C32 0x05a4 -#define POL_mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP0_GAMUT_REMAP_C33_C34 0x05a5 -#define POL_mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6 -#define POL_mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP0_DCP_RANDOM_SEEDS 0x05a7 -#define POL_mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8 -#define POL_mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP0_CUR_CONTROL 0x05a9 -#define POL_mmDCP0_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_CUR_SURFACE_ADDRESS 0x05aa -#define POL_mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP0_CUR_SIZE 0x05ab -#define POL_mmDCP0_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac -#define POL_mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP0_CUR_POSITION 0x05ad -#define POL_mmDCP0_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP0_CUR_HOT_SPOT 0x05ae -#define POL_mmDCP0_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP0_CUR_COLOR1 0x05af -#define POL_mmDCP0_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP0_CUR_COLOR2 0x05b0 -#define POL_mmDCP0_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP0_CUR_UPDATE 0x05b1 -#define POL_mmDCP0_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb -#define POL_mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP0_CUR_STEREO_CONTROL 0x05bc -#define POL_mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_RW_MODE 0x05be -#define POL_mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_RW_INDEX 0x05bf -#define POL_mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_SEQ_COLOR 0x05c0 -#define POL_mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_PWL_DATA 0x05c1 -#define POL_mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_30_COLOR 0x05c2 -#define POL_mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3 -#define POL_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4 -#define POL_mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_AUTOFILL 0x05c5 -#define POL_mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_CONTROL 0x05c6 -#define POL_mmDCP0_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9 -#define POL_mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc -#define POL_mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP0_DCP_CRC_CONTROL 0x05cd -#define POL_mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_DCP_CRC_MASK 0x05ce -#define POL_mmDCP0_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP0_DCP_CRC_CURRENT 0x05cf -#define POL_mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP0_DVMM_PTE_CONTROL 0x05d0 -#define POL_mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_DCP_CRC_LAST 0x05d1 -#define POL_mmDCP0_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2 -#define POL_mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4 -#define POL_mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP0_DCP_GSL_CONTROL 0x05d5 -#define POL_mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6 -#define POL_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc -#define POL_mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP0_HW_ROTATION 0x05de -#define POL_mmDCP0_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df -#define POL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CONTROL 0x05e0 -#define POL_mmDCP0_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_LUT_INDEX 0x05e1 -#define POL_mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_LUT_DATA 0x05e2 -#define POL_mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3 -#define POL_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4 -#define POL_mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5 -#define POL_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6 -#define POL_mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7 -#define POL_mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef -#define POL_mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0 -#define POL_mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1 -#define POL_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2 -#define POL_mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3 -#define POL_mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb -#define POL_mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP0_ALPHA_CONTROL 0x05fc -#define POL_mmDCP0_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd -#define POL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe -#define POL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff -#define POL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600 -#define POL_mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601 -#define POL_mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602 -#define POL_mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603 -#define POL_mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb0_dispdec -// base address: 0x0 -#define POL_mmLB0_LB_DATA_FORMAT 0x061a -#define POL_mmLB0_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB0_LB_MEMORY_CTRL 0x061b -#define POL_mmLB0_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB0_LB_MEMORY_SIZE_STATUS 0x061c -#define POL_mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_DESKTOP_HEIGHT 0x061d -#define POL_mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB0_LB_VLINE_START_END 0x061e -#define POL_mmLB0_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB0_LB_VLINE2_START_END 0x061f -#define POL_mmLB0_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB0_LB_V_COUNTER 0x0620 -#define POL_mmLB0_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621 -#define POL_mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB0_LB_INTERRUPT_MASK 0x0622 -#define POL_mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB0_LB_VLINE_STATUS 0x0623 -#define POL_mmLB0_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_VLINE2_STATUS 0x0624 -#define POL_mmLB0_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_VBLANK_STATUS 0x0625 -#define POL_mmLB0_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_SYNC_RESET_SEL 0x0626 -#define POL_mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB0_LB_BLACK_KEYER_R_CR 0x0627 -#define POL_mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB0_LB_BLACK_KEYER_G_Y 0x0628 -#define POL_mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB0_LB_BLACK_KEYER_B_CB 0x0629 -#define POL_mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_CTRL 0x062a -#define POL_mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_R_CR 0x062b -#define POL_mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_G_Y 0x062c -#define POL_mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_B_CB 0x062d -#define POL_mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e -#define POL_mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f -#define POL_mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630 -#define POL_mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631 -#define POL_mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632 -#define POL_mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633 -#define POL_mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_BUFFER_STATUS 0x0634 -#define POL_mmLB0_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635 -#define POL_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB0_MVP_AFR_FLIP_MODE 0x0636 -#define POL_mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637 -#define POL_mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638 -#define POL_mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB0_DC_MVP_LB_CONTROL 0x0639 -#define POL_mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe0_dispdec -// base address: 0x0 -#define POL_mmDCFE0_DCFE_CLOCK_CONTROL 0x065a -#define POL_mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_SOFT_RESET 0x065b -#define POL_mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d -#define POL_mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e -#define POL_mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f -#define POL_mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_MISC 0x0660 -#define POL_mmDCFE0_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE0_DCFE_FLUSH 0x0661 -#define POL_mmDCFE0_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon3_dispdec -// base address: 0x1938 -#define POL_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e -#define POL_mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f -#define POL_mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670 -#define POL_mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_CNTL 0x0671 -#define POL_mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_CNTL2 0x0672 -#define POL_mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673 -#define POL_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674 -#define POL_mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_HI 0x0675 -#define POL_mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON3_PERFMON_LOW 0x0676 -#define POL_mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg0_dispdec -// base address: 0x0 -#define POL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a -#define POL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b -#define POL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c -#define POL_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d -#define POL_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e -#define POL_mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f -#define POL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680 -#define POL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681 -#define POL_mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682 -#define POL_mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686 -#define POL_mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG0_DPG_DVMM_STATUS 0x0687 -#define POL_mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl0_dispdec -// base address: 0x0 -#define POL_mmSCL0_SCL_COEF_RAM_SELECT 0x069a -#define POL_mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b -#define POL_mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL0_SCL_MODE 0x069c -#define POL_mmSCL0_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL0_SCL_TAP_CONTROL 0x069d -#define POL_mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_CONTROL 0x069e -#define POL_mmSCL0_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_BYPASS_CONTROL 0x069f -#define POL_mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0 -#define POL_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1 -#define POL_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2 -#define POL_mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3 -#define POL_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4 -#define POL_mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5 -#define POL_mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6 -#define POL_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL0_SCL_VERT_FILTER_INIT 0x06a7 -#define POL_mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8 -#define POL_mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL0_SCL_ROUND_OFFSET 0x06a9 -#define POL_mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL0_SCL_UPDATE 0x06aa -#define POL_mmSCL0_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL0_SCL_F_SHARP_CONTROL 0x06ab -#define POL_mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_ALU_CONTROL 0x06ac -#define POL_mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad -#define POL_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL0_VIEWPORT_START_SECONDARY 0x06ae -#define POL_mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL0_VIEWPORT_START 0x06af -#define POL_mmSCL0_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL0_VIEWPORT_SIZE 0x06b0 -#define POL_mmSCL0_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1 -#define POL_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2 -#define POL_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5 -#define POL_mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6 -#define POL_mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd0_dispdec -// base address: 0x0 -#define POL_mmBLND0_BLND_CONTROL 0x06c7 -#define POL_mmBLND0_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND0_BLND_SM_CONTROL2 0x06c8 -#define POL_mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND0_BLND_CONTROL2 0x06c9 -#define POL_mmBLND0_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND0_BLND_UPDATE 0x06ca -#define POL_mmBLND0_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb -#define POL_mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND0_BLND_V_UPDATE_LOCK 0x06cc -#define POL_mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd -#define POL_mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc0_dispdec -// base address: 0x0 -#define POL_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2 -#define POL_mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_TOTAL 0x06d3 -#define POL_mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_BLANK_START_END 0x06d4 -#define POL_mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_SYNC_A 0x06d5 -#define POL_mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6 -#define POL_mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_SYNC_B 0x06d7 -#define POL_mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8 -#define POL_mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VBI_END 0x06d9 -#define POL_mmCRTC0_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_TOTAL 0x06da -#define POL_mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_TOTAL_MIN 0x06db -#define POL_mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc -#define POL_mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd -#define POL_mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de -#define POL_mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df -#define POL_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_BLANK_START_END 0x06e0 -#define POL_mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_SYNC_A 0x06e1 -#define POL_mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2 -#define POL_mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_SYNC_B 0x06e3 -#define POL_mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4 -#define POL_mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5 -#define POL_mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6 -#define POL_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TRIGA_CNTL 0x06e7 -#define POL_mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8 -#define POL_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TRIGB_CNTL 0x06e9 -#define POL_mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea -#define POL_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb -#define POL_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_FLOW_CONTROL 0x06ec -#define POL_mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed -#define POL_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee -#define POL_mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CONTROL 0x06ef -#define POL_mmCRTC0_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_BLANK_CONTROL 0x06f0 -#define POL_mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1 -#define POL_mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2 -#define POL_mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3 -#define POL_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4 -#define POL_mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5 -#define POL_mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATUS 0x06f6 -#define POL_mmCRTC0_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATUS_POSITION 0x06f7 -#define POL_mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8 -#define POL_mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9 -#define POL_mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa -#define POL_mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb -#define POL_mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_COUNT_CONTROL 0x06fc -#define POL_mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_COUNT_RESET 0x06fd -#define POL_mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe -#define POL_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff -#define POL_mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STEREO_STATUS 0x0700 -#define POL_mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STEREO_CONTROL 0x0701 -#define POL_mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702 -#define POL_mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703 -#define POL_mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704 -#define POL_mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705 -#define POL_mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_START_LINE_CONTROL 0x0706 -#define POL_mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707 -#define POL_mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_UPDATE_LOCK 0x0708 -#define POL_mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709 -#define POL_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a -#define POL_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b -#define POL_mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c -#define POL_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d -#define POL_mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e -#define POL_mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f -#define POL_mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710 -#define POL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711 -#define POL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MVP_STATUS 0x0712 -#define POL_mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_MASTER_EN 0x0713 -#define POL_mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714 -#define POL_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715 -#define POL_mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717 -#define POL_mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718 -#define POL_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719 -#define POL_mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a -#define POL_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_BLACK_COLOR 0x071b -#define POL_mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c -#define POL_mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722 -#define POL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC_CNTL 0x0723 -#define POL_mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727 -#define POL_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_DATA_RG 0x0728 -#define POL_mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC0_DATA_B 0x0729 -#define POL_mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a -#define POL_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b -#define POL_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c -#define POL_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d -#define POL_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_DATA_RG 0x072e -#define POL_mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_CRC1_DATA_B 0x072f -#define POL_mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735 -#define POL_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736 -#define POL_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737 -#define POL_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738 -#define POL_mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_GSL_WINDOW 0x0739 -#define POL_mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_GSL_CONTROL 0x073a -#define POL_mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d -#define POL_mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC0_CRTC_DRR_CONTROL 0x073e -#define POL_mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt0_dispdec -// base address: 0x0 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744 -#define POL_mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745 -#define POL_mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT0_FMT_CONTROL 0x0746 -#define POL_mmFMT0_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747 -#define POL_mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748 -#define POL_mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749 -#define POL_mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a -#define POL_mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT0_FMT_CLAMP_CNTL 0x074e -#define POL_mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT0_FMT_CRC_CNTL 0x074f -#define POL_mmFMT0_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750 -#define POL_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751 -#define POL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752 -#define POL_mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753 -#define POL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754 -#define POL_mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755 -#define POL_mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp1_dispdec -// base address: 0x800 -#define POL_mmDCP1_GRPH_ENABLE 0x075a -#define POL_mmDCP1_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP1_GRPH_CONTROL 0x075b -#define POL_mmDCP1_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c -#define POL_mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SWAP_CNTL 0x075d -#define POL_mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e -#define POL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f -#define POL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_PITCH 0x0760 -#define POL_mmDCP1_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761 -#define POL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762 -#define POL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763 -#define POL_mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764 -#define POL_mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP1_GRPH_X_START 0x0765 -#define POL_mmDCP1_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP1_GRPH_Y_START 0x0766 -#define POL_mmDCP1_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP1_GRPH_X_END 0x0767 -#define POL_mmDCP1_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP1_GRPH_Y_END 0x0768 -#define POL_mmDCP1_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP1_INPUT_GAMMA_CONTROL 0x0769 -#define POL_mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_UPDATE 0x076a -#define POL_mmDCP1_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP1_GRPH_FLIP_CONTROL 0x076b -#define POL_mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c -#define POL_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP1_GRPH_DFQ_CONTROL 0x076d -#define POL_mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_DFQ_STATUS 0x076e -#define POL_mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_INTERRUPT_STATUS 0x076f -#define POL_mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770 -#define POL_mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771 -#define POL_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772 -#define POL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_COMPRESS_PITCH 0x0773 -#define POL_mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774 -#define POL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775 -#define POL_mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP1_PRESCALE_GRPH_CONTROL 0x0776 -#define POL_mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779 -#define POL_mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_CONTROL 0x077a -#define POL_mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C11_C12 0x077b -#define POL_mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C13_C14 0x077c -#define POL_mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C21_C22 0x077d -#define POL_mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C23_C24 0x077e -#define POL_mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C31_C32 0x077f -#define POL_mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP1_INPUT_CSC_C33_C34 0x0780 -#define POL_mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_CONTROL 0x0781 -#define POL_mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C11_C12 0x0782 -#define POL_mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C13_C14 0x0783 -#define POL_mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C21_C22 0x0784 -#define POL_mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C23_C24 0x0785 -#define POL_mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C31_C32 0x0786 -#define POL_mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP1_OUTPUT_CSC_C33_C34 0x0787 -#define POL_mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d -#define POL_mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793 -#define POL_mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP1_DENORM_CONTROL 0x0794 -#define POL_mmDCP1_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_OUT_ROUND_CONTROL 0x0795 -#define POL_mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798 -#define POL_mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP1_KEY_CONTROL 0x0799 -#define POL_mmDCP1_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_KEY_RANGE_ALPHA 0x079a -#define POL_mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP1_KEY_RANGE_RED 0x079b -#define POL_mmDCP1_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP1_KEY_RANGE_GREEN 0x079c -#define POL_mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP1_KEY_RANGE_BLUE 0x079d -#define POL_mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP1_DEGAMMA_CONTROL 0x079e -#define POL_mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_CONTROL 0x079f -#define POL_mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C11_C12 0x07a0 -#define POL_mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C13_C14 0x07a1 -#define POL_mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C21_C22 0x07a2 -#define POL_mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C23_C24 0x07a3 -#define POL_mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C31_C32 0x07a4 -#define POL_mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP1_GAMUT_REMAP_C33_C34 0x07a5 -#define POL_mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6 -#define POL_mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP1_DCP_RANDOM_SEEDS 0x07a7 -#define POL_mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8 -#define POL_mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP1_CUR_CONTROL 0x07a9 -#define POL_mmDCP1_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_CUR_SURFACE_ADDRESS 0x07aa -#define POL_mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP1_CUR_SIZE 0x07ab -#define POL_mmDCP1_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac -#define POL_mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP1_CUR_POSITION 0x07ad -#define POL_mmDCP1_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP1_CUR_HOT_SPOT 0x07ae -#define POL_mmDCP1_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP1_CUR_COLOR1 0x07af -#define POL_mmDCP1_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP1_CUR_COLOR2 0x07b0 -#define POL_mmDCP1_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP1_CUR_UPDATE 0x07b1 -#define POL_mmDCP1_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb -#define POL_mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP1_CUR_STEREO_CONTROL 0x07bc -#define POL_mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_RW_MODE 0x07be -#define POL_mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_RW_INDEX 0x07bf -#define POL_mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_SEQ_COLOR 0x07c0 -#define POL_mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_PWL_DATA 0x07c1 -#define POL_mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_30_COLOR 0x07c2 -#define POL_mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3 -#define POL_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4 -#define POL_mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_AUTOFILL 0x07c5 -#define POL_mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_CONTROL 0x07c6 -#define POL_mmDCP1_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9 -#define POL_mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc -#define POL_mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP1_DCP_CRC_CONTROL 0x07cd -#define POL_mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_DCP_CRC_MASK 0x07ce -#define POL_mmDCP1_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP1_DCP_CRC_CURRENT 0x07cf -#define POL_mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP1_DVMM_PTE_CONTROL 0x07d0 -#define POL_mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_DCP_CRC_LAST 0x07d1 -#define POL_mmDCP1_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2 -#define POL_mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4 -#define POL_mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP1_DCP_GSL_CONTROL 0x07d5 -#define POL_mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6 -#define POL_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc -#define POL_mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP1_HW_ROTATION 0x07de -#define POL_mmDCP1_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df -#define POL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CONTROL 0x07e0 -#define POL_mmDCP1_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_LUT_INDEX 0x07e1 -#define POL_mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_LUT_DATA 0x07e2 -#define POL_mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3 -#define POL_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4 -#define POL_mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5 -#define POL_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6 -#define POL_mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7 -#define POL_mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef -#define POL_mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0 -#define POL_mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1 -#define POL_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2 -#define POL_mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3 -#define POL_mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb -#define POL_mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP1_ALPHA_CONTROL 0x07fc -#define POL_mmDCP1_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd -#define POL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe -#define POL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff -#define POL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800 -#define POL_mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801 -#define POL_mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802 -#define POL_mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803 -#define POL_mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb1_dispdec -// base address: 0x800 -#define POL_mmLB1_LB_DATA_FORMAT 0x081a -#define POL_mmLB1_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB1_LB_MEMORY_CTRL 0x081b -#define POL_mmLB1_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB1_LB_MEMORY_SIZE_STATUS 0x081c -#define POL_mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_DESKTOP_HEIGHT 0x081d -#define POL_mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB1_LB_VLINE_START_END 0x081e -#define POL_mmLB1_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB1_LB_VLINE2_START_END 0x081f -#define POL_mmLB1_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB1_LB_V_COUNTER 0x0820 -#define POL_mmLB1_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821 -#define POL_mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB1_LB_INTERRUPT_MASK 0x0822 -#define POL_mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB1_LB_VLINE_STATUS 0x0823 -#define POL_mmLB1_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_VLINE2_STATUS 0x0824 -#define POL_mmLB1_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_VBLANK_STATUS 0x0825 -#define POL_mmLB1_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_SYNC_RESET_SEL 0x0826 -#define POL_mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB1_LB_BLACK_KEYER_R_CR 0x0827 -#define POL_mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB1_LB_BLACK_KEYER_G_Y 0x0828 -#define POL_mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB1_LB_BLACK_KEYER_B_CB 0x0829 -#define POL_mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_CTRL 0x082a -#define POL_mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_R_CR 0x082b -#define POL_mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_G_Y 0x082c -#define POL_mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_B_CB 0x082d -#define POL_mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e -#define POL_mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f -#define POL_mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830 -#define POL_mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831 -#define POL_mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832 -#define POL_mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833 -#define POL_mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_BUFFER_STATUS 0x0834 -#define POL_mmLB1_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835 -#define POL_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB1_MVP_AFR_FLIP_MODE 0x0836 -#define POL_mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837 -#define POL_mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838 -#define POL_mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB1_DC_MVP_LB_CONTROL 0x0839 -#define POL_mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe1_dispdec -// base address: 0x800 -#define POL_mmDCFE1_DCFE_CLOCK_CONTROL 0x085a -#define POL_mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_SOFT_RESET 0x085b -#define POL_mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d -#define POL_mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e -#define POL_mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f -#define POL_mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_MISC 0x0860 -#define POL_mmDCFE1_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE1_DCFE_FLUSH 0x0861 -#define POL_mmDCFE1_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon4_dispdec -// base address: 0x2138 -#define POL_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e -#define POL_mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f -#define POL_mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870 -#define POL_mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_CNTL 0x0871 -#define POL_mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_CNTL2 0x0872 -#define POL_mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873 -#define POL_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874 -#define POL_mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_HI 0x0875 -#define POL_mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON4_PERFMON_LOW 0x0876 -#define POL_mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg1_dispdec -// base address: 0x800 -#define POL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a -#define POL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b -#define POL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c -#define POL_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d -#define POL_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e -#define POL_mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f -#define POL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880 -#define POL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881 -#define POL_mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882 -#define POL_mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886 -#define POL_mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG1_DPG_DVMM_STATUS 0x0887 -#define POL_mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl1_dispdec -// base address: 0x800 -#define POL_mmSCL1_SCL_COEF_RAM_SELECT 0x089a -#define POL_mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b -#define POL_mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL1_SCL_MODE 0x089c -#define POL_mmSCL1_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL1_SCL_TAP_CONTROL 0x089d -#define POL_mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_CONTROL 0x089e -#define POL_mmSCL1_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_BYPASS_CONTROL 0x089f -#define POL_mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0 -#define POL_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1 -#define POL_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2 -#define POL_mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3 -#define POL_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4 -#define POL_mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5 -#define POL_mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6 -#define POL_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL1_SCL_VERT_FILTER_INIT 0x08a7 -#define POL_mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8 -#define POL_mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL1_SCL_ROUND_OFFSET 0x08a9 -#define POL_mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL1_SCL_UPDATE 0x08aa -#define POL_mmSCL1_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL1_SCL_F_SHARP_CONTROL 0x08ab -#define POL_mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_ALU_CONTROL 0x08ac -#define POL_mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad -#define POL_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL1_VIEWPORT_START_SECONDARY 0x08ae -#define POL_mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL1_VIEWPORT_START 0x08af -#define POL_mmSCL1_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL1_VIEWPORT_SIZE 0x08b0 -#define POL_mmSCL1_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1 -#define POL_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2 -#define POL_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5 -#define POL_mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6 -#define POL_mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd1_dispdec -// base address: 0x800 -#define POL_mmBLND1_BLND_CONTROL 0x08c7 -#define POL_mmBLND1_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND1_BLND_SM_CONTROL2 0x08c8 -#define POL_mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND1_BLND_CONTROL2 0x08c9 -#define POL_mmBLND1_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND1_BLND_UPDATE 0x08ca -#define POL_mmBLND1_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb -#define POL_mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND1_BLND_V_UPDATE_LOCK 0x08cc -#define POL_mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd -#define POL_mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc1_dispdec -// base address: 0x800 -#define POL_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2 -#define POL_mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_TOTAL 0x08d3 -#define POL_mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_BLANK_START_END 0x08d4 -#define POL_mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_SYNC_A 0x08d5 -#define POL_mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6 -#define POL_mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_SYNC_B 0x08d7 -#define POL_mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8 -#define POL_mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VBI_END 0x08d9 -#define POL_mmCRTC1_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_TOTAL 0x08da -#define POL_mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_TOTAL_MIN 0x08db -#define POL_mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc -#define POL_mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd -#define POL_mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de -#define POL_mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df -#define POL_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_BLANK_START_END 0x08e0 -#define POL_mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_SYNC_A 0x08e1 -#define POL_mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2 -#define POL_mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_SYNC_B 0x08e3 -#define POL_mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4 -#define POL_mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5 -#define POL_mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6 -#define POL_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TRIGA_CNTL 0x08e7 -#define POL_mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8 -#define POL_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TRIGB_CNTL 0x08e9 -#define POL_mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea -#define POL_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb -#define POL_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_FLOW_CONTROL 0x08ec -#define POL_mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed -#define POL_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee -#define POL_mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CONTROL 0x08ef -#define POL_mmCRTC1_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_BLANK_CONTROL 0x08f0 -#define POL_mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1 -#define POL_mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2 -#define POL_mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3 -#define POL_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4 -#define POL_mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5 -#define POL_mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATUS 0x08f6 -#define POL_mmCRTC1_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATUS_POSITION 0x08f7 -#define POL_mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8 -#define POL_mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9 -#define POL_mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa -#define POL_mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb -#define POL_mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_COUNT_CONTROL 0x08fc -#define POL_mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_COUNT_RESET 0x08fd -#define POL_mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe -#define POL_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff -#define POL_mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STEREO_STATUS 0x0900 -#define POL_mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STEREO_CONTROL 0x0901 -#define POL_mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902 -#define POL_mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903 -#define POL_mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904 -#define POL_mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905 -#define POL_mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_START_LINE_CONTROL 0x0906 -#define POL_mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907 -#define POL_mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_UPDATE_LOCK 0x0908 -#define POL_mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909 -#define POL_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a -#define POL_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b -#define POL_mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c -#define POL_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d -#define POL_mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e -#define POL_mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f -#define POL_mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910 -#define POL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911 -#define POL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MVP_STATUS 0x0912 -#define POL_mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_MASTER_EN 0x0913 -#define POL_mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914 -#define POL_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915 -#define POL_mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917 -#define POL_mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918 -#define POL_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919 -#define POL_mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a -#define POL_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_BLACK_COLOR 0x091b -#define POL_mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c -#define POL_mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922 -#define POL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC_CNTL 0x0923 -#define POL_mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927 -#define POL_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_DATA_RG 0x0928 -#define POL_mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC0_DATA_B 0x0929 -#define POL_mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a -#define POL_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b -#define POL_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c -#define POL_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d -#define POL_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_DATA_RG 0x092e -#define POL_mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_CRC1_DATA_B 0x092f -#define POL_mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935 -#define POL_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936 -#define POL_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937 -#define POL_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938 -#define POL_mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_GSL_WINDOW 0x0939 -#define POL_mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_GSL_CONTROL 0x093a -#define POL_mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d -#define POL_mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC1_CRTC_DRR_CONTROL 0x093e -#define POL_mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt1_dispdec -// base address: 0x800 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944 -#define POL_mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945 -#define POL_mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT1_FMT_CONTROL 0x0946 -#define POL_mmFMT1_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947 -#define POL_mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948 -#define POL_mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949 -#define POL_mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a -#define POL_mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT1_FMT_CLAMP_CNTL 0x094e -#define POL_mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT1_FMT_CRC_CNTL 0x094f -#define POL_mmFMT1_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950 -#define POL_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951 -#define POL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952 -#define POL_mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953 -#define POL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954 -#define POL_mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955 -#define POL_mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp2_dispdec -// base address: 0x1000 -#define POL_mmDCP2_GRPH_ENABLE 0x095a -#define POL_mmDCP2_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP2_GRPH_CONTROL 0x095b -#define POL_mmDCP2_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c -#define POL_mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SWAP_CNTL 0x095d -#define POL_mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e -#define POL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f -#define POL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_PITCH 0x0960 -#define POL_mmDCP2_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961 -#define POL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962 -#define POL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963 -#define POL_mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964 -#define POL_mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP2_GRPH_X_START 0x0965 -#define POL_mmDCP2_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP2_GRPH_Y_START 0x0966 -#define POL_mmDCP2_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP2_GRPH_X_END 0x0967 -#define POL_mmDCP2_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP2_GRPH_Y_END 0x0968 -#define POL_mmDCP2_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP2_INPUT_GAMMA_CONTROL 0x0969 -#define POL_mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_UPDATE 0x096a -#define POL_mmDCP2_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP2_GRPH_FLIP_CONTROL 0x096b -#define POL_mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c -#define POL_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP2_GRPH_DFQ_CONTROL 0x096d -#define POL_mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_DFQ_STATUS 0x096e -#define POL_mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_INTERRUPT_STATUS 0x096f -#define POL_mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970 -#define POL_mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971 -#define POL_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972 -#define POL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_COMPRESS_PITCH 0x0973 -#define POL_mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974 -#define POL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975 -#define POL_mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP2_PRESCALE_GRPH_CONTROL 0x0976 -#define POL_mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979 -#define POL_mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_CONTROL 0x097a -#define POL_mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C11_C12 0x097b -#define POL_mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C13_C14 0x097c -#define POL_mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C21_C22 0x097d -#define POL_mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C23_C24 0x097e -#define POL_mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C31_C32 0x097f -#define POL_mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP2_INPUT_CSC_C33_C34 0x0980 -#define POL_mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_CONTROL 0x0981 -#define POL_mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C11_C12 0x0982 -#define POL_mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C13_C14 0x0983 -#define POL_mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C21_C22 0x0984 -#define POL_mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C23_C24 0x0985 -#define POL_mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C31_C32 0x0986 -#define POL_mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP2_OUTPUT_CSC_C33_C34 0x0987 -#define POL_mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d -#define POL_mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993 -#define POL_mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP2_DENORM_CONTROL 0x0994 -#define POL_mmDCP2_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_OUT_ROUND_CONTROL 0x0995 -#define POL_mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998 -#define POL_mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP2_KEY_CONTROL 0x0999 -#define POL_mmDCP2_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_KEY_RANGE_ALPHA 0x099a -#define POL_mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP2_KEY_RANGE_RED 0x099b -#define POL_mmDCP2_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP2_KEY_RANGE_GREEN 0x099c -#define POL_mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP2_KEY_RANGE_BLUE 0x099d -#define POL_mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP2_DEGAMMA_CONTROL 0x099e -#define POL_mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_CONTROL 0x099f -#define POL_mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C11_C12 0x09a0 -#define POL_mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C13_C14 0x09a1 -#define POL_mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C21_C22 0x09a2 -#define POL_mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C23_C24 0x09a3 -#define POL_mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C31_C32 0x09a4 -#define POL_mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP2_GAMUT_REMAP_C33_C34 0x09a5 -#define POL_mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6 -#define POL_mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP2_DCP_RANDOM_SEEDS 0x09a7 -#define POL_mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8 -#define POL_mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP2_CUR_CONTROL 0x09a9 -#define POL_mmDCP2_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_CUR_SURFACE_ADDRESS 0x09aa -#define POL_mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP2_CUR_SIZE 0x09ab -#define POL_mmDCP2_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac -#define POL_mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP2_CUR_POSITION 0x09ad -#define POL_mmDCP2_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP2_CUR_HOT_SPOT 0x09ae -#define POL_mmDCP2_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP2_CUR_COLOR1 0x09af -#define POL_mmDCP2_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP2_CUR_COLOR2 0x09b0 -#define POL_mmDCP2_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP2_CUR_UPDATE 0x09b1 -#define POL_mmDCP2_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb -#define POL_mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP2_CUR_STEREO_CONTROL 0x09bc -#define POL_mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_RW_MODE 0x09be -#define POL_mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_RW_INDEX 0x09bf -#define POL_mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_SEQ_COLOR 0x09c0 -#define POL_mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_PWL_DATA 0x09c1 -#define POL_mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_30_COLOR 0x09c2 -#define POL_mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3 -#define POL_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4 -#define POL_mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_AUTOFILL 0x09c5 -#define POL_mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_CONTROL 0x09c6 -#define POL_mmDCP2_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9 -#define POL_mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc -#define POL_mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP2_DCP_CRC_CONTROL 0x09cd -#define POL_mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_DCP_CRC_MASK 0x09ce -#define POL_mmDCP2_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP2_DCP_CRC_CURRENT 0x09cf -#define POL_mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP2_DVMM_PTE_CONTROL 0x09d0 -#define POL_mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_DCP_CRC_LAST 0x09d1 -#define POL_mmDCP2_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2 -#define POL_mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4 -#define POL_mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP2_DCP_GSL_CONTROL 0x09d5 -#define POL_mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6 -#define POL_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc -#define POL_mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP2_HW_ROTATION 0x09de -#define POL_mmDCP2_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df -#define POL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CONTROL 0x09e0 -#define POL_mmDCP2_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_LUT_INDEX 0x09e1 -#define POL_mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_LUT_DATA 0x09e2 -#define POL_mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3 -#define POL_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4 -#define POL_mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5 -#define POL_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6 -#define POL_mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7 -#define POL_mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef -#define POL_mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0 -#define POL_mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1 -#define POL_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2 -#define POL_mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3 -#define POL_mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb -#define POL_mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP2_ALPHA_CONTROL 0x09fc -#define POL_mmDCP2_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd -#define POL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe -#define POL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff -#define POL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00 -#define POL_mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01 -#define POL_mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02 -#define POL_mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03 -#define POL_mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb2_dispdec -// base address: 0x1000 -#define POL_mmLB2_LB_DATA_FORMAT 0x0a1a -#define POL_mmLB2_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB2_LB_MEMORY_CTRL 0x0a1b -#define POL_mmLB2_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c -#define POL_mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_DESKTOP_HEIGHT 0x0a1d -#define POL_mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB2_LB_VLINE_START_END 0x0a1e -#define POL_mmLB2_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB2_LB_VLINE2_START_END 0x0a1f -#define POL_mmLB2_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB2_LB_V_COUNTER 0x0a20 -#define POL_mmLB2_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21 -#define POL_mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB2_LB_INTERRUPT_MASK 0x0a22 -#define POL_mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB2_LB_VLINE_STATUS 0x0a23 -#define POL_mmLB2_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_VLINE2_STATUS 0x0a24 -#define POL_mmLB2_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_VBLANK_STATUS 0x0a25 -#define POL_mmLB2_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_SYNC_RESET_SEL 0x0a26 -#define POL_mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB2_LB_BLACK_KEYER_R_CR 0x0a27 -#define POL_mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB2_LB_BLACK_KEYER_G_Y 0x0a28 -#define POL_mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB2_LB_BLACK_KEYER_B_CB 0x0a29 -#define POL_mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a -#define POL_mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b -#define POL_mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c -#define POL_mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d -#define POL_mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e -#define POL_mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f -#define POL_mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30 -#define POL_mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31 -#define POL_mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32 -#define POL_mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33 -#define POL_mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_BUFFER_STATUS 0x0a34 -#define POL_mmLB2_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35 -#define POL_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB2_MVP_AFR_FLIP_MODE 0x0a36 -#define POL_mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37 -#define POL_mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38 -#define POL_mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB2_DC_MVP_LB_CONTROL 0x0a39 -#define POL_mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe2_dispdec -// base address: 0x1000 -#define POL_mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a -#define POL_mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_SOFT_RESET 0x0a5b -#define POL_mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d -#define POL_mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e -#define POL_mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f -#define POL_mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_MISC 0x0a60 -#define POL_mmDCFE2_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE2_DCFE_FLUSH 0x0a61 -#define POL_mmDCFE2_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon5_dispdec -// base address: 0x2938 -#define POL_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e -#define POL_mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f -#define POL_mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70 -#define POL_mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_CNTL 0x0a71 -#define POL_mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_CNTL2 0x0a72 -#define POL_mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73 -#define POL_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74 -#define POL_mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_HI 0x0a75 -#define POL_mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON5_PERFMON_LOW 0x0a76 -#define POL_mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg2_dispdec -// base address: 0x1000 -#define POL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a -#define POL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b -#define POL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c -#define POL_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d -#define POL_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e -#define POL_mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f -#define POL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80 -#define POL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81 -#define POL_mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82 -#define POL_mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86 -#define POL_mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87 -#define POL_mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl2_dispdec -// base address: 0x1000 -#define POL_mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a -#define POL_mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b -#define POL_mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL2_SCL_MODE 0x0a9c -#define POL_mmSCL2_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL2_SCL_TAP_CONTROL 0x0a9d -#define POL_mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_CONTROL 0x0a9e -#define POL_mmSCL2_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_BYPASS_CONTROL 0x0a9f -#define POL_mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0 -#define POL_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1 -#define POL_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2 -#define POL_mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3 -#define POL_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4 -#define POL_mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5 -#define POL_mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6 -#define POL_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7 -#define POL_mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8 -#define POL_mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL2_SCL_ROUND_OFFSET 0x0aa9 -#define POL_mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL2_SCL_UPDATE 0x0aaa -#define POL_mmSCL2_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL2_SCL_F_SHARP_CONTROL 0x0aab -#define POL_mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_ALU_CONTROL 0x0aac -#define POL_mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad -#define POL_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL2_VIEWPORT_START_SECONDARY 0x0aae -#define POL_mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL2_VIEWPORT_START 0x0aaf -#define POL_mmSCL2_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL2_VIEWPORT_SIZE 0x0ab0 -#define POL_mmSCL2_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1 -#define POL_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2 -#define POL_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5 -#define POL_mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6 -#define POL_mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd2_dispdec -// base address: 0x1000 -#define POL_mmBLND2_BLND_CONTROL 0x0ac7 -#define POL_mmBLND2_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND2_BLND_SM_CONTROL2 0x0ac8 -#define POL_mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND2_BLND_CONTROL2 0x0ac9 -#define POL_mmBLND2_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND2_BLND_UPDATE 0x0aca -#define POL_mmBLND2_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb -#define POL_mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND2_BLND_V_UPDATE_LOCK 0x0acc -#define POL_mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd -#define POL_mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc2_dispdec -// base address: 0x1000 -#define POL_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2 -#define POL_mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_TOTAL 0x0ad3 -#define POL_mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4 -#define POL_mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_SYNC_A 0x0ad5 -#define POL_mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6 -#define POL_mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_SYNC_B 0x0ad7 -#define POL_mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8 -#define POL_mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VBI_END 0x0ad9 -#define POL_mmCRTC2_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_TOTAL 0x0ada -#define POL_mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb -#define POL_mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc -#define POL_mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add -#define POL_mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade -#define POL_mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf -#define POL_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0 -#define POL_mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_SYNC_A 0x0ae1 -#define POL_mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2 -#define POL_mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_SYNC_B 0x0ae3 -#define POL_mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4 -#define POL_mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5 -#define POL_mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6 -#define POL_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7 -#define POL_mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8 -#define POL_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9 -#define POL_mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea -#define POL_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb -#define POL_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_FLOW_CONTROL 0x0aec -#define POL_mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed -#define POL_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee -#define POL_mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CONTROL 0x0aef -#define POL_mmCRTC2_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_BLANK_CONTROL 0x0af0 -#define POL_mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1 -#define POL_mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2 -#define POL_mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3 -#define POL_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4 -#define POL_mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5 -#define POL_mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATUS 0x0af6 -#define POL_mmCRTC2_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATUS_POSITION 0x0af7 -#define POL_mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8 -#define POL_mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9 -#define POL_mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa -#define POL_mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb -#define POL_mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_COUNT_CONTROL 0x0afc -#define POL_mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_COUNT_RESET 0x0afd -#define POL_mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe -#define POL_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff -#define POL_mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STEREO_STATUS 0x0b00 -#define POL_mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STEREO_CONTROL 0x0b01 -#define POL_mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02 -#define POL_mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03 -#define POL_mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04 -#define POL_mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05 -#define POL_mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06 -#define POL_mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07 -#define POL_mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_UPDATE_LOCK 0x0b08 -#define POL_mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09 -#define POL_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a -#define POL_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b -#define POL_mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c -#define POL_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d -#define POL_mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e -#define POL_mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f -#define POL_mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10 -#define POL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11 -#define POL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MVP_STATUS 0x0b12 -#define POL_mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_MASTER_EN 0x0b13 -#define POL_mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14 -#define POL_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15 -#define POL_mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17 -#define POL_mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18 -#define POL_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19 -#define POL_mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a -#define POL_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_BLACK_COLOR 0x0b1b -#define POL_mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c -#define POL_mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22 -#define POL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC_CNTL 0x0b23 -#define POL_mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27 -#define POL_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28 -#define POL_mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC0_DATA_B 0x0b29 -#define POL_mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a -#define POL_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b -#define POL_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c -#define POL_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d -#define POL_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e -#define POL_mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f -#define POL_mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35 -#define POL_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36 -#define POL_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37 -#define POL_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38 -#define POL_mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_GSL_WINDOW 0x0b39 -#define POL_mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_GSL_CONTROL 0x0b3a -#define POL_mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d -#define POL_mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC2_CRTC_DRR_CONTROL 0x0b3e -#define POL_mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt2_dispdec -// base address: 0x1000 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44 -#define POL_mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45 -#define POL_mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT2_FMT_CONTROL 0x0b46 -#define POL_mmFMT2_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47 -#define POL_mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48 -#define POL_mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49 -#define POL_mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a -#define POL_mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT2_FMT_CLAMP_CNTL 0x0b4e -#define POL_mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT2_FMT_CRC_CNTL 0x0b4f -#define POL_mmFMT2_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50 -#define POL_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51 -#define POL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52 -#define POL_mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53 -#define POL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54 -#define POL_mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55 -#define POL_mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp3_dispdec -// base address: 0x1800 -#define POL_mmDCP3_GRPH_ENABLE 0x0b5a -#define POL_mmDCP3_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP3_GRPH_CONTROL 0x0b5b -#define POL_mmDCP3_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c -#define POL_mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SWAP_CNTL 0x0b5d -#define POL_mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e -#define POL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f -#define POL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_PITCH 0x0b60 -#define POL_mmDCP3_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61 -#define POL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62 -#define POL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63 -#define POL_mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64 -#define POL_mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP3_GRPH_X_START 0x0b65 -#define POL_mmDCP3_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP3_GRPH_Y_START 0x0b66 -#define POL_mmDCP3_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP3_GRPH_X_END 0x0b67 -#define POL_mmDCP3_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP3_GRPH_Y_END 0x0b68 -#define POL_mmDCP3_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP3_INPUT_GAMMA_CONTROL 0x0b69 -#define POL_mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_UPDATE 0x0b6a -#define POL_mmDCP3_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP3_GRPH_FLIP_CONTROL 0x0b6b -#define POL_mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c -#define POL_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP3_GRPH_DFQ_CONTROL 0x0b6d -#define POL_mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_DFQ_STATUS 0x0b6e -#define POL_mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f -#define POL_mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70 -#define POL_mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71 -#define POL_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72 -#define POL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_COMPRESS_PITCH 0x0b73 -#define POL_mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74 -#define POL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75 -#define POL_mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76 -#define POL_mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79 -#define POL_mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_CONTROL 0x0b7a -#define POL_mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C11_C12 0x0b7b -#define POL_mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C13_C14 0x0b7c -#define POL_mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C21_C22 0x0b7d -#define POL_mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C23_C24 0x0b7e -#define POL_mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C31_C32 0x0b7f -#define POL_mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP3_INPUT_CSC_C33_C34 0x0b80 -#define POL_mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_CONTROL 0x0b81 -#define POL_mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C11_C12 0x0b82 -#define POL_mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C13_C14 0x0b83 -#define POL_mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C21_C22 0x0b84 -#define POL_mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C23_C24 0x0b85 -#define POL_mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C31_C32 0x0b86 -#define POL_mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP3_OUTPUT_CSC_C33_C34 0x0b87 -#define POL_mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d -#define POL_mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93 -#define POL_mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP3_DENORM_CONTROL 0x0b94 -#define POL_mmDCP3_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_OUT_ROUND_CONTROL 0x0b95 -#define POL_mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98 -#define POL_mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP3_KEY_CONTROL 0x0b99 -#define POL_mmDCP3_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_KEY_RANGE_ALPHA 0x0b9a -#define POL_mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP3_KEY_RANGE_RED 0x0b9b -#define POL_mmDCP3_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP3_KEY_RANGE_GREEN 0x0b9c -#define POL_mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP3_KEY_RANGE_BLUE 0x0b9d -#define POL_mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP3_DEGAMMA_CONTROL 0x0b9e -#define POL_mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f -#define POL_mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0 -#define POL_mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1 -#define POL_mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2 -#define POL_mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3 -#define POL_mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4 -#define POL_mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5 -#define POL_mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6 -#define POL_mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP3_DCP_RANDOM_SEEDS 0x0ba7 -#define POL_mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8 -#define POL_mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP3_CUR_CONTROL 0x0ba9 -#define POL_mmDCP3_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_CUR_SURFACE_ADDRESS 0x0baa -#define POL_mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP3_CUR_SIZE 0x0bab -#define POL_mmDCP3_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac -#define POL_mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP3_CUR_POSITION 0x0bad -#define POL_mmDCP3_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP3_CUR_HOT_SPOT 0x0bae -#define POL_mmDCP3_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP3_CUR_COLOR1 0x0baf -#define POL_mmDCP3_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP3_CUR_COLOR2 0x0bb0 -#define POL_mmDCP3_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP3_CUR_UPDATE 0x0bb1 -#define POL_mmDCP3_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb -#define POL_mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP3_CUR_STEREO_CONTROL 0x0bbc -#define POL_mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_RW_MODE 0x0bbe -#define POL_mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_RW_INDEX 0x0bbf -#define POL_mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0 -#define POL_mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_PWL_DATA 0x0bc1 -#define POL_mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_30_COLOR 0x0bc2 -#define POL_mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3 -#define POL_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4 -#define POL_mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_AUTOFILL 0x0bc5 -#define POL_mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_CONTROL 0x0bc6 -#define POL_mmDCP3_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9 -#define POL_mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc -#define POL_mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP3_DCP_CRC_CONTROL 0x0bcd -#define POL_mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_DCP_CRC_MASK 0x0bce -#define POL_mmDCP3_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP3_DCP_CRC_CURRENT 0x0bcf -#define POL_mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP3_DVMM_PTE_CONTROL 0x0bd0 -#define POL_mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_DCP_CRC_LAST 0x0bd1 -#define POL_mmDCP3_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2 -#define POL_mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4 -#define POL_mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP3_DCP_GSL_CONTROL 0x0bd5 -#define POL_mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6 -#define POL_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc -#define POL_mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP3_HW_ROTATION 0x0bde -#define POL_mmDCP3_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf -#define POL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CONTROL 0x0be0 -#define POL_mmDCP3_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_LUT_INDEX 0x0be1 -#define POL_mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_LUT_DATA 0x0be2 -#define POL_mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3 -#define POL_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4 -#define POL_mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5 -#define POL_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6 -#define POL_mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7 -#define POL_mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef -#define POL_mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0 -#define POL_mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1 -#define POL_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2 -#define POL_mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3 -#define POL_mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb -#define POL_mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP3_ALPHA_CONTROL 0x0bfc -#define POL_mmDCP3_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd -#define POL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe -#define POL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff -#define POL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00 -#define POL_mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01 -#define POL_mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02 -#define POL_mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03 -#define POL_mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb3_dispdec -// base address: 0x1800 -#define POL_mmLB3_LB_DATA_FORMAT 0x0c1a -#define POL_mmLB3_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB3_LB_MEMORY_CTRL 0x0c1b -#define POL_mmLB3_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c -#define POL_mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_DESKTOP_HEIGHT 0x0c1d -#define POL_mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB3_LB_VLINE_START_END 0x0c1e -#define POL_mmLB3_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB3_LB_VLINE2_START_END 0x0c1f -#define POL_mmLB3_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB3_LB_V_COUNTER 0x0c20 -#define POL_mmLB3_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21 -#define POL_mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB3_LB_INTERRUPT_MASK 0x0c22 -#define POL_mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB3_LB_VLINE_STATUS 0x0c23 -#define POL_mmLB3_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_VLINE2_STATUS 0x0c24 -#define POL_mmLB3_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_VBLANK_STATUS 0x0c25 -#define POL_mmLB3_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_SYNC_RESET_SEL 0x0c26 -#define POL_mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB3_LB_BLACK_KEYER_R_CR 0x0c27 -#define POL_mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB3_LB_BLACK_KEYER_G_Y 0x0c28 -#define POL_mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB3_LB_BLACK_KEYER_B_CB 0x0c29 -#define POL_mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a -#define POL_mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b -#define POL_mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c -#define POL_mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d -#define POL_mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e -#define POL_mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f -#define POL_mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30 -#define POL_mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31 -#define POL_mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32 -#define POL_mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33 -#define POL_mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_BUFFER_STATUS 0x0c34 -#define POL_mmLB3_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35 -#define POL_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB3_MVP_AFR_FLIP_MODE 0x0c36 -#define POL_mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37 -#define POL_mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38 -#define POL_mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB3_DC_MVP_LB_CONTROL 0x0c39 -#define POL_mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe3_dispdec -// base address: 0x1800 -#define POL_mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a -#define POL_mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_SOFT_RESET 0x0c5b -#define POL_mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d -#define POL_mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e -#define POL_mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f -#define POL_mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_MISC 0x0c60 -#define POL_mmDCFE3_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE3_DCFE_FLUSH 0x0c61 -#define POL_mmDCFE3_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon6_dispdec -// base address: 0x3138 -#define POL_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e -#define POL_mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f -#define POL_mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70 -#define POL_mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_CNTL 0x0c71 -#define POL_mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_CNTL2 0x0c72 -#define POL_mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73 -#define POL_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74 -#define POL_mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_HI 0x0c75 -#define POL_mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON6_PERFMON_LOW 0x0c76 -#define POL_mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg3_dispdec -// base address: 0x1800 -#define POL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a -#define POL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b -#define POL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c -#define POL_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d -#define POL_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e -#define POL_mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f -#define POL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80 -#define POL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81 -#define POL_mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82 -#define POL_mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86 -#define POL_mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87 -#define POL_mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl3_dispdec -// base address: 0x1800 -#define POL_mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a -#define POL_mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b -#define POL_mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL3_SCL_MODE 0x0c9c -#define POL_mmSCL3_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL3_SCL_TAP_CONTROL 0x0c9d -#define POL_mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_CONTROL 0x0c9e -#define POL_mmSCL3_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_BYPASS_CONTROL 0x0c9f -#define POL_mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0 -#define POL_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1 -#define POL_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2 -#define POL_mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3 -#define POL_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4 -#define POL_mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5 -#define POL_mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6 -#define POL_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7 -#define POL_mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8 -#define POL_mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL3_SCL_ROUND_OFFSET 0x0ca9 -#define POL_mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL3_SCL_UPDATE 0x0caa -#define POL_mmSCL3_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL3_SCL_F_SHARP_CONTROL 0x0cab -#define POL_mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_ALU_CONTROL 0x0cac -#define POL_mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad -#define POL_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL3_VIEWPORT_START_SECONDARY 0x0cae -#define POL_mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL3_VIEWPORT_START 0x0caf -#define POL_mmSCL3_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL3_VIEWPORT_SIZE 0x0cb0 -#define POL_mmSCL3_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1 -#define POL_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2 -#define POL_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5 -#define POL_mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6 -#define POL_mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd3_dispdec -// base address: 0x1800 -#define POL_mmBLND3_BLND_CONTROL 0x0cc7 -#define POL_mmBLND3_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND3_BLND_SM_CONTROL2 0x0cc8 -#define POL_mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND3_BLND_CONTROL2 0x0cc9 -#define POL_mmBLND3_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND3_BLND_UPDATE 0x0cca -#define POL_mmBLND3_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb -#define POL_mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc -#define POL_mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd -#define POL_mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc3_dispdec -// base address: 0x1800 -#define POL_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2 -#define POL_mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_TOTAL 0x0cd3 -#define POL_mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4 -#define POL_mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_SYNC_A 0x0cd5 -#define POL_mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6 -#define POL_mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_SYNC_B 0x0cd7 -#define POL_mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8 -#define POL_mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VBI_END 0x0cd9 -#define POL_mmCRTC3_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_TOTAL 0x0cda -#define POL_mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb -#define POL_mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc -#define POL_mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd -#define POL_mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde -#define POL_mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf -#define POL_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0 -#define POL_mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_SYNC_A 0x0ce1 -#define POL_mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2 -#define POL_mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_SYNC_B 0x0ce3 -#define POL_mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4 -#define POL_mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5 -#define POL_mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6 -#define POL_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7 -#define POL_mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8 -#define POL_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9 -#define POL_mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea -#define POL_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb -#define POL_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_FLOW_CONTROL 0x0cec -#define POL_mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced -#define POL_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee -#define POL_mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CONTROL 0x0cef -#define POL_mmCRTC3_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0 -#define POL_mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1 -#define POL_mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2 -#define POL_mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3 -#define POL_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4 -#define POL_mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5 -#define POL_mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATUS 0x0cf6 -#define POL_mmCRTC3_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATUS_POSITION 0x0cf7 -#define POL_mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8 -#define POL_mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9 -#define POL_mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa -#define POL_mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb -#define POL_mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc -#define POL_mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_COUNT_RESET 0x0cfd -#define POL_mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe -#define POL_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff -#define POL_mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STEREO_STATUS 0x0d00 -#define POL_mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STEREO_CONTROL 0x0d01 -#define POL_mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02 -#define POL_mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03 -#define POL_mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04 -#define POL_mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05 -#define POL_mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06 -#define POL_mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07 -#define POL_mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_UPDATE_LOCK 0x0d08 -#define POL_mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09 -#define POL_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a -#define POL_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b -#define POL_mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c -#define POL_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d -#define POL_mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e -#define POL_mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f -#define POL_mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10 -#define POL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11 -#define POL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MVP_STATUS 0x0d12 -#define POL_mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_MASTER_EN 0x0d13 -#define POL_mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14 -#define POL_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15 -#define POL_mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17 -#define POL_mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18 -#define POL_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19 -#define POL_mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a -#define POL_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_BLACK_COLOR 0x0d1b -#define POL_mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c -#define POL_mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22 -#define POL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC_CNTL 0x0d23 -#define POL_mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27 -#define POL_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28 -#define POL_mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC0_DATA_B 0x0d29 -#define POL_mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a -#define POL_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b -#define POL_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c -#define POL_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d -#define POL_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e -#define POL_mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f -#define POL_mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35 -#define POL_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36 -#define POL_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37 -#define POL_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38 -#define POL_mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_GSL_WINDOW 0x0d39 -#define POL_mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_GSL_CONTROL 0x0d3a -#define POL_mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d -#define POL_mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC3_CRTC_DRR_CONTROL 0x0d3e -#define POL_mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt3_dispdec -// base address: 0x1800 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44 -#define POL_mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45 -#define POL_mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT3_FMT_CONTROL 0x0d46 -#define POL_mmFMT3_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47 -#define POL_mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48 -#define POL_mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49 -#define POL_mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a -#define POL_mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT3_FMT_CLAMP_CNTL 0x0d4e -#define POL_mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT3_FMT_CRC_CNTL 0x0d4f -#define POL_mmFMT3_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50 -#define POL_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51 -#define POL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52 -#define POL_mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53 -#define POL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54 -#define POL_mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55 -#define POL_mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp4_dispdec -// base address: 0x2000 -#define POL_mmDCP4_GRPH_ENABLE 0x0d5a -#define POL_mmDCP4_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP4_GRPH_CONTROL 0x0d5b -#define POL_mmDCP4_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c -#define POL_mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SWAP_CNTL 0x0d5d -#define POL_mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e -#define POL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f -#define POL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_PITCH 0x0d60 -#define POL_mmDCP4_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61 -#define POL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62 -#define POL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63 -#define POL_mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64 -#define POL_mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP4_GRPH_X_START 0x0d65 -#define POL_mmDCP4_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP4_GRPH_Y_START 0x0d66 -#define POL_mmDCP4_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP4_GRPH_X_END 0x0d67 -#define POL_mmDCP4_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP4_GRPH_Y_END 0x0d68 -#define POL_mmDCP4_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP4_INPUT_GAMMA_CONTROL 0x0d69 -#define POL_mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_UPDATE 0x0d6a -#define POL_mmDCP4_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP4_GRPH_FLIP_CONTROL 0x0d6b -#define POL_mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c -#define POL_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP4_GRPH_DFQ_CONTROL 0x0d6d -#define POL_mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_DFQ_STATUS 0x0d6e -#define POL_mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f -#define POL_mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70 -#define POL_mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71 -#define POL_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72 -#define POL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_COMPRESS_PITCH 0x0d73 -#define POL_mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74 -#define POL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75 -#define POL_mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76 -#define POL_mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79 -#define POL_mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_CONTROL 0x0d7a -#define POL_mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C11_C12 0x0d7b -#define POL_mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C13_C14 0x0d7c -#define POL_mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C21_C22 0x0d7d -#define POL_mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C23_C24 0x0d7e -#define POL_mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C31_C32 0x0d7f -#define POL_mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP4_INPUT_CSC_C33_C34 0x0d80 -#define POL_mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_CONTROL 0x0d81 -#define POL_mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C11_C12 0x0d82 -#define POL_mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C13_C14 0x0d83 -#define POL_mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C21_C22 0x0d84 -#define POL_mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C23_C24 0x0d85 -#define POL_mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C31_C32 0x0d86 -#define POL_mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP4_OUTPUT_CSC_C33_C34 0x0d87 -#define POL_mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d -#define POL_mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93 -#define POL_mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP4_DENORM_CONTROL 0x0d94 -#define POL_mmDCP4_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_OUT_ROUND_CONTROL 0x0d95 -#define POL_mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98 -#define POL_mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP4_KEY_CONTROL 0x0d99 -#define POL_mmDCP4_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_KEY_RANGE_ALPHA 0x0d9a -#define POL_mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP4_KEY_RANGE_RED 0x0d9b -#define POL_mmDCP4_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP4_KEY_RANGE_GREEN 0x0d9c -#define POL_mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP4_KEY_RANGE_BLUE 0x0d9d -#define POL_mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP4_DEGAMMA_CONTROL 0x0d9e -#define POL_mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f -#define POL_mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C11_C12 0x0da0 -#define POL_mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C13_C14 0x0da1 -#define POL_mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C21_C22 0x0da2 -#define POL_mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C23_C24 0x0da3 -#define POL_mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C31_C32 0x0da4 -#define POL_mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP4_GAMUT_REMAP_C33_C34 0x0da5 -#define POL_mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6 -#define POL_mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP4_DCP_RANDOM_SEEDS 0x0da7 -#define POL_mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8 -#define POL_mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP4_CUR_CONTROL 0x0da9 -#define POL_mmDCP4_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_CUR_SURFACE_ADDRESS 0x0daa -#define POL_mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP4_CUR_SIZE 0x0dab -#define POL_mmDCP4_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac -#define POL_mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP4_CUR_POSITION 0x0dad -#define POL_mmDCP4_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP4_CUR_HOT_SPOT 0x0dae -#define POL_mmDCP4_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP4_CUR_COLOR1 0x0daf -#define POL_mmDCP4_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP4_CUR_COLOR2 0x0db0 -#define POL_mmDCP4_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP4_CUR_UPDATE 0x0db1 -#define POL_mmDCP4_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb -#define POL_mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP4_CUR_STEREO_CONTROL 0x0dbc -#define POL_mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_RW_MODE 0x0dbe -#define POL_mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_RW_INDEX 0x0dbf -#define POL_mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0 -#define POL_mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_PWL_DATA 0x0dc1 -#define POL_mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_30_COLOR 0x0dc2 -#define POL_mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3 -#define POL_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4 -#define POL_mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_AUTOFILL 0x0dc5 -#define POL_mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_CONTROL 0x0dc6 -#define POL_mmDCP4_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9 -#define POL_mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc -#define POL_mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP4_DCP_CRC_CONTROL 0x0dcd -#define POL_mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_DCP_CRC_MASK 0x0dce -#define POL_mmDCP4_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP4_DCP_CRC_CURRENT 0x0dcf -#define POL_mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP4_DVMM_PTE_CONTROL 0x0dd0 -#define POL_mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_DCP_CRC_LAST 0x0dd1 -#define POL_mmDCP4_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2 -#define POL_mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4 -#define POL_mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP4_DCP_GSL_CONTROL 0x0dd5 -#define POL_mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6 -#define POL_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc -#define POL_mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP4_HW_ROTATION 0x0dde -#define POL_mmDCP4_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf -#define POL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CONTROL 0x0de0 -#define POL_mmDCP4_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_LUT_INDEX 0x0de1 -#define POL_mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_LUT_DATA 0x0de2 -#define POL_mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3 -#define POL_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4 -#define POL_mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5 -#define POL_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6 -#define POL_mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7 -#define POL_mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def -#define POL_mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0 -#define POL_mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1 -#define POL_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2 -#define POL_mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3 -#define POL_mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb -#define POL_mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP4_ALPHA_CONTROL 0x0dfc -#define POL_mmDCP4_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd -#define POL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe -#define POL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff -#define POL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00 -#define POL_mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01 -#define POL_mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02 -#define POL_mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03 -#define POL_mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb4_dispdec -// base address: 0x2000 -#define POL_mmLB4_LB_DATA_FORMAT 0x0e1a -#define POL_mmLB4_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB4_LB_MEMORY_CTRL 0x0e1b -#define POL_mmLB4_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c -#define POL_mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_DESKTOP_HEIGHT 0x0e1d -#define POL_mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB4_LB_VLINE_START_END 0x0e1e -#define POL_mmLB4_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB4_LB_VLINE2_START_END 0x0e1f -#define POL_mmLB4_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB4_LB_V_COUNTER 0x0e20 -#define POL_mmLB4_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21 -#define POL_mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB4_LB_INTERRUPT_MASK 0x0e22 -#define POL_mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB4_LB_VLINE_STATUS 0x0e23 -#define POL_mmLB4_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_VLINE2_STATUS 0x0e24 -#define POL_mmLB4_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_VBLANK_STATUS 0x0e25 -#define POL_mmLB4_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_SYNC_RESET_SEL 0x0e26 -#define POL_mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB4_LB_BLACK_KEYER_R_CR 0x0e27 -#define POL_mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB4_LB_BLACK_KEYER_G_Y 0x0e28 -#define POL_mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB4_LB_BLACK_KEYER_B_CB 0x0e29 -#define POL_mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a -#define POL_mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b -#define POL_mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c -#define POL_mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d -#define POL_mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e -#define POL_mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f -#define POL_mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30 -#define POL_mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31 -#define POL_mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32 -#define POL_mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33 -#define POL_mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_BUFFER_STATUS 0x0e34 -#define POL_mmLB4_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35 -#define POL_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB4_MVP_AFR_FLIP_MODE 0x0e36 -#define POL_mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37 -#define POL_mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38 -#define POL_mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB4_DC_MVP_LB_CONTROL 0x0e39 -#define POL_mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe4_dispdec -// base address: 0x2000 -#define POL_mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a -#define POL_mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_SOFT_RESET 0x0e5b -#define POL_mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d -#define POL_mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e -#define POL_mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f -#define POL_mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_MISC 0x0e60 -#define POL_mmDCFE4_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE4_DCFE_FLUSH 0x0e61 -#define POL_mmDCFE4_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon7_dispdec -// base address: 0x3938 -#define POL_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e -#define POL_mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f -#define POL_mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70 -#define POL_mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_CNTL 0x0e71 -#define POL_mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_CNTL2 0x0e72 -#define POL_mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73 -#define POL_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74 -#define POL_mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_HI 0x0e75 -#define POL_mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON7_PERFMON_LOW 0x0e76 -#define POL_mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg4_dispdec -// base address: 0x2000 -#define POL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a -#define POL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b -#define POL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c -#define POL_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d -#define POL_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e -#define POL_mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f -#define POL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80 -#define POL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81 -#define POL_mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82 -#define POL_mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86 -#define POL_mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87 -#define POL_mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl4_dispdec -// base address: 0x2000 -#define POL_mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a -#define POL_mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b -#define POL_mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL4_SCL_MODE 0x0e9c -#define POL_mmSCL4_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL4_SCL_TAP_CONTROL 0x0e9d -#define POL_mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_CONTROL 0x0e9e -#define POL_mmSCL4_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_BYPASS_CONTROL 0x0e9f -#define POL_mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0 -#define POL_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1 -#define POL_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2 -#define POL_mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3 -#define POL_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4 -#define POL_mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5 -#define POL_mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6 -#define POL_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7 -#define POL_mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8 -#define POL_mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL4_SCL_ROUND_OFFSET 0x0ea9 -#define POL_mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL4_SCL_UPDATE 0x0eaa -#define POL_mmSCL4_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL4_SCL_F_SHARP_CONTROL 0x0eab -#define POL_mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_ALU_CONTROL 0x0eac -#define POL_mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead -#define POL_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL4_VIEWPORT_START_SECONDARY 0x0eae -#define POL_mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL4_VIEWPORT_START 0x0eaf -#define POL_mmSCL4_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL4_VIEWPORT_SIZE 0x0eb0 -#define POL_mmSCL4_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1 -#define POL_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2 -#define POL_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5 -#define POL_mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6 -#define POL_mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd4_dispdec -// base address: 0x2000 -#define POL_mmBLND4_BLND_CONTROL 0x0ec7 -#define POL_mmBLND4_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND4_BLND_SM_CONTROL2 0x0ec8 -#define POL_mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND4_BLND_CONTROL2 0x0ec9 -#define POL_mmBLND4_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND4_BLND_UPDATE 0x0eca -#define POL_mmBLND4_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb -#define POL_mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc -#define POL_mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd -#define POL_mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc4_dispdec -// base address: 0x2000 -#define POL_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2 -#define POL_mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_TOTAL 0x0ed3 -#define POL_mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4 -#define POL_mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_SYNC_A 0x0ed5 -#define POL_mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6 -#define POL_mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_SYNC_B 0x0ed7 -#define POL_mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8 -#define POL_mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VBI_END 0x0ed9 -#define POL_mmCRTC4_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_TOTAL 0x0eda -#define POL_mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb -#define POL_mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc -#define POL_mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd -#define POL_mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede -#define POL_mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf -#define POL_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0 -#define POL_mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_SYNC_A 0x0ee1 -#define POL_mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2 -#define POL_mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_SYNC_B 0x0ee3 -#define POL_mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4 -#define POL_mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5 -#define POL_mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6 -#define POL_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7 -#define POL_mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8 -#define POL_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9 -#define POL_mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea -#define POL_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb -#define POL_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_FLOW_CONTROL 0x0eec -#define POL_mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed -#define POL_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee -#define POL_mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CONTROL 0x0eef -#define POL_mmCRTC4_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0 -#define POL_mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1 -#define POL_mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2 -#define POL_mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3 -#define POL_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4 -#define POL_mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5 -#define POL_mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATUS 0x0ef6 -#define POL_mmCRTC4_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATUS_POSITION 0x0ef7 -#define POL_mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8 -#define POL_mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9 -#define POL_mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa -#define POL_mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb -#define POL_mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_COUNT_CONTROL 0x0efc -#define POL_mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_COUNT_RESET 0x0efd -#define POL_mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe -#define POL_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff -#define POL_mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STEREO_STATUS 0x0f00 -#define POL_mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STEREO_CONTROL 0x0f01 -#define POL_mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02 -#define POL_mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03 -#define POL_mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04 -#define POL_mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05 -#define POL_mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06 -#define POL_mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07 -#define POL_mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_UPDATE_LOCK 0x0f08 -#define POL_mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09 -#define POL_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a -#define POL_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b -#define POL_mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c -#define POL_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d -#define POL_mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e -#define POL_mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f -#define POL_mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10 -#define POL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11 -#define POL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MVP_STATUS 0x0f12 -#define POL_mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_MASTER_EN 0x0f13 -#define POL_mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14 -#define POL_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15 -#define POL_mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17 -#define POL_mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18 -#define POL_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19 -#define POL_mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a -#define POL_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_BLACK_COLOR 0x0f1b -#define POL_mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c -#define POL_mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22 -#define POL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC_CNTL 0x0f23 -#define POL_mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27 -#define POL_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28 -#define POL_mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC0_DATA_B 0x0f29 -#define POL_mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a -#define POL_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b -#define POL_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c -#define POL_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d -#define POL_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e -#define POL_mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f -#define POL_mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35 -#define POL_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36 -#define POL_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37 -#define POL_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38 -#define POL_mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_GSL_WINDOW 0x0f39 -#define POL_mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_GSL_CONTROL 0x0f3a -#define POL_mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d -#define POL_mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC4_CRTC_DRR_CONTROL 0x0f3e -#define POL_mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt4_dispdec -// base address: 0x2000 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44 -#define POL_mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45 -#define POL_mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT4_FMT_CONTROL 0x0f46 -#define POL_mmFMT4_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47 -#define POL_mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48 -#define POL_mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49 -#define POL_mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a -#define POL_mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT4_FMT_CLAMP_CNTL 0x0f4e -#define POL_mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT4_FMT_CRC_CNTL 0x0f4f -#define POL_mmFMT4_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50 -#define POL_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51 -#define POL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52 -#define POL_mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53 -#define POL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54 -#define POL_mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55 -#define POL_mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_dcp5_dispdec -// base address: 0x2800 -#define POL_mmDCP5_GRPH_ENABLE 0x0f5a -#define POL_mmDCP5_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmDCP5_GRPH_CONTROL 0x0f5b -#define POL_mmDCP5_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c -#define POL_mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SWAP_CNTL 0x0f5d -#define POL_mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e -#define POL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f -#define POL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_PITCH 0x0f60 -#define POL_mmDCP5_GRPH_PITCH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61 -#define POL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62 -#define POL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63 -#define POL_mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64 -#define POL_mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 -#define POL_mmDCP5_GRPH_X_START 0x0f65 -#define POL_mmDCP5_GRPH_X_START_BASE_IDX 2 -#define POL_mmDCP5_GRPH_Y_START 0x0f66 -#define POL_mmDCP5_GRPH_Y_START_BASE_IDX 2 -#define POL_mmDCP5_GRPH_X_END 0x0f67 -#define POL_mmDCP5_GRPH_X_END_BASE_IDX 2 -#define POL_mmDCP5_GRPH_Y_END 0x0f68 -#define POL_mmDCP5_GRPH_Y_END_BASE_IDX 2 -#define POL_mmDCP5_INPUT_GAMMA_CONTROL 0x0f69 -#define POL_mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_UPDATE 0x0f6a -#define POL_mmDCP5_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmDCP5_GRPH_FLIP_CONTROL 0x0f6b -#define POL_mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c -#define POL_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 -#define POL_mmDCP5_GRPH_DFQ_CONTROL 0x0f6d -#define POL_mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_DFQ_STATUS 0x0f6e -#define POL_mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f -#define POL_mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70 -#define POL_mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71 -#define POL_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 -#define POL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72 -#define POL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_COMPRESS_PITCH 0x0f73 -#define POL_mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74 -#define POL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75 -#define POL_mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76 -#define POL_mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79 -#define POL_mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_CONTROL 0x0f7a -#define POL_mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C11_C12 0x0f7b -#define POL_mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C13_C14 0x0f7c -#define POL_mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C21_C22 0x0f7d -#define POL_mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C23_C24 0x0f7e -#define POL_mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C31_C32 0x0f7f -#define POL_mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP5_INPUT_CSC_C33_C34 0x0f80 -#define POL_mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_CONTROL 0x0f81 -#define POL_mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C11_C12 0x0f82 -#define POL_mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C13_C14 0x0f83 -#define POL_mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C21_C22 0x0f84 -#define POL_mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C23_C24 0x0f85 -#define POL_mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C31_C32 0x0f86 -#define POL_mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2 -#define POL_mmDCP5_OUTPUT_CSC_C33_C34 0x0f87 -#define POL_mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d -#define POL_mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93 -#define POL_mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 -#define POL_mmDCP5_DENORM_CONTROL 0x0f94 -#define POL_mmDCP5_DENORM_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_OUT_ROUND_CONTROL 0x0f95 -#define POL_mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98 -#define POL_mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 -#define POL_mmDCP5_KEY_CONTROL 0x0f99 -#define POL_mmDCP5_KEY_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_KEY_RANGE_ALPHA 0x0f9a -#define POL_mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2 -#define POL_mmDCP5_KEY_RANGE_RED 0x0f9b -#define POL_mmDCP5_KEY_RANGE_RED_BASE_IDX 2 -#define POL_mmDCP5_KEY_RANGE_GREEN 0x0f9c -#define POL_mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2 -#define POL_mmDCP5_KEY_RANGE_BLUE 0x0f9d -#define POL_mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2 -#define POL_mmDCP5_DEGAMMA_CONTROL 0x0f9e -#define POL_mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f -#define POL_mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0 -#define POL_mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1 -#define POL_mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2 -#define POL_mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3 -#define POL_mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4 -#define POL_mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5 -#define POL_mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2 -#define POL_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6 -#define POL_mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 -#define POL_mmDCP5_DCP_RANDOM_SEEDS 0x0fa7 -#define POL_mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2 -#define POL_mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8 -#define POL_mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmDCP5_CUR_CONTROL 0x0fa9 -#define POL_mmDCP5_CUR_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_CUR_SURFACE_ADDRESS 0x0faa -#define POL_mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP5_CUR_SIZE 0x0fab -#define POL_mmDCP5_CUR_SIZE_BASE_IDX 2 -#define POL_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac -#define POL_mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP5_CUR_POSITION 0x0fad -#define POL_mmDCP5_CUR_POSITION_BASE_IDX 2 -#define POL_mmDCP5_CUR_HOT_SPOT 0x0fae -#define POL_mmDCP5_CUR_HOT_SPOT_BASE_IDX 2 -#define POL_mmDCP5_CUR_COLOR1 0x0faf -#define POL_mmDCP5_CUR_COLOR1_BASE_IDX 2 -#define POL_mmDCP5_CUR_COLOR2 0x0fb0 -#define POL_mmDCP5_CUR_COLOR2_BASE_IDX 2 -#define POL_mmDCP5_CUR_UPDATE 0x0fb1 -#define POL_mmDCP5_CUR_UPDATE_BASE_IDX 2 -#define POL_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb -#define POL_mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 -#define POL_mmDCP5_CUR_STEREO_CONTROL 0x0fbc -#define POL_mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_RW_MODE 0x0fbe -#define POL_mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_RW_INDEX 0x0fbf -#define POL_mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0 -#define POL_mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_PWL_DATA 0x0fc1 -#define POL_mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_30_COLOR 0x0fc2 -#define POL_mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3 -#define POL_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4 -#define POL_mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_AUTOFILL 0x0fc5 -#define POL_mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_CONTROL 0x0fc6 -#define POL_mmDCP5_DC_LUT_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9 -#define POL_mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc -#define POL_mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 -#define POL_mmDCP5_DCP_CRC_CONTROL 0x0fcd -#define POL_mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_DCP_CRC_MASK 0x0fce -#define POL_mmDCP5_DCP_CRC_MASK_BASE_IDX 2 -#define POL_mmDCP5_DCP_CRC_CURRENT 0x0fcf -#define POL_mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmDCP5_DVMM_PTE_CONTROL 0x0fd0 -#define POL_mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_DCP_CRC_LAST 0x0fd1 -#define POL_mmDCP5_DCP_CRC_LAST_BASE_IDX 2 -#define POL_mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2 -#define POL_mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4 -#define POL_mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 -#define POL_mmDCP5_DCP_GSL_CONTROL 0x0fd5 -#define POL_mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6 -#define POL_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc -#define POL_mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmDCP5_HW_ROTATION 0x0fde -#define POL_mmDCP5_HW_ROTATION_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf -#define POL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CONTROL 0x0fe0 -#define POL_mmDCP5_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_LUT_INDEX 0x0fe1 -#define POL_mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_LUT_DATA 0x0fe2 -#define POL_mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3 -#define POL_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4 -#define POL_mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5 -#define POL_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6 -#define POL_mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7 -#define POL_mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef -#define POL_mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0 -#define POL_mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1 -#define POL_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2 -#define POL_mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3 -#define POL_mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb -#define POL_mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmDCP5_ALPHA_CONTROL 0x0ffc -#define POL_mmDCP5_ALPHA_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd -#define POL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe -#define POL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff -#define POL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000 -#define POL_mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 -#define POL_mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001 -#define POL_mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002 -#define POL_mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 -#define POL_mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003 -#define POL_mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 - - -// addressBlock: dce_dc_lb5_dispdec -// base address: 0x2800 -#define POL_mmLB5_LB_DATA_FORMAT 0x101a -#define POL_mmLB5_LB_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLB5_LB_MEMORY_CTRL 0x101b -#define POL_mmLB5_LB_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLB5_LB_MEMORY_SIZE_STATUS 0x101c -#define POL_mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_DESKTOP_HEIGHT 0x101d -#define POL_mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLB5_LB_VLINE_START_END 0x101e -#define POL_mmLB5_LB_VLINE_START_END_BASE_IDX 2 -#define POL_mmLB5_LB_VLINE2_START_END 0x101f -#define POL_mmLB5_LB_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLB5_LB_V_COUNTER 0x1020 -#define POL_mmLB5_LB_V_COUNTER_BASE_IDX 2 -#define POL_mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021 -#define POL_mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLB5_LB_INTERRUPT_MASK 0x1022 -#define POL_mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLB5_LB_VLINE_STATUS 0x1023 -#define POL_mmLB5_LB_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_VLINE2_STATUS 0x1024 -#define POL_mmLB5_LB_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_VBLANK_STATUS 0x1025 -#define POL_mmLB5_LB_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_SYNC_RESET_SEL 0x1026 -#define POL_mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLB5_LB_BLACK_KEYER_R_CR 0x1027 -#define POL_mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLB5_LB_BLACK_KEYER_G_Y 0x1028 -#define POL_mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLB5_LB_BLACK_KEYER_B_CB 0x1029 -#define POL_mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_CTRL 0x102a -#define POL_mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_R_CR 0x102b -#define POL_mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_G_Y 0x102c -#define POL_mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_B_CB 0x102d -#define POL_mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e -#define POL_mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f -#define POL_mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030 -#define POL_mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031 -#define POL_mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032 -#define POL_mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033 -#define POL_mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_BUFFER_STATUS 0x1034 -#define POL_mmLB5_LB_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035 -#define POL_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 -#define POL_mmLB5_MVP_AFR_FLIP_MODE 0x1036 -#define POL_mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2 -#define POL_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037 -#define POL_mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 -#define POL_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038 -#define POL_mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 -#define POL_mmLB5_DC_MVP_LB_CONTROL 0x1039 -#define POL_mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfe5_dispdec -// base address: 0x2800 -#define POL_mmDCFE5_DCFE_CLOCK_CONTROL 0x105a -#define POL_mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_SOFT_RESET 0x105b -#define POL_mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d -#define POL_mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e -#define POL_mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f -#define POL_mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_MISC 0x1060 -#define POL_mmDCFE5_DCFE_MISC_BASE_IDX 2 -#define POL_mmDCFE5_DCFE_FLUSH 0x1061 -#define POL_mmDCFE5_DCFE_FLUSH_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon8_dispdec -// base address: 0x4138 -#define POL_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e -#define POL_mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f -#define POL_mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070 -#define POL_mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_CNTL 0x1071 -#define POL_mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_CNTL2 0x1072 -#define POL_mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073 -#define POL_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074 -#define POL_mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_HI 0x1075 -#define POL_mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON8_PERFMON_LOW 0x1076 -#define POL_mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmif_pg5_dispdec -// base address: 0x2800 -#define POL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a -#define POL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b -#define POL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c -#define POL_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d -#define POL_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e -#define POL_mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f -#define POL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080 -#define POL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081 -#define POL_mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082 -#define POL_mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086 -#define POL_mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIF_PG5_DPG_DVMM_STATUS 0x1087 -#define POL_mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_scl5_dispdec -// base address: 0x2800 -#define POL_mmSCL5_SCL_COEF_RAM_SELECT 0x109a -#define POL_mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b -#define POL_mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCL5_SCL_MODE 0x109c -#define POL_mmSCL5_SCL_MODE_BASE_IDX 2 -#define POL_mmSCL5_SCL_TAP_CONTROL 0x109d -#define POL_mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_CONTROL 0x109e -#define POL_mmSCL5_SCL_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_BYPASS_CONTROL 0x109f -#define POL_mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0 -#define POL_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1 -#define POL_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2 -#define POL_mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3 -#define POL_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4 -#define POL_mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5 -#define POL_mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6 -#define POL_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCL5_SCL_VERT_FILTER_INIT 0x10a7 -#define POL_mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8 -#define POL_mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCL5_SCL_ROUND_OFFSET 0x10a9 -#define POL_mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCL5_SCL_UPDATE 0x10aa -#define POL_mmSCL5_SCL_UPDATE_BASE_IDX 2 -#define POL_mmSCL5_SCL_F_SHARP_CONTROL 0x10ab -#define POL_mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_ALU_CONTROL 0x10ac -#define POL_mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad -#define POL_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 -#define POL_mmSCL5_VIEWPORT_START_SECONDARY 0x10ae -#define POL_mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCL5_VIEWPORT_START 0x10af -#define POL_mmSCL5_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCL5_VIEWPORT_SIZE 0x10b0 -#define POL_mmSCL5_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1 -#define POL_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2 -#define POL_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5 -#define POL_mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6 -#define POL_mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2 - - -// addressBlock: dce_dc_blnd5_dispdec -// base address: 0x2800 -#define POL_mmBLND5_BLND_CONTROL 0x10c7 -#define POL_mmBLND5_BLND_CONTROL_BASE_IDX 2 -#define POL_mmBLND5_BLND_SM_CONTROL2 0x10c8 -#define POL_mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLND5_BLND_CONTROL2 0x10c9 -#define POL_mmBLND5_BLND_CONTROL2_BASE_IDX 2 -#define POL_mmBLND5_BLND_UPDATE 0x10ca -#define POL_mmBLND5_BLND_UPDATE_BASE_IDX 2 -#define POL_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb -#define POL_mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLND5_BLND_V_UPDATE_LOCK 0x10cc -#define POL_mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd -#define POL_mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtc5_dispdec -// base address: 0x2800 -#define POL_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2 -#define POL_mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_TOTAL 0x10d3 -#define POL_mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_BLANK_START_END 0x10d4 -#define POL_mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_SYNC_A 0x10d5 -#define POL_mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6 -#define POL_mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_SYNC_B 0x10d7 -#define POL_mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8 -#define POL_mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VBI_END 0x10d9 -#define POL_mmCRTC5_CRTC_VBI_END_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_TOTAL 0x10da -#define POL_mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_TOTAL_MIN 0x10db -#define POL_mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc -#define POL_mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd -#define POL_mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de -#define POL_mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df -#define POL_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_BLANK_START_END 0x10e0 -#define POL_mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_SYNC_A 0x10e1 -#define POL_mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2 -#define POL_mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_SYNC_B 0x10e3 -#define POL_mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4 -#define POL_mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5 -#define POL_mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6 -#define POL_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TRIGA_CNTL 0x10e7 -#define POL_mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8 -#define POL_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TRIGB_CNTL 0x10e9 -#define POL_mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea -#define POL_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb -#define POL_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_FLOW_CONTROL 0x10ec -#define POL_mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed -#define POL_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee -#define POL_mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CONTROL 0x10ef -#define POL_mmCRTC5_CRTC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_BLANK_CONTROL 0x10f0 -#define POL_mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1 -#define POL_mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2 -#define POL_mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3 -#define POL_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4 -#define POL_mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5 -#define POL_mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATUS 0x10f6 -#define POL_mmCRTC5_CRTC_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATUS_POSITION 0x10f7 -#define POL_mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8 -#define POL_mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9 -#define POL_mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa -#define POL_mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb -#define POL_mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_COUNT_CONTROL 0x10fc -#define POL_mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_COUNT_RESET 0x10fd -#define POL_mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe -#define POL_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff -#define POL_mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STEREO_STATUS 0x1100 -#define POL_mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STEREO_CONTROL 0x1101 -#define POL_mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102 -#define POL_mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103 -#define POL_mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104 -#define POL_mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105 -#define POL_mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_START_LINE_CONTROL 0x1106 -#define POL_mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107 -#define POL_mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_UPDATE_LOCK 0x1108 -#define POL_mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109 -#define POL_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a -#define POL_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b -#define POL_mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c -#define POL_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d -#define POL_mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e -#define POL_mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f -#define POL_mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110 -#define POL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111 -#define POL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MVP_STATUS 0x1112 -#define POL_mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_MASTER_EN 0x1113 -#define POL_mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114 -#define POL_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115 -#define POL_mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117 -#define POL_mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118 -#define POL_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119 -#define POL_mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a -#define POL_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_BLACK_COLOR 0x111b -#define POL_mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c -#define POL_mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122 -#define POL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC_CNTL 0x1123 -#define POL_mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127 -#define POL_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_DATA_RG 0x1128 -#define POL_mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC0_DATA_B 0x1129 -#define POL_mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a -#define POL_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b -#define POL_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c -#define POL_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d -#define POL_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_DATA_RG 0x112e -#define POL_mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_CRC1_DATA_B 0x112f -#define POL_mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135 -#define POL_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136 -#define POL_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137 -#define POL_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138 -#define POL_mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_GSL_WINDOW 0x1139 -#define POL_mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_GSL_CONTROL 0x113a -#define POL_mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d -#define POL_mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTC5_CRTC_DRR_CONTROL 0x113e -#define POL_mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_fmt5_dispdec -// base address: 0x2800 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144 -#define POL_mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 -#define POL_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145 -#define POL_mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 -#define POL_mmFMT5_FMT_CONTROL 0x1146 -#define POL_mmFMT5_FMT_CONTROL_BASE_IDX 2 -#define POL_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147 -#define POL_mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 -#define POL_mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148 -#define POL_mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 -#define POL_mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149 -#define POL_mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 -#define POL_mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a -#define POL_mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 -#define POL_mmFMT5_FMT_CLAMP_CNTL 0x114e -#define POL_mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 -#define POL_mmFMT5_FMT_CRC_CNTL 0x114f -#define POL_mmFMT5_FMT_CRC_CNTL_BASE_IDX 2 -#define POL_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150 -#define POL_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 -#define POL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151 -#define POL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 -#define POL_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152 -#define POL_mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 -#define POL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153 -#define POL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 -#define POL_mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154 -#define POL_mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155 -#define POL_mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 - - -// addressBlock: dce_dc_unp0_dispdec -// base address: 0x0 -#define POL_mmUNP0_UNP_GRPH_ENABLE 0x115a -#define POL_mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_CONTROL 0x115b -#define POL_mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_CONTROL_C 0x115c -#define POL_mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d -#define POL_mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e -#define POL_mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166 -#define POL_mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a -#define POL_mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e -#define POL_mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PITCH_L 0x116f -#define POL_mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_PITCH_C 0x1170 -#define POL_mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174 -#define POL_mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_X_START_L 0x1175 -#define POL_mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_X_START_C 0x1176 -#define POL_mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_Y_START_L 0x1177 -#define POL_mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_Y_START_C 0x1178 -#define POL_mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_X_END_L 0x1179 -#define POL_mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_X_END_C 0x117a -#define POL_mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_Y_END_L 0x117b -#define POL_mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_Y_END_C 0x117c -#define POL_mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_UPDATE 0x117d -#define POL_mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e -#define POL_mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182 -#define POL_mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183 -#define POL_mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184 -#define POL_mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185 -#define POL_mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186 -#define POL_mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187 -#define POL_mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188 -#define POL_mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189 -#define POL_mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmUNP0_UNP_FLIP_CONTROL 0x118a -#define POL_mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_CRC_CONTROL 0x118b -#define POL_mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmUNP0_UNP_CRC_MASK 0x118c -#define POL_mmUNP0_UNP_CRC_MASK_BASE_IDX 2 -#define POL_mmUNP0_UNP_CRC_CURRENT 0x118d -#define POL_mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmUNP0_UNP_CRC_LAST 0x118e -#define POL_mmUNP0_UNP_CRC_LAST_BASE_IDX 2 -#define POL_mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f -#define POL_mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmUNP0_UNP_HW_ROTATION 0x1190 -#define POL_mmUNP0_UNP_HW_ROTATION_BASE_IDX 2 - - -// addressBlock: dce_dc_lbv0_dispdec -// base address: 0x0 -#define POL_mmLBV0_LBV_DATA_FORMAT 0x1196 -#define POL_mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLBV0_LBV_MEMORY_CTRL 0x1197 -#define POL_mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198 -#define POL_mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_DESKTOP_HEIGHT 0x1199 -#define POL_mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLBV0_LBV_VLINE_START_END 0x119a -#define POL_mmLBV0_LBV_VLINE_START_END_BASE_IDX 2 -#define POL_mmLBV0_LBV_VLINE2_START_END 0x119b -#define POL_mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLBV0_LBV_V_COUNTER 0x119c -#define POL_mmLBV0_LBV_V_COUNTER_BASE_IDX 2 -#define POL_mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d -#define POL_mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLBV0_LBV_V_COUNTER_CHROMA 0x119e -#define POL_mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2 -#define POL_mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f -#define POL_mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2 -#define POL_mmLBV0_LBV_INTERRUPT_MASK 0x11a0 -#define POL_mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLBV0_LBV_VLINE_STATUS 0x11a1 -#define POL_mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_VLINE2_STATUS 0x11a2 -#define POL_mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_VBLANK_STATUS 0x11a3 -#define POL_mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_SYNC_RESET_SEL 0x11a4 -#define POL_mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5 -#define POL_mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6 -#define POL_mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7 -#define POL_mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8 -#define POL_mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9 -#define POL_mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa -#define POL_mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab -#define POL_mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae -#define POL_mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af -#define POL_mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0 -#define POL_mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1 -#define POL_mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_BUFFER_STATUS 0x11b2 -#define POL_mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3 -#define POL_mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_sclv0_dispdec -// base address: 0x0 -#define POL_mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca -#define POL_mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb -#define POL_mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MODE 0x11cc -#define POL_mmSCLV0_SCLV_MODE_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_TAP_CONTROL 0x11cd -#define POL_mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_CONTROL 0x11ce -#define POL_mmSCLV0_SCLV_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf -#define POL_mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0 -#define POL_mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6 -#define POL_mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7 -#define POL_mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da -#define POL_mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc -#define POL_mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_ROUND_OFFSET 0x11dd -#define POL_mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_UPDATE 0x11de -#define POL_mmSCLV0_SCLV_UPDATE_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_ALU_CONTROL 0x11df -#define POL_mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_START 0x11e0 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2 -#define POL_mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4 -#define POL_mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5 -#define POL_mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6 -#define POL_mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7 -#define POL_mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea -#define POL_mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb -#define POL_mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed -#define POL_mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2 - - -// addressBlock: dce_dc_col_man0_dispdec -// base address: 0x0 -#define POL_mmCOL_MAN0_COL_MAN_UPDATE 0x11fe -#define POL_mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff -#define POL_mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200 -#define POL_mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201 -#define POL_mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202 -#define POL_mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203 -#define POL_mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204 -#define POL_mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205 -#define POL_mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206 -#define POL_mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207 -#define POL_mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208 -#define POL_mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209 -#define POL_mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a -#define POL_mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b -#define POL_mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_PRESCALE_CONTROL 0x120c -#define POL_mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_PRESCALE_VALUES_R 0x120d -#define POL_mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2 -#define POL_mmCOL_MAN0_PRESCALE_VALUES_G 0x120e -#define POL_mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2 -#define POL_mmCOL_MAN0_PRESCALE_VALUES_B 0x120f -#define POL_mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210 -#define POL_mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a -#define POL_mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b -#define POL_mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c -#define POL_mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d -#define POL_mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2 -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2 -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220 -#define POL_mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221 -#define POL_mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d -#define POL_mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmCOL_MAN0_PACK_FIFO_ERROR 0x123e -#define POL_mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2 -#define POL_mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f -#define POL_mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244 -#define POL_mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245 -#define POL_mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246 -#define POL_mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249 -#define POL_mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a -#define POL_mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251 -#define POL_mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfev0_dispdec -// base address: 0x0 -#define POL_mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e -#define POL_mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_SOFT_RESET 0x127f -#define POL_mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280 -#define POL_mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282 -#define POL_mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283 -#define POL_mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286 -#define POL_mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_L_FLUSH 0x1287 -#define POL_mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_C_FLUSH 0x1288 -#define POL_mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2 -#define POL_mmDCFEV0_DCFEV_MISC 0x128a -#define POL_mmDCFEV0_DCFEV_MISC_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon11_dispdec -// base address: 0x49c8 -#define POL_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292 -#define POL_mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293 -#define POL_mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294 -#define POL_mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_CNTL 0x1295 -#define POL_mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_CNTL2 0x1296 -#define POL_mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297 -#define POL_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298 -#define POL_mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_HI 0x1299 -#define POL_mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON11_PERFMON_LOW 0x129a -#define POL_mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmifv_pg0_dispdec -// base address: 0x0 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e -#define POL_mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f -#define POL_mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0 -#define POL_mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5 -#define POL_mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6 -#define POL_mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa -#define POL_mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab -#define POL_mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac -#define POL_mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad -#define POL_mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae -#define POL_mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af -#define POL_mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2 -#define POL_mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3 -#define POL_mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7 -#define POL_mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_blndv0_dispdec -// base address: 0x0 -#define POL_mmBLNDV0_BLNDV_CONTROL 0x12db -#define POL_mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc -#define POL_mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_CONTROL2 0x12dd -#define POL_mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_UPDATE 0x12de -#define POL_mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df -#define POL_mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0 -#define POL_mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1 -#define POL_mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtcv0_dispdec -// base address: 0x0 -#define POL_mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6 -#define POL_mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_TOTAL 0x12e7 -#define POL_mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8 -#define POL_mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_SYNC_A 0x12e9 -#define POL_mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea -#define POL_mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_SYNC_B 0x12eb -#define POL_mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec -#define POL_mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VBI_END 0x12ed -#define POL_mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL 0x12ee -#define POL_mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef -#define POL_mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2 -#define POL_mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3 -#define POL_mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4 -#define POL_mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_SYNC_A 0x12f5 -#define POL_mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6 -#define POL_mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_SYNC_B 0x12f7 -#define POL_mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8 -#define POL_mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9 -#define POL_mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa -#define POL_mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb -#define POL_mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc -#define POL_mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd -#define POL_mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe -#define POL_mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff -#define POL_mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300 -#define POL_mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301 -#define POL_mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302 -#define POL_mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CONTROL 0x1303 -#define POL_mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304 -#define POL_mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305 -#define POL_mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306 -#define POL_mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307 -#define POL_mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308 -#define POL_mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309 -#define POL_mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATUS 0x130a -#define POL_mmCRTCV0_CRTCV_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATUS_POSITION 0x130b -#define POL_mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c -#define POL_mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d -#define POL_mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e -#define POL_mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f -#define POL_mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310 -#define POL_mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_COUNT_RESET 0x1311 -#define POL_mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312 -#define POL_mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313 -#define POL_mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STEREO_STATUS 0x1314 -#define POL_mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315 -#define POL_mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319 -#define POL_mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a -#define POL_mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b -#define POL_mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c -#define POL_mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d -#define POL_mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e -#define POL_mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320 -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321 -#define POL_mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322 -#define POL_mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323 -#define POL_mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324 -#define POL_mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325 -#define POL_mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MVP_STATUS 0x1326 -#define POL_mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_MASTER_EN 0x1327 -#define POL_mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328 -#define POL_mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329 -#define POL_mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b -#define POL_mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c -#define POL_mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d -#define POL_mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e -#define POL_mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_BLACK_COLOR 0x132f -#define POL_mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330 -#define POL_mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336 -#define POL_mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC_CNTL 0x1337 -#define POL_mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b -#define POL_mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c -#define POL_mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d -#define POL_mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341 -#define POL_mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342 -#define POL_mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343 -#define POL_mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349 -#define POL_mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a -#define POL_mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b -#define POL_mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c -#define POL_mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_GSL_WINDOW 0x134d -#define POL_mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTCV0_CRTCV_GSL_CONTROL 0x134e -#define POL_mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_unp1_dispdec -// base address: 0x800 -#define POL_mmUNP1_UNP_GRPH_ENABLE 0x135a -#define POL_mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_CONTROL 0x135b -#define POL_mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_CONTROL_C 0x135c -#define POL_mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d -#define POL_mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e -#define POL_mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366 -#define POL_mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a -#define POL_mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e -#define POL_mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PITCH_L 0x136f -#define POL_mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_PITCH_C 0x1370 -#define POL_mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374 -#define POL_mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_X_START_L 0x1375 -#define POL_mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_X_START_C 0x1376 -#define POL_mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_Y_START_L 0x1377 -#define POL_mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_Y_START_C 0x1378 -#define POL_mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_X_END_L 0x1379 -#define POL_mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_X_END_C 0x137a -#define POL_mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_Y_END_L 0x137b -#define POL_mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_Y_END_C 0x137c -#define POL_mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_UPDATE 0x137d -#define POL_mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2 -#define POL_mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e -#define POL_mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382 -#define POL_mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383 -#define POL_mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384 -#define POL_mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385 -#define POL_mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386 -#define POL_mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387 -#define POL_mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388 -#define POL_mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389 -#define POL_mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 -#define POL_mmUNP1_UNP_FLIP_CONTROL 0x138a -#define POL_mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_CRC_CONTROL 0x138b -#define POL_mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2 -#define POL_mmUNP1_UNP_CRC_MASK 0x138c -#define POL_mmUNP1_UNP_CRC_MASK_BASE_IDX 2 -#define POL_mmUNP1_UNP_CRC_CURRENT 0x138d -#define POL_mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2 -#define POL_mmUNP1_UNP_CRC_LAST 0x138e -#define POL_mmUNP1_UNP_CRC_LAST_BASE_IDX 2 -#define POL_mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f -#define POL_mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 -#define POL_mmUNP1_UNP_HW_ROTATION 0x1390 -#define POL_mmUNP1_UNP_HW_ROTATION_BASE_IDX 2 - - -// addressBlock: dce_dc_lbv1_dispdec -// base address: 0x800 -#define POL_mmLBV1_LBV_DATA_FORMAT 0x1396 -#define POL_mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2 -#define POL_mmLBV1_LBV_MEMORY_CTRL 0x1397 -#define POL_mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2 -#define POL_mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398 -#define POL_mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_DESKTOP_HEIGHT 0x1399 -#define POL_mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2 -#define POL_mmLBV1_LBV_VLINE_START_END 0x139a -#define POL_mmLBV1_LBV_VLINE_START_END_BASE_IDX 2 -#define POL_mmLBV1_LBV_VLINE2_START_END 0x139b -#define POL_mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2 -#define POL_mmLBV1_LBV_V_COUNTER 0x139c -#define POL_mmLBV1_LBV_V_COUNTER_BASE_IDX 2 -#define POL_mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d -#define POL_mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2 -#define POL_mmLBV1_LBV_V_COUNTER_CHROMA 0x139e -#define POL_mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2 -#define POL_mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f -#define POL_mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2 -#define POL_mmLBV1_LBV_INTERRUPT_MASK 0x13a0 -#define POL_mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmLBV1_LBV_VLINE_STATUS 0x13a1 -#define POL_mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_VLINE2_STATUS 0x13a2 -#define POL_mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_VBLANK_STATUS 0x13a3 -#define POL_mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_SYNC_RESET_SEL 0x13a4 -#define POL_mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2 -#define POL_mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5 -#define POL_mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2 -#define POL_mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6 -#define POL_mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2 -#define POL_mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7 -#define POL_mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8 -#define POL_mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9 -#define POL_mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa -#define POL_mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab -#define POL_mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2 -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae -#define POL_mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2 -#define POL_mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af -#define POL_mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0 -#define POL_mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2 -#define POL_mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1 -#define POL_mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_BUFFER_STATUS 0x13b2 -#define POL_mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2 -#define POL_mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3 -#define POL_mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_sclv1_dispdec -// base address: 0x800 -#define POL_mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca -#define POL_mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb -#define POL_mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MODE 0x13cc -#define POL_mmSCLV1_SCLV_MODE_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_TAP_CONTROL 0x13cd -#define POL_mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_CONTROL 0x13ce -#define POL_mmSCLV1_SCLV_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf -#define POL_mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0 -#define POL_mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6 -#define POL_mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7 -#define POL_mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da -#define POL_mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc -#define POL_mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_ROUND_OFFSET 0x13dd -#define POL_mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_UPDATE 0x13de -#define POL_mmSCLV1_SCLV_UPDATE_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_ALU_CONTROL 0x13df -#define POL_mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_START 0x13e0 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2 -#define POL_mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4 -#define POL_mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5 -#define POL_mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6 -#define POL_mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7 -#define POL_mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea -#define POL_mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb -#define POL_mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2 -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed -#define POL_mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2 - - -// addressBlock: dce_dc_col_man1_dispdec -// base address: 0x800 -#define POL_mmCOL_MAN1_COL_MAN_UPDATE 0x13fe -#define POL_mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff -#define POL_mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400 -#define POL_mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401 -#define POL_mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402 -#define POL_mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403 -#define POL_mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404 -#define POL_mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405 -#define POL_mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406 -#define POL_mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407 -#define POL_mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408 -#define POL_mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409 -#define POL_mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a -#define POL_mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b -#define POL_mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_PRESCALE_CONTROL 0x140c -#define POL_mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_PRESCALE_VALUES_R 0x140d -#define POL_mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2 -#define POL_mmCOL_MAN1_PRESCALE_VALUES_G 0x140e -#define POL_mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2 -#define POL_mmCOL_MAN1_PRESCALE_VALUES_B 0x140f -#define POL_mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410 -#define POL_mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a -#define POL_mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b -#define POL_mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c -#define POL_mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d -#define POL_mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2 -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2 -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420 -#define POL_mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421 -#define POL_mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d -#define POL_mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 -#define POL_mmCOL_MAN1_PACK_FIFO_ERROR 0x143e -#define POL_mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2 -#define POL_mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f -#define POL_mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444 -#define POL_mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445 -#define POL_mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446 -#define POL_mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449 -#define POL_mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a -#define POL_mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451 -#define POL_mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2 - - -// addressBlock: dce_dc_dcfev1_dispdec -// base address: 0x800 -#define POL_mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e -#define POL_mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_SOFT_RESET 0x147f -#define POL_mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480 -#define POL_mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482 -#define POL_mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483 -#define POL_mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486 -#define POL_mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_L_FLUSH 0x1487 -#define POL_mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_C_FLUSH 0x1488 -#define POL_mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2 -#define POL_mmDCFEV1_DCFEV_MISC 0x148a -#define POL_mmDCFEV1_DCFEV_MISC_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon12_dispdec -// base address: 0x51c8 -#define POL_mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492 -#define POL_mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493 -#define POL_mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494 -#define POL_mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_CNTL 0x1495 -#define POL_mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_CNTL2 0x1496 -#define POL_mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497 -#define POL_mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498 -#define POL_mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_HI 0x1499 -#define POL_mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON12_PERFMON_LOW 0x149a -#define POL_mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dmifv_pg1_dispdec -// base address: 0x800 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e -#define POL_mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f -#define POL_mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0 -#define POL_mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5 -#define POL_mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6 -#define POL_mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa -#define POL_mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab -#define POL_mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac -#define POL_mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad -#define POL_mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae -#define POL_mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af -#define POL_mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2 -#define POL_mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3 -#define POL_mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2 -#define POL_mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7 -#define POL_mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_blndv1_dispdec -// base address: 0x800 -#define POL_mmBLNDV1_BLNDV_CONTROL 0x14db -#define POL_mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc -#define POL_mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_CONTROL2 0x14dd -#define POL_mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_UPDATE 0x14de -#define POL_mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df -#define POL_mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0 -#define POL_mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1 -#define POL_mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_crtcv1_dispdec -// base address: 0x800 -#define POL_mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6 -#define POL_mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_TOTAL 0x14e7 -#define POL_mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8 -#define POL_mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_SYNC_A 0x14e9 -#define POL_mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea -#define POL_mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_SYNC_B 0x14eb -#define POL_mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec -#define POL_mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VBI_END 0x14ed -#define POL_mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL 0x14ee -#define POL_mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef -#define POL_mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2 -#define POL_mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3 -#define POL_mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4 -#define POL_mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_SYNC_A 0x14f5 -#define POL_mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6 -#define POL_mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_SYNC_B 0x14f7 -#define POL_mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8 -#define POL_mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9 -#define POL_mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa -#define POL_mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb -#define POL_mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc -#define POL_mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd -#define POL_mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe -#define POL_mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff -#define POL_mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500 -#define POL_mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501 -#define POL_mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502 -#define POL_mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CONTROL 0x1503 -#define POL_mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504 -#define POL_mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505 -#define POL_mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506 -#define POL_mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507 -#define POL_mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508 -#define POL_mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509 -#define POL_mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATUS 0x150a -#define POL_mmCRTCV1_CRTCV_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATUS_POSITION 0x150b -#define POL_mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c -#define POL_mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d -#define POL_mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e -#define POL_mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f -#define POL_mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510 -#define POL_mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_COUNT_RESET 0x1511 -#define POL_mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512 -#define POL_mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513 -#define POL_mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STEREO_STATUS 0x1514 -#define POL_mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515 -#define POL_mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519 -#define POL_mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a -#define POL_mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b -#define POL_mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c -#define POL_mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d -#define POL_mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e -#define POL_mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520 -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521 -#define POL_mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522 -#define POL_mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523 -#define POL_mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524 -#define POL_mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525 -#define POL_mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MVP_STATUS 0x1526 -#define POL_mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_MASTER_EN 0x1527 -#define POL_mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528 -#define POL_mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529 -#define POL_mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b -#define POL_mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c -#define POL_mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d -#define POL_mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e -#define POL_mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_BLACK_COLOR 0x152f -#define POL_mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530 -#define POL_mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536 -#define POL_mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC_CNTL 0x1537 -#define POL_mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b -#define POL_mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c -#define POL_mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d -#define POL_mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541 -#define POL_mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542 -#define POL_mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543 -#define POL_mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549 -#define POL_mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a -#define POL_mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b -#define POL_mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c -#define POL_mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_GSL_WINDOW 0x154d -#define POL_mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2 -#define POL_mmCRTCV1_CRTCV_GSL_CONTROL 0x154e -#define POL_mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd0_dispdec -// base address: 0x0 -#define POL_mmHPD0_DC_HPD_INT_STATUS 0x1600 -#define POL_mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD0_DC_HPD_INT_CONTROL 0x1601 -#define POL_mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD0_DC_HPD_CONTROL 0x1602 -#define POL_mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603 -#define POL_mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604 -#define POL_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd1_dispdec -// base address: 0x20 -#define POL_mmHPD1_DC_HPD_INT_STATUS 0x1608 -#define POL_mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD1_DC_HPD_INT_CONTROL 0x1609 -#define POL_mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD1_DC_HPD_CONTROL 0x160a -#define POL_mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b -#define POL_mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c -#define POL_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd2_dispdec -// base address: 0x40 -#define POL_mmHPD2_DC_HPD_INT_STATUS 0x1610 -#define POL_mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD2_DC_HPD_INT_CONTROL 0x1611 -#define POL_mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD2_DC_HPD_CONTROL 0x1612 -#define POL_mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613 -#define POL_mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614 -#define POL_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd3_dispdec -// base address: 0x60 -#define POL_mmHPD3_DC_HPD_INT_STATUS 0x1618 -#define POL_mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD3_DC_HPD_INT_CONTROL 0x1619 -#define POL_mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD3_DC_HPD_CONTROL 0x161a -#define POL_mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b -#define POL_mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c -#define POL_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd4_dispdec -// base address: 0x80 -#define POL_mmHPD4_DC_HPD_INT_STATUS 0x1620 -#define POL_mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD4_DC_HPD_INT_CONTROL 0x1621 -#define POL_mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD4_DC_HPD_CONTROL 0x1622 -#define POL_mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623 -#define POL_mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624 -#define POL_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_hpd5_dispdec -// base address: 0xa0 -#define POL_mmHPD5_DC_HPD_INT_STATUS 0x1628 -#define POL_mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 -#define POL_mmHPD5_DC_HPD_INT_CONTROL 0x1629 -#define POL_mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 -#define POL_mmHPD5_DC_HPD_CONTROL 0x162a -#define POL_mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 -#define POL_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b -#define POL_mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 -#define POL_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c -#define POL_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon2_dispdec -// base address: 0x5840 -#define POL_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630 -#define POL_mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631 -#define POL_mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632 -#define POL_mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_CNTL 0x1633 -#define POL_mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_CNTL2 0x1634 -#define POL_mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635 -#define POL_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636 -#define POL_mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_HI 0x1637 -#define POL_mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON2_PERFMON_LOW 0x1638 -#define POL_mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux0_dispdec -// base address: 0x0 -#define POL_mmDP_AUX0_AUX_CONTROL 0x1766 -#define POL_mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_SW_CONTROL 0x1767 -#define POL_mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_ARB_CONTROL 0x1768 -#define POL_mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769 -#define POL_mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_SW_STATUS 0x176a -#define POL_mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_LS_STATUS 0x176b -#define POL_mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_SW_DATA 0x176c -#define POL_mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_LS_DATA 0x176d -#define POL_mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e -#define POL_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f -#define POL_mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770 -#define POL_mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771 -#define POL_mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772 -#define POL_mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773 -#define POL_mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777 -#define POL_mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux1_dispdec -// base address: 0x70 -#define POL_mmDP_AUX1_AUX_CONTROL 0x1782 -#define POL_mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_SW_CONTROL 0x1783 -#define POL_mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_ARB_CONTROL 0x1784 -#define POL_mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785 -#define POL_mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_SW_STATUS 0x1786 -#define POL_mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_LS_STATUS 0x1787 -#define POL_mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_SW_DATA 0x1788 -#define POL_mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_LS_DATA 0x1789 -#define POL_mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a -#define POL_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b -#define POL_mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c -#define POL_mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d -#define POL_mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e -#define POL_mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f -#define POL_mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793 -#define POL_mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux2_dispdec -// base address: 0xe0 -#define POL_mmDP_AUX2_AUX_CONTROL 0x179e -#define POL_mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_SW_CONTROL 0x179f -#define POL_mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_ARB_CONTROL 0x17a0 -#define POL_mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1 -#define POL_mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_SW_STATUS 0x17a2 -#define POL_mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_LS_STATUS 0x17a3 -#define POL_mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_SW_DATA 0x17a4 -#define POL_mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_LS_DATA 0x17a5 -#define POL_mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6 -#define POL_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7 -#define POL_mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8 -#define POL_mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9 -#define POL_mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa -#define POL_mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab -#define POL_mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad -#define POL_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae -#define POL_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af -#define POL_mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux3_dispdec -// base address: 0x150 -#define POL_mmDP_AUX3_AUX_CONTROL 0x17ba -#define POL_mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_SW_CONTROL 0x17bb -#define POL_mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_ARB_CONTROL 0x17bc -#define POL_mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd -#define POL_mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_SW_STATUS 0x17be -#define POL_mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_LS_STATUS 0x17bf -#define POL_mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_SW_DATA 0x17c0 -#define POL_mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_LS_DATA 0x17c1 -#define POL_mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2 -#define POL_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3 -#define POL_mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4 -#define POL_mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5 -#define POL_mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6 -#define POL_mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7 -#define POL_mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9 -#define POL_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca -#define POL_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb -#define POL_mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux4_dispdec -// base address: 0x1c0 -#define POL_mmDP_AUX4_AUX_CONTROL 0x17d6 -#define POL_mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_SW_CONTROL 0x17d7 -#define POL_mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_ARB_CONTROL 0x17d8 -#define POL_mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9 -#define POL_mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_SW_STATUS 0x17da -#define POL_mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_LS_STATUS 0x17db -#define POL_mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_SW_DATA 0x17dc -#define POL_mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_LS_DATA 0x17dd -#define POL_mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de -#define POL_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df -#define POL_mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0 -#define POL_mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1 -#define POL_mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2 -#define POL_mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3 -#define POL_mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7 -#define POL_mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dp_aux5_dispdec -// base address: 0x230 -#define POL_mmDP_AUX5_AUX_CONTROL 0x17f2 -#define POL_mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_SW_CONTROL 0x17f3 -#define POL_mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_ARB_CONTROL 0x17f4 -#define POL_mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5 -#define POL_mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_SW_STATUS 0x17f6 -#define POL_mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_LS_STATUS 0x17f7 -#define POL_mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_SW_DATA 0x17f8 -#define POL_mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_LS_DATA 0x17f9 -#define POL_mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa -#define POL_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb -#define POL_mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc -#define POL_mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd -#define POL_mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe -#define POL_mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff -#define POL_mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803 -#define POL_mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig0_dispdec -// base address: 0x0 -#define POL_mmDIG0_DIG_FE_CNTL 0x187e -#define POL_mmDIG0_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f -#define POL_mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880 -#define POL_mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG0_DIG_CLOCK_PATTERN 0x1881 -#define POL_mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG0_DIG_TEST_PATTERN 0x1882 -#define POL_mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883 -#define POL_mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG0_DIG_FIFO_STATUS 0x1884 -#define POL_mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG0_HDMI_CONTROL 0x1887 -#define POL_mmDIG0_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_HDMI_STATUS 0x1888 -#define POL_mmDIG0_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889 -#define POL_mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a -#define POL_mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b -#define POL_mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c -#define POL_mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d -#define POL_mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e -#define POL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_INTERRUPT_STATUS 0x188f -#define POL_mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG0_HDMI_GC 0x1891 -#define POL_mmDIG0_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892 -#define POL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC1_0 0x1893 -#define POL_mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC1_1 0x1894 -#define POL_mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC1_2 0x1895 -#define POL_mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC1_3 0x1896 -#define POL_mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC1_4 0x1897 -#define POL_mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC2_0 0x1898 -#define POL_mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC2_1 0x1899 -#define POL_mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC2_2 0x189a -#define POL_mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_ISRC2_3 0x189b -#define POL_mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AVI_INFO0 0x189c -#define POL_mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AVI_INFO1 0x189d -#define POL_mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AVI_INFO2 0x189e -#define POL_mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AVI_INFO3 0x189f -#define POL_mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG0_AFMT_MPEG_INFO0 0x18a0 -#define POL_mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_MPEG_INFO1 0x18a1 -#define POL_mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_HDR 0x18a2 -#define POL_mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_0 0x18a3 -#define POL_mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_1 0x18a4 -#define POL_mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_2 0x18a5 -#define POL_mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_3 0x18a6 -#define POL_mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_4 0x18a7 -#define POL_mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_5 0x18a8 -#define POL_mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_6 0x18a9 -#define POL_mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG0_AFMT_GENERIC_7 0x18aa -#define POL_mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab -#define POL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_32_0 0x18ac -#define POL_mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_32_1 0x18ad -#define POL_mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_44_0 0x18ae -#define POL_mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_44_1 0x18af -#define POL_mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_48_0 0x18b0 -#define POL_mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_48_1 0x18b1 -#define POL_mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_STATUS_0 0x18b2 -#define POL_mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG0_HDMI_ACR_STATUS_1 0x18b3 -#define POL_mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_INFO0 0x18b4 -#define POL_mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_INFO1 0x18b5 -#define POL_mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_60958_0 0x18b6 -#define POL_mmDIG0_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_60958_1 0x18b7 -#define POL_mmDIG0_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8 -#define POL_mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_AFMT_RAMP_CONTROL0 0x18b9 -#define POL_mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_RAMP_CONTROL1 0x18ba -#define POL_mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG0_AFMT_RAMP_CONTROL2 0x18bb -#define POL_mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_RAMP_CONTROL3 0x18bc -#define POL_mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG0_AFMT_60958_2 0x18bd -#define POL_mmDIG0_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be -#define POL_mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG0_AFMT_STATUS 0x18bf -#define POL_mmDIG0_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0 -#define POL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1 -#define POL_mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2 -#define POL_mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3 -#define POL_mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_DIG_BE_CNTL 0x18c5 -#define POL_mmDIG0_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG0_DIG_BE_EN_CNTL 0x18c6 -#define POL_mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CNTL 0x18e9 -#define POL_mmDIG0_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CONTROL_CHAR 0x18ea -#define POL_mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb -#define POL_mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec -#define POL_mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed -#define POL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee -#define POL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CTL_BITS 0x18f0 -#define POL_mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1 -#define POL_mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3 -#define POL_mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4 -#define POL_mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG0_DIG_VERSION 0x18f6 -#define POL_mmDIG0_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG0_DIG_LANE_ENABLE 0x18f7 -#define POL_mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG0_AFMT_CNTL 0x18fc -#define POL_mmDIG0_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp0_dispdec -// base address: 0x0 -#define POL_mmDP0_DP_LINK_CNTL 0x191e -#define POL_mmDP0_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_PIXEL_FORMAT 0x191f -#define POL_mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP0_DP_MSA_COLORIMETRY 0x1920 -#define POL_mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP0_DP_CONFIG 0x1921 -#define POL_mmDP0_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP0_DP_VID_STREAM_CNTL 0x1922 -#define POL_mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_STEER_FIFO 0x1923 -#define POL_mmDP0_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP0_DP_MSA_MISC 0x1924 -#define POL_mmDP0_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP0_DP_VID_TIMING 0x1926 -#define POL_mmDP0_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP0_DP_VID_N 0x1927 -#define POL_mmDP0_DP_VID_N_BASE_IDX 2 -#define POL_mmDP0_DP_VID_M 0x1928 -#define POL_mmDP0_DP_VID_M_BASE_IDX 2 -#define POL_mmDP0_DP_LINK_FRAMING_CNTL 0x1929 -#define POL_mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_HBR2_EYE_PATTERN 0x192a -#define POL_mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP0_DP_VID_MSA_VBID 0x192b -#define POL_mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP0_DP_VID_INTERRUPT_CNTL 0x192c -#define POL_mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CNTL 0x192d -#define POL_mmDP0_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e -#define POL_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_SYM0 0x192f -#define POL_mmDP0_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_SYM1 0x1930 -#define POL_mmDP0_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_SYM2 0x1931 -#define POL_mmDP0_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_8B10B_CNTL 0x1932 -#define POL_mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_PRBS_CNTL 0x1933 -#define POL_mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_SCRAM_CNTL 0x1934 -#define POL_mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CRC_EN 0x1935 -#define POL_mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CRC_CNTL 0x1936 -#define POL_mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CRC_RESULT 0x1937 -#define POL_mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938 -#define POL_mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939 -#define POL_mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_FAST_TRAINING 0x193a -#define POL_mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b -#define POL_mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c -#define POL_mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d -#define POL_mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_CNTL 0x1941 -#define POL_mmDP0_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_CNTL1 0x1942 -#define POL_mmDP0_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_FRAMING1 0x1943 -#define POL_mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_FRAMING2 0x1944 -#define POL_mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_FRAMING3 0x1945 -#define POL_mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_FRAMING4 0x1946 -#define POL_mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_AUD_N 0x1947 -#define POL_mmDP0_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_AUD_N_READBACK 0x1948 -#define POL_mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_AUD_M 0x1949 -#define POL_mmDP0_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_AUD_M_READBACK 0x194a -#define POL_mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_TIMESTAMP 0x194b -#define POL_mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP0_DP_SEC_PACKET_CNTL 0x194c -#define POL_mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_RATE_CNTL 0x194d -#define POL_mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_RATE_UPDATE 0x194f -#define POL_mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT0 0x1950 -#define POL_mmDP0_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT1 0x1951 -#define POL_mmDP0_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT2 0x1952 -#define POL_mmDP0_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT_UPDATE 0x1953 -#define POL_mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_LINK_TIMING 0x1954 -#define POL_mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_MISC_CNTL 0x1955 -#define POL_mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a -#define POL_mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b -#define POL_mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT0_STATUS 0x195d -#define POL_mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT1_STATUS 0x195e -#define POL_mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP0_DP_MSE_SAT2_STATUS 0x195f -#define POL_mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig1_dispdec -// base address: 0x400 -#define POL_mmDIG1_DIG_FE_CNTL 0x197e -#define POL_mmDIG1_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f -#define POL_mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980 -#define POL_mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG1_DIG_CLOCK_PATTERN 0x1981 -#define POL_mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG1_DIG_TEST_PATTERN 0x1982 -#define POL_mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983 -#define POL_mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG1_DIG_FIFO_STATUS 0x1984 -#define POL_mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG1_HDMI_CONTROL 0x1987 -#define POL_mmDIG1_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_HDMI_STATUS 0x1988 -#define POL_mmDIG1_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989 -#define POL_mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a -#define POL_mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b -#define POL_mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c -#define POL_mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d -#define POL_mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e -#define POL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_INTERRUPT_STATUS 0x198f -#define POL_mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG1_HDMI_GC 0x1991 -#define POL_mmDIG1_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992 -#define POL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC1_0 0x1993 -#define POL_mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC1_1 0x1994 -#define POL_mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC1_2 0x1995 -#define POL_mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC1_3 0x1996 -#define POL_mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC1_4 0x1997 -#define POL_mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC2_0 0x1998 -#define POL_mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC2_1 0x1999 -#define POL_mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC2_2 0x199a -#define POL_mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_ISRC2_3 0x199b -#define POL_mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AVI_INFO0 0x199c -#define POL_mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AVI_INFO1 0x199d -#define POL_mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AVI_INFO2 0x199e -#define POL_mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AVI_INFO3 0x199f -#define POL_mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG1_AFMT_MPEG_INFO0 0x19a0 -#define POL_mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_MPEG_INFO1 0x19a1 -#define POL_mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_HDR 0x19a2 -#define POL_mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_0 0x19a3 -#define POL_mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_1 0x19a4 -#define POL_mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_2 0x19a5 -#define POL_mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_3 0x19a6 -#define POL_mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_4 0x19a7 -#define POL_mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_5 0x19a8 -#define POL_mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_6 0x19a9 -#define POL_mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG1_AFMT_GENERIC_7 0x19aa -#define POL_mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab -#define POL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_32_0 0x19ac -#define POL_mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_32_1 0x19ad -#define POL_mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_44_0 0x19ae -#define POL_mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_44_1 0x19af -#define POL_mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_48_0 0x19b0 -#define POL_mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_48_1 0x19b1 -#define POL_mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_STATUS_0 0x19b2 -#define POL_mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG1_HDMI_ACR_STATUS_1 0x19b3 -#define POL_mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_INFO0 0x19b4 -#define POL_mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_INFO1 0x19b5 -#define POL_mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_60958_0 0x19b6 -#define POL_mmDIG1_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_60958_1 0x19b7 -#define POL_mmDIG1_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8 -#define POL_mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_AFMT_RAMP_CONTROL0 0x19b9 -#define POL_mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_RAMP_CONTROL1 0x19ba -#define POL_mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG1_AFMT_RAMP_CONTROL2 0x19bb -#define POL_mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_RAMP_CONTROL3 0x19bc -#define POL_mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG1_AFMT_60958_2 0x19bd -#define POL_mmDIG1_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be -#define POL_mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG1_AFMT_STATUS 0x19bf -#define POL_mmDIG1_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0 -#define POL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1 -#define POL_mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2 -#define POL_mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3 -#define POL_mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_DIG_BE_CNTL 0x19c5 -#define POL_mmDIG1_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG1_DIG_BE_EN_CNTL 0x19c6 -#define POL_mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CNTL 0x19e9 -#define POL_mmDIG1_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CONTROL_CHAR 0x19ea -#define POL_mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb -#define POL_mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec -#define POL_mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed -#define POL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee -#define POL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CTL_BITS 0x19f0 -#define POL_mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1 -#define POL_mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3 -#define POL_mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4 -#define POL_mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG1_DIG_VERSION 0x19f6 -#define POL_mmDIG1_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG1_DIG_LANE_ENABLE 0x19f7 -#define POL_mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG1_AFMT_CNTL 0x19fc -#define POL_mmDIG1_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp1_dispdec -// base address: 0x400 -#define POL_mmDP1_DP_LINK_CNTL 0x1a1e -#define POL_mmDP1_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_PIXEL_FORMAT 0x1a1f -#define POL_mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP1_DP_MSA_COLORIMETRY 0x1a20 -#define POL_mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP1_DP_CONFIG 0x1a21 -#define POL_mmDP1_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP1_DP_VID_STREAM_CNTL 0x1a22 -#define POL_mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_STEER_FIFO 0x1a23 -#define POL_mmDP1_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP1_DP_MSA_MISC 0x1a24 -#define POL_mmDP1_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP1_DP_VID_TIMING 0x1a26 -#define POL_mmDP1_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP1_DP_VID_N 0x1a27 -#define POL_mmDP1_DP_VID_N_BASE_IDX 2 -#define POL_mmDP1_DP_VID_M 0x1a28 -#define POL_mmDP1_DP_VID_M_BASE_IDX 2 -#define POL_mmDP1_DP_LINK_FRAMING_CNTL 0x1a29 -#define POL_mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a -#define POL_mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP1_DP_VID_MSA_VBID 0x1a2b -#define POL_mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c -#define POL_mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CNTL 0x1a2d -#define POL_mmDP1_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e -#define POL_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_SYM0 0x1a2f -#define POL_mmDP1_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_SYM1 0x1a30 -#define POL_mmDP1_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_SYM2 0x1a31 -#define POL_mmDP1_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_8B10B_CNTL 0x1a32 -#define POL_mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_PRBS_CNTL 0x1a33 -#define POL_mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34 -#define POL_mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CRC_EN 0x1a35 -#define POL_mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CRC_CNTL 0x1a36 -#define POL_mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CRC_RESULT 0x1a37 -#define POL_mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38 -#define POL_mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39 -#define POL_mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a -#define POL_mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b -#define POL_mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c -#define POL_mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d -#define POL_mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_CNTL 0x1a41 -#define POL_mmDP1_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_CNTL1 0x1a42 -#define POL_mmDP1_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_FRAMING1 0x1a43 -#define POL_mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_FRAMING2 0x1a44 -#define POL_mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_FRAMING3 0x1a45 -#define POL_mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_FRAMING4 0x1a46 -#define POL_mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_AUD_N 0x1a47 -#define POL_mmDP1_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_AUD_N_READBACK 0x1a48 -#define POL_mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_AUD_M 0x1a49 -#define POL_mmDP1_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a -#define POL_mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_TIMESTAMP 0x1a4b -#define POL_mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP1_DP_SEC_PACKET_CNTL 0x1a4c -#define POL_mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_RATE_CNTL 0x1a4d -#define POL_mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_RATE_UPDATE 0x1a4f -#define POL_mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT0 0x1a50 -#define POL_mmDP1_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT1 0x1a51 -#define POL_mmDP1_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT2 0x1a52 -#define POL_mmDP1_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT_UPDATE 0x1a53 -#define POL_mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_LINK_TIMING 0x1a54 -#define POL_mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_MISC_CNTL 0x1a55 -#define POL_mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a -#define POL_mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b -#define POL_mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT0_STATUS 0x1a5d -#define POL_mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT1_STATUS 0x1a5e -#define POL_mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP1_DP_MSE_SAT2_STATUS 0x1a5f -#define POL_mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig2_dispdec -// base address: 0x800 -#define POL_mmDIG2_DIG_FE_CNTL 0x1a7e -#define POL_mmDIG2_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f -#define POL_mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80 -#define POL_mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG2_DIG_CLOCK_PATTERN 0x1a81 -#define POL_mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG2_DIG_TEST_PATTERN 0x1a82 -#define POL_mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83 -#define POL_mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG2_DIG_FIFO_STATUS 0x1a84 -#define POL_mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG2_HDMI_CONTROL 0x1a87 -#define POL_mmDIG2_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_HDMI_STATUS 0x1a88 -#define POL_mmDIG2_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89 -#define POL_mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a -#define POL_mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b -#define POL_mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c -#define POL_mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d -#define POL_mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e -#define POL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f -#define POL_mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG2_HDMI_GC 0x1a91 -#define POL_mmDIG2_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92 -#define POL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC1_0 0x1a93 -#define POL_mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC1_1 0x1a94 -#define POL_mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC1_2 0x1a95 -#define POL_mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC1_3 0x1a96 -#define POL_mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC1_4 0x1a97 -#define POL_mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC2_0 0x1a98 -#define POL_mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC2_1 0x1a99 -#define POL_mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC2_2 0x1a9a -#define POL_mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_ISRC2_3 0x1a9b -#define POL_mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AVI_INFO0 0x1a9c -#define POL_mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AVI_INFO1 0x1a9d -#define POL_mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AVI_INFO2 0x1a9e -#define POL_mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AVI_INFO3 0x1a9f -#define POL_mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG2_AFMT_MPEG_INFO0 0x1aa0 -#define POL_mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_MPEG_INFO1 0x1aa1 -#define POL_mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_HDR 0x1aa2 -#define POL_mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_0 0x1aa3 -#define POL_mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_1 0x1aa4 -#define POL_mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_2 0x1aa5 -#define POL_mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_3 0x1aa6 -#define POL_mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_4 0x1aa7 -#define POL_mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_5 0x1aa8 -#define POL_mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_6 0x1aa9 -#define POL_mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG2_AFMT_GENERIC_7 0x1aaa -#define POL_mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab -#define POL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_32_0 0x1aac -#define POL_mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_32_1 0x1aad -#define POL_mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_44_0 0x1aae -#define POL_mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_44_1 0x1aaf -#define POL_mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_48_0 0x1ab0 -#define POL_mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_48_1 0x1ab1 -#define POL_mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_STATUS_0 0x1ab2 -#define POL_mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG2_HDMI_ACR_STATUS_1 0x1ab3 -#define POL_mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_INFO0 0x1ab4 -#define POL_mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_INFO1 0x1ab5 -#define POL_mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_60958_0 0x1ab6 -#define POL_mmDIG2_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_60958_1 0x1ab7 -#define POL_mmDIG2_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8 -#define POL_mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9 -#define POL_mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_RAMP_CONTROL1 0x1aba -#define POL_mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG2_AFMT_RAMP_CONTROL2 0x1abb -#define POL_mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_RAMP_CONTROL3 0x1abc -#define POL_mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG2_AFMT_60958_2 0x1abd -#define POL_mmDIG2_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe -#define POL_mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG2_AFMT_STATUS 0x1abf -#define POL_mmDIG2_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0 -#define POL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1 -#define POL_mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2 -#define POL_mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3 -#define POL_mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_DIG_BE_CNTL 0x1ac5 -#define POL_mmDIG2_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG2_DIG_BE_EN_CNTL 0x1ac6 -#define POL_mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CNTL 0x1ae9 -#define POL_mmDIG2_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CONTROL_CHAR 0x1aea -#define POL_mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb -#define POL_mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec -#define POL_mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed -#define POL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee -#define POL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CTL_BITS 0x1af0 -#define POL_mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1 -#define POL_mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3 -#define POL_mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4 -#define POL_mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG2_DIG_VERSION 0x1af6 -#define POL_mmDIG2_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG2_DIG_LANE_ENABLE 0x1af7 -#define POL_mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG2_AFMT_CNTL 0x1afc -#define POL_mmDIG2_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp2_dispdec -// base address: 0x800 -#define POL_mmDP2_DP_LINK_CNTL 0x1b1e -#define POL_mmDP2_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_PIXEL_FORMAT 0x1b1f -#define POL_mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP2_DP_MSA_COLORIMETRY 0x1b20 -#define POL_mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP2_DP_CONFIG 0x1b21 -#define POL_mmDP2_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP2_DP_VID_STREAM_CNTL 0x1b22 -#define POL_mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_STEER_FIFO 0x1b23 -#define POL_mmDP2_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP2_DP_MSA_MISC 0x1b24 -#define POL_mmDP2_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP2_DP_VID_TIMING 0x1b26 -#define POL_mmDP2_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP2_DP_VID_N 0x1b27 -#define POL_mmDP2_DP_VID_N_BASE_IDX 2 -#define POL_mmDP2_DP_VID_M 0x1b28 -#define POL_mmDP2_DP_VID_M_BASE_IDX 2 -#define POL_mmDP2_DP_LINK_FRAMING_CNTL 0x1b29 -#define POL_mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a -#define POL_mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP2_DP_VID_MSA_VBID 0x1b2b -#define POL_mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c -#define POL_mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CNTL 0x1b2d -#define POL_mmDP2_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e -#define POL_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_SYM0 0x1b2f -#define POL_mmDP2_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_SYM1 0x1b30 -#define POL_mmDP2_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_SYM2 0x1b31 -#define POL_mmDP2_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_8B10B_CNTL 0x1b32 -#define POL_mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_PRBS_CNTL 0x1b33 -#define POL_mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34 -#define POL_mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CRC_EN 0x1b35 -#define POL_mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CRC_CNTL 0x1b36 -#define POL_mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CRC_RESULT 0x1b37 -#define POL_mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38 -#define POL_mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39 -#define POL_mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a -#define POL_mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b -#define POL_mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c -#define POL_mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d -#define POL_mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_CNTL 0x1b41 -#define POL_mmDP2_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_CNTL1 0x1b42 -#define POL_mmDP2_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_FRAMING1 0x1b43 -#define POL_mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_FRAMING2 0x1b44 -#define POL_mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_FRAMING3 0x1b45 -#define POL_mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_FRAMING4 0x1b46 -#define POL_mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_AUD_N 0x1b47 -#define POL_mmDP2_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_AUD_N_READBACK 0x1b48 -#define POL_mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_AUD_M 0x1b49 -#define POL_mmDP2_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a -#define POL_mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_TIMESTAMP 0x1b4b -#define POL_mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP2_DP_SEC_PACKET_CNTL 0x1b4c -#define POL_mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_RATE_CNTL 0x1b4d -#define POL_mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_RATE_UPDATE 0x1b4f -#define POL_mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT0 0x1b50 -#define POL_mmDP2_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT1 0x1b51 -#define POL_mmDP2_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT2 0x1b52 -#define POL_mmDP2_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT_UPDATE 0x1b53 -#define POL_mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_LINK_TIMING 0x1b54 -#define POL_mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_MISC_CNTL 0x1b55 -#define POL_mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a -#define POL_mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b -#define POL_mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT0_STATUS 0x1b5d -#define POL_mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT1_STATUS 0x1b5e -#define POL_mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP2_DP_MSE_SAT2_STATUS 0x1b5f -#define POL_mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig3_dispdec -// base address: 0xc00 -#define POL_mmDIG3_DIG_FE_CNTL 0x1b7e -#define POL_mmDIG3_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f -#define POL_mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80 -#define POL_mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG3_DIG_CLOCK_PATTERN 0x1b81 -#define POL_mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG3_DIG_TEST_PATTERN 0x1b82 -#define POL_mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83 -#define POL_mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG3_DIG_FIFO_STATUS 0x1b84 -#define POL_mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG3_HDMI_CONTROL 0x1b87 -#define POL_mmDIG3_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_HDMI_STATUS 0x1b88 -#define POL_mmDIG3_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89 -#define POL_mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a -#define POL_mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b -#define POL_mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c -#define POL_mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d -#define POL_mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e -#define POL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f -#define POL_mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG3_HDMI_GC 0x1b91 -#define POL_mmDIG3_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92 -#define POL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC1_0 0x1b93 -#define POL_mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC1_1 0x1b94 -#define POL_mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC1_2 0x1b95 -#define POL_mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC1_3 0x1b96 -#define POL_mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC1_4 0x1b97 -#define POL_mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC2_0 0x1b98 -#define POL_mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC2_1 0x1b99 -#define POL_mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC2_2 0x1b9a -#define POL_mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_ISRC2_3 0x1b9b -#define POL_mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AVI_INFO0 0x1b9c -#define POL_mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AVI_INFO1 0x1b9d -#define POL_mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AVI_INFO2 0x1b9e -#define POL_mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AVI_INFO3 0x1b9f -#define POL_mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG3_AFMT_MPEG_INFO0 0x1ba0 -#define POL_mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_MPEG_INFO1 0x1ba1 -#define POL_mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_HDR 0x1ba2 -#define POL_mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_0 0x1ba3 -#define POL_mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_1 0x1ba4 -#define POL_mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_2 0x1ba5 -#define POL_mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_3 0x1ba6 -#define POL_mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_4 0x1ba7 -#define POL_mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_5 0x1ba8 -#define POL_mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_6 0x1ba9 -#define POL_mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG3_AFMT_GENERIC_7 0x1baa -#define POL_mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab -#define POL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_32_0 0x1bac -#define POL_mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_32_1 0x1bad -#define POL_mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_44_0 0x1bae -#define POL_mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_44_1 0x1baf -#define POL_mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_48_0 0x1bb0 -#define POL_mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_48_1 0x1bb1 -#define POL_mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_STATUS_0 0x1bb2 -#define POL_mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG3_HDMI_ACR_STATUS_1 0x1bb3 -#define POL_mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_INFO0 0x1bb4 -#define POL_mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_INFO1 0x1bb5 -#define POL_mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_60958_0 0x1bb6 -#define POL_mmDIG3_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_60958_1 0x1bb7 -#define POL_mmDIG3_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8 -#define POL_mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9 -#define POL_mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_RAMP_CONTROL1 0x1bba -#define POL_mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb -#define POL_mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc -#define POL_mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG3_AFMT_60958_2 0x1bbd -#define POL_mmDIG3_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe -#define POL_mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG3_AFMT_STATUS 0x1bbf -#define POL_mmDIG3_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0 -#define POL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1 -#define POL_mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2 -#define POL_mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3 -#define POL_mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_DIG_BE_CNTL 0x1bc5 -#define POL_mmDIG3_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG3_DIG_BE_EN_CNTL 0x1bc6 -#define POL_mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CNTL 0x1be9 -#define POL_mmDIG3_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CONTROL_CHAR 0x1bea -#define POL_mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb -#define POL_mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec -#define POL_mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed -#define POL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee -#define POL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CTL_BITS 0x1bf0 -#define POL_mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1 -#define POL_mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3 -#define POL_mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4 -#define POL_mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG3_DIG_VERSION 0x1bf6 -#define POL_mmDIG3_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG3_DIG_LANE_ENABLE 0x1bf7 -#define POL_mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG3_AFMT_CNTL 0x1bfc -#define POL_mmDIG3_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp3_dispdec -// base address: 0xc00 -#define POL_mmDP3_DP_LINK_CNTL 0x1c1e -#define POL_mmDP3_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_PIXEL_FORMAT 0x1c1f -#define POL_mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP3_DP_MSA_COLORIMETRY 0x1c20 -#define POL_mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP3_DP_CONFIG 0x1c21 -#define POL_mmDP3_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP3_DP_VID_STREAM_CNTL 0x1c22 -#define POL_mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_STEER_FIFO 0x1c23 -#define POL_mmDP3_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP3_DP_MSA_MISC 0x1c24 -#define POL_mmDP3_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP3_DP_VID_TIMING 0x1c26 -#define POL_mmDP3_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP3_DP_VID_N 0x1c27 -#define POL_mmDP3_DP_VID_N_BASE_IDX 2 -#define POL_mmDP3_DP_VID_M 0x1c28 -#define POL_mmDP3_DP_VID_M_BASE_IDX 2 -#define POL_mmDP3_DP_LINK_FRAMING_CNTL 0x1c29 -#define POL_mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a -#define POL_mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP3_DP_VID_MSA_VBID 0x1c2b -#define POL_mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c -#define POL_mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CNTL 0x1c2d -#define POL_mmDP3_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e -#define POL_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_SYM0 0x1c2f -#define POL_mmDP3_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_SYM1 0x1c30 -#define POL_mmDP3_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_SYM2 0x1c31 -#define POL_mmDP3_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_8B10B_CNTL 0x1c32 -#define POL_mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_PRBS_CNTL 0x1c33 -#define POL_mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34 -#define POL_mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CRC_EN 0x1c35 -#define POL_mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CRC_CNTL 0x1c36 -#define POL_mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CRC_RESULT 0x1c37 -#define POL_mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38 -#define POL_mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39 -#define POL_mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a -#define POL_mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b -#define POL_mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c -#define POL_mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d -#define POL_mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_CNTL 0x1c41 -#define POL_mmDP3_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_CNTL1 0x1c42 -#define POL_mmDP3_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_FRAMING1 0x1c43 -#define POL_mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_FRAMING2 0x1c44 -#define POL_mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_FRAMING3 0x1c45 -#define POL_mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_FRAMING4 0x1c46 -#define POL_mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_AUD_N 0x1c47 -#define POL_mmDP3_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_AUD_N_READBACK 0x1c48 -#define POL_mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_AUD_M 0x1c49 -#define POL_mmDP3_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a -#define POL_mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_TIMESTAMP 0x1c4b -#define POL_mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP3_DP_SEC_PACKET_CNTL 0x1c4c -#define POL_mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_RATE_CNTL 0x1c4d -#define POL_mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_RATE_UPDATE 0x1c4f -#define POL_mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT0 0x1c50 -#define POL_mmDP3_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT1 0x1c51 -#define POL_mmDP3_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT2 0x1c52 -#define POL_mmDP3_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT_UPDATE 0x1c53 -#define POL_mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_LINK_TIMING 0x1c54 -#define POL_mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_MISC_CNTL 0x1c55 -#define POL_mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a -#define POL_mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b -#define POL_mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT0_STATUS 0x1c5d -#define POL_mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT1_STATUS 0x1c5e -#define POL_mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP3_DP_MSE_SAT2_STATUS 0x1c5f -#define POL_mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig4_dispdec -// base address: 0x1000 -#define POL_mmDIG4_DIG_FE_CNTL 0x1c7e -#define POL_mmDIG4_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f -#define POL_mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80 -#define POL_mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG4_DIG_CLOCK_PATTERN 0x1c81 -#define POL_mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG4_DIG_TEST_PATTERN 0x1c82 -#define POL_mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83 -#define POL_mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG4_DIG_FIFO_STATUS 0x1c84 -#define POL_mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG4_HDMI_CONTROL 0x1c87 -#define POL_mmDIG4_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_HDMI_STATUS 0x1c88 -#define POL_mmDIG4_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89 -#define POL_mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a -#define POL_mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b -#define POL_mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c -#define POL_mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d -#define POL_mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e -#define POL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f -#define POL_mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG4_HDMI_GC 0x1c91 -#define POL_mmDIG4_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92 -#define POL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC1_0 0x1c93 -#define POL_mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC1_1 0x1c94 -#define POL_mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC1_2 0x1c95 -#define POL_mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC1_3 0x1c96 -#define POL_mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC1_4 0x1c97 -#define POL_mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC2_0 0x1c98 -#define POL_mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC2_1 0x1c99 -#define POL_mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC2_2 0x1c9a -#define POL_mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_ISRC2_3 0x1c9b -#define POL_mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AVI_INFO0 0x1c9c -#define POL_mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AVI_INFO1 0x1c9d -#define POL_mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AVI_INFO2 0x1c9e -#define POL_mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AVI_INFO3 0x1c9f -#define POL_mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG4_AFMT_MPEG_INFO0 0x1ca0 -#define POL_mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_MPEG_INFO1 0x1ca1 -#define POL_mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_HDR 0x1ca2 -#define POL_mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_0 0x1ca3 -#define POL_mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_1 0x1ca4 -#define POL_mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_2 0x1ca5 -#define POL_mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_3 0x1ca6 -#define POL_mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_4 0x1ca7 -#define POL_mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_5 0x1ca8 -#define POL_mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_6 0x1ca9 -#define POL_mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG4_AFMT_GENERIC_7 0x1caa -#define POL_mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab -#define POL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_32_0 0x1cac -#define POL_mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_32_1 0x1cad -#define POL_mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_44_0 0x1cae -#define POL_mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_44_1 0x1caf -#define POL_mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_48_0 0x1cb0 -#define POL_mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_48_1 0x1cb1 -#define POL_mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_STATUS_0 0x1cb2 -#define POL_mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG4_HDMI_ACR_STATUS_1 0x1cb3 -#define POL_mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_INFO0 0x1cb4 -#define POL_mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_INFO1 0x1cb5 -#define POL_mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_60958_0 0x1cb6 -#define POL_mmDIG4_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_60958_1 0x1cb7 -#define POL_mmDIG4_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8 -#define POL_mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9 -#define POL_mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_RAMP_CONTROL1 0x1cba -#define POL_mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb -#define POL_mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc -#define POL_mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG4_AFMT_60958_2 0x1cbd -#define POL_mmDIG4_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe -#define POL_mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG4_AFMT_STATUS 0x1cbf -#define POL_mmDIG4_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0 -#define POL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1 -#define POL_mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2 -#define POL_mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3 -#define POL_mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_DIG_BE_CNTL 0x1cc5 -#define POL_mmDIG4_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG4_DIG_BE_EN_CNTL 0x1cc6 -#define POL_mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CNTL 0x1ce9 -#define POL_mmDIG4_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CONTROL_CHAR 0x1cea -#define POL_mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb -#define POL_mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec -#define POL_mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced -#define POL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee -#define POL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CTL_BITS 0x1cf0 -#define POL_mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1 -#define POL_mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3 -#define POL_mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4 -#define POL_mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG4_DIG_VERSION 0x1cf6 -#define POL_mmDIG4_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG4_DIG_LANE_ENABLE 0x1cf7 -#define POL_mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG4_AFMT_CNTL 0x1cfc -#define POL_mmDIG4_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp4_dispdec -// base address: 0x1000 -#define POL_mmDP4_DP_LINK_CNTL 0x1d1e -#define POL_mmDP4_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_PIXEL_FORMAT 0x1d1f -#define POL_mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP4_DP_MSA_COLORIMETRY 0x1d20 -#define POL_mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP4_DP_CONFIG 0x1d21 -#define POL_mmDP4_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP4_DP_VID_STREAM_CNTL 0x1d22 -#define POL_mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_STEER_FIFO 0x1d23 -#define POL_mmDP4_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP4_DP_MSA_MISC 0x1d24 -#define POL_mmDP4_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP4_DP_VID_TIMING 0x1d26 -#define POL_mmDP4_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP4_DP_VID_N 0x1d27 -#define POL_mmDP4_DP_VID_N_BASE_IDX 2 -#define POL_mmDP4_DP_VID_M 0x1d28 -#define POL_mmDP4_DP_VID_M_BASE_IDX 2 -#define POL_mmDP4_DP_LINK_FRAMING_CNTL 0x1d29 -#define POL_mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a -#define POL_mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP4_DP_VID_MSA_VBID 0x1d2b -#define POL_mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c -#define POL_mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CNTL 0x1d2d -#define POL_mmDP4_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e -#define POL_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_SYM0 0x1d2f -#define POL_mmDP4_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_SYM1 0x1d30 -#define POL_mmDP4_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_SYM2 0x1d31 -#define POL_mmDP4_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_8B10B_CNTL 0x1d32 -#define POL_mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_PRBS_CNTL 0x1d33 -#define POL_mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34 -#define POL_mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CRC_EN 0x1d35 -#define POL_mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CRC_CNTL 0x1d36 -#define POL_mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CRC_RESULT 0x1d37 -#define POL_mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38 -#define POL_mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39 -#define POL_mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a -#define POL_mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b -#define POL_mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c -#define POL_mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d -#define POL_mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_CNTL 0x1d41 -#define POL_mmDP4_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_CNTL1 0x1d42 -#define POL_mmDP4_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_FRAMING1 0x1d43 -#define POL_mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_FRAMING2 0x1d44 -#define POL_mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_FRAMING3 0x1d45 -#define POL_mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_FRAMING4 0x1d46 -#define POL_mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_AUD_N 0x1d47 -#define POL_mmDP4_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_AUD_N_READBACK 0x1d48 -#define POL_mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_AUD_M 0x1d49 -#define POL_mmDP4_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a -#define POL_mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_TIMESTAMP 0x1d4b -#define POL_mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP4_DP_SEC_PACKET_CNTL 0x1d4c -#define POL_mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_RATE_CNTL 0x1d4d -#define POL_mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_RATE_UPDATE 0x1d4f -#define POL_mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT0 0x1d50 -#define POL_mmDP4_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT1 0x1d51 -#define POL_mmDP4_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT2 0x1d52 -#define POL_mmDP4_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT_UPDATE 0x1d53 -#define POL_mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_LINK_TIMING 0x1d54 -#define POL_mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_MISC_CNTL 0x1d55 -#define POL_mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a -#define POL_mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b -#define POL_mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT0_STATUS 0x1d5d -#define POL_mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT1_STATUS 0x1d5e -#define POL_mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP4_DP_MSE_SAT2_STATUS 0x1d5f -#define POL_mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig5_dispdec -// base address: 0x1400 -#define POL_mmDIG5_DIG_FE_CNTL 0x1d7e -#define POL_mmDIG5_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f -#define POL_mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80 -#define POL_mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG5_DIG_CLOCK_PATTERN 0x1d81 -#define POL_mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG5_DIG_TEST_PATTERN 0x1d82 -#define POL_mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83 -#define POL_mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG5_DIG_FIFO_STATUS 0x1d84 -#define POL_mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG5_HDMI_CONTROL 0x1d87 -#define POL_mmDIG5_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_HDMI_STATUS 0x1d88 -#define POL_mmDIG5_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89 -#define POL_mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a -#define POL_mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b -#define POL_mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c -#define POL_mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d -#define POL_mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e -#define POL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f -#define POL_mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG5_HDMI_GC 0x1d91 -#define POL_mmDIG5_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92 -#define POL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC1_0 0x1d93 -#define POL_mmDIG5_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC1_1 0x1d94 -#define POL_mmDIG5_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC1_2 0x1d95 -#define POL_mmDIG5_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC1_3 0x1d96 -#define POL_mmDIG5_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC1_4 0x1d97 -#define POL_mmDIG5_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC2_0 0x1d98 -#define POL_mmDIG5_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC2_1 0x1d99 -#define POL_mmDIG5_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC2_2 0x1d9a -#define POL_mmDIG5_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_ISRC2_3 0x1d9b -#define POL_mmDIG5_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AVI_INFO0 0x1d9c -#define POL_mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AVI_INFO1 0x1d9d -#define POL_mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AVI_INFO2 0x1d9e -#define POL_mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AVI_INFO3 0x1d9f -#define POL_mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG5_AFMT_MPEG_INFO0 0x1da0 -#define POL_mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_MPEG_INFO1 0x1da1 -#define POL_mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_HDR 0x1da2 -#define POL_mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_0 0x1da3 -#define POL_mmDIG5_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_1 0x1da4 -#define POL_mmDIG5_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_2 0x1da5 -#define POL_mmDIG5_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_3 0x1da6 -#define POL_mmDIG5_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_4 0x1da7 -#define POL_mmDIG5_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_5 0x1da8 -#define POL_mmDIG5_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_6 0x1da9 -#define POL_mmDIG5_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG5_AFMT_GENERIC_7 0x1daa -#define POL_mmDIG5_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab -#define POL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_32_0 0x1dac -#define POL_mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_32_1 0x1dad -#define POL_mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_44_0 0x1dae -#define POL_mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_44_1 0x1daf -#define POL_mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_48_0 0x1db0 -#define POL_mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_48_1 0x1db1 -#define POL_mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_STATUS_0 0x1db2 -#define POL_mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG5_HDMI_ACR_STATUS_1 0x1db3 -#define POL_mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_INFO0 0x1db4 -#define POL_mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_INFO1 0x1db5 -#define POL_mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_60958_0 0x1db6 -#define POL_mmDIG5_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_60958_1 0x1db7 -#define POL_mmDIG5_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8 -#define POL_mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_AFMT_RAMP_CONTROL0 0x1db9 -#define POL_mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_RAMP_CONTROL1 0x1dba -#define POL_mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb -#define POL_mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc -#define POL_mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG5_AFMT_60958_2 0x1dbd -#define POL_mmDIG5_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe -#define POL_mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG5_AFMT_STATUS 0x1dbf -#define POL_mmDIG5_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0 -#define POL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1 -#define POL_mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2 -#define POL_mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3 -#define POL_mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_DIG_BE_CNTL 0x1dc5 -#define POL_mmDIG5_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG5_DIG_BE_EN_CNTL 0x1dc6 -#define POL_mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CNTL 0x1de9 -#define POL_mmDIG5_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CONTROL_CHAR 0x1dea -#define POL_mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb -#define POL_mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec -#define POL_mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded -#define POL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee -#define POL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CTL_BITS 0x1df0 -#define POL_mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1 -#define POL_mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3 -#define POL_mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4 -#define POL_mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG5_DIG_VERSION 0x1df6 -#define POL_mmDIG5_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG5_DIG_LANE_ENABLE 0x1df7 -#define POL_mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG5_AFMT_CNTL 0x1dfc -#define POL_mmDIG5_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp5_dispdec -// base address: 0x1400 -#define POL_mmDP5_DP_LINK_CNTL 0x1e1e -#define POL_mmDP5_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_PIXEL_FORMAT 0x1e1f -#define POL_mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP5_DP_MSA_COLORIMETRY 0x1e20 -#define POL_mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP5_DP_CONFIG 0x1e21 -#define POL_mmDP5_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP5_DP_VID_STREAM_CNTL 0x1e22 -#define POL_mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_STEER_FIFO 0x1e23 -#define POL_mmDP5_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP5_DP_MSA_MISC 0x1e24 -#define POL_mmDP5_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP5_DP_VID_TIMING 0x1e26 -#define POL_mmDP5_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP5_DP_VID_N 0x1e27 -#define POL_mmDP5_DP_VID_N_BASE_IDX 2 -#define POL_mmDP5_DP_VID_M 0x1e28 -#define POL_mmDP5_DP_VID_M_BASE_IDX 2 -#define POL_mmDP5_DP_LINK_FRAMING_CNTL 0x1e29 -#define POL_mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a -#define POL_mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP5_DP_VID_MSA_VBID 0x1e2b -#define POL_mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c -#define POL_mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CNTL 0x1e2d -#define POL_mmDP5_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e -#define POL_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_SYM0 0x1e2f -#define POL_mmDP5_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_SYM1 0x1e30 -#define POL_mmDP5_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_SYM2 0x1e31 -#define POL_mmDP5_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_8B10B_CNTL 0x1e32 -#define POL_mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_PRBS_CNTL 0x1e33 -#define POL_mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34 -#define POL_mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CRC_EN 0x1e35 -#define POL_mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CRC_CNTL 0x1e36 -#define POL_mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CRC_RESULT 0x1e37 -#define POL_mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38 -#define POL_mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39 -#define POL_mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a -#define POL_mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b -#define POL_mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c -#define POL_mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d -#define POL_mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_CNTL 0x1e41 -#define POL_mmDP5_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_CNTL1 0x1e42 -#define POL_mmDP5_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_FRAMING1 0x1e43 -#define POL_mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_FRAMING2 0x1e44 -#define POL_mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_FRAMING3 0x1e45 -#define POL_mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_FRAMING4 0x1e46 -#define POL_mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_AUD_N 0x1e47 -#define POL_mmDP5_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_AUD_N_READBACK 0x1e48 -#define POL_mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_AUD_M 0x1e49 -#define POL_mmDP5_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a -#define POL_mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_TIMESTAMP 0x1e4b -#define POL_mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP5_DP_SEC_PACKET_CNTL 0x1e4c -#define POL_mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_RATE_CNTL 0x1e4d -#define POL_mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_RATE_UPDATE 0x1e4f -#define POL_mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT0 0x1e50 -#define POL_mmDP5_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT1 0x1e51 -#define POL_mmDP5_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT2 0x1e52 -#define POL_mmDP5_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT_UPDATE 0x1e53 -#define POL_mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_LINK_TIMING 0x1e54 -#define POL_mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_MISC_CNTL 0x1e55 -#define POL_mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a -#define POL_mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b -#define POL_mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT0_STATUS 0x1e5d -#define POL_mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT1_STATUS 0x1e5e -#define POL_mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP5_DP_MSE_SAT2_STATUS 0x1e5f -#define POL_mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dig6_dispdec -// base address: 0x1800 -#define POL_mmDIG6_DIG_FE_CNTL 0x1e7e -#define POL_mmDIG6_DIG_FE_CNTL_BASE_IDX 2 -#define POL_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f -#define POL_mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 -#define POL_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80 -#define POL_mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG6_DIG_CLOCK_PATTERN 0x1e81 -#define POL_mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2 -#define POL_mmDIG6_DIG_TEST_PATTERN 0x1e82 -#define POL_mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2 -#define POL_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83 -#define POL_mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 -#define POL_mmDIG6_DIG_FIFO_STATUS 0x1e84 -#define POL_mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDIG6_HDMI_CONTROL 0x1e87 -#define POL_mmDIG6_HDMI_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_HDMI_STATUS 0x1e88 -#define POL_mmDIG6_HDMI_STATUS_BASE_IDX 2 -#define POL_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89 -#define POL_mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a -#define POL_mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b -#define POL_mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c -#define POL_mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d -#define POL_mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 -#define POL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e -#define POL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f -#define POL_mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2 -#define POL_mmDIG6_HDMI_GC 0x1e91 -#define POL_mmDIG6_HDMI_GC_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92 -#define POL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC1_0 0x1e93 -#define POL_mmDIG6_AFMT_ISRC1_0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC1_1 0x1e94 -#define POL_mmDIG6_AFMT_ISRC1_1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC1_2 0x1e95 -#define POL_mmDIG6_AFMT_ISRC1_2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC1_3 0x1e96 -#define POL_mmDIG6_AFMT_ISRC1_3_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC1_4 0x1e97 -#define POL_mmDIG6_AFMT_ISRC1_4_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC2_0 0x1e98 -#define POL_mmDIG6_AFMT_ISRC2_0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC2_1 0x1e99 -#define POL_mmDIG6_AFMT_ISRC2_1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC2_2 0x1e9a -#define POL_mmDIG6_AFMT_ISRC2_2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_ISRC2_3 0x1e9b -#define POL_mmDIG6_AFMT_ISRC2_3_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AVI_INFO0 0x1e9c -#define POL_mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AVI_INFO1 0x1e9d -#define POL_mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AVI_INFO2 0x1e9e -#define POL_mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AVI_INFO3 0x1e9f -#define POL_mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2 -#define POL_mmDIG6_AFMT_MPEG_INFO0 0x1ea0 -#define POL_mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_MPEG_INFO1 0x1ea1 -#define POL_mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_HDR 0x1ea2 -#define POL_mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_0 0x1ea3 -#define POL_mmDIG6_AFMT_GENERIC_0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_1 0x1ea4 -#define POL_mmDIG6_AFMT_GENERIC_1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_2 0x1ea5 -#define POL_mmDIG6_AFMT_GENERIC_2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_3 0x1ea6 -#define POL_mmDIG6_AFMT_GENERIC_3_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_4 0x1ea7 -#define POL_mmDIG6_AFMT_GENERIC_4_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_5 0x1ea8 -#define POL_mmDIG6_AFMT_GENERIC_5_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_6 0x1ea9 -#define POL_mmDIG6_AFMT_GENERIC_6_BASE_IDX 2 -#define POL_mmDIG6_AFMT_GENERIC_7 0x1eaa -#define POL_mmDIG6_AFMT_GENERIC_7_BASE_IDX 2 -#define POL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab -#define POL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_32_0 0x1eac -#define POL_mmDIG6_HDMI_ACR_32_0_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_32_1 0x1ead -#define POL_mmDIG6_HDMI_ACR_32_1_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_44_0 0x1eae -#define POL_mmDIG6_HDMI_ACR_44_0_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_44_1 0x1eaf -#define POL_mmDIG6_HDMI_ACR_44_1_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_48_0 0x1eb0 -#define POL_mmDIG6_HDMI_ACR_48_0_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_48_1 0x1eb1 -#define POL_mmDIG6_HDMI_ACR_48_1_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_STATUS_0 0x1eb2 -#define POL_mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2 -#define POL_mmDIG6_HDMI_ACR_STATUS_1 0x1eb3 -#define POL_mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_INFO0 0x1eb4 -#define POL_mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_INFO1 0x1eb5 -#define POL_mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_60958_0 0x1eb6 -#define POL_mmDIG6_AFMT_60958_0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_60958_1 0x1eb7 -#define POL_mmDIG6_AFMT_60958_1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8 -#define POL_mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9 -#define POL_mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_RAMP_CONTROL1 0x1eba -#define POL_mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2 -#define POL_mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb -#define POL_mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc -#define POL_mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2 -#define POL_mmDIG6_AFMT_60958_2 0x1ebd -#define POL_mmDIG6_AFMT_60958_2_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe -#define POL_mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 -#define POL_mmDIG6_AFMT_STATUS 0x1ebf -#define POL_mmDIG6_AFMT_STATUS_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0 -#define POL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1 -#define POL_mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2 -#define POL_mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 -#define POL_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3 -#define POL_mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_DIG_BE_CNTL 0x1ec5 -#define POL_mmDIG6_DIG_BE_CNTL_BASE_IDX 2 -#define POL_mmDIG6_DIG_BE_EN_CNTL 0x1ec6 -#define POL_mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CNTL 0x1ee9 -#define POL_mmDIG6_TMDS_CNTL_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CONTROL_CHAR 0x1eea -#define POL_mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb -#define POL_mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 -#define POL_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec -#define POL_mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 -#define POL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed -#define POL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 -#define POL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee -#define POL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CTL_BITS 0x1ef0 -#define POL_mmDIG6_TMDS_CTL_BITS_BASE_IDX 2 -#define POL_mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1 -#define POL_mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3 -#define POL_mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4 -#define POL_mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 -#define POL_mmDIG6_DIG_VERSION 0x1ef6 -#define POL_mmDIG6_DIG_VERSION_BASE_IDX 2 -#define POL_mmDIG6_DIG_LANE_ENABLE 0x1ef7 -#define POL_mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2 -#define POL_mmDIG6_AFMT_CNTL 0x1efc -#define POL_mmDIG6_AFMT_CNTL_BASE_IDX 2 - - -// addressBlock: dce_dc_dp6_dispdec -// base address: 0x1800 -#define POL_mmDP6_DP_LINK_CNTL 0x1f1e -#define POL_mmDP6_DP_LINK_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_PIXEL_FORMAT 0x1f1f -#define POL_mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDP6_DP_MSA_COLORIMETRY 0x1f20 -#define POL_mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2 -#define POL_mmDP6_DP_CONFIG 0x1f21 -#define POL_mmDP6_DP_CONFIG_BASE_IDX 2 -#define POL_mmDP6_DP_VID_STREAM_CNTL 0x1f22 -#define POL_mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_STEER_FIFO 0x1f23 -#define POL_mmDP6_DP_STEER_FIFO_BASE_IDX 2 -#define POL_mmDP6_DP_MSA_MISC 0x1f24 -#define POL_mmDP6_DP_MSA_MISC_BASE_IDX 2 -#define POL_mmDP6_DP_VID_TIMING 0x1f26 -#define POL_mmDP6_DP_VID_TIMING_BASE_IDX 2 -#define POL_mmDP6_DP_VID_N 0x1f27 -#define POL_mmDP6_DP_VID_N_BASE_IDX 2 -#define POL_mmDP6_DP_VID_M 0x1f28 -#define POL_mmDP6_DP_VID_M_BASE_IDX 2 -#define POL_mmDP6_DP_LINK_FRAMING_CNTL 0x1f29 -#define POL_mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a -#define POL_mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2 -#define POL_mmDP6_DP_VID_MSA_VBID 0x1f2b -#define POL_mmDP6_DP_VID_MSA_VBID_BASE_IDX 2 -#define POL_mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c -#define POL_mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CNTL 0x1f2d -#define POL_mmDP6_DP_DPHY_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e -#define POL_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_SYM0 0x1f2f -#define POL_mmDP6_DP_DPHY_SYM0_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_SYM1 0x1f30 -#define POL_mmDP6_DP_DPHY_SYM1_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_SYM2 0x1f31 -#define POL_mmDP6_DP_DPHY_SYM2_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_8B10B_CNTL 0x1f32 -#define POL_mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_PRBS_CNTL 0x1f33 -#define POL_mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34 -#define POL_mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CRC_EN 0x1f35 -#define POL_mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CRC_CNTL 0x1f36 -#define POL_mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CRC_RESULT 0x1f37 -#define POL_mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38 -#define POL_mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39 -#define POL_mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a -#define POL_mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b -#define POL_mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 -#define POL_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c -#define POL_mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 -#define POL_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d -#define POL_mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_CNTL 0x1f41 -#define POL_mmDP6_DP_SEC_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_CNTL1 0x1f42 -#define POL_mmDP6_DP_SEC_CNTL1_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_FRAMING1 0x1f43 -#define POL_mmDP6_DP_SEC_FRAMING1_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_FRAMING2 0x1f44 -#define POL_mmDP6_DP_SEC_FRAMING2_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_FRAMING3 0x1f45 -#define POL_mmDP6_DP_SEC_FRAMING3_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_FRAMING4 0x1f46 -#define POL_mmDP6_DP_SEC_FRAMING4_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_AUD_N 0x1f47 -#define POL_mmDP6_DP_SEC_AUD_N_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_AUD_N_READBACK 0x1f48 -#define POL_mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_AUD_M 0x1f49 -#define POL_mmDP6_DP_SEC_AUD_M_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a -#define POL_mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_TIMESTAMP 0x1f4b -#define POL_mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2 -#define POL_mmDP6_DP_SEC_PACKET_CNTL 0x1f4c -#define POL_mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_RATE_CNTL 0x1f4d -#define POL_mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_RATE_UPDATE 0x1f4f -#define POL_mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT0 0x1f50 -#define POL_mmDP6_DP_MSE_SAT0_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT1 0x1f51 -#define POL_mmDP6_DP_MSE_SAT1_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT2 0x1f52 -#define POL_mmDP6_DP_MSE_SAT2_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT_UPDATE 0x1f53 -#define POL_mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_LINK_TIMING 0x1f54 -#define POL_mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_MISC_CNTL 0x1f55 -#define POL_mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a -#define POL_mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 -#define POL_mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b -#define POL_mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT0_STATUS 0x1f5d -#define POL_mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT1_STATUS 0x1f5e -#define POL_mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2 -#define POL_mmDP6_DP_MSE_SAT2_STATUS 0x1f5f -#define POL_mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy0_dispdec -// base address: 0x0 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd -#define POL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs0_dispdec -// base address: 0x0 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d -#define POL_mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs0_dispdec -// base address: 0x0 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f -#define POL_mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190 -#define POL_mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d -#define POL_mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs0_dispdec -// base address: 0x0 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1 -#define POL_mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2 -#define POL_mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3 -#define POL_mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4 -#define POL_mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5 -#define POL_mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7 -#define POL_mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8 -#define POL_mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9 -#define POL_mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa -#define POL_mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy1_dispdec -// base address: 0x320 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5 -#define POL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs1_dispdec -// base address: 0x320 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215 -#define POL_mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs1_dispdec -// base address: 0x320 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257 -#define POL_mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258 -#define POL_mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265 -#define POL_mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs1_dispdec -// base address: 0x320 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269 -#define POL_mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a -#define POL_mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b -#define POL_mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c -#define POL_mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d -#define POL_mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f -#define POL_mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270 -#define POL_mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271 -#define POL_mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272 -#define POL_mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy2_dispdec -// base address: 0x640 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d -#define POL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs2_dispdec -// base address: 0x640 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd -#define POL_mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs2_dispdec -// base address: 0x640 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f -#define POL_mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320 -#define POL_mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d -#define POL_mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs2_dispdec -// base address: 0x640 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331 -#define POL_mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332 -#define POL_mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333 -#define POL_mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334 -#define POL_mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335 -#define POL_mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337 -#define POL_mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338 -#define POL_mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339 -#define POL_mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a -#define POL_mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy3_dispdec -// base address: 0x960 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435 -#define POL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs3_dispdec -// base address: 0x960 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5 -#define POL_mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs3_dispdec -// base address: 0x960 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7 -#define POL_mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8 -#define POL_mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5 -#define POL_mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs3_dispdec -// base address: 0x960 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9 -#define POL_mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa -#define POL_mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb -#define POL_mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc -#define POL_mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd -#define POL_mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff -#define POL_mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400 -#define POL_mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401 -#define POL_mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402 -#define POL_mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy4_dispdec -// base address: 0xc80 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd -#define POL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs4_dispdec -// base address: 0xc80 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d -#define POL_mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs4_dispdec -// base address: 0xc80 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af -#define POL_mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0 -#define POL_mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd -#define POL_mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs4_dispdec -// base address: 0xc80 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1 -#define POL_mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2 -#define POL_mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3 -#define POL_mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4 -#define POL_mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5 -#define POL_mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7 -#define POL_mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8 -#define POL_mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9 -#define POL_mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca -#define POL_mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy5_dispdec -// base address: 0xfa0 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5 -#define POL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs5_dispdec -// base address: 0xfa0 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535 -#define POL_mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs5_dispdec -// base address: 0xfa0 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577 -#define POL_mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578 -#define POL_mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585 -#define POL_mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs5_dispdec -// base address: 0xfa0 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589 -#define POL_mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a -#define POL_mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b -#define POL_mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c -#define POL_mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d -#define POL_mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f -#define POL_mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590 -#define POL_mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591 -#define POL_mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592 -#define POL_mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy6_dispdec -// base address: 0x12c0 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d -#define POL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs6_dispdec -// base address: 0x12c0 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd -#define POL_mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs6_dispdec -// base address: 0x12c0 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f -#define POL_mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640 -#define POL_mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d -#define POL_mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs6_dispdec -// base address: 0x12c0 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651 -#define POL_mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652 -#define POL_mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653 -#define POL_mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654 -#define POL_mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655 -#define POL_mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657 -#define POL_mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658 -#define POL_mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659 -#define POL_mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a -#define POL_mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dcio_uniphy8_dispdec -// base address: 0x15e0 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755 -#define POL_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophycmregs8_dispdec -// base address: 0x15e0 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5 -#define POL_mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophytxregs8_dispdec -// base address: 0x15e0 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707 -#define POL_mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708 -#define POL_mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715 -#define POL_mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_combophypllregs8_dispdec -// base address: 0x15e0 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719 -#define POL_mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a -#define POL_mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b -#define POL_mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c -#define POL_mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d -#define POL_mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f -#define POL_mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720 -#define POL_mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721 -#define POL_mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2 -#define POL_mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722 -#define POL_mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2 - - -// addressBlock: dce_dc_dsi0_dispdec -// base address: 0x0 -#define POL_mmDSI0_DISP_DSI_CTRL 0x27be -#define POL_mmDSI0_DISP_DSI_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_STATUS 0x27bf -#define POL_mmDSI0_DISP_DSI_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6 -#define POL_mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9 -#define POL_mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca -#define POL_mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb -#define POL_mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc -#define POL_mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd -#define POL_mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce -#define POL_mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf -#define POL_mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0 -#define POL_mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1 -#define POL_mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2 -#define POL_mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3 -#define POL_mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4 -#define POL_mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8 -#define POL_mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9 -#define POL_mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da -#define POL_mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_TRIG_CTRL 0x27db -#define POL_mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_EXT_MUX 0x27dc -#define POL_mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd -#define POL_mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de -#define POL_mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df -#define POL_mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0 -#define POL_mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1 -#define POL_mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_EXT_RESET 0x27e2 -#define POL_mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5 -#define POL_mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6 -#define POL_mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LANE_CTRL 0x27e7 -#define POL_mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8 -#define POL_mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9 -#define POL_mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea -#define POL_mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb -#define POL_mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec -#define POL_mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed -#define POL_mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_EOT_PACKET 0x27ee -#define POL_mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef -#define POL_mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0 -#define POL_mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8 -#define POL_mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9 -#define POL_mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa -#define POL_mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CLK_CTRL 0x27fb -#define POL_mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CLK_STATUS 0x27fc -#define POL_mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd -#define POL_mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe -#define POL_mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff -#define POL_mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800 -#define POL_mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_TE_CTRL 0x2801 -#define POL_mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_LANE_STATUS 0x2805 -#define POL_mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_PERF_CTRL 0x2806 -#define POL_mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807 -#define POL_mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_RDBK_NUM 0x2808 -#define POL_mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2 -#define POL_mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809 -#define POL_mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2 - - -// addressBlock: dce_dc_dsi1_dispdec -// base address: 0x400 -#define POL_mmDSI1_DISP_DSI_CTRL 0x28be -#define POL_mmDSI1_DISP_DSI_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_STATUS 0x28bf -#define POL_mmDSI1_DISP_DSI_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6 -#define POL_mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9 -#define POL_mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca -#define POL_mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb -#define POL_mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc -#define POL_mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd -#define POL_mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce -#define POL_mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf -#define POL_mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0 -#define POL_mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1 -#define POL_mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2 -#define POL_mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3 -#define POL_mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4 -#define POL_mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8 -#define POL_mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9 -#define POL_mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da -#define POL_mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_TRIG_CTRL 0x28db -#define POL_mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_EXT_MUX 0x28dc -#define POL_mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd -#define POL_mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de -#define POL_mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df -#define POL_mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0 -#define POL_mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1 -#define POL_mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_EXT_RESET 0x28e2 -#define POL_mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5 -#define POL_mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6 -#define POL_mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LANE_CTRL 0x28e7 -#define POL_mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8 -#define POL_mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9 -#define POL_mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea -#define POL_mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb -#define POL_mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec -#define POL_mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed -#define POL_mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_EOT_PACKET 0x28ee -#define POL_mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef -#define POL_mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0 -#define POL_mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8 -#define POL_mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9 -#define POL_mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa -#define POL_mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CLK_CTRL 0x28fb -#define POL_mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CLK_STATUS 0x28fc -#define POL_mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd -#define POL_mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe -#define POL_mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff -#define POL_mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900 -#define POL_mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_TE_CTRL 0x2901 -#define POL_mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_LANE_STATUS 0x2905 -#define POL_mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_PERF_CTRL 0x2906 -#define POL_mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907 -#define POL_mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_RDBK_NUM 0x2908 -#define POL_mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2 -#define POL_mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909 -#define POL_mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2 - - -// addressBlock: dce_dc_dprx_sd0_dispdec -// base address: 0x0 -#define POL_mmDPRX_SD0_DPRX_SD_CONTROL 0x29be -#define POL_mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf -#define POL_mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA0 0x29c0 -#define POL_mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA1 0x29c1 -#define POL_mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA2 0x29c2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA3 0x29c3 -#define POL_mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA4 0x29c4 -#define POL_mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA5 0x29c5 -#define POL_mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA6 0x29c6 -#define POL_mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA7 0x29c7 -#define POL_mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA8 0x29c8 -#define POL_mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_VBID 0x29c9 -#define POL_mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca -#define POL_mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb -#define POL_mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc -#define POL_mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce -#define POL_mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf -#define POL_mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0 -#define POL_mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1 -#define POL_mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2 -#define POL_mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3 -#define POL_mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4 -#define POL_mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8 -#define POL_mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9 -#define POL_mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da -#define POL_mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db -#define POL_mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc -#define POL_mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd -#define POL_mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de -#define POL_mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df -#define POL_mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1 -#define POL_mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8 -#define POL_mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9 -#define POL_mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea -#define POL_mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb -#define POL_mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec -#define POL_mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed -#define POL_mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2 -#define POL_mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee -#define POL_mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2 - - -// addressBlock: dce_dc_dprx_sd1_dispdec -// base address: 0x180 -#define POL_mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e -#define POL_mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f -#define POL_mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA0 0x2a20 -#define POL_mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA1 0x2a21 -#define POL_mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA2 0x2a22 -#define POL_mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA3 0x2a23 -#define POL_mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA4 0x2a24 -#define POL_mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA5 0x2a25 -#define POL_mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA6 0x2a26 -#define POL_mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA7 0x2a27 -#define POL_mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA8 0x2a28 -#define POL_mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_VBID 0x2a29 -#define POL_mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a -#define POL_mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b -#define POL_mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c -#define POL_mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e -#define POL_mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f -#define POL_mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30 -#define POL_mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31 -#define POL_mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32 -#define POL_mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33 -#define POL_mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34 -#define POL_mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38 -#define POL_mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39 -#define POL_mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a -#define POL_mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b -#define POL_mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c -#define POL_mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d -#define POL_mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e -#define POL_mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f -#define POL_mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41 -#define POL_mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48 -#define POL_mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49 -#define POL_mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a -#define POL_mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b -#define POL_mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c -#define POL_mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d -#define POL_mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2 -#define POL_mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e -#define POL_mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_perfmon10_dispdec -// base address: 0xacf8 -#define POL_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e -#define POL_mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f -#define POL_mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60 -#define POL_mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_CNTL 0x2b61 -#define POL_mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_CNTL2 0x2b62 -#define POL_mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63 -#define POL_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64 -#define POL_mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_HI 0x2b65 -#define POL_mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 -#define POL_mmDC_PERFMON10_PERFMON_LOW 0x2b66 -#define POL_mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 - - -// addressBlock: dce_dc_dc_zcalregs_dispdec -// base address: 0x0 -#define POL_mmCOMP_EN_CTL 0x2d96 -#define POL_mmCOMP_EN_CTL_BASE_IDX 2 -#define POL_mmCOMP_EN_DFX 0x2d97 -#define POL_mmCOMP_EN_DFX_BASE_IDX 2 -#define POL_mmZCAL_FUSES 0x2d98 -#define POL_mmZCAL_FUSES_BASE_IDX 2 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR -// base address: 0x48 -//#define POL_mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR -// base address: 0x4c -//#define POL_mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014 - - -// addressBlock: dce_dc_dispdec[948..986] -// base address: 0x3b4 -//#define POL_mmVGA_CRTC8_IDX 0x002d -//#define POL_mmVGA_CRTC8_DATA 0x002d -//#define POL_mmVGA_GENFC_WT 0x002e -//#define POL_mmVGA_GENS1 0x002e -//#define POL_mmVGA_ATTRDW 0x0030 -//#define POL_mmVGA_ATTRX 0x0030 -//#define POL_mmVGA_ATTRDR 0x0030 -//#define POL_mmVGA_GENMO_WT 0x0030 -//#define POL_mmVGA_GENS0 0x0030 -//#define POL_mmVGA_GENENB 0x0030 -//#define POL_mmVGA_SEQ8_IDX 0x0031 -//#define POL_mmVGA_SEQ8_DATA 0x0031 -//#define POL_mmVGA_DAC_MASK 0x0031 -//#define POL_mmVGA_DAC_R_INDEX 0x0031 -//#define POL_mmVGA_DAC_W_INDEX 0x0032 -//#define POL_mmVGA_DAC_DATA 0x0032 -//#define POL_mmVGA_GENFC_RD 0x0032 -//#define POL_mmVGA_GENMO_RD 0x0033 -//#define POL_mmVGA_GRPH8_IDX 0x0033 -//#define POL_mmVGA_GRPH8_DATA 0x0033 -//#define POL_mmVGA_CRTC8_IDX_1 0x0035 -//#define POL_mmVGA_CRTC8_DATA_1 0x0035 -//#define POL_mmVGA_GENFC_WT_1 0x0036 -//#define POL_mmVGA_GENS1_1 0x0036 - - -// addressBlock: dce_dc_azdec -// base address: 0x0 -#define POL_mmCORB_WRITE_POINTER 0x0000 -#define POL_mmCORB_WRITE_POINTER_BASE_IDX 0 -#define POL_mmCORB_READ_POINTER 0x0000 -#define POL_mmCORB_READ_POINTER_BASE_IDX 0 -#define POL_mmCORB_CONTROL 0x0001 -#define POL_mmCORB_CONTROL_BASE_IDX 0 -#define POL_mmCORB_STATUS 0x0001 -#define POL_mmCORB_STATUS_BASE_IDX 0 -#define POL_mmCORB_SIZE 0x0001 -#define POL_mmCORB_SIZE_BASE_IDX 0 -#define POL_mmRIRB_LOWER_BASE_ADDRESS 0x0002 -#define POL_mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmRIRB_UPPER_BASE_ADDRESS 0x0003 -#define POL_mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmRIRB_WRITE_POINTER 0x0004 -#define POL_mmRIRB_WRITE_POINTER_BASE_IDX 0 -#define POL_mmRESPONSE_INTERRUPT_COUNT 0x0004 -#define POL_mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 -#define POL_mmRIRB_CONTROL 0x0005 -#define POL_mmRIRB_CONTROL_BASE_IDX 0 -#define POL_mmRIRB_STATUS 0x0005 -#define POL_mmRIRB_STATUS_BASE_IDX 0 -#define POL_mmRIRB_SIZE 0x0005 -#define POL_mmRIRB_SIZE_BASE_IDX 0 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 -#define POL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 -#define POL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 -#define POL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 -#define POL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 -#define POL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 -#define POL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 -#define POL_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 -#define POL_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 -#define POL_mmIMMEDIATE_COMMAND_STATUS 0x0008 -#define POL_mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 -#define POL_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a -#define POL_mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b -#define POL_mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmWALL_CLOCK_COUNTER_ALIAS 0x074c -#define POL_mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream0_azdec -// base address: 0x0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 -#define POL_mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream1_azdec -// base address: 0x20 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 -#define POL_mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream2_azdec -// base address: 0x40 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 -#define POL_mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream3_azdec -// base address: 0x60 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 -#define POL_mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream4_azdec -// base address: 0x80 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 -#define POL_mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream5_azdec -// base address: 0xa0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 -#define POL_mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream6_azdec -// base address: 0xc0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 -#define POL_mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: dce_dc_azstream7_azdec -// base address: 0xe0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 -#define POL_mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 - - -// addressBlock: azf0stream0_streamind -// base address: 0x0 -#define POL_izAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream1_streamind -// base address: 0x0 -#define POL_izAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream2_streamind -// base address: 0x0 -#define POL_izAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream3_streamind -// base address: 0x0 -#define POL_izAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream4_streamind -// base address: 0x0 -#define POL_izAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream5_streamind -// base address: 0x0 -#define POL_izAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream6_streamind -// base address: 0x0 -#define POL_izAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream7_streamind -// base address: 0x0 -#define POL_izAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream8_streamind -// base address: 0x0 -#define POL_izAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream9_streamind -// base address: 0x0 -#define POL_izAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream10_streamind -// base address: 0x0 -#define POL_izAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream11_streamind -// base address: 0x0 -#define POL_izAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream12_streamind -// base address: 0x0 -#define POL_izAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream13_streamind -// base address: 0x0 -#define POL_izAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream14_streamind -// base address: 0x0 -#define POL_izAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0stream15_streamind -// base address: 0x0 -#define POL_izAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 -#define POL_izAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 -#define POL_izAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 -#define POL_izAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 -#define POL_izAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 - - -// addressBlock: azf0endpoint0_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint1_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint2_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint3_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint4_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint5_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint6_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0endpoint7_endpointind -// base address: 0x0 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 -#define POL_izAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a -#define POL_izAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b -#define POL_izAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c -#define POL_izAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d -#define POL_izAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e - - -// addressBlock: azf0inputendpoint0_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint1_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint2_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint3_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint4_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint5_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint6_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: azf0inputendpoint7_inputendpointind -// base address: 0x0 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 -#define POL_izAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 - - -// addressBlock: f2codecind -// base address: 0x0 -#define POL_izAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 -#define POL_izAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 -#define POL_izAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 -#define POL_izAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff -#define POL_izAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 -#define POL_izAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 -#define POL_izAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a -#define POL_izAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b -#define POL_izAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e -#define POL_izAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 -#define POL_izAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 -#define POL_izAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 -#define POL_izAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a -#define POL_izAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 -#define POL_izAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 -#define POL_izAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e -#define POL_izAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 -#define POL_izAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c -#define POL_izAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a -#define POL_izAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 -#define POL_izAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c - - -// addressBlock: descriptorind -// base address: 0x0 -#define POL_ixAUDIO_DESCRIPTOR0 0x0001 -#define POL_ixAUDIO_DESCRIPTOR1 0x0002 -#define POL_ixAUDIO_DESCRIPTOR2 0x0003 -#define POL_ixAUDIO_DESCRIPTOR3 0x0004 -#define POL_ixAUDIO_DESCRIPTOR4 0x0005 -#define POL_ixAUDIO_DESCRIPTOR5 0x0006 -#define POL_ixAUDIO_DESCRIPTOR6 0x0007 -#define POL_ixAUDIO_DESCRIPTOR7 0x0008 -#define POL_ixAUDIO_DESCRIPTOR8 0x0009 -#define POL_ixAUDIO_DESCRIPTOR9 0x000a -#define POL_ixAUDIO_DESCRIPTOR10 0x000b -#define POL_ixAUDIO_DESCRIPTOR11 0x000c -#define POL_ixAUDIO_DESCRIPTOR12 0x000d -#define POL_ixAUDIO_DESCRIPTOR13 0x000e - - -// addressBlock: sinkinfoind -// base address: 0x0 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 -#define POL_izAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 -#define POL_ixSINK_DESCRIPTION0 0x0005 -#define POL_ixSINK_DESCRIPTION1 0x0006 -#define POL_ixSINK_DESCRIPTION2 0x0007 -#define POL_ixSINK_DESCRIPTION3 0x0008 -#define POL_ixSINK_DESCRIPTION4 0x0009 -#define POL_ixSINK_DESCRIPTION5 0x000a -#define POL_ixSINK_DESCRIPTION6 0x000b -#define POL_ixSINK_DESCRIPTION7 0x000c -#define POL_ixSINK_DESCRIPTION8 0x000d -#define POL_ixSINK_DESCRIPTION9 0x000e -#define POL_ixSINK_DESCRIPTION10 0x000f -#define POL_ixSINK_DESCRIPTION11 0x0010 -#define POL_ixSINK_DESCRIPTION12 0x0011 -#define POL_ixSINK_DESCRIPTION13 0x0012 -#define POL_ixSINK_DESCRIPTION14 0x0013 -#define POL_ixSINK_DESCRIPTION15 0x0014 -#define POL_ixSINK_DESCRIPTION16 0x0015 -#define POL_ixSINK_DESCRIPTION17 0x0016 - - -// addressBlock: azinputcrc0resultind -// base address: 0x0 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL0 0x0000 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL1 0x0001 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL2 0x0002 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL3 0x0003 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL4 0x0004 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL5 0x0005 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL6 0x0006 -#define POL_izAZALIA_INPUT_CRC0_CHANNEL7 0x0007 - - -// addressBlock: azinputcrc1resultind -// base address: 0x0 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL0 0x0000 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL1 0x0001 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL2 0x0002 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL3 0x0003 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL4 0x0004 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL5 0x0005 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL6 0x0006 -#define POL_izAZALIA_INPUT_CRC1_CHANNEL7 0x0007 - - -// addressBlock: azcrc0resultind -// base address: 0x0 -#define POL_izAZALIA_CRC0_CHANNEL0 0x0000 -#define POL_izAZALIA_CRC0_CHANNEL1 0x0001 -#define POL_izAZALIA_CRC0_CHANNEL2 0x0002 -#define POL_izAZALIA_CRC0_CHANNEL3 0x0003 -#define POL_izAZALIA_CRC0_CHANNEL4 0x0004 -#define POL_izAZALIA_CRC0_CHANNEL5 0x0005 -#define POL_izAZALIA_CRC0_CHANNEL6 0x0006 -#define POL_izAZALIA_CRC0_CHANNEL7 0x0007 - - -// addressBlock: azcrc1resultind -// base address: 0x0 -#define POL_izAZALIA_CRC1_CHANNEL0 0x0000 -#define POL_izAZALIA_CRC1_CHANNEL1 0x0001 -#define POL_izAZALIA_CRC1_CHANNEL2 0x0002 -#define POL_izAZALIA_CRC1_CHANNEL3 0x0003 -#define POL_izAZALIA_CRC1_CHANNEL4 0x0004 -#define POL_izAZALIA_CRC1_CHANNEL5 0x0005 -#define POL_izAZALIA_CRC1_CHANNEL6 0x0006 -#define POL_izAZALIA_CRC1_CHANNEL7 0x0007 - - -// addressBlock: vgaseqind -// base address: 0x0 -#define POL_ixSEQ00 0x0000 -#define POL_ixSEQ01 0x0001 -#define POL_ixSEQ02 0x0002 -#define POL_ixSEQ03 0x0003 -#define POL_ixSEQ04 0x0004 - - -// addressBlock: vgacrtind -// base address: 0x0 -#define POL_ixCRT00 0x0000 -#define POL_ixCRT01 0x0001 -#define POL_ixCRT02 0x0002 -#define POL_ixCRT03 0x0003 -#define POL_ixCRT04 0x0004 -#define POL_ixCRT05 0x0005 -#define POL_ixCRT06 0x0006 -#define POL_ixCRT07 0x0007 -#define POL_ixCRT08 0x0008 -#define POL_ixCRT09 0x0009 -#define POL_ixCRT0A 0x000a -#define POL_ixCRT0B 0x000b -#define POL_ixCRT0C 0x000c -#define POL_ixCRT0D 0x000d -#define POL_ixCRT0E 0x000e -#define POL_ixCRT0F 0x000f -#define POL_ixCRT10 0x0010 -#define POL_ixCRT11 0x0011 -#define POL_ixCRT12 0x0012 -#define POL_ixCRT13 0x0013 -#define POL_ixCRT14 0x0014 -#define POL_ixCRT15 0x0015 -#define POL_ixCRT16 0x0016 -#define POL_ixCRT17 0x0017 -#define POL_ixCRT18 0x0018 -#define POL_ixCRT1E 0x001e -#define POL_ixCRT1F 0x001f -#define POL_ixCRT22 0x0022 - - -// addressBlock: vgagrphind -// base address: 0x0 -#define POL_ixGRA00 0x0000 -#define POL_ixGRA01 0x0001 -#define POL_ixGRA02 0x0002 -#define POL_ixGRA03 0x0003 -#define POL_ixGRA04 0x0004 -#define POL_ixGRA05 0x0005 -#define POL_ixGRA06 0x0006 -#define POL_ixGRA07 0x0007 -#define POL_ixGRA08 0x0008 - - -// addressBlock: vgaattrind -// base address: 0x0 -#define POL_ixATTR00 0x0000 -#define POL_ixATTR01 0x0001 -#define POL_ixATTR02 0x0002 -#define POL_ixATTR03 0x0003 -#define POL_ixATTR04 0x0004 -#define POL_ixATTR05 0x0005 -#define POL_ixATTR06 0x0006 -#define POL_ixATTR07 0x0007 -#define POL_ixATTR08 0x0008 -#define POL_ixATTR09 0x0009 -#define POL_ixATTR0A 0x000a -#define POL_ixATTR0B 0x000b -#define POL_ixATTR0C 0x000c -#define POL_ixATTR0D 0x000d -#define POL_ixATTR0E 0x000e -#define POL_ixATTR0F 0x000f -#define POL_ixATTR10 0x0010 -#define POL_ixATTR11 0x0011 -#define POL_ixATTR12 0x0012 -#define POL_ixATTR13 0x0013 -#define POL_ixATTR14 0x0014 - #endif diff --git a/headers/private/graphics/radeon_hd/sea_reg.h b/headers/private/graphics/radeon_hd/sea_reg.h index 21a31b17e1..612550af27 100644 --- a/headers/private/graphics/radeon_hd/sea_reg.h +++ b/headers/private/graphics/radeon_hd/sea_reg.h @@ -21,5683 +21,12 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +/* This header has been modified from its original version: + * it has been formatted to contain only what Haiku needs. */ + #ifndef DCE_8_0_D_H #define DCE_8_0_D_H -#define SEA_mmPIPE0_PG_CONFIG 0x1760 -#define SEA_mmPIPE0_PG_ENABLE 0x1761 -#define SEA_mmPIPE0_PG_STATUS 0x1762 -#define SEA_mmPIPE1_PG_CONFIG 0x1764 -#define SEA_mmPIPE1_PG_ENABLE 0x1765 -#define SEA_mmPIPE1_PG_STATUS 0x1766 -#define SEA_mmPIPE2_PG_CONFIG 0x1768 -#define SEA_mmPIPE2_PG_ENABLE 0x1769 -#define SEA_mmPIPE2_PG_STATUS 0x176a -#define SEA_mmPIPE3_PG_CONFIG 0x176c -#define SEA_mmPIPE3_PG_ENABLE 0x176d -#define SEA_mmPIPE3_PG_STATUS 0x176e -#define SEA_mmPIPE4_PG_CONFIG 0x1770 -#define SEA_mmPIPE4_PG_ENABLE 0x1771 -#define SEA_mmPIPE4_PG_STATUS 0x1772 -#define SEA_mmPIPE5_PG_CONFIG 0x1774 -#define SEA_mmPIPE5_PG_ENABLE 0x1775 -#define SEA_mmPIPE5_PG_STATUS 0x1776 -#define SEA_mmDC_IP_REQUEST_CNTL 0x1778 -#define SEA_mmDC_PGFSM_CONFIG_REG 0x177c -#define SEA_mmDC_PGFSM_WRITE_REG 0x177d -#define SEA_mmDC_PGCNTL_STATUS_REG 0x177e -#define SEA_mmDCPG_TEST_DEBUG_INDEX 0x1779 -#define SEA_mmDCPG_TEST_DEBUG_DATA 0x177b -#define SEA_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 -#define SEA_mmBL1_PWM_USER_LEVEL 0x1629 -#define SEA_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a -#define SEA_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b -#define SEA_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c -#define SEA_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d -#define SEA_mmBL1_PWM_ABM_CNTL 0x162e -#define SEA_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f -#define SEA_mmBL1_PWM_GRP2_REG_LOCK 0x1630 -#define SEA_mmDC_ABM1_CNTL 0x1638 -#define SEA_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 -#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a -#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b -#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c -#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d -#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e -#define SEA_mmDC_ABM1_ACE_THRES_12 0x163f -#define SEA_mmDC_ABM1_ACE_THRES_34 0x1640 -#define SEA_mmDC_ABM1_ACE_CNTL_MISC 0x1641 -#define SEA_mmDC_ABM1_DEBUG_MISC 0x1649 -#define SEA_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a -#define SEA_mmDC_ABM1_HG_MISC_CTRL 0x164b -#define SEA_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c -#define SEA_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d -#define SEA_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e -#define SEA_mmDC_ABM1_LS_PIXEL_COUNT 0x164f -#define SEA_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 -#define SEA_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 -#define SEA_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 -#define SEA_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 -#define SEA_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 -#define SEA_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 -#define SEA_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 -#define SEA_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 -#define SEA_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 -#define SEA_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 -#define SEA_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a -#define SEA_mmDC_ABM1_HG_RESULT_1 0x165b -#define SEA_mmDC_ABM1_HG_RESULT_2 0x165c -#define SEA_mmDC_ABM1_HG_RESULT_3 0x165d -#define SEA_mmDC_ABM1_HG_RESULT_4 0x165e -#define SEA_mmDC_ABM1_HG_RESULT_5 0x165f -#define SEA_mmDC_ABM1_HG_RESULT_6 0x1660 -#define SEA_mmDC_ABM1_HG_RESULT_7 0x1661 -#define SEA_mmDC_ABM1_HG_RESULT_8 0x1662 -#define SEA_mmDC_ABM1_HG_RESULT_9 0x1663 -#define SEA_mmDC_ABM1_HG_RESULT_10 0x1664 -#define SEA_mmDC_ABM1_HG_RESULT_11 0x1665 -#define SEA_mmDC_ABM1_HG_RESULT_12 0x1666 -#define SEA_mmDC_ABM1_HG_RESULT_13 0x1667 -#define SEA_mmDC_ABM1_HG_RESULT_14 0x1668 -#define SEA_mmDC_ABM1_HG_RESULT_15 0x1669 -#define SEA_mmDC_ABM1_HG_RESULT_16 0x166a -#define SEA_mmDC_ABM1_HG_RESULT_17 0x166b -#define SEA_mmDC_ABM1_HG_RESULT_18 0x166c -#define SEA_mmDC_ABM1_HG_RESULT_19 0x166d -#define SEA_mmDC_ABM1_HG_RESULT_20 0x166e -#define SEA_mmDC_ABM1_HG_RESULT_21 0x166f -#define SEA_mmDC_ABM1_HG_RESULT_22 0x1670 -#define SEA_mmDC_ABM1_HG_RESULT_23 0x1671 -#define SEA_mmDC_ABM1_HG_RESULT_24 0x1672 -#define SEA_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b -#define SEA_mmDC_ABM1_BL_MASTER_LOCK 0x169c -#define SEA_mmABM_TEST_DEBUG_INDEX 0x169e -#define SEA_mmABM_TEST_DEBUG_DATA 0x169f -#define SEA_mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c -#define SEA_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c -#define SEA_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c -#define SEA_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c -#define SEA_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c -#define SEA_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c -#define SEA_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c -#define SEA_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d -#define SEA_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d -#define SEA_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d -#define SEA_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d -#define SEA_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d -#define SEA_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d -#define SEA_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d -#define SEA_mmDCFE_DBG_SEL 0x1b7e -#define SEA_mmCRTC0_DCFE_DBG_SEL 0x1b7e -#define SEA_mmCRTC1_DCFE_DBG_SEL 0x1e7e -#define SEA_mmCRTC2_DCFE_DBG_SEL 0x417e -#define SEA_mmCRTC3_DCFE_DBG_SEL 0x447e -#define SEA_mmCRTC4_DCFE_DBG_SEL 0x477e -#define SEA_mmCRTC5_DCFE_DBG_SEL 0x4a7e -#define SEA_mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f -#define SEA_mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f -#define SEA_mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f -#define SEA_mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f -#define SEA_mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f -#define SEA_mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f -#define SEA_mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f -#define SEA_mmCRTC_H_TOTAL 0x1b80 -#define SEA_mmCRTC0_CRTC_H_TOTAL 0x1b80 -#define SEA_mmCRTC1_CRTC_H_TOTAL 0x1e80 -#define SEA_mmCRTC2_CRTC_H_TOTAL 0x4180 -#define SEA_mmCRTC3_CRTC_H_TOTAL 0x4480 -#define SEA_mmCRTC4_CRTC_H_TOTAL 0x4780 -#define SEA_mmCRTC5_CRTC_H_TOTAL 0x4a80 -#define SEA_mmCRTC_H_BLANK_START_END 0x1b81 -#define SEA_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 -#define SEA_mmCRTC1_CRTC_H_BLANK_START_END 0x1e81 -#define SEA_mmCRTC2_CRTC_H_BLANK_START_END 0x4181 -#define SEA_mmCRTC3_CRTC_H_BLANK_START_END 0x4481 -#define SEA_mmCRTC4_CRTC_H_BLANK_START_END 0x4781 -#define SEA_mmCRTC5_CRTC_H_BLANK_START_END 0x4a81 -#define SEA_mmCRTC_H_SYNC_A 0x1b82 -#define SEA_mmCRTC0_CRTC_H_SYNC_A 0x1b82 -#define SEA_mmCRTC1_CRTC_H_SYNC_A 0x1e82 -#define SEA_mmCRTC2_CRTC_H_SYNC_A 0x4182 -#define SEA_mmCRTC3_CRTC_H_SYNC_A 0x4482 -#define SEA_mmCRTC4_CRTC_H_SYNC_A 0x4782 -#define SEA_mmCRTC5_CRTC_H_SYNC_A 0x4a82 -#define SEA_mmCRTC_H_SYNC_A_CNTL 0x1b83 -#define SEA_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 -#define SEA_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83 -#define SEA_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 -#define SEA_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 -#define SEA_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 -#define SEA_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83 -#define SEA_mmCRTC_H_SYNC_B 0x1b84 -#define SEA_mmCRTC0_CRTC_H_SYNC_B 0x1b84 -#define SEA_mmCRTC1_CRTC_H_SYNC_B 0x1e84 -#define SEA_mmCRTC2_CRTC_H_SYNC_B 0x4184 -#define SEA_mmCRTC3_CRTC_H_SYNC_B 0x4484 -#define SEA_mmCRTC4_CRTC_H_SYNC_B 0x4784 -#define SEA_mmCRTC5_CRTC_H_SYNC_B 0x4a84 -#define SEA_mmCRTC_H_SYNC_B_CNTL 0x1b85 -#define SEA_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 -#define SEA_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85 -#define SEA_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 -#define SEA_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 -#define SEA_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 -#define SEA_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85 -#define SEA_mmCRTC_VBI_END 0x1b86 -#define SEA_mmCRTC0_CRTC_VBI_END 0x1b86 -#define SEA_mmCRTC1_CRTC_VBI_END 0x1e86 -#define SEA_mmCRTC2_CRTC_VBI_END 0x4186 -#define SEA_mmCRTC3_CRTC_VBI_END 0x4486 -#define SEA_mmCRTC4_CRTC_VBI_END 0x4786 -#define SEA_mmCRTC5_CRTC_VBI_END 0x4a86 -#define SEA_mmCRTC_V_TOTAL 0x1b87 -#define SEA_mmCRTC0_CRTC_V_TOTAL 0x1b87 -#define SEA_mmCRTC1_CRTC_V_TOTAL 0x1e87 -#define SEA_mmCRTC2_CRTC_V_TOTAL 0x4187 -#define SEA_mmCRTC3_CRTC_V_TOTAL 0x4487 -#define SEA_mmCRTC4_CRTC_V_TOTAL 0x4787 -#define SEA_mmCRTC5_CRTC_V_TOTAL 0x4a87 -#define SEA_mmCRTC_V_TOTAL_MIN 0x1b88 -#define SEA_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 -#define SEA_mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88 -#define SEA_mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 -#define SEA_mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 -#define SEA_mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 -#define SEA_mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88 -#define SEA_mmCRTC_V_TOTAL_MAX 0x1b89 -#define SEA_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 -#define SEA_mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89 -#define SEA_mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 -#define SEA_mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 -#define SEA_mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 -#define SEA_mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89 -#define SEA_mmCRTC_V_TOTAL_CONTROL 0x1b8a -#define SEA_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a -#define SEA_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a -#define SEA_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a -#define SEA_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a -#define SEA_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a -#define SEA_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a -#define SEA_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b -#define SEA_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b -#define SEA_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b -#define SEA_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b -#define SEA_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b -#define SEA_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b -#define SEA_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b -#define SEA_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define SEA_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define SEA_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c -#define SEA_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c -#define SEA_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c -#define SEA_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c -#define SEA_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c -#define SEA_mmCRTC_V_BLANK_START_END 0x1b8d -#define SEA_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d -#define SEA_mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d -#define SEA_mmCRTC2_CRTC_V_BLANK_START_END 0x418d -#define SEA_mmCRTC3_CRTC_V_BLANK_START_END 0x448d -#define SEA_mmCRTC4_CRTC_V_BLANK_START_END 0x478d -#define SEA_mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d -#define SEA_mmCRTC_V_SYNC_A 0x1b8e -#define SEA_mmCRTC0_CRTC_V_SYNC_A 0x1b8e -#define SEA_mmCRTC1_CRTC_V_SYNC_A 0x1e8e -#define SEA_mmCRTC2_CRTC_V_SYNC_A 0x418e -#define SEA_mmCRTC3_CRTC_V_SYNC_A 0x448e -#define SEA_mmCRTC4_CRTC_V_SYNC_A 0x478e -#define SEA_mmCRTC5_CRTC_V_SYNC_A 0x4a8e -#define SEA_mmCRTC_V_SYNC_A_CNTL 0x1b8f -#define SEA_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f -#define SEA_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f -#define SEA_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f -#define SEA_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f -#define SEA_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f -#define SEA_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f -#define SEA_mmCRTC_V_SYNC_B 0x1b90 -#define SEA_mmCRTC0_CRTC_V_SYNC_B 0x1b90 -#define SEA_mmCRTC1_CRTC_V_SYNC_B 0x1e90 -#define SEA_mmCRTC2_CRTC_V_SYNC_B 0x4190 -#define SEA_mmCRTC3_CRTC_V_SYNC_B 0x4490 -#define SEA_mmCRTC4_CRTC_V_SYNC_B 0x4790 -#define SEA_mmCRTC5_CRTC_V_SYNC_B 0x4a90 -#define SEA_mmCRTC_V_SYNC_B_CNTL 0x1b91 -#define SEA_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 -#define SEA_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91 -#define SEA_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 -#define SEA_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 -#define SEA_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 -#define SEA_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91 -#define SEA_mmCRTC_DTMTEST_CNTL 0x1b92 -#define SEA_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 -#define SEA_mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92 -#define SEA_mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 -#define SEA_mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 -#define SEA_mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 -#define SEA_mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92 -#define SEA_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define SEA_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define SEA_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93 -#define SEA_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 -#define SEA_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 -#define SEA_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 -#define SEA_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93 -#define SEA_mmCRTC_TRIGA_CNTL 0x1b94 -#define SEA_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 -#define SEA_mmCRTC1_CRTC_TRIGA_CNTL 0x1e94 -#define SEA_mmCRTC2_CRTC_TRIGA_CNTL 0x4194 -#define SEA_mmCRTC3_CRTC_TRIGA_CNTL 0x4494 -#define SEA_mmCRTC4_CRTC_TRIGA_CNTL 0x4794 -#define SEA_mmCRTC5_CRTC_TRIGA_CNTL 0x4a94 -#define SEA_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define SEA_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define SEA_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95 -#define SEA_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 -#define SEA_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 -#define SEA_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 -#define SEA_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95 -#define SEA_mmCRTC_TRIGB_CNTL 0x1b96 -#define SEA_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 -#define SEA_mmCRTC1_CRTC_TRIGB_CNTL 0x1e96 -#define SEA_mmCRTC2_CRTC_TRIGB_CNTL 0x4196 -#define SEA_mmCRTC3_CRTC_TRIGB_CNTL 0x4496 -#define SEA_mmCRTC4_CRTC_TRIGB_CNTL 0x4796 -#define SEA_mmCRTC5_CRTC_TRIGB_CNTL 0x4a96 -#define SEA_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define SEA_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define SEA_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97 -#define SEA_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 -#define SEA_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 -#define SEA_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 -#define SEA_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97 -#define SEA_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define SEA_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define SEA_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98 -#define SEA_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 -#define SEA_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 -#define SEA_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 -#define SEA_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98 -#define SEA_mmCRTC_FLOW_CONTROL 0x1b99 -#define SEA_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 -#define SEA_mmCRTC1_CRTC_FLOW_CONTROL 0x1e99 -#define SEA_mmCRTC2_CRTC_FLOW_CONTROL 0x4199 -#define SEA_mmCRTC3_CRTC_FLOW_CONTROL 0x4499 -#define SEA_mmCRTC4_CRTC_FLOW_CONTROL 0x4799 -#define SEA_mmCRTC5_CRTC_FLOW_CONTROL 0x4a99 -#define SEA_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b -#define SEA_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b -#define SEA_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b -#define SEA_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b -#define SEA_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b -#define SEA_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b -#define SEA_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b -#define SEA_mmCRTC_CONTROL 0x1b9c -#define SEA_mmCRTC0_CRTC_CONTROL 0x1b9c -#define SEA_mmCRTC1_CRTC_CONTROL 0x1e9c -#define SEA_mmCRTC2_CRTC_CONTROL 0x419c -#define SEA_mmCRTC3_CRTC_CONTROL 0x449c -#define SEA_mmCRTC4_CRTC_CONTROL 0x479c -#define SEA_mmCRTC5_CRTC_CONTROL 0x4a9c -#define SEA_mmCRTC_BLANK_CONTROL 0x1b9d -#define SEA_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d -#define SEA_mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d -#define SEA_mmCRTC2_CRTC_BLANK_CONTROL 0x419d -#define SEA_mmCRTC3_CRTC_BLANK_CONTROL 0x449d -#define SEA_mmCRTC4_CRTC_BLANK_CONTROL 0x479d -#define SEA_mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d -#define SEA_mmCRTC_INTERLACE_CONTROL 0x1b9e -#define SEA_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e -#define SEA_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e -#define SEA_mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e -#define SEA_mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e -#define SEA_mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e -#define SEA_mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e -#define SEA_mmCRTC_INTERLACE_STATUS 0x1b9f -#define SEA_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f -#define SEA_mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f -#define SEA_mmCRTC2_CRTC_INTERLACE_STATUS 0x419f -#define SEA_mmCRTC3_CRTC_INTERLACE_STATUS 0x449f -#define SEA_mmCRTC4_CRTC_INTERLACE_STATUS 0x479f -#define SEA_mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f -#define SEA_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define SEA_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define SEA_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0 -#define SEA_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0 -#define SEA_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0 -#define SEA_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0 -#define SEA_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0 -#define SEA_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1 -#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1 -#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1 -#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1 -#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1 -#define SEA_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2 -#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2 -#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2 -#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2 -#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2 -#define SEA_mmCRTC_STATUS 0x1ba3 -#define SEA_mmCRTC0_CRTC_STATUS 0x1ba3 -#define SEA_mmCRTC1_CRTC_STATUS 0x1ea3 -#define SEA_mmCRTC2_CRTC_STATUS 0x41a3 -#define SEA_mmCRTC3_CRTC_STATUS 0x44a3 -#define SEA_mmCRTC4_CRTC_STATUS 0x47a3 -#define SEA_mmCRTC5_CRTC_STATUS 0x4aa3 -#define SEA_mmCRTC_STATUS_POSITION 0x1ba4 -#define SEA_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 -#define SEA_mmCRTC1_CRTC_STATUS_POSITION 0x1ea4 -#define SEA_mmCRTC2_CRTC_STATUS_POSITION 0x41a4 -#define SEA_mmCRTC3_CRTC_STATUS_POSITION 0x44a4 -#define SEA_mmCRTC4_CRTC_STATUS_POSITION 0x47a4 -#define SEA_mmCRTC5_CRTC_STATUS_POSITION 0x4aa4 -#define SEA_mmCRTC_NOM_VERT_POSITION 0x1ba5 -#define SEA_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 -#define SEA_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5 -#define SEA_mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5 -#define SEA_mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5 -#define SEA_mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5 -#define SEA_mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5 -#define SEA_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 -#define SEA_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 -#define SEA_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6 -#define SEA_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6 -#define SEA_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6 -#define SEA_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6 -#define SEA_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6 -#define SEA_mmCRTC_STATUS_VF_COUNT 0x1ba7 -#define SEA_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 -#define SEA_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7 -#define SEA_mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7 -#define SEA_mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7 -#define SEA_mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7 -#define SEA_mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7 -#define SEA_mmCRTC_STATUS_HV_COUNT 0x1ba8 -#define SEA_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 -#define SEA_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8 -#define SEA_mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8 -#define SEA_mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8 -#define SEA_mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8 -#define SEA_mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8 -#define SEA_mmCRTC_COUNT_CONTROL 0x1ba9 -#define SEA_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 -#define SEA_mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9 -#define SEA_mmCRTC2_CRTC_COUNT_CONTROL 0x41a9 -#define SEA_mmCRTC3_CRTC_COUNT_CONTROL 0x44a9 -#define SEA_mmCRTC4_CRTC_COUNT_CONTROL 0x47a9 -#define SEA_mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9 -#define SEA_mmCRTC_COUNT_RESET 0x1baa -#define SEA_mmCRTC0_CRTC_COUNT_RESET 0x1baa -#define SEA_mmCRTC1_CRTC_COUNT_RESET 0x1eaa -#define SEA_mmCRTC2_CRTC_COUNT_RESET 0x41aa -#define SEA_mmCRTC3_CRTC_COUNT_RESET 0x44aa -#define SEA_mmCRTC4_CRTC_COUNT_RESET 0x47aa -#define SEA_mmCRTC5_CRTC_COUNT_RESET 0x4aaa -#define SEA_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define SEA_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define SEA_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab -#define SEA_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab -#define SEA_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab -#define SEA_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab -#define SEA_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab -#define SEA_mmCRTC_VERT_SYNC_CONTROL 0x1bac -#define SEA_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac -#define SEA_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac -#define SEA_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac -#define SEA_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac -#define SEA_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac -#define SEA_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac -#define SEA_mmCRTC_STEREO_STATUS 0x1bad -#define SEA_mmCRTC0_CRTC_STEREO_STATUS 0x1bad -#define SEA_mmCRTC1_CRTC_STEREO_STATUS 0x1ead -#define SEA_mmCRTC2_CRTC_STEREO_STATUS 0x41ad -#define SEA_mmCRTC3_CRTC_STEREO_STATUS 0x44ad -#define SEA_mmCRTC4_CRTC_STEREO_STATUS 0x47ad -#define SEA_mmCRTC5_CRTC_STEREO_STATUS 0x4aad -#define SEA_mmCRTC_STEREO_CONTROL 0x1bae -#define SEA_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae -#define SEA_mmCRTC1_CRTC_STEREO_CONTROL 0x1eae -#define SEA_mmCRTC2_CRTC_STEREO_CONTROL 0x41ae -#define SEA_mmCRTC3_CRTC_STEREO_CONTROL 0x44ae -#define SEA_mmCRTC4_CRTC_STEREO_CONTROL 0x47ae -#define SEA_mmCRTC5_CRTC_STEREO_CONTROL 0x4aae -#define SEA_mmCRTC_SNAPSHOT_STATUS 0x1baf -#define SEA_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf -#define SEA_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf -#define SEA_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af -#define SEA_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af -#define SEA_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af -#define SEA_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf -#define SEA_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 -#define SEA_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 -#define SEA_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0 -#define SEA_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0 -#define SEA_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0 -#define SEA_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0 -#define SEA_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0 -#define SEA_mmCRTC_SNAPSHOT_POSITION 0x1bb1 -#define SEA_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 -#define SEA_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1 -#define SEA_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1 -#define SEA_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1 -#define SEA_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1 -#define SEA_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1 -#define SEA_mmCRTC_SNAPSHOT_FRAME 0x1bb2 -#define SEA_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 -#define SEA_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2 -#define SEA_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2 -#define SEA_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2 -#define SEA_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2 -#define SEA_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2 -#define SEA_mmCRTC_START_LINE_CONTROL 0x1bb3 -#define SEA_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 -#define SEA_mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3 -#define SEA_mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3 -#define SEA_mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3 -#define SEA_mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3 -#define SEA_mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3 -#define SEA_mmCRTC_INTERRUPT_CONTROL 0x1bb4 -#define SEA_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 -#define SEA_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4 -#define SEA_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4 -#define SEA_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4 -#define SEA_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4 -#define SEA_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4 -#define SEA_mmCRTC_UPDATE_LOCK 0x1bb5 -#define SEA_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 -#define SEA_mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5 -#define SEA_mmCRTC2_CRTC_UPDATE_LOCK 0x41b5 -#define SEA_mmCRTC3_CRTC_UPDATE_LOCK 0x44b5 -#define SEA_mmCRTC4_CRTC_UPDATE_LOCK 0x47b5 -#define SEA_mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5 -#define SEA_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define SEA_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define SEA_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6 -#define SEA_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 -#define SEA_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6 -#define SEA_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 -#define SEA_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6 -#define SEA_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define SEA_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define SEA_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7 -#define SEA_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 -#define SEA_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7 -#define SEA_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 -#define SEA_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7 -#define SEA_mmCRTC_TEST_PATTERN_CONTROL 0x1bba -#define SEA_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba -#define SEA_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba -#define SEA_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba -#define SEA_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba -#define SEA_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba -#define SEA_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba -#define SEA_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define SEA_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define SEA_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb -#define SEA_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb -#define SEA_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb -#define SEA_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb -#define SEA_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb -#define SEA_mmCRTC_TEST_PATTERN_COLOR 0x1bbc -#define SEA_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc -#define SEA_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc -#define SEA_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc -#define SEA_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc -#define SEA_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc -#define SEA_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc -#define SEA_mmMASTER_UPDATE_LOCK 0x1bbd -#define SEA_mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd -#define SEA_mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd -#define SEA_mmCRTC2_MASTER_UPDATE_LOCK 0x41bd -#define SEA_mmCRTC3_MASTER_UPDATE_LOCK 0x44bd -#define SEA_mmCRTC4_MASTER_UPDATE_LOCK 0x47bd -#define SEA_mmCRTC5_MASTER_UPDATE_LOCK 0x4abd -#define SEA_mmMASTER_UPDATE_MODE 0x1bbe -#define SEA_mmCRTC0_MASTER_UPDATE_MODE 0x1bbe -#define SEA_mmCRTC1_MASTER_UPDATE_MODE 0x1ebe -#define SEA_mmCRTC2_MASTER_UPDATE_MODE 0x41be -#define SEA_mmCRTC3_MASTER_UPDATE_MODE 0x44be -#define SEA_mmCRTC4_MASTER_UPDATE_MODE 0x47be -#define SEA_mmCRTC5_MASTER_UPDATE_MODE 0x4abe -#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf -#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf -#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf -#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf -#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf -#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0 -#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 -#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0 -#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 -#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0 -#define SEA_mmCRTC_MVP_STATUS 0x1bc1 -#define SEA_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 -#define SEA_mmCRTC1_CRTC_MVP_STATUS 0x1ec1 -#define SEA_mmCRTC2_CRTC_MVP_STATUS 0x41c1 -#define SEA_mmCRTC3_CRTC_MVP_STATUS 0x44c1 -#define SEA_mmCRTC4_CRTC_MVP_STATUS 0x47c1 -#define SEA_mmCRTC5_CRTC_MVP_STATUS 0x4ac1 -#define SEA_mmCRTC_MASTER_EN 0x1bc2 -#define SEA_mmCRTC0_CRTC_MASTER_EN 0x1bc2 -#define SEA_mmCRTC1_CRTC_MASTER_EN 0x1ec2 -#define SEA_mmCRTC2_CRTC_MASTER_EN 0x41c2 -#define SEA_mmCRTC3_CRTC_MASTER_EN 0x44c2 -#define SEA_mmCRTC4_CRTC_MASTER_EN 0x47c2 -#define SEA_mmCRTC5_CRTC_MASTER_EN 0x4ac2 -#define SEA_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define SEA_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define SEA_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3 -#define SEA_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 -#define SEA_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3 -#define SEA_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 -#define SEA_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3 -#define SEA_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define SEA_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define SEA_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4 -#define SEA_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4 -#define SEA_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4 -#define SEA_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4 -#define SEA_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4 -#define SEA_mmCRTC_OVERSCAN_COLOR 0x1bc8 -#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 -#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8 -#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8 -#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8 -#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8 -#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8 -#define SEA_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9 -#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9 -#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9 -#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9 -#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9 -#define SEA_mmCRTC_BLANK_DATA_COLOR 0x1bca -#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca -#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca -#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca -#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca -#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca -#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca -#define SEA_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb -#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb -#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb -#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb -#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb -#define SEA_mmCRTC_BLACK_COLOR 0x1bcc -#define SEA_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc -#define SEA_mmCRTC1_CRTC_BLACK_COLOR 0x1ecc -#define SEA_mmCRTC2_CRTC_BLACK_COLOR 0x41cc -#define SEA_mmCRTC3_CRTC_BLACK_COLOR 0x44cc -#define SEA_mmCRTC4_CRTC_BLACK_COLOR 0x47cc -#define SEA_mmCRTC5_CRTC_BLACK_COLOR 0x4acc -#define SEA_mmCRTC_BLACK_COLOR_EXT 0x1bcd -#define SEA_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd -#define SEA_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd -#define SEA_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd -#define SEA_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd -#define SEA_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd -#define SEA_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd -#define SEA_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace -#define SEA_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf -#define SEA_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0 -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0 -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0 -#define SEA_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1 -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1 -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1 -#define SEA_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2 -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2 -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2 -#define SEA_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3 -#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 -#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3 -#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 -#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3 -#define SEA_mmCRTC_CRC_CNTL 0x1bd4 -#define SEA_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 -#define SEA_mmCRTC1_CRTC_CRC_CNTL 0x1ed4 -#define SEA_mmCRTC2_CRTC_CRC_CNTL 0x41d4 -#define SEA_mmCRTC3_CRTC_CRC_CNTL 0x44d4 -#define SEA_mmCRTC4_CRTC_CRC_CNTL 0x47d4 -#define SEA_mmCRTC5_CRTC_CRC_CNTL 0x4ad4 -#define SEA_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5 -#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 -#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5 -#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 -#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5 -#define SEA_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6 -#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 -#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6 -#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 -#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6 -#define SEA_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7 -#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 -#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7 -#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 -#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7 -#define SEA_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8 -#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 -#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8 -#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 -#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8 -#define SEA_mmCRTC_CRC0_DATA_RG 0x1bd9 -#define SEA_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 -#define SEA_mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9 -#define SEA_mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9 -#define SEA_mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9 -#define SEA_mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9 -#define SEA_mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9 -#define SEA_mmCRTC_CRC0_DATA_B 0x1bda -#define SEA_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda -#define SEA_mmCRTC1_CRTC_CRC0_DATA_B 0x1eda -#define SEA_mmCRTC2_CRTC_CRC0_DATA_B 0x41da -#define SEA_mmCRTC3_CRTC_CRC0_DATA_B 0x44da -#define SEA_mmCRTC4_CRTC_CRC0_DATA_B 0x47da -#define SEA_mmCRTC5_CRTC_CRC0_DATA_B 0x4ada -#define SEA_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb -#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db -#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db -#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db -#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb -#define SEA_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc -#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc -#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc -#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc -#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc -#define SEA_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd -#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd -#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd -#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd -#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add -#define SEA_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede -#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de -#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de -#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de -#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade -#define SEA_mmCRTC_CRC1_DATA_RG 0x1bdf -#define SEA_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf -#define SEA_mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf -#define SEA_mmCRTC2_CRTC_CRC1_DATA_RG 0x41df -#define SEA_mmCRTC3_CRTC_CRC1_DATA_RG 0x44df -#define SEA_mmCRTC4_CRTC_CRC1_DATA_RG 0x47df -#define SEA_mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf -#define SEA_mmCRTC_CRC1_DATA_B 0x1be0 -#define SEA_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 -#define SEA_mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0 -#define SEA_mmCRTC2_CRTC_CRC1_DATA_B 0x41e0 -#define SEA_mmCRTC3_CRTC_CRC1_DATA_B 0x44e0 -#define SEA_mmCRTC4_CRTC_CRC1_DATA_B 0x47e0 -#define SEA_mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0 -#define SEA_mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1 -#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2 -#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3 -#define SEA_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4 -#define SEA_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5 -#define SEA_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6 -#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 -#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6 -#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 -#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6 -#define SEA_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define SEA_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define SEA_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7 -#define SEA_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7 -#define SEA_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7 -#define SEA_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7 -#define SEA_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7 -#define SEA_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define SEA_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define SEA_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78 -#define SEA_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 -#define SEA_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 -#define SEA_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 -#define SEA_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78 -#define SEA_mmCRTC_GSL_VSYNC_GAP 0x1b79 -#define SEA_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 -#define SEA_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79 -#define SEA_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 -#define SEA_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 -#define SEA_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 -#define SEA_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79 -#define SEA_mmCRTC_GSL_WINDOW 0x1b7a -#define SEA_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a -#define SEA_mmCRTC1_CRTC_GSL_WINDOW 0x1e7a -#define SEA_mmCRTC2_CRTC_GSL_WINDOW 0x417a -#define SEA_mmCRTC3_CRTC_GSL_WINDOW 0x447a -#define SEA_mmCRTC4_CRTC_GSL_WINDOW 0x477a -#define SEA_mmCRTC5_CRTC_GSL_WINDOW 0x4a7a -#define SEA_mmCRTC_GSL_CONTROL 0x1b7b -#define SEA_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b -#define SEA_mmCRTC1_CRTC_GSL_CONTROL 0x1e7b -#define SEA_mmCRTC2_CRTC_GSL_CONTROL 0x417b -#define SEA_mmCRTC3_CRTC_GSL_CONTROL 0x447b -#define SEA_mmCRTC4_CRTC_GSL_CONTROL 0x477b -#define SEA_mmCRTC5_CRTC_GSL_CONTROL 0x4a7b -#define SEA_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 -#define SEA_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 -#define SEA_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6 -#define SEA_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6 -#define SEA_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6 -#define SEA_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6 -#define SEA_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6 -#define SEA_mmCRTC_TEST_DEBUG_DATA 0x1bc7 -#define SEA_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 -#define SEA_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7 -#define SEA_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7 -#define SEA_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7 -#define SEA_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7 -#define SEA_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7 -#define SEA_mmDAC_ENABLE 0x19e4 -#define SEA_mmDAC_SOURCE_SELECT 0x19e5 -#define SEA_mmDAC_CRC_EN 0x19e6 -#define SEA_mmDAC_CRC_CONTROL 0x19e7 -#define SEA_mmDAC_CRC_SIG_RGB_MASK 0x19e8 -#define SEA_mmDAC_CRC_SIG_CONTROL_MASK 0x19e9 -#define SEA_mmDAC_CRC_SIG_RGB 0x19ea -#define SEA_mmDAC_CRC_SIG_CONTROL 0x19eb -#define SEA_mmDAC_SYNC_TRISTATE_CONTROL 0x19ec -#define SEA_mmDAC_STEREOSYNC_SELECT 0x19ed -#define SEA_mmDAC_AUTODETECT_CONTROL 0x19ee -#define SEA_mmDAC_AUTODETECT_CONTROL2 0x19ef -#define SEA_mmDAC_AUTODETECT_CONTROL3 0x19f0 -#define SEA_mmDAC_AUTODETECT_STATUS 0x19f1 -#define SEA_mmDAC_AUTODETECT_INT_CONTROL 0x19f2 -#define SEA_mmDAC_FORCE_OUTPUT_CNTL 0x19f3 -#define SEA_mmDAC_FORCE_DATA 0x19f4 -#define SEA_mmDAC_POWERDOWN 0x19f5 -#define SEA_mmDAC_CONTROL 0x19f6 -#define SEA_mmDAC_COMPARATOR_ENABLE 0x19f7 -#define SEA_mmDAC_COMPARATOR_OUTPUT 0x19f8 -#define SEA_mmDAC_PWR_CNTL 0x19f9 -#define SEA_mmDAC_DFT_CONFIG 0x19fa -#define SEA_mmDAC_FIFO_STATUS 0x19fb -#define SEA_mmPERFCOUNTER_CNTL 0x170 -#define SEA_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 -#define SEA_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870 -#define SEA_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24 -#define SEA_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24 -#define SEA_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124 -#define SEA_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424 -#define SEA_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724 -#define SEA_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24 -#define SEA_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40 -#define SEA_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14 -#define SEA_mmPERFCOUNTER_STATE 0x171 -#define SEA_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 -#define SEA_mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871 -#define SEA_mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25 -#define SEA_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25 -#define SEA_mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125 -#define SEA_mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425 -#define SEA_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725 -#define SEA_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25 -#define SEA_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41 -#define SEA_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15 -#define SEA_mmPERFMON_CNTL 0x173 -#define SEA_mmDC_PERFMON0_PERFMON_CNTL 0x173 -#define SEA_mmDC_PERFMON1_PERFMON_CNTL 0x1873 -#define SEA_mmDC_PERFMON2_PERFMON_CNTL 0x1b27 -#define SEA_mmDC_PERFMON3_PERFMON_CNTL 0x1e27 -#define SEA_mmDC_PERFMON4_PERFMON_CNTL 0x4127 -#define SEA_mmDC_PERFMON5_PERFMON_CNTL 0x4427 -#define SEA_mmDC_PERFMON6_PERFMON_CNTL 0x4727 -#define SEA_mmDC_PERFMON7_PERFMON_CNTL 0x4a27 -#define SEA_mmDC_PERFMON8_PERFMON_CNTL 0x4c43 -#define SEA_mmDC_PERFMON9_PERFMON_CNTL 0x4d17 -#define SEA_mmPERFMON_CVALUE_INT_MISC 0x172 -#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 -#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872 -#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26 -#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26 -#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126 -#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426 -#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726 -#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26 -#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42 -#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16 -#define SEA_mmPERFMON_CVALUE_LOW 0x174 -#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 -#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874 -#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28 -#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28 -#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128 -#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428 -#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728 -#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28 -#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44 -#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18 -#define SEA_mmPERFMON_HI 0x175 -#define SEA_mmDC_PERFMON0_PERFMON_HI 0x175 -#define SEA_mmDC_PERFMON1_PERFMON_HI 0x1875 -#define SEA_mmDC_PERFMON2_PERFMON_HI 0x1b29 -#define SEA_mmDC_PERFMON3_PERFMON_HI 0x1e29 -#define SEA_mmDC_PERFMON4_PERFMON_HI 0x4129 -#define SEA_mmDC_PERFMON5_PERFMON_HI 0x4429 -#define SEA_mmDC_PERFMON6_PERFMON_HI 0x4729 -#define SEA_mmDC_PERFMON7_PERFMON_HI 0x4a29 -#define SEA_mmDC_PERFMON8_PERFMON_HI 0x4c45 -#define SEA_mmDC_PERFMON9_PERFMON_HI 0x4d19 -#define SEA_mmPERFMON_LOW 0x176 -#define SEA_mmDC_PERFMON0_PERFMON_LOW 0x176 -#define SEA_mmDC_PERFMON1_PERFMON_LOW 0x1876 -#define SEA_mmDC_PERFMON2_PERFMON_LOW 0x1b2a -#define SEA_mmDC_PERFMON3_PERFMON_LOW 0x1e2a -#define SEA_mmDC_PERFMON4_PERFMON_LOW 0x412a -#define SEA_mmDC_PERFMON5_PERFMON_LOW 0x442a -#define SEA_mmDC_PERFMON6_PERFMON_LOW 0x472a -#define SEA_mmDC_PERFMON7_PERFMON_LOW 0x4a2a -#define SEA_mmDC_PERFMON8_PERFMON_LOW 0x4c46 -#define SEA_mmDC_PERFMON9_PERFMON_LOW 0x4d1a -#define SEA_mmPERFMON_TEST_DEBUG_INDEX 0x177 -#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 -#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877 -#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b -#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b -#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b -#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b -#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b -#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b -#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47 -#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b -#define SEA_mmPERFMON_TEST_DEBUG_DATA 0x178 -#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 -#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878 -#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c -#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c -#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c -#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c -#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c -#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c -#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48 -#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c -#define SEA_mmVGA25_PPLL_REF_DIV 0xd8 -#define SEA_mmVGA28_PPLL_REF_DIV 0xd9 -#define SEA_mmVGA41_PPLL_REF_DIV 0xda -#define SEA_mmVGA25_PPLL_FB_DIV 0xdc -#define SEA_mmVGA28_PPLL_FB_DIV 0xdd -#define SEA_mmVGA41_PPLL_FB_DIV 0xde -#define SEA_mmVGA25_PPLL_POST_DIV 0xe0 -#define SEA_mmVGA28_PPLL_POST_DIV 0xe1 -#define SEA_mmVGA41_PPLL_POST_DIV 0xe2 -#define SEA_mmVGA25_PPLL_ANALOG 0xe4 -#define SEA_mmVGA28_PPLL_ANALOG 0xe5 -#define SEA_mmVGA41_PPLL_ANALOG 0xe6 -#define SEA_mmDPREFCLK_CNTL 0x118 -#define SEA_mmSCANIN_SOFT_RESET 0x11e -#define SEA_mmDCCG_GTC_CNTL 0x120 -#define SEA_mmDCCG_GTC_DTO_INCR 0x121 -#define SEA_mmDCCG_GTC_DTO_MODULO 0x122 -#define SEA_mmDCCG_GTC_CURRENT 0x123 -#define SEA_mmDCCG_DS_DTO_INCR 0x113 -#define SEA_mmDCCG_DS_DTO_MODULO 0x114 -#define SEA_mmDCCG_DS_CNTL 0x115 -#define SEA_mmDCCG_DS_HW_CAL_INTERVAL 0x116 -#define SEA_mmDCCG_DS_DEBUG_CNTL 0x112 -#define SEA_mmDMCU_SMU_INTERRUPT_CNTL 0x12c -#define SEA_mmSMU_CONTROL 0x12d -#define SEA_mmSMU_INTERRUPT_CONTROL 0x12e -#define SEA_mmDAC_CLK_ENABLE 0x128 -#define SEA_mmDVO_CLK_ENABLE 0x129 -#define SEA_mmDCCG_GATE_DISABLE_CNTL 0x134 -#define SEA_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 -#define SEA_mmSCLK_CGTT_BLK_CTRL_REG 0x136 -#define SEA_mmDCCG_CAC_STATUS 0x137 -#define SEA_mmPIXCLK1_RESYNC_CNTL 0x138 -#define SEA_mmPIXCLK2_RESYNC_CNTL 0x139 -#define SEA_mmPIXCLK0_RESYNC_CNTL 0x13a -#define SEA_mmMICROSECOND_TIME_BASE_DIV 0x13b -#define SEA_mmDCCG_DISP_CNTL_REG 0x13f -#define SEA_mmDISPPLL_BG_CNTL 0x13c -#define SEA_mmDIG_SOFT_RESET 0x13d -#define SEA_mmMILLISECOND_TIME_BASE_DIV 0x130 -#define SEA_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 -#define SEA_mmLIGHT_SLEEP_CNTL 0x132 -#define SEA_mmDCCG_PERFMON_CNTL 0x133 -#define SEA_mmCRTC0_PIXEL_RATE_CNTL 0x140 -#define SEA_mmDP_DTO0_PHASE 0x141 -#define SEA_mmDP_DTO0_MODULO 0x142 -#define SEA_mmCRTC1_PIXEL_RATE_CNTL 0x144 -#define SEA_mmDP_DTO1_PHASE 0x145 -#define SEA_mmDP_DTO1_MODULO 0x146 -#define SEA_mmCRTC2_PIXEL_RATE_CNTL 0x148 -#define SEA_mmDP_DTO2_PHASE 0x149 -#define SEA_mmDP_DTO2_MODULO 0x14a -#define SEA_mmCRTC3_PIXEL_RATE_CNTL 0x14c -#define SEA_mmDP_DTO3_PHASE 0x14d -#define SEA_mmDP_DTO3_MODULO 0x14e -#define SEA_mmCRTC4_PIXEL_RATE_CNTL 0x150 -#define SEA_mmDP_DTO4_PHASE 0x151 -#define SEA_mmDP_DTO4_MODULO 0x152 -#define SEA_mmCRTC5_PIXEL_RATE_CNTL 0x154 -#define SEA_mmDP_DTO5_PHASE 0x155 -#define SEA_mmDP_DTO5_MODULO 0x156 -#define SEA_mmDCFE0_SOFT_RESET 0x158 -#define SEA_mmDCFE1_SOFT_RESET 0x159 -#define SEA_mmDCFE2_SOFT_RESET 0x15a -#define SEA_mmDCFE3_SOFT_RESET 0x15b -#define SEA_mmDCFE4_SOFT_RESET 0x15c -#define SEA_mmDCFE5_SOFT_RESET 0x15d -#define SEA_mmDCI_SOFT_RESET 0x15e -#define SEA_mmDCCG_SOFT_RESET 0x15f -#define SEA_mmSYMCLKA_CLOCK_ENABLE 0x160 -#define SEA_mmSYMCLKB_CLOCK_ENABLE 0x161 -#define SEA_mmSYMCLKC_CLOCK_ENABLE 0x162 -#define SEA_mmSYMCLKD_CLOCK_ENABLE 0x163 -#define SEA_mmSYMCLKE_CLOCK_ENABLE 0x164 -#define SEA_mmSYMCLKF_CLOCK_ENABLE 0x165 -#define SEA_mmSYMCLKG_CLOCK_ENABLE 0x117 -#define SEA_mmUNIPHY_SOFT_RESET 0x166 -#define SEA_mmDCO_SOFT_RESET 0x167 -#define SEA_mmDVOACLKD_CNTL 0x168 -#define SEA_mmDVOACLKC_MVP_CNTL 0x169 -#define SEA_mmDVOACLKC_CNTL 0x16a -#define SEA_mmDCCG_AUDIO_DTO_SOURCE 0x16b -#define SEA_mmDCCG_AUDIO_DTO0_PHASE 0x16c -#define SEA_mmDCCG_AUDIO_DTO0_MODULE 0x16d -#define SEA_mmDCCG_AUDIO_DTO1_PHASE 0x16e -#define SEA_mmDCCG_AUDIO_DTO1_MODULE 0x16f -#define SEA_mmDCCG_TEST_DEBUG_INDEX 0x17c -#define SEA_mmDCCG_TEST_DEBUG_DATA 0x17d -#define SEA_mmDCCG_TEST_CLK_SEL 0x17e -#define SEA_mmPLL_REF_DIV 0x1700 -#define SEA_mmDCCG_PLL0_PLL_REF_DIV 0x1700 -#define SEA_mmDCCG_PLL1_PLL_REF_DIV 0x1714 -#define SEA_mmDCCG_PLL2_PLL_REF_DIV 0x1728 -#define SEA_mmDCCG_PLL3_PLL_REF_DIV 0x173c -#define SEA_mmPLL_FB_DIV 0x1701 -#define SEA_mmDCCG_PLL0_PLL_FB_DIV 0x1701 -#define SEA_mmDCCG_PLL1_PLL_FB_DIV 0x1715 -#define SEA_mmDCCG_PLL2_PLL_FB_DIV 0x1729 -#define SEA_mmDCCG_PLL3_PLL_FB_DIV 0x173d -#define SEA_mmPLL_POST_DIV 0x1702 -#define SEA_mmDCCG_PLL0_PLL_POST_DIV 0x1702 -#define SEA_mmDCCG_PLL1_PLL_POST_DIV 0x1716 -#define SEA_mmDCCG_PLL2_PLL_POST_DIV 0x172a -#define SEA_mmDCCG_PLL3_PLL_POST_DIV 0x173e -#define SEA_mmPLL_SS_AMOUNT_DSFRAC 0x1703 -#define SEA_mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 -#define SEA_mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717 -#define SEA_mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b -#define SEA_mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f -#define SEA_mmPLL_SS_CNTL 0x1704 -#define SEA_mmDCCG_PLL0_PLL_SS_CNTL 0x1704 -#define SEA_mmDCCG_PLL1_PLL_SS_CNTL 0x1718 -#define SEA_mmDCCG_PLL2_PLL_SS_CNTL 0x172c -#define SEA_mmDCCG_PLL3_PLL_SS_CNTL 0x1740 -#define SEA_mmPLL_DS_CNTL 0x1705 -#define SEA_mmDCCG_PLL0_PLL_DS_CNTL 0x1705 -#define SEA_mmDCCG_PLL1_PLL_DS_CNTL 0x1719 -#define SEA_mmDCCG_PLL2_PLL_DS_CNTL 0x172d -#define SEA_mmDCCG_PLL3_PLL_DS_CNTL 0x1741 -#define SEA_mmPLL_IDCLK_CNTL 0x1706 -#define SEA_mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 -#define SEA_mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a -#define SEA_mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e -#define SEA_mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742 -#define SEA_mmPLL_CNTL 0x1707 -#define SEA_mmDCCG_PLL0_PLL_CNTL 0x1707 -#define SEA_mmDCCG_PLL1_PLL_CNTL 0x171b -#define SEA_mmDCCG_PLL2_PLL_CNTL 0x172f -#define SEA_mmDCCG_PLL3_PLL_CNTL 0x1743 -#define SEA_mmPLL_ANALOG 0x1708 -#define SEA_mmDCCG_PLL0_PLL_ANALOG 0x1708 -#define SEA_mmDCCG_PLL1_PLL_ANALOG 0x171c -#define SEA_mmDCCG_PLL2_PLL_ANALOG 0x1730 -#define SEA_mmDCCG_PLL3_PLL_ANALOG 0x1744 -#define SEA_mmPLL_ANALOG_CNTL 0x1711 -#define SEA_mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711 -#define SEA_mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725 -#define SEA_mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739 -#define SEA_mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d -#define SEA_mmPLL_VREG_CNTL 0x1709 -#define SEA_mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 -#define SEA_mmDCCG_PLL1_PLL_VREG_CNTL 0x171d -#define SEA_mmDCCG_PLL2_PLL_VREG_CNTL 0x1731 -#define SEA_mmDCCG_PLL3_PLL_VREG_CNTL 0x1745 -#define SEA_mmPLL_XOR_LOCK 0x1710 -#define SEA_mmDCCG_PLL0_PLL_XOR_LOCK 0x1710 -#define SEA_mmDCCG_PLL1_PLL_XOR_LOCK 0x1724 -#define SEA_mmDCCG_PLL2_PLL_XOR_LOCK 0x1738 -#define SEA_mmDCCG_PLL3_PLL_XOR_LOCK 0x174c -#define SEA_mmPLL_UNLOCK_DETECT_CNTL 0x170a -#define SEA_mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a -#define SEA_mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e -#define SEA_mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732 -#define SEA_mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746 -#define SEA_mmPLL_DEBUG_CNTL 0x170b -#define SEA_mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b -#define SEA_mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f -#define SEA_mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733 -#define SEA_mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747 -#define SEA_mmPLL_UPDATE_LOCK 0x170c -#define SEA_mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c -#define SEA_mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720 -#define SEA_mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734 -#define SEA_mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748 -#define SEA_mmPLL_UPDATE_CNTL 0x170d -#define SEA_mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d -#define SEA_mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721 -#define SEA_mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735 -#define SEA_mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749 -#define SEA_mmPLL_DISPCLK_DTO_CNTL 0x170e -#define SEA_mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e -#define SEA_mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722 -#define SEA_mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736 -#define SEA_mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a -#define SEA_mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f -#define SEA_mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f -#define SEA_mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723 -#define SEA_mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737 -#define SEA_mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b -#define SEA_mmDENTIST_DISPCLK_CNTL 0x124 -#define SEA_mmDCDEBUG_BUS_CLK1_SEL 0x1860 -#define SEA_mmDCDEBUG_BUS_CLK2_SEL 0x1861 -#define SEA_mmDCDEBUG_BUS_CLK3_SEL 0x1862 -#define SEA_mmDCDEBUG_BUS_CLK4_SEL 0x1863 -#define SEA_mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a -#define SEA_mmDCDEBUG_OUT_CNTL 0x186b -#define SEA_mmDCDEBUG_OUT_DATA 0x186e -#define SEA_mmDMIF_ADDR_CONFIG 0x2f5 -#define SEA_mmDMIF_CONTROL 0x2f6 -#define SEA_mmDMIF_STATUS 0x2f7 -#define SEA_mmDMIF_HW_DEBUG 0x2f8 -#define SEA_mmDMIF_ARBITRATION_CONTROL 0x2f9 -#define SEA_mmPIPE0_ARBITRATION_CONTROL3 0x2fa -#define SEA_mmPIPE1_ARBITRATION_CONTROL3 0x2fb -#define SEA_mmPIPE2_ARBITRATION_CONTROL3 0x2fc -#define SEA_mmPIPE3_ARBITRATION_CONTROL3 0x2fd -#define SEA_mmPIPE4_ARBITRATION_CONTROL3 0x2fe -#define SEA_mmPIPE5_ARBITRATION_CONTROL3 0x2ff -#define SEA_mmDMIF_TEST_DEBUG_INDEX 0x312 -#define SEA_mmDMIF_TEST_DEBUG_DATA 0x313 -#define SEA_ixDMIF_DEBUG02_CORE0 0x2 -#define SEA_ixDMIF_DEBUG02_CORE1 0xa -#define SEA_mmDMIF_ADDR_CALC 0x300 -#define SEA_mmDMIF_STATUS2 0x301 -#define SEA_mmPIPE0_MAX_REQUESTS 0x302 -#define SEA_mmPIPE1_MAX_REQUESTS 0x303 -#define SEA_mmPIPE2_MAX_REQUESTS 0x304 -#define SEA_mmPIPE3_MAX_REQUESTS 0x305 -#define SEA_mmPIPE4_MAX_REQUESTS 0x306 -#define SEA_mmPIPE5_MAX_REQUESTS 0x307 -#define SEA_mmLOW_POWER_TILING_CONTROL 0x325 -#define SEA_mmMCIF_CONTROL 0x314 -#define SEA_mmMCIF_WRITE_COMBINE_CONTROL 0x315 -#define SEA_mmMCIF_TEST_DEBUG_INDEX 0x316 -#define SEA_mmMCIF_TEST_DEBUG_DATA 0x317 -#define SEA_ixIDDCCIF02_DBG_DCCIF_C 0x9 -#define SEA_ixIDDCCIF04_DBG_DCCIF_E 0xb -#define SEA_ixIDDCCIF05_DBG_DCCIF_F 0xc -#define SEA_mmMCIF_VMID 0x318 -#define SEA_mmMCIF_MEM_CONTROL 0x319 -#define SEA_mmCC_DC_PIPE_DIS 0x177f -#define SEA_mmMC_DC_INTERFACE_NACK_STATUS 0x31c -#define SEA_mmDC_RBBMIF_RDWR_CNTL1 0x31a -#define SEA_mmDC_RBBMIF_RDWR_CNTL2 0x31d -#define SEA_mmDC_RBBMIF_RDWR_CNTL3 0x311 -#define SEA_mmDCI_MEM_PWR_STATE 0x31b -#define SEA_mmDCI_MEM_PWR_STATE2 0x322 -#define SEA_mmDCI_CLK_CNTL 0x31e -#define SEA_mmDCCG_VPCLK_CNTL 0x31f -#define SEA_mmDCI_MEM_PWR_CNTL 0x326 -#define SEA_mmDC_XDMA_INTERFACE_CNTL 0x327 -#define SEA_mmDCI_TEST_DEBUG_INDEX 0x320 -#define SEA_mmDCI_TEST_DEBUG_DATA 0x321 -#define SEA_mmDCI_DEBUG_CONFIG 0x323 -#define SEA_mmPIPE0_DMIF_BUFFER_CONTROL 0x328 -#define SEA_mmPIPE1_DMIF_BUFFER_CONTROL 0x330 -#define SEA_mmPIPE2_DMIF_BUFFER_CONTROL 0x338 -#define SEA_mmPIPE3_DMIF_BUFFER_CONTROL 0x340 -#define SEA_mmPIPE4_DMIF_BUFFER_CONTROL 0x348 -#define SEA_mmPIPE5_DMIF_BUFFER_CONTROL 0x350 -#define SEA_mmMCIF_BUFMGR_SW_CONTROL 0x358 -#define SEA_mmMCIF_BUFMGR_STATUS 0x35a -#define SEA_mmMCIF_BUF_PITCH 0x35b -#define SEA_mmMCIF_BUF_1_ADDR_Y_LOW 0x35c -#define SEA_mmMCIF_BUF_2_ADDR_Y_LOW 0x360 -#define SEA_mmMCIF_BUF_3_ADDR_Y_LOW 0x364 -#define SEA_mmMCIF_BUF_4_ADDR_Y_LOW 0x368 -#define SEA_mmMCIF_BUF_1_ADDR_UP 0x35d -#define SEA_mmMCIF_BUF_2_ADDR_UP 0x361 -#define SEA_mmMCIF_BUF_3_ADDR_UP 0x365 -#define SEA_mmMCIF_BUF_4_ADDR_UP 0x369 -#define SEA_mmMCIF_BUF_1_ADDR_C_LOW 0x35e -#define SEA_mmMCIF_BUF_2_ADDR_C_LOW 0x362 -#define SEA_mmMCIF_BUF_3_ADDR_C_LOW 0x366 -#define SEA_mmMCIF_BUF_4_ADDR_C_LOW 0x36a -#define SEA_mmMCIF_BUF_1_STATUS 0x35f -#define SEA_mmMCIF_BUF_2_STATUS 0x363 -#define SEA_mmMCIF_BUF_3_STATUS 0x367 -#define SEA_mmMCIF_BUF_4_STATUS 0x36b -#define SEA_mmMCIF_SI_ARBITRATION_CONTROL 0x36c -#define SEA_mmMCIF_URGENCY_WATERMARK 0x36d -#define SEA_mmDC_GENERICA 0x1900 -#define SEA_mmDC_GENERICB 0x1901 -#define SEA_mmDC_PAD_EXTERN_SIG 0x1902 -#define SEA_mmDC_REF_CLK_CNTL 0x1903 -#define SEA_mmDC_GPIO_DEBUG 0x1904 -#define SEA_mmDCO_MEM_POWER_STATE 0x1906 -#define SEA_mmDCO_MEM_POWER_STATE_2 0x193a -#define SEA_mmDCO_LIGHT_SLEEP_DIS 0x1907 -#define SEA_mmUNIPHY_IMPCAL_LINKA 0x1908 -#define SEA_mmUNIPHY_IMPCAL_LINKB 0x1909 -#define SEA_mmUNIPHY_IMPCAL_PERIOD 0x190a -#define SEA_mmAUXP_IMPCAL 0x190b -#define SEA_mmAUXN_IMPCAL 0x190c -#define SEA_mmDCIO_IMPCAL_CNTL_AB 0x190d -#define SEA_mmUNIPHY_IMPCAL_PSW_AB 0x190e -#define SEA_mmUNIPHY_IMPCAL_LINKC 0x190f -#define SEA_mmUNIPHY_IMPCAL_LINKD 0x1910 -#define SEA_mmDCIO_IMPCAL_CNTL_CD 0x1911 -#define SEA_mmUNIPHY_IMPCAL_PSW_CD 0x1912 -#define SEA_mmUNIPHY_IMPCAL_LINKE 0x1913 -#define SEA_mmUNIPHY_IMPCAL_LINKF 0x1914 -#define SEA_mmDCIO_IMPCAL_CNTL_EF 0x1915 -#define SEA_mmUNIPHY_IMPCAL_PSW_EF 0x1916 -#define SEA_mmDC_PINSTRAPS 0x1917 -#define SEA_mmDC_DVODATA_CONFIG 0x1905 -#define SEA_mmLVTMA_PWRSEQ_CNTL 0x1919 -#define SEA_mmLVTMA_PWRSEQ_STATE 0x191a -#define SEA_mmLVTMA_PWRSEQ_REF_DIV 0x191b -#define SEA_mmLVTMA_PWRSEQ_DELAY1 0x191c -#define SEA_mmLVTMA_PWRSEQ_DELAY2 0x191d -#define SEA_mmBL_PWM_CNTL 0x191e -#define SEA_mmBL_PWM_CNTL2 0x191f -#define SEA_mmBL_PWM_PERIOD_CNTL 0x1920 -#define SEA_mmBL_PWM_GRP1_REG_LOCK 0x1921 -#define SEA_mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 -#define SEA_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 -#define SEA_mmDCIO_GSL0_CNTL 0x1924 -#define SEA_mmDCIO_GSL1_CNTL 0x1925 -#define SEA_mmDCIO_GSL2_CNTL 0x1926 -#define SEA_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 -#define SEA_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 -#define SEA_mmDC_GPU_TIMER_READ 0x1929 -#define SEA_mmDC_GPU_TIMER_READ_CNTL 0x192a -#define SEA_mmDCO_CLK_CNTL 0x192b -#define SEA_mmDCO_CLK_RAMP_CNTL 0x192c -#define SEA_mmDCIO_DEBUG 0x192e -#define SEA_mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937 -#define SEA_mmDCIO_TEST_DEBUG_INDEX 0x192f -#define SEA_mmDCIO_TEST_DEBUG_DATA 0x1930 -#define SEA_ixDCIO_DEBUG1 0x1 -#define SEA_ixDCIO_DEBUG2 0x2 -#define SEA_ixDCIO_DEBUG3 0x3 -#define SEA_ixDCIO_DEBUG4 0x4 -#define SEA_ixDCIO_DEBUG5 0x5 -#define SEA_ixDCIO_DEBUG6 0x6 -#define SEA_ixDCIO_DEBUG7 0x7 -#define SEA_ixDCIO_DEBUG8 0x8 -#define SEA_ixDCIO_DEBUG9 0x9 -#define SEA_ixDCIO_DEBUGA 0xa -#define SEA_ixDCIO_DEBUGB 0xb -#define SEA_ixDCIO_DEBUGC 0xc -#define SEA_ixDCIO_DEBUGD 0xd -#define SEA_ixDCIO_DEBUGE 0xe -#define SEA_ixDCIO_DEBUGF 0xf -#define SEA_ixDCIO_DEBUG10 0x10 -#define SEA_ixDCIO_DEBUG11 0x11 -#define SEA_ixDCIO_DEBUG12 0x12 -#define SEA_ixDCIO_DEBUG13 0x13 -#define SEA_ixDCIO_DEBUG14 0x14 -#define SEA_ixDCIO_DEBUG15 0x15 -#define SEA_ixDCIO_DEBUG_ID 0x0 -#define SEA_mmDC_GPIO_GENERIC_MASK 0x1944 -#define SEA_mmDC_GPIO_GENERIC_A 0x1945 -#define SEA_mmDC_GPIO_GENERIC_EN 0x1946 -#define SEA_mmDC_GPIO_GENERIC_Y 0x1947 -#define SEA_mmDC_GPIO_DVODATA_MASK 0x1948 -#define SEA_mmDC_GPIO_DVODATA_A 0x1949 -#define SEA_mmDC_GPIO_DVODATA_EN 0x194a -#define SEA_mmDC_GPIO_DVODATA_Y 0x194b -#define SEA_mmDC_GPIO_DDC1_MASK 0x194c -#define SEA_mmDC_GPIO_DDC1_A 0x194d -#define SEA_mmDC_GPIO_DDC1_EN 0x194e -#define SEA_mmDC_GPIO_DDC1_Y 0x194f -#define SEA_mmDC_GPIO_DDC2_MASK 0x1950 -#define SEA_mmDC_GPIO_DDC2_A 0x1951 -#define SEA_mmDC_GPIO_DDC2_EN 0x1952 -#define SEA_mmDC_GPIO_DDC2_Y 0x1953 -#define SEA_mmDC_GPIO_DDC3_MASK 0x1954 -#define SEA_mmDC_GPIO_DDC3_A 0x1955 -#define SEA_mmDC_GPIO_DDC3_EN 0x1956 -#define SEA_mmDC_GPIO_DDC3_Y 0x1957 -#define SEA_mmDC_GPIO_DDC4_MASK 0x1958 -#define SEA_mmDC_GPIO_DDC4_A 0x1959 -#define SEA_mmDC_GPIO_DDC4_EN 0x195a -#define SEA_mmDC_GPIO_DDC4_Y 0x195b -#define SEA_mmDC_GPIO_DDC5_MASK 0x195c -#define SEA_mmDC_GPIO_DDC5_A 0x195d -#define SEA_mmDC_GPIO_DDC5_EN 0x195e -#define SEA_mmDC_GPIO_DDC5_Y 0x195f -#define SEA_mmDC_GPIO_DDC6_MASK 0x1960 -#define SEA_mmDC_GPIO_DDC6_A 0x1961 -#define SEA_mmDC_GPIO_DDC6_EN 0x1962 -#define SEA_mmDC_GPIO_DDC6_Y 0x1963 -#define SEA_mmDC_GPIO_DDCVGA_MASK 0x1970 -#define SEA_mmDC_GPIO_DDCVGA_A 0x1971 -#define SEA_mmDC_GPIO_DDCVGA_EN 0x1972 -#define SEA_mmDC_GPIO_DDCVGA_Y 0x1973 -#define SEA_mmDC_GPIO_SYNCA_MASK 0x1964 -#define SEA_mmDC_GPIO_SYNCA_A 0x1965 -#define SEA_mmDC_GPIO_SYNCA_EN 0x1966 -#define SEA_mmDC_GPIO_SYNCA_Y 0x1967 -#define SEA_mmDC_GPIO_GENLK_MASK 0x1968 -#define SEA_mmDC_GPIO_GENLK_A 0x1969 -#define SEA_mmDC_GPIO_GENLK_EN 0x196a -#define SEA_mmDC_GPIO_GENLK_Y 0x196b -#define SEA_mmDC_GPIO_HPD_MASK 0x196c #define SEA_mmDC_GPIO_HPD_A 0x196d -#define SEA_mmDC_GPIO_HPD_EN 0x196e -#define SEA_mmDC_GPIO_HPD_Y 0x196f -#define SEA_mmDC_GPIO_PWRSEQ_MASK 0x1940 -#define SEA_mmDC_GPIO_PWRSEQ_A 0x1941 -#define SEA_mmDC_GPIO_PWRSEQ_EN 0x1942 -#define SEA_mmDC_GPIO_PWRSEQ_Y 0x1943 -#define SEA_mmDC_GPIO_PAD_STRENGTH_1 0x1978 -#define SEA_mmDC_GPIO_PAD_STRENGTH_2 0x1979 -#define SEA_mmPHY_AUX_CNTL 0x197f -#define SEA_mmDC_GPIO_I2CPAD_A 0x1975 -#define SEA_mmDC_GPIO_I2CPAD_EN 0x1976 -#define SEA_mmDC_GPIO_I2CPAD_Y 0x1977 -#define SEA_mmDC_GPIO_I2CPAD_STRENGTH 0x197a -#define SEA_mmDVO_STRENGTH_CONTROL 0x197b -#define SEA_mmDVO_VREF_CONTROL 0x197c -#define SEA_mmDVO_SKEW_ADJUST 0x197d -#define SEA_mmUNIPHYAB_TPG_CONTROL 0x1931 -#define SEA_mmUNIPHYAB_TPG_SEED 0x1932 -#define SEA_mmUNIPHYCD_TPG_CONTROL 0x1933 -#define SEA_mmUNIPHYCD_TPG_SEED 0x1934 -#define SEA_mmUNIPHYEF_TPG_CONTROL 0x1935 -#define SEA_mmUNIPHYEF_TPG_SEED 0x1936 -#define SEA_mmUNIPHYGH_TPG_CONTROL 0x1938 -#define SEA_mmUNIPHYGH_TPG_SEED 0x1939 -#define SEA_mmDC_GPIO_I2S_SPDIF_MASK 0x193c -#define SEA_mmDC_GPIO_I2S_SPDIF_A 0x193d -#define SEA_mmDC_GPIO_I2S_SPDIF_EN 0x193e -#define SEA_mmDC_GPIO_I2S_SPDIF_Y 0x193f -#define SEA_mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b -#define SEA_mmDAC_MACRO_CNTL_RESERVED0 0x19fc -#define SEA_mmDAC_MACRO_CNTL_RESERVED1 0x19fd -#define SEA_mmDAC_MACRO_CNTL_RESERVED2 0x19fe -#define SEA_mmDAC_MACRO_CNTL_RESERVED3 0x19ff -#define SEA_mmUNIPHY_TX_CONTROL1 0x1980 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0 -#define SEA_mmUNIPHY_TX_CONTROL2 0x1981 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1 -#define SEA_mmUNIPHY_TX_CONTROL3 0x1982 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2 -#define SEA_mmUNIPHY_TX_CONTROL4 0x1983 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3 -#define SEA_mmUNIPHY_POWER_CONTROL 0x1984 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4 -#define SEA_mmUNIPHY_PLL_FBDIV 0x1985 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5 -#define SEA_mmUNIPHY_PLL_CONTROL1 0x1986 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6 -#define SEA_mmUNIPHY_PLL_CONTROL2 0x1987 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7 -#define SEA_mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8 -#define SEA_mmUNIPHY_PLL_SS_CNTL 0x1989 -#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 -#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 -#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9 -#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9 -#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9 -#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9 -#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9 -#define SEA_mmUNIPHY_DATA_SYNCHRONIZATION 0x198a -#define SEA_mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a -#define SEA_mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a -#define SEA_mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa -#define SEA_mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba -#define SEA_mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca -#define SEA_mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da -#define SEA_mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa -#define SEA_mmUNIPHY_REG_TEST_OUTPUT 0x198b -#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b -#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b -#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab -#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb -#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb -#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db -#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb -#define SEA_mmUNIPHY_ANG_BIST_CNTL 0x198c -#define SEA_mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c -#define SEA_mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c -#define SEA_mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac -#define SEA_mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc -#define SEA_mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc -#define SEA_mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc -#define SEA_mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc -#define SEA_mmUNIPHY_LINK_CNTL 0x198d -#define SEA_mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d -#define SEA_mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d -#define SEA_mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad -#define SEA_mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd -#define SEA_mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd -#define SEA_mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd -#define SEA_mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd -#define SEA_mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e -#define SEA_mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e -#define SEA_mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e -#define SEA_mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae -#define SEA_mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be -#define SEA_mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce -#define SEA_mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de -#define SEA_mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe -#define SEA_mmUNIPHY_REG_TEST_OUTPUT2 0x198f -#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f -#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f -#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af -#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf -#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf -#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df -#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff -#define SEA_mmGRPH_ENABLE 0x1a00 -#define SEA_mmDCP0_GRPH_ENABLE 0x1a00 -#define SEA_mmDCP1_GRPH_ENABLE 0x1d00 -#define SEA_mmDCP2_GRPH_ENABLE 0x4000 -#define SEA_mmDCP3_GRPH_ENABLE 0x4300 -#define SEA_mmDCP4_GRPH_ENABLE 0x4600 -#define SEA_mmDCP5_GRPH_ENABLE 0x4900 -#define SEA_mmGRPH_CONTROL 0x1a01 -#define SEA_mmDCP0_GRPH_CONTROL 0x1a01 -#define SEA_mmDCP1_GRPH_CONTROL 0x1d01 -#define SEA_mmDCP2_GRPH_CONTROL 0x4001 -#define SEA_mmDCP3_GRPH_CONTROL 0x4301 -#define SEA_mmDCP4_GRPH_CONTROL 0x4601 -#define SEA_mmDCP5_GRPH_CONTROL 0x4901 -#define SEA_mmGRPH_LUT_10BIT_BYPASS 0x1a02 -#define SEA_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 -#define SEA_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02 -#define SEA_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 -#define SEA_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 -#define SEA_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 -#define SEA_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 -#define SEA_mmGRPH_SWAP_CNTL 0x1a03 -#define SEA_mmDCP0_GRPH_SWAP_CNTL 0x1a03 -#define SEA_mmDCP1_GRPH_SWAP_CNTL 0x1d03 -#define SEA_mmDCP2_GRPH_SWAP_CNTL 0x4003 -#define SEA_mmDCP3_GRPH_SWAP_CNTL 0x4303 -#define SEA_mmDCP4_GRPH_SWAP_CNTL 0x4603 -#define SEA_mmDCP5_GRPH_SWAP_CNTL 0x4903 -#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04 -#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 -#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 -#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 -#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 -#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05 -#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 -#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 -#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 -#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 -#define SEA_mmGRPH_PITCH 0x1a06 -#define SEA_mmDCP0_GRPH_PITCH 0x1a06 -#define SEA_mmDCP1_GRPH_PITCH 0x1d06 -#define SEA_mmDCP2_GRPH_PITCH 0x4006 -#define SEA_mmDCP3_GRPH_PITCH 0x4306 -#define SEA_mmDCP4_GRPH_PITCH 0x4606 -#define SEA_mmDCP5_GRPH_PITCH 0x4906 -#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07 -#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 -#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 -#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 -#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 -#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08 -#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 -#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 -#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 -#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 -#define SEA_mmGRPH_SURFACE_OFFSET_X 0x1a09 -#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 -#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09 -#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 -#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 -#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 -#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 -#define SEA_mmGRPH_SURFACE_OFFSET_Y 0x1a0a -#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a -#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a -#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a -#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a -#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a -#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a -#define SEA_mmGRPH_X_START 0x1a0b -#define SEA_mmDCP0_GRPH_X_START 0x1a0b -#define SEA_mmDCP1_GRPH_X_START 0x1d0b -#define SEA_mmDCP2_GRPH_X_START 0x400b -#define SEA_mmDCP3_GRPH_X_START 0x430b -#define SEA_mmDCP4_GRPH_X_START 0x460b -#define SEA_mmDCP5_GRPH_X_START 0x490b -#define SEA_mmGRPH_Y_START 0x1a0c -#define SEA_mmDCP0_GRPH_Y_START 0x1a0c -#define SEA_mmDCP1_GRPH_Y_START 0x1d0c -#define SEA_mmDCP2_GRPH_Y_START 0x400c -#define SEA_mmDCP3_GRPH_Y_START 0x430c -#define SEA_mmDCP4_GRPH_Y_START 0x460c -#define SEA_mmDCP5_GRPH_Y_START 0x490c -#define SEA_mmGRPH_X_END 0x1a0d -#define SEA_mmDCP0_GRPH_X_END 0x1a0d -#define SEA_mmDCP1_GRPH_X_END 0x1d0d -#define SEA_mmDCP2_GRPH_X_END 0x400d -#define SEA_mmDCP3_GRPH_X_END 0x430d -#define SEA_mmDCP4_GRPH_X_END 0x460d -#define SEA_mmDCP5_GRPH_X_END 0x490d -#define SEA_mmGRPH_Y_END 0x1a0e -#define SEA_mmDCP0_GRPH_Y_END 0x1a0e -#define SEA_mmDCP1_GRPH_Y_END 0x1d0e -#define SEA_mmDCP2_GRPH_Y_END 0x400e -#define SEA_mmDCP3_GRPH_Y_END 0x430e -#define SEA_mmDCP4_GRPH_Y_END 0x460e -#define SEA_mmDCP5_GRPH_Y_END 0x490e -#define SEA_mmINPUT_GAMMA_CONTROL 0x1a10 -#define SEA_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 -#define SEA_mmDCP1_INPUT_GAMMA_CONTROL 0x1d10 -#define SEA_mmDCP2_INPUT_GAMMA_CONTROL 0x4010 -#define SEA_mmDCP3_INPUT_GAMMA_CONTROL 0x4310 -#define SEA_mmDCP4_INPUT_GAMMA_CONTROL 0x4610 -#define SEA_mmDCP5_INPUT_GAMMA_CONTROL 0x4910 -#define SEA_mmGRPH_UPDATE 0x1a11 -#define SEA_mmDCP0_GRPH_UPDATE 0x1a11 -#define SEA_mmDCP1_GRPH_UPDATE 0x1d11 -#define SEA_mmDCP2_GRPH_UPDATE 0x4011 -#define SEA_mmDCP3_GRPH_UPDATE 0x4311 -#define SEA_mmDCP4_GRPH_UPDATE 0x4611 -#define SEA_mmDCP5_GRPH_UPDATE 0x4911 -#define SEA_mmGRPH_FLIP_CONTROL 0x1a12 -#define SEA_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 -#define SEA_mmDCP1_GRPH_FLIP_CONTROL 0x1d12 -#define SEA_mmDCP2_GRPH_FLIP_CONTROL 0x4012 -#define SEA_mmDCP3_GRPH_FLIP_CONTROL 0x4312 -#define SEA_mmDCP4_GRPH_FLIP_CONTROL 0x4612 -#define SEA_mmDCP5_GRPH_FLIP_CONTROL 0x4912 -#define SEA_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13 -#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 -#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 -#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 -#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 -#define SEA_mmGRPH_DFQ_CONTROL 0x1a14 -#define SEA_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 -#define SEA_mmDCP1_GRPH_DFQ_CONTROL 0x1d14 -#define SEA_mmDCP2_GRPH_DFQ_CONTROL 0x4014 -#define SEA_mmDCP3_GRPH_DFQ_CONTROL 0x4314 -#define SEA_mmDCP4_GRPH_DFQ_CONTROL 0x4614 -#define SEA_mmDCP5_GRPH_DFQ_CONTROL 0x4914 -#define SEA_mmGRPH_DFQ_STATUS 0x1a15 -#define SEA_mmDCP0_GRPH_DFQ_STATUS 0x1a15 -#define SEA_mmDCP1_GRPH_DFQ_STATUS 0x1d15 -#define SEA_mmDCP2_GRPH_DFQ_STATUS 0x4015 -#define SEA_mmDCP3_GRPH_DFQ_STATUS 0x4315 -#define SEA_mmDCP4_GRPH_DFQ_STATUS 0x4615 -#define SEA_mmDCP5_GRPH_DFQ_STATUS 0x4915 -#define SEA_mmGRPH_INTERRUPT_STATUS 0x1a16 -#define SEA_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 -#define SEA_mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16 -#define SEA_mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 -#define SEA_mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 -#define SEA_mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 -#define SEA_mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 -#define SEA_mmGRPH_INTERRUPT_CONTROL 0x1a17 -#define SEA_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 -#define SEA_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17 -#define SEA_mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 -#define SEA_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 -#define SEA_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 -#define SEA_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 -#define SEA_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18 -#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 -#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 -#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 -#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 -#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19 -#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 -#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 -#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 -#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 -#define SEA_mmGRPH_COMPRESS_PITCH 0x1a1a -#define SEA_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a -#define SEA_mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a -#define SEA_mmDCP2_GRPH_COMPRESS_PITCH 0x401a -#define SEA_mmDCP3_GRPH_COMPRESS_PITCH 0x431a -#define SEA_mmDCP4_GRPH_COMPRESS_PITCH 0x461a -#define SEA_mmDCP5_GRPH_COMPRESS_PITCH 0x491a -#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b -#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b -#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b -#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b -#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b -#define SEA_mmOVL_ENABLE 0x1a1c -#define SEA_mmDCP0_OVL_ENABLE 0x1a1c -#define SEA_mmDCP1_OVL_ENABLE 0x1d1c -#define SEA_mmDCP2_OVL_ENABLE 0x401c -#define SEA_mmDCP3_OVL_ENABLE 0x431c -#define SEA_mmDCP4_OVL_ENABLE 0x461c -#define SEA_mmDCP5_OVL_ENABLE 0x491c -#define SEA_mmOVL_CONTROL1 0x1a1d -#define SEA_mmDCP0_OVL_CONTROL1 0x1a1d -#define SEA_mmDCP1_OVL_CONTROL1 0x1d1d -#define SEA_mmDCP2_OVL_CONTROL1 0x401d -#define SEA_mmDCP3_OVL_CONTROL1 0x431d -#define SEA_mmDCP4_OVL_CONTROL1 0x461d -#define SEA_mmDCP5_OVL_CONTROL1 0x491d -#define SEA_mmOVL_CONTROL2 0x1a1e -#define SEA_mmDCP0_OVL_CONTROL2 0x1a1e -#define SEA_mmDCP1_OVL_CONTROL2 0x1d1e -#define SEA_mmDCP2_OVL_CONTROL2 0x401e -#define SEA_mmDCP3_OVL_CONTROL2 0x431e -#define SEA_mmDCP4_OVL_CONTROL2 0x461e -#define SEA_mmDCP5_OVL_CONTROL2 0x491e -#define SEA_mmOVL_SWAP_CNTL 0x1a1f -#define SEA_mmDCP0_OVL_SWAP_CNTL 0x1a1f -#define SEA_mmDCP1_OVL_SWAP_CNTL 0x1d1f -#define SEA_mmDCP2_OVL_SWAP_CNTL 0x401f -#define SEA_mmDCP3_OVL_SWAP_CNTL 0x431f -#define SEA_mmDCP4_OVL_SWAP_CNTL 0x461f -#define SEA_mmDCP5_OVL_SWAP_CNTL 0x491f -#define SEA_mmOVL_SURFACE_ADDRESS 0x1a20 -#define SEA_mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 -#define SEA_mmDCP1_OVL_SURFACE_ADDRESS 0x1d20 -#define SEA_mmDCP2_OVL_SURFACE_ADDRESS 0x4020 -#define SEA_mmDCP3_OVL_SURFACE_ADDRESS 0x4320 -#define SEA_mmDCP4_OVL_SURFACE_ADDRESS 0x4620 -#define SEA_mmDCP5_OVL_SURFACE_ADDRESS 0x4920 -#define SEA_mmOVL_PITCH 0x1a21 -#define SEA_mmDCP0_OVL_PITCH 0x1a21 -#define SEA_mmDCP1_OVL_PITCH 0x1d21 -#define SEA_mmDCP2_OVL_PITCH 0x4021 -#define SEA_mmDCP3_OVL_PITCH 0x4321 -#define SEA_mmDCP4_OVL_PITCH 0x4621 -#define SEA_mmDCP5_OVL_PITCH 0x4921 -#define SEA_mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 -#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 -#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22 -#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 -#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 -#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 -#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 -#define SEA_mmOVL_SURFACE_OFFSET_X 0x1a23 -#define SEA_mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 -#define SEA_mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23 -#define SEA_mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 -#define SEA_mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 -#define SEA_mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 -#define SEA_mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 -#define SEA_mmOVL_SURFACE_OFFSET_Y 0x1a24 -#define SEA_mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 -#define SEA_mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24 -#define SEA_mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 -#define SEA_mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 -#define SEA_mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 -#define SEA_mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 -#define SEA_mmOVL_START 0x1a25 -#define SEA_mmDCP0_OVL_START 0x1a25 -#define SEA_mmDCP1_OVL_START 0x1d25 -#define SEA_mmDCP2_OVL_START 0x4025 -#define SEA_mmDCP3_OVL_START 0x4325 -#define SEA_mmDCP4_OVL_START 0x4625 -#define SEA_mmDCP5_OVL_START 0x4925 -#define SEA_mmOVL_END 0x1a26 -#define SEA_mmDCP0_OVL_END 0x1a26 -#define SEA_mmDCP1_OVL_END 0x1d26 -#define SEA_mmDCP2_OVL_END 0x4026 -#define SEA_mmDCP3_OVL_END 0x4326 -#define SEA_mmDCP4_OVL_END 0x4626 -#define SEA_mmDCP5_OVL_END 0x4926 -#define SEA_mmOVL_UPDATE 0x1a27 -#define SEA_mmDCP0_OVL_UPDATE 0x1a27 -#define SEA_mmDCP1_OVL_UPDATE 0x1d27 -#define SEA_mmDCP2_OVL_UPDATE 0x4027 -#define SEA_mmDCP3_OVL_UPDATE 0x4327 -#define SEA_mmDCP4_OVL_UPDATE 0x4627 -#define SEA_mmDCP5_OVL_UPDATE 0x4927 -#define SEA_mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 -#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 -#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28 -#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 -#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 -#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 -#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 -#define SEA_mmOVL_DFQ_CONTROL 0x1a29 -#define SEA_mmDCP0_OVL_DFQ_CONTROL 0x1a29 -#define SEA_mmDCP1_OVL_DFQ_CONTROL 0x1d29 -#define SEA_mmDCP2_OVL_DFQ_CONTROL 0x4029 -#define SEA_mmDCP3_OVL_DFQ_CONTROL 0x4329 -#define SEA_mmDCP4_OVL_DFQ_CONTROL 0x4629 -#define SEA_mmDCP5_OVL_DFQ_CONTROL 0x4929 -#define SEA_mmOVL_DFQ_STATUS 0x1a2a -#define SEA_mmDCP0_OVL_DFQ_STATUS 0x1a2a -#define SEA_mmDCP1_OVL_DFQ_STATUS 0x1d2a -#define SEA_mmDCP2_OVL_DFQ_STATUS 0x402a -#define SEA_mmDCP3_OVL_DFQ_STATUS 0x432a -#define SEA_mmDCP4_OVL_DFQ_STATUS 0x462a -#define SEA_mmDCP5_OVL_DFQ_STATUS 0x492a -#define SEA_mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b -#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b -#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b -#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b -#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b -#define SEA_mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c -#define SEA_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c -#define SEA_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c -#define SEA_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c -#define SEA_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c -#define SEA_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c -#define SEA_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c -#define SEA_mmPRESCALE_GRPH_CONTROL 0x1a2d -#define SEA_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d -#define SEA_mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d -#define SEA_mmDCP2_PRESCALE_GRPH_CONTROL 0x402d -#define SEA_mmDCP3_PRESCALE_GRPH_CONTROL 0x432d -#define SEA_mmDCP4_PRESCALE_GRPH_CONTROL 0x462d -#define SEA_mmDCP5_PRESCALE_GRPH_CONTROL 0x492d -#define SEA_mmPRESCALE_VALUES_GRPH_R 0x1a2e -#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e -#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e -#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e -#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e -#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e -#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e -#define SEA_mmPRESCALE_VALUES_GRPH_G 0x1a2f -#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f -#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f -#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f -#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f -#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f -#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f -#define SEA_mmPRESCALE_VALUES_GRPH_B 0x1a30 -#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 -#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30 -#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 -#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 -#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 -#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 -#define SEA_mmPRESCALE_OVL_CONTROL 0x1a31 -#define SEA_mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 -#define SEA_mmDCP1_PRESCALE_OVL_CONTROL 0x1d31 -#define SEA_mmDCP2_PRESCALE_OVL_CONTROL 0x4031 -#define SEA_mmDCP3_PRESCALE_OVL_CONTROL 0x4331 -#define SEA_mmDCP4_PRESCALE_OVL_CONTROL 0x4631 -#define SEA_mmDCP5_PRESCALE_OVL_CONTROL 0x4931 -#define SEA_mmPRESCALE_VALUES_OVL_CB 0x1a32 -#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 -#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32 -#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 -#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 -#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 -#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 -#define SEA_mmPRESCALE_VALUES_OVL_Y 0x1a33 -#define SEA_mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 -#define SEA_mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33 -#define SEA_mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 -#define SEA_mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 -#define SEA_mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 -#define SEA_mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 -#define SEA_mmPRESCALE_VALUES_OVL_CR 0x1a34 -#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 -#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34 -#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 -#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 -#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 -#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 -#define SEA_mmINPUT_CSC_CONTROL 0x1a35 -#define SEA_mmDCP0_INPUT_CSC_CONTROL 0x1a35 -#define SEA_mmDCP1_INPUT_CSC_CONTROL 0x1d35 -#define SEA_mmDCP2_INPUT_CSC_CONTROL 0x4035 -#define SEA_mmDCP3_INPUT_CSC_CONTROL 0x4335 -#define SEA_mmDCP4_INPUT_CSC_CONTROL 0x4635 -#define SEA_mmDCP5_INPUT_CSC_CONTROL 0x4935 -#define SEA_mmINPUT_CSC_C11_C12 0x1a36 -#define SEA_mmDCP0_INPUT_CSC_C11_C12 0x1a36 -#define SEA_mmDCP1_INPUT_CSC_C11_C12 0x1d36 -#define SEA_mmDCP2_INPUT_CSC_C11_C12 0x4036 -#define SEA_mmDCP3_INPUT_CSC_C11_C12 0x4336 -#define SEA_mmDCP4_INPUT_CSC_C11_C12 0x4636 -#define SEA_mmDCP5_INPUT_CSC_C11_C12 0x4936 -#define SEA_mmINPUT_CSC_C13_C14 0x1a37 -#define SEA_mmDCP0_INPUT_CSC_C13_C14 0x1a37 -#define SEA_mmDCP1_INPUT_CSC_C13_C14 0x1d37 -#define SEA_mmDCP2_INPUT_CSC_C13_C14 0x4037 -#define SEA_mmDCP3_INPUT_CSC_C13_C14 0x4337 -#define SEA_mmDCP4_INPUT_CSC_C13_C14 0x4637 -#define SEA_mmDCP5_INPUT_CSC_C13_C14 0x4937 -#define SEA_mmINPUT_CSC_C21_C22 0x1a38 -#define SEA_mmDCP0_INPUT_CSC_C21_C22 0x1a38 -#define SEA_mmDCP1_INPUT_CSC_C21_C22 0x1d38 -#define SEA_mmDCP2_INPUT_CSC_C21_C22 0x4038 -#define SEA_mmDCP3_INPUT_CSC_C21_C22 0x4338 -#define SEA_mmDCP4_INPUT_CSC_C21_C22 0x4638 -#define SEA_mmDCP5_INPUT_CSC_C21_C22 0x4938 -#define SEA_mmINPUT_CSC_C23_C24 0x1a39 -#define SEA_mmDCP0_INPUT_CSC_C23_C24 0x1a39 -#define SEA_mmDCP1_INPUT_CSC_C23_C24 0x1d39 -#define SEA_mmDCP2_INPUT_CSC_C23_C24 0x4039 -#define SEA_mmDCP3_INPUT_CSC_C23_C24 0x4339 -#define SEA_mmDCP4_INPUT_CSC_C23_C24 0x4639 -#define SEA_mmDCP5_INPUT_CSC_C23_C24 0x4939 -#define SEA_mmINPUT_CSC_C31_C32 0x1a3a -#define SEA_mmDCP0_INPUT_CSC_C31_C32 0x1a3a -#define SEA_mmDCP1_INPUT_CSC_C31_C32 0x1d3a -#define SEA_mmDCP2_INPUT_CSC_C31_C32 0x403a -#define SEA_mmDCP3_INPUT_CSC_C31_C32 0x433a -#define SEA_mmDCP4_INPUT_CSC_C31_C32 0x463a -#define SEA_mmDCP5_INPUT_CSC_C31_C32 0x493a -#define SEA_mmINPUT_CSC_C33_C34 0x1a3b -#define SEA_mmDCP0_INPUT_CSC_C33_C34 0x1a3b -#define SEA_mmDCP1_INPUT_CSC_C33_C34 0x1d3b -#define SEA_mmDCP2_INPUT_CSC_C33_C34 0x403b -#define SEA_mmDCP3_INPUT_CSC_C33_C34 0x433b -#define SEA_mmDCP4_INPUT_CSC_C33_C34 0x463b -#define SEA_mmDCP5_INPUT_CSC_C33_C34 0x493b -#define SEA_mmOUTPUT_CSC_CONTROL 0x1a3c -#define SEA_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c -#define SEA_mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c -#define SEA_mmDCP2_OUTPUT_CSC_CONTROL 0x403c -#define SEA_mmDCP3_OUTPUT_CSC_CONTROL 0x433c -#define SEA_mmDCP4_OUTPUT_CSC_CONTROL 0x463c -#define SEA_mmDCP5_OUTPUT_CSC_CONTROL 0x493c -#define SEA_mmOUTPUT_CSC_C11_C12 0x1a3d -#define SEA_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d -#define SEA_mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d -#define SEA_mmDCP2_OUTPUT_CSC_C11_C12 0x403d -#define SEA_mmDCP3_OUTPUT_CSC_C11_C12 0x433d -#define SEA_mmDCP4_OUTPUT_CSC_C11_C12 0x463d -#define SEA_mmDCP5_OUTPUT_CSC_C11_C12 0x493d -#define SEA_mmOUTPUT_CSC_C13_C14 0x1a3e -#define SEA_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e -#define SEA_mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e -#define SEA_mmDCP2_OUTPUT_CSC_C13_C14 0x403e -#define SEA_mmDCP3_OUTPUT_CSC_C13_C14 0x433e -#define SEA_mmDCP4_OUTPUT_CSC_C13_C14 0x463e -#define SEA_mmDCP5_OUTPUT_CSC_C13_C14 0x493e -#define SEA_mmOUTPUT_CSC_C21_C22 0x1a3f -#define SEA_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f -#define SEA_mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f -#define SEA_mmDCP2_OUTPUT_CSC_C21_C22 0x403f -#define SEA_mmDCP3_OUTPUT_CSC_C21_C22 0x433f -#define SEA_mmDCP4_OUTPUT_CSC_C21_C22 0x463f -#define SEA_mmDCP5_OUTPUT_CSC_C21_C22 0x493f -#define SEA_mmOUTPUT_CSC_C23_C24 0x1a40 -#define SEA_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 -#define SEA_mmDCP1_OUTPUT_CSC_C23_C24 0x1d40 -#define SEA_mmDCP2_OUTPUT_CSC_C23_C24 0x4040 -#define SEA_mmDCP3_OUTPUT_CSC_C23_C24 0x4340 -#define SEA_mmDCP4_OUTPUT_CSC_C23_C24 0x4640 -#define SEA_mmDCP5_OUTPUT_CSC_C23_C24 0x4940 -#define SEA_mmOUTPUT_CSC_C31_C32 0x1a41 -#define SEA_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 -#define SEA_mmDCP1_OUTPUT_CSC_C31_C32 0x1d41 -#define SEA_mmDCP2_OUTPUT_CSC_C31_C32 0x4041 -#define SEA_mmDCP3_OUTPUT_CSC_C31_C32 0x4341 -#define SEA_mmDCP4_OUTPUT_CSC_C31_C32 0x4641 -#define SEA_mmDCP5_OUTPUT_CSC_C31_C32 0x4941 -#define SEA_mmOUTPUT_CSC_C33_C34 0x1a42 -#define SEA_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 -#define SEA_mmDCP1_OUTPUT_CSC_C33_C34 0x1d42 -#define SEA_mmDCP2_OUTPUT_CSC_C33_C34 0x4042 -#define SEA_mmDCP3_OUTPUT_CSC_C33_C34 0x4342 -#define SEA_mmDCP4_OUTPUT_CSC_C33_C34 0x4642 -#define SEA_mmDCP5_OUTPUT_CSC_C33_C34 0x4942 -#define SEA_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 -#define SEA_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 -#define SEA_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 -#define SEA_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 -#define SEA_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 -#define SEA_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48 -#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 -#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 -#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 -#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 -#define SEA_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49 -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 -#define SEA_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a -#define SEA_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b -#define SEA_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c -#define SEA_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d -#define SEA_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e -#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e -#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e -#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e -#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e -#define SEA_mmDENORM_CONTROL 0x1a50 -#define SEA_mmDCP0_DENORM_CONTROL 0x1a50 -#define SEA_mmDCP1_DENORM_CONTROL 0x1d50 -#define SEA_mmDCP2_DENORM_CONTROL 0x4050 -#define SEA_mmDCP3_DENORM_CONTROL 0x4350 -#define SEA_mmDCP4_DENORM_CONTROL 0x4650 -#define SEA_mmDCP5_DENORM_CONTROL 0x4950 -#define SEA_mmOUT_ROUND_CONTROL 0x1a51 -#define SEA_mmDCP0_OUT_ROUND_CONTROL 0x1a51 -#define SEA_mmDCP1_OUT_ROUND_CONTROL 0x1d51 -#define SEA_mmDCP2_OUT_ROUND_CONTROL 0x4051 -#define SEA_mmDCP3_OUT_ROUND_CONTROL 0x4351 -#define SEA_mmDCP4_OUT_ROUND_CONTROL 0x4651 -#define SEA_mmDCP5_OUT_ROUND_CONTROL 0x4951 -#define SEA_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 -#define SEA_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 -#define SEA_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52 -#define SEA_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052 -#define SEA_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352 -#define SEA_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652 -#define SEA_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952 -#define SEA_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c -#define SEA_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c -#define SEA_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c -#define SEA_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c -#define SEA_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c -#define SEA_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c -#define SEA_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c -#define SEA_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d -#define SEA_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d -#define SEA_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d -#define SEA_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d -#define SEA_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d -#define SEA_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d -#define SEA_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d -#define SEA_mmKEY_CONTROL 0x1a53 -#define SEA_mmDCP0_KEY_CONTROL 0x1a53 -#define SEA_mmDCP1_KEY_CONTROL 0x1d53 -#define SEA_mmDCP2_KEY_CONTROL 0x4053 -#define SEA_mmDCP3_KEY_CONTROL 0x4353 -#define SEA_mmDCP4_KEY_CONTROL 0x4653 -#define SEA_mmDCP5_KEY_CONTROL 0x4953 -#define SEA_mmKEY_RANGE_ALPHA 0x1a54 -#define SEA_mmDCP0_KEY_RANGE_ALPHA 0x1a54 -#define SEA_mmDCP1_KEY_RANGE_ALPHA 0x1d54 -#define SEA_mmDCP2_KEY_RANGE_ALPHA 0x4054 -#define SEA_mmDCP3_KEY_RANGE_ALPHA 0x4354 -#define SEA_mmDCP4_KEY_RANGE_ALPHA 0x4654 -#define SEA_mmDCP5_KEY_RANGE_ALPHA 0x4954 -#define SEA_mmKEY_RANGE_RED 0x1a55 -#define SEA_mmDCP0_KEY_RANGE_RED 0x1a55 -#define SEA_mmDCP1_KEY_RANGE_RED 0x1d55 -#define SEA_mmDCP2_KEY_RANGE_RED 0x4055 -#define SEA_mmDCP3_KEY_RANGE_RED 0x4355 -#define SEA_mmDCP4_KEY_RANGE_RED 0x4655 -#define SEA_mmDCP5_KEY_RANGE_RED 0x4955 -#define SEA_mmKEY_RANGE_GREEN 0x1a56 -#define SEA_mmDCP0_KEY_RANGE_GREEN 0x1a56 -#define SEA_mmDCP1_KEY_RANGE_GREEN 0x1d56 -#define SEA_mmDCP2_KEY_RANGE_GREEN 0x4056 -#define SEA_mmDCP3_KEY_RANGE_GREEN 0x4356 -#define SEA_mmDCP4_KEY_RANGE_GREEN 0x4656 -#define SEA_mmDCP5_KEY_RANGE_GREEN 0x4956 -#define SEA_mmKEY_RANGE_BLUE 0x1a57 -#define SEA_mmDCP0_KEY_RANGE_BLUE 0x1a57 -#define SEA_mmDCP1_KEY_RANGE_BLUE 0x1d57 -#define SEA_mmDCP2_KEY_RANGE_BLUE 0x4057 -#define SEA_mmDCP3_KEY_RANGE_BLUE 0x4357 -#define SEA_mmDCP4_KEY_RANGE_BLUE 0x4657 -#define SEA_mmDCP5_KEY_RANGE_BLUE 0x4957 -#define SEA_mmDEGAMMA_CONTROL 0x1a58 -#define SEA_mmDCP0_DEGAMMA_CONTROL 0x1a58 -#define SEA_mmDCP1_DEGAMMA_CONTROL 0x1d58 -#define SEA_mmDCP2_DEGAMMA_CONTROL 0x4058 -#define SEA_mmDCP3_DEGAMMA_CONTROL 0x4358 -#define SEA_mmDCP4_DEGAMMA_CONTROL 0x4658 -#define SEA_mmDCP5_DEGAMMA_CONTROL 0x4958 -#define SEA_mmGAMUT_REMAP_CONTROL 0x1a59 -#define SEA_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 -#define SEA_mmDCP1_GAMUT_REMAP_CONTROL 0x1d59 -#define SEA_mmDCP2_GAMUT_REMAP_CONTROL 0x4059 -#define SEA_mmDCP3_GAMUT_REMAP_CONTROL 0x4359 -#define SEA_mmDCP4_GAMUT_REMAP_CONTROL 0x4659 -#define SEA_mmDCP5_GAMUT_REMAP_CONTROL 0x4959 -#define SEA_mmGAMUT_REMAP_C11_C12 0x1a5a -#define SEA_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a -#define SEA_mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a -#define SEA_mmDCP2_GAMUT_REMAP_C11_C12 0x405a -#define SEA_mmDCP3_GAMUT_REMAP_C11_C12 0x435a -#define SEA_mmDCP4_GAMUT_REMAP_C11_C12 0x465a -#define SEA_mmDCP5_GAMUT_REMAP_C11_C12 0x495a -#define SEA_mmGAMUT_REMAP_C13_C14 0x1a5b -#define SEA_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b -#define SEA_mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b -#define SEA_mmDCP2_GAMUT_REMAP_C13_C14 0x405b -#define SEA_mmDCP3_GAMUT_REMAP_C13_C14 0x435b -#define SEA_mmDCP4_GAMUT_REMAP_C13_C14 0x465b -#define SEA_mmDCP5_GAMUT_REMAP_C13_C14 0x495b -#define SEA_mmGAMUT_REMAP_C21_C22 0x1a5c -#define SEA_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c -#define SEA_mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c -#define SEA_mmDCP2_GAMUT_REMAP_C21_C22 0x405c -#define SEA_mmDCP3_GAMUT_REMAP_C21_C22 0x435c -#define SEA_mmDCP4_GAMUT_REMAP_C21_C22 0x465c -#define SEA_mmDCP5_GAMUT_REMAP_C21_C22 0x495c -#define SEA_mmGAMUT_REMAP_C23_C24 0x1a5d -#define SEA_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d -#define SEA_mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d -#define SEA_mmDCP2_GAMUT_REMAP_C23_C24 0x405d -#define SEA_mmDCP3_GAMUT_REMAP_C23_C24 0x435d -#define SEA_mmDCP4_GAMUT_REMAP_C23_C24 0x465d -#define SEA_mmDCP5_GAMUT_REMAP_C23_C24 0x495d -#define SEA_mmGAMUT_REMAP_C31_C32 0x1a5e -#define SEA_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e -#define SEA_mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e -#define SEA_mmDCP2_GAMUT_REMAP_C31_C32 0x405e -#define SEA_mmDCP3_GAMUT_REMAP_C31_C32 0x435e -#define SEA_mmDCP4_GAMUT_REMAP_C31_C32 0x465e -#define SEA_mmDCP5_GAMUT_REMAP_C31_C32 0x495e -#define SEA_mmGAMUT_REMAP_C33_C34 0x1a5f -#define SEA_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f -#define SEA_mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f -#define SEA_mmDCP2_GAMUT_REMAP_C33_C34 0x405f -#define SEA_mmDCP3_GAMUT_REMAP_C33_C34 0x435f -#define SEA_mmDCP4_GAMUT_REMAP_C33_C34 0x465f -#define SEA_mmDCP5_GAMUT_REMAP_C33_C34 0x495f -#define SEA_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 -#define SEA_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 -#define SEA_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60 -#define SEA_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 -#define SEA_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 -#define SEA_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 -#define SEA_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 -#define SEA_mmDCP_RANDOM_SEEDS 0x1a61 -#define SEA_mmDCP0_DCP_RANDOM_SEEDS 0x1a61 -#define SEA_mmDCP1_DCP_RANDOM_SEEDS 0x1d61 -#define SEA_mmDCP2_DCP_RANDOM_SEEDS 0x4061 -#define SEA_mmDCP3_DCP_RANDOM_SEEDS 0x4361 -#define SEA_mmDCP4_DCP_RANDOM_SEEDS 0x4661 -#define SEA_mmDCP5_DCP_RANDOM_SEEDS 0x4961 -#define SEA_mmDCP_FP_CONVERTED_FIELD 0x1a65 -#define SEA_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 -#define SEA_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65 -#define SEA_mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 -#define SEA_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 -#define SEA_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 -#define SEA_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 -#define SEA_mmCUR_CONTROL 0x1a66 -#define SEA_mmDCP0_CUR_CONTROL 0x1a66 -#define SEA_mmDCP1_CUR_CONTROL 0x1d66 -#define SEA_mmDCP2_CUR_CONTROL 0x4066 -#define SEA_mmDCP3_CUR_CONTROL 0x4366 -#define SEA_mmDCP4_CUR_CONTROL 0x4666 -#define SEA_mmDCP5_CUR_CONTROL 0x4966 -#define SEA_mmCUR_SURFACE_ADDRESS 0x1a67 -#define SEA_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 -#define SEA_mmDCP1_CUR_SURFACE_ADDRESS 0x1d67 -#define SEA_mmDCP2_CUR_SURFACE_ADDRESS 0x4067 -#define SEA_mmDCP3_CUR_SURFACE_ADDRESS 0x4367 -#define SEA_mmDCP4_CUR_SURFACE_ADDRESS 0x4667 -#define SEA_mmDCP5_CUR_SURFACE_ADDRESS 0x4967 -#define SEA_mmCUR_SIZE 0x1a68 -#define SEA_mmDCP0_CUR_SIZE 0x1a68 -#define SEA_mmDCP1_CUR_SIZE 0x1d68 -#define SEA_mmDCP2_CUR_SIZE 0x4068 -#define SEA_mmDCP3_CUR_SIZE 0x4368 -#define SEA_mmDCP4_CUR_SIZE 0x4668 -#define SEA_mmDCP5_CUR_SIZE 0x4968 -#define SEA_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define SEA_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define SEA_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69 -#define SEA_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 -#define SEA_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 -#define SEA_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 -#define SEA_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 -#define SEA_mmCUR_POSITION 0x1a6a -#define SEA_mmDCP0_CUR_POSITION 0x1a6a -#define SEA_mmDCP1_CUR_POSITION 0x1d6a -#define SEA_mmDCP2_CUR_POSITION 0x406a -#define SEA_mmDCP3_CUR_POSITION 0x436a -#define SEA_mmDCP4_CUR_POSITION 0x466a -#define SEA_mmDCP5_CUR_POSITION 0x496a -#define SEA_mmCUR_HOT_SPOT 0x1a6b -#define SEA_mmDCP0_CUR_HOT_SPOT 0x1a6b -#define SEA_mmDCP1_CUR_HOT_SPOT 0x1d6b -#define SEA_mmDCP2_CUR_HOT_SPOT 0x406b -#define SEA_mmDCP3_CUR_HOT_SPOT 0x436b -#define SEA_mmDCP4_CUR_HOT_SPOT 0x466b -#define SEA_mmDCP5_CUR_HOT_SPOT 0x496b -#define SEA_mmCUR_COLOR1 0x1a6c -#define SEA_mmDCP0_CUR_COLOR1 0x1a6c -#define SEA_mmDCP1_CUR_COLOR1 0x1d6c -#define SEA_mmDCP2_CUR_COLOR1 0x406c -#define SEA_mmDCP3_CUR_COLOR1 0x436c -#define SEA_mmDCP4_CUR_COLOR1 0x466c -#define SEA_mmDCP5_CUR_COLOR1 0x496c -#define SEA_mmCUR_COLOR2 0x1a6d -#define SEA_mmDCP0_CUR_COLOR2 0x1a6d -#define SEA_mmDCP1_CUR_COLOR2 0x1d6d -#define SEA_mmDCP2_CUR_COLOR2 0x406d -#define SEA_mmDCP3_CUR_COLOR2 0x436d -#define SEA_mmDCP4_CUR_COLOR2 0x466d -#define SEA_mmDCP5_CUR_COLOR2 0x496d -#define SEA_mmCUR_UPDATE 0x1a6e -#define SEA_mmDCP0_CUR_UPDATE 0x1a6e -#define SEA_mmDCP1_CUR_UPDATE 0x1d6e -#define SEA_mmDCP2_CUR_UPDATE 0x406e -#define SEA_mmDCP3_CUR_UPDATE 0x436e -#define SEA_mmDCP4_CUR_UPDATE 0x466e -#define SEA_mmDCP5_CUR_UPDATE 0x496e -#define SEA_mmCUR2_CONTROL 0x1a6f -#define SEA_mmDCP0_CUR2_CONTROL 0x1a6f -#define SEA_mmDCP1_CUR2_CONTROL 0x1d6f -#define SEA_mmDCP2_CUR2_CONTROL 0x406f -#define SEA_mmDCP3_CUR2_CONTROL 0x436f -#define SEA_mmDCP4_CUR2_CONTROL 0x466f -#define SEA_mmDCP5_CUR2_CONTROL 0x496f -#define SEA_mmCUR2_SURFACE_ADDRESS 0x1a70 -#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70 -#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70 -#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS 0x4070 -#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS 0x4370 -#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS 0x4670 -#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS 0x4970 -#define SEA_mmCUR2_SIZE 0x1a71 -#define SEA_mmDCP0_CUR2_SIZE 0x1a71 -#define SEA_mmDCP1_CUR2_SIZE 0x1d71 -#define SEA_mmDCP2_CUR2_SIZE 0x4071 -#define SEA_mmDCP3_CUR2_SIZE 0x4371 -#define SEA_mmDCP4_CUR2_SIZE 0x4671 -#define SEA_mmDCP5_CUR2_SIZE 0x4971 -#define SEA_mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72 -#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72 -#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72 -#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072 -#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372 -#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672 -#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972 -#define SEA_mmCUR2_POSITION 0x1a73 -#define SEA_mmDCP0_CUR2_POSITION 0x1a73 -#define SEA_mmDCP1_CUR2_POSITION 0x1d73 -#define SEA_mmDCP2_CUR2_POSITION 0x4073 -#define SEA_mmDCP3_CUR2_POSITION 0x4373 -#define SEA_mmDCP4_CUR2_POSITION 0x4673 -#define SEA_mmDCP5_CUR2_POSITION 0x4973 -#define SEA_mmCUR2_HOT_SPOT 0x1a74 -#define SEA_mmDCP0_CUR2_HOT_SPOT 0x1a74 -#define SEA_mmDCP1_CUR2_HOT_SPOT 0x1d74 -#define SEA_mmDCP2_CUR2_HOT_SPOT 0x4074 -#define SEA_mmDCP3_CUR2_HOT_SPOT 0x4374 -#define SEA_mmDCP4_CUR2_HOT_SPOT 0x4674 -#define SEA_mmDCP5_CUR2_HOT_SPOT 0x4974 -#define SEA_mmCUR2_COLOR1 0x1a75 -#define SEA_mmDCP0_CUR2_COLOR1 0x1a75 -#define SEA_mmDCP1_CUR2_COLOR1 0x1d75 -#define SEA_mmDCP2_CUR2_COLOR1 0x4075 -#define SEA_mmDCP3_CUR2_COLOR1 0x4375 -#define SEA_mmDCP4_CUR2_COLOR1 0x4675 -#define SEA_mmDCP5_CUR2_COLOR1 0x4975 -#define SEA_mmCUR2_COLOR2 0x1a76 -#define SEA_mmDCP0_CUR2_COLOR2 0x1a76 -#define SEA_mmDCP1_CUR2_COLOR2 0x1d76 -#define SEA_mmDCP2_CUR2_COLOR2 0x4076 -#define SEA_mmDCP3_CUR2_COLOR2 0x4376 -#define SEA_mmDCP4_CUR2_COLOR2 0x4676 -#define SEA_mmDCP5_CUR2_COLOR2 0x4976 -#define SEA_mmCUR2_UPDATE 0x1a77 -#define SEA_mmDCP0_CUR2_UPDATE 0x1a77 -#define SEA_mmDCP1_CUR2_UPDATE 0x1d77 -#define SEA_mmDCP2_CUR2_UPDATE 0x4077 -#define SEA_mmDCP3_CUR2_UPDATE 0x4377 -#define SEA_mmDCP4_CUR2_UPDATE 0x4677 -#define SEA_mmDCP5_CUR2_UPDATE 0x4977 -#define SEA_mmCUR_REQUEST_FILTER_CNTL 0x1a99 -#define SEA_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 -#define SEA_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99 -#define SEA_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 -#define SEA_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 -#define SEA_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 -#define SEA_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 -#define SEA_mmCUR_STEREO_CONTROL 0x1a9a -#define SEA_mmDCP0_CUR_STEREO_CONTROL 0x1a9a -#define SEA_mmDCP1_CUR_STEREO_CONTROL 0x1d9a -#define SEA_mmDCP2_CUR_STEREO_CONTROL 0x409a -#define SEA_mmDCP3_CUR_STEREO_CONTROL 0x439a -#define SEA_mmDCP4_CUR_STEREO_CONTROL 0x469a -#define SEA_mmDCP5_CUR_STEREO_CONTROL 0x499a -#define SEA_mmCUR2_STEREO_CONTROL 0x1a9b -#define SEA_mmDCP0_CUR2_STEREO_CONTROL 0x1a9b -#define SEA_mmDCP1_CUR2_STEREO_CONTROL 0x1d9b -#define SEA_mmDCP2_CUR2_STEREO_CONTROL 0x409b -#define SEA_mmDCP3_CUR2_STEREO_CONTROL 0x439b -#define SEA_mmDCP4_CUR2_STEREO_CONTROL 0x469b -#define SEA_mmDCP5_CUR2_STEREO_CONTROL 0x499b -#define SEA_mmDC_LUT_RW_MODE 0x1a78 -#define SEA_mmDCP0_DC_LUT_RW_MODE 0x1a78 -#define SEA_mmDCP1_DC_LUT_RW_MODE 0x1d78 -#define SEA_mmDCP2_DC_LUT_RW_MODE 0x4078 -#define SEA_mmDCP3_DC_LUT_RW_MODE 0x4378 -#define SEA_mmDCP4_DC_LUT_RW_MODE 0x4678 -#define SEA_mmDCP5_DC_LUT_RW_MODE 0x4978 -#define SEA_mmDC_LUT_RW_INDEX 0x1a79 -#define SEA_mmDCP0_DC_LUT_RW_INDEX 0x1a79 -#define SEA_mmDCP1_DC_LUT_RW_INDEX 0x1d79 -#define SEA_mmDCP2_DC_LUT_RW_INDEX 0x4079 -#define SEA_mmDCP3_DC_LUT_RW_INDEX 0x4379 -#define SEA_mmDCP4_DC_LUT_RW_INDEX 0x4679 -#define SEA_mmDCP5_DC_LUT_RW_INDEX 0x4979 -#define SEA_mmDC_LUT_SEQ_COLOR 0x1a7a -#define SEA_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a -#define SEA_mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a -#define SEA_mmDCP2_DC_LUT_SEQ_COLOR 0x407a -#define SEA_mmDCP3_DC_LUT_SEQ_COLOR 0x437a -#define SEA_mmDCP4_DC_LUT_SEQ_COLOR 0x467a -#define SEA_mmDCP5_DC_LUT_SEQ_COLOR 0x497a -#define SEA_mmDC_LUT_PWL_DATA 0x1a7b -#define SEA_mmDCP0_DC_LUT_PWL_DATA 0x1a7b -#define SEA_mmDCP1_DC_LUT_PWL_DATA 0x1d7b -#define SEA_mmDCP2_DC_LUT_PWL_DATA 0x407b -#define SEA_mmDCP3_DC_LUT_PWL_DATA 0x437b -#define SEA_mmDCP4_DC_LUT_PWL_DATA 0x467b -#define SEA_mmDCP5_DC_LUT_PWL_DATA 0x497b -#define SEA_mmDC_LUT_30_COLOR 0x1a7c -#define SEA_mmDCP0_DC_LUT_30_COLOR 0x1a7c -#define SEA_mmDCP1_DC_LUT_30_COLOR 0x1d7c -#define SEA_mmDCP2_DC_LUT_30_COLOR 0x407c -#define SEA_mmDCP3_DC_LUT_30_COLOR 0x437c -#define SEA_mmDCP4_DC_LUT_30_COLOR 0x467c -#define SEA_mmDCP5_DC_LUT_30_COLOR 0x497c -#define SEA_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define SEA_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define SEA_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d -#define SEA_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d -#define SEA_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d -#define SEA_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d -#define SEA_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d -#define SEA_mmDC_LUT_WRITE_EN_MASK 0x1a7e -#define SEA_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e -#define SEA_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e -#define SEA_mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e -#define SEA_mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e -#define SEA_mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e -#define SEA_mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e -#define SEA_mmDC_LUT_AUTOFILL 0x1a7f -#define SEA_mmDCP0_DC_LUT_AUTOFILL 0x1a7f -#define SEA_mmDCP1_DC_LUT_AUTOFILL 0x1d7f -#define SEA_mmDCP2_DC_LUT_AUTOFILL 0x407f -#define SEA_mmDCP3_DC_LUT_AUTOFILL 0x437f -#define SEA_mmDCP4_DC_LUT_AUTOFILL 0x467f -#define SEA_mmDCP5_DC_LUT_AUTOFILL 0x497f -#define SEA_mmDC_LUT_CONTROL 0x1a80 -#define SEA_mmDCP0_DC_LUT_CONTROL 0x1a80 -#define SEA_mmDCP1_DC_LUT_CONTROL 0x1d80 -#define SEA_mmDCP2_DC_LUT_CONTROL 0x4080 -#define SEA_mmDCP3_DC_LUT_CONTROL 0x4380 -#define SEA_mmDCP4_DC_LUT_CONTROL 0x4680 -#define SEA_mmDCP5_DC_LUT_CONTROL 0x4980 -#define SEA_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81 -#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 -#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 -#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 -#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 -#define SEA_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82 -#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 -#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 -#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 -#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 -#define SEA_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 -#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 -#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83 -#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 -#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 -#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 -#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 -#define SEA_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84 -#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 -#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 -#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 -#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 -#define SEA_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85 -#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 -#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 -#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 -#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 -#define SEA_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 -#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 -#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86 -#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 -#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 -#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 -#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 -#define SEA_mmDCP_CRC_CONTROL 0x1a87 -#define SEA_mmDCP0_DCP_CRC_CONTROL 0x1a87 -#define SEA_mmDCP1_DCP_CRC_CONTROL 0x1d87 -#define SEA_mmDCP2_DCP_CRC_CONTROL 0x4087 -#define SEA_mmDCP3_DCP_CRC_CONTROL 0x4387 -#define SEA_mmDCP4_DCP_CRC_CONTROL 0x4687 -#define SEA_mmDCP5_DCP_CRC_CONTROL 0x4987 -#define SEA_mmDCP_CRC_MASK 0x1a88 -#define SEA_mmDCP0_DCP_CRC_MASK 0x1a88 -#define SEA_mmDCP1_DCP_CRC_MASK 0x1d88 -#define SEA_mmDCP2_DCP_CRC_MASK 0x4088 -#define SEA_mmDCP3_DCP_CRC_MASK 0x4388 -#define SEA_mmDCP4_DCP_CRC_MASK 0x4688 -#define SEA_mmDCP5_DCP_CRC_MASK 0x4988 -#define SEA_mmDCP_CRC_CURRENT 0x1a89 -#define SEA_mmDCP0_DCP_CRC_CURRENT 0x1a89 -#define SEA_mmDCP1_DCP_CRC_CURRENT 0x1d89 -#define SEA_mmDCP2_DCP_CRC_CURRENT 0x4089 -#define SEA_mmDCP3_DCP_CRC_CURRENT 0x4389 -#define SEA_mmDCP4_DCP_CRC_CURRENT 0x4689 -#define SEA_mmDCP5_DCP_CRC_CURRENT 0x4989 -#define SEA_mmDCP_CRC_LAST 0x1a8b -#define SEA_mmDCP0_DCP_CRC_LAST 0x1a8b -#define SEA_mmDCP1_DCP_CRC_LAST 0x1d8b -#define SEA_mmDCP2_DCP_CRC_LAST 0x408b -#define SEA_mmDCP3_DCP_CRC_LAST 0x438b -#define SEA_mmDCP4_DCP_CRC_LAST 0x468b -#define SEA_mmDCP5_DCP_CRC_LAST 0x498b -#define SEA_mmDCP_DEBUG 0x1a8d -#define SEA_mmDCP0_DCP_DEBUG 0x1a8d -#define SEA_mmDCP1_DCP_DEBUG 0x1d8d -#define SEA_mmDCP2_DCP_DEBUG 0x408d -#define SEA_mmDCP3_DCP_DEBUG 0x438d -#define SEA_mmDCP4_DCP_DEBUG 0x468d -#define SEA_mmDCP5_DCP_DEBUG 0x498d -#define SEA_mmGRPH_FLIP_RATE_CNTL 0x1a8e -#define SEA_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e -#define SEA_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e -#define SEA_mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e -#define SEA_mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e -#define SEA_mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e -#define SEA_mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e -#define SEA_mmDCP_GSL_CONTROL 0x1a90 -#define SEA_mmDCP0_DCP_GSL_CONTROL 0x1a90 -#define SEA_mmDCP1_DCP_GSL_CONTROL 0x1d90 -#define SEA_mmDCP2_DCP_GSL_CONTROL 0x4090 -#define SEA_mmDCP3_DCP_GSL_CONTROL 0x4390 -#define SEA_mmDCP4_DCP_GSL_CONTROL 0x4690 -#define SEA_mmDCP5_DCP_GSL_CONTROL 0x4990 -#define SEA_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define SEA_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define SEA_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91 -#define SEA_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 -#define SEA_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 -#define SEA_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 -#define SEA_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 -#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92 -#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 -#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 -#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 -#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 -#define SEA_mmOVL_STEREOSYNC_FLIP 0x1a93 -#define SEA_mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 -#define SEA_mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93 -#define SEA_mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 -#define SEA_mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 -#define SEA_mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 -#define SEA_mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 -#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94 -#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 -#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 -#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 -#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 -#define SEA_mmDCP_TEST_DEBUG_INDEX 0x1a95 -#define SEA_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 -#define SEA_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95 -#define SEA_mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 -#define SEA_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 -#define SEA_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 -#define SEA_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 -#define SEA_mmDCP_TEST_DEBUG_DATA 0x1a96 -#define SEA_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 -#define SEA_mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96 -#define SEA_mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 -#define SEA_mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 -#define SEA_mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 -#define SEA_mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 -#define SEA_mmGRPH_STEREOSYNC_FLIP 0x1a97 -#define SEA_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 -#define SEA_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97 -#define SEA_mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 -#define SEA_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 -#define SEA_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 -#define SEA_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 -#define SEA_mmDCP_DEBUG2 0x1a98 -#define SEA_mmDCP0_DCP_DEBUG2 0x1a98 -#define SEA_mmDCP1_DCP_DEBUG2 0x1d98 -#define SEA_mmDCP2_DCP_DEBUG2 0x4098 -#define SEA_mmDCP3_DCP_DEBUG2 0x4398 -#define SEA_mmDCP4_DCP_DEBUG2 0x4698 -#define SEA_mmDCP5_DCP_DEBUG2 0x4998 -#define SEA_mmHW_ROTATION 0x1a9e -#define SEA_mmDCP0_HW_ROTATION 0x1a9e -#define SEA_mmDCP1_HW_ROTATION 0x1d9e -#define SEA_mmDCP2_HW_ROTATION 0x409e -#define SEA_mmDCP3_HW_ROTATION 0x439e -#define SEA_mmDCP4_HW_ROTATION 0x469e -#define SEA_mmDCP5_HW_ROTATION 0x499e -#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f -#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f -#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f -#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f -#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f -#define SEA_mmREGAMMA_CONTROL 0x1aa0 -#define SEA_mmDCP0_REGAMMA_CONTROL 0x1aa0 -#define SEA_mmDCP1_REGAMMA_CONTROL 0x1da0 -#define SEA_mmDCP2_REGAMMA_CONTROL 0x40a0 -#define SEA_mmDCP3_REGAMMA_CONTROL 0x43a0 -#define SEA_mmDCP4_REGAMMA_CONTROL 0x46a0 -#define SEA_mmDCP5_REGAMMA_CONTROL 0x49a0 -#define SEA_mmREGAMMA_LUT_INDEX 0x1aa1 -#define SEA_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 -#define SEA_mmDCP1_REGAMMA_LUT_INDEX 0x1da1 -#define SEA_mmDCP2_REGAMMA_LUT_INDEX 0x40a1 -#define SEA_mmDCP3_REGAMMA_LUT_INDEX 0x43a1 -#define SEA_mmDCP4_REGAMMA_LUT_INDEX 0x46a1 -#define SEA_mmDCP5_REGAMMA_LUT_INDEX 0x49a1 -#define SEA_mmREGAMMA_LUT_DATA 0x1aa2 -#define SEA_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 -#define SEA_mmDCP1_REGAMMA_LUT_DATA 0x1da2 -#define SEA_mmDCP2_REGAMMA_LUT_DATA 0x40a2 -#define SEA_mmDCP3_REGAMMA_LUT_DATA 0x43a2 -#define SEA_mmDCP4_REGAMMA_LUT_DATA 0x46a2 -#define SEA_mmDCP5_REGAMMA_LUT_DATA 0x49a2 -#define SEA_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define SEA_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define SEA_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3 -#define SEA_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 -#define SEA_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3 -#define SEA_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3 -#define SEA_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3 -#define SEA_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 -#define SEA_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 -#define SEA_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4 -#define SEA_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4 -#define SEA_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4 -#define SEA_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4 -#define SEA_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4 -#define SEA_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define SEA_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define SEA_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5 -#define SEA_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 -#define SEA_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5 -#define SEA_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5 -#define SEA_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5 -#define SEA_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6 -#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6 -#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6 -#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6 -#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6 -#define SEA_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7 -#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7 -#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7 -#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7 -#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7 -#define SEA_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8 -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8 -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8 -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8 -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8 -#define SEA_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9 -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9 -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9 -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9 -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9 -#define SEA_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa -#define SEA_mmREGAMMA_CNTLA_REGION_6_7 0x1aab -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab -#define SEA_mmREGAMMA_CNTLA_REGION_8_9 0x1aac -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac -#define SEA_mmREGAMMA_CNTLA_REGION_10_11 0x1aad -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad -#define SEA_mmREGAMMA_CNTLA_REGION_12_13 0x1aae -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae -#define SEA_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf -#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf -#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf -#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af -#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af -#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af -#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af -#define SEA_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 -#define SEA_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 -#define SEA_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0 -#define SEA_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0 -#define SEA_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0 -#define SEA_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0 -#define SEA_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0 -#define SEA_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define SEA_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define SEA_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1 -#define SEA_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 -#define SEA_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1 -#define SEA_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1 -#define SEA_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1 -#define SEA_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2 -#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2 -#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2 -#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2 -#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2 -#define SEA_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3 -#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3 -#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3 -#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3 -#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3 -#define SEA_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4 -#define SEA_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5 -#define SEA_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6 -#define SEA_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7 -#define SEA_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8 -#define SEA_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9 -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9 -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9 -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9 -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9 -#define SEA_mmREGAMMA_CNTLB_REGION_12_13 0x1aba -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba -#define SEA_mmREGAMMA_CNTLB_REGION_14_15 0x1abb -#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb -#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb -#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb -#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb -#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb -#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb -#define SEA_mmALPHA_CONTROL 0x1abc -#define SEA_mmDCP0_ALPHA_CONTROL 0x1abc -#define SEA_mmDCP1_ALPHA_CONTROL 0x1dbc -#define SEA_mmDCP2_ALPHA_CONTROL 0x40bc -#define SEA_mmDCP3_ALPHA_CONTROL 0x43bc -#define SEA_mmDCP4_ALPHA_CONTROL 0x46bc -#define SEA_mmDCP5_ALPHA_CONTROL 0x49bc -#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd -#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd -#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd -#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd -#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd -#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe -#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be -#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be -#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be -#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be -#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf -#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf -#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf -#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf -#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf -#define SEA_mmDIG_FE_CNTL 0x1c00 -#define SEA_mmDIG0_DIG_FE_CNTL 0x1c00 -#define SEA_mmDIG1_DIG_FE_CNTL 0x1f00 -#define SEA_mmDIG2_DIG_FE_CNTL 0x4200 -#define SEA_mmDIG3_DIG_FE_CNTL 0x4500 -#define SEA_mmDIG4_DIG_FE_CNTL 0x4800 -#define SEA_mmDIG5_DIG_FE_CNTL 0x4b00 -#define SEA_mmDIG6_DIG_FE_CNTL 0x4e00 -#define SEA_mmDIG_OUTPUT_CRC_CNTL 0x1c01 -#define SEA_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01 -#define SEA_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01 -#define SEA_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 -#define SEA_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 -#define SEA_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 -#define SEA_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01 -#define SEA_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01 -#define SEA_mmDIG_OUTPUT_CRC_RESULT 0x1c02 -#define SEA_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02 -#define SEA_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02 -#define SEA_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 -#define SEA_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 -#define SEA_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 -#define SEA_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02 -#define SEA_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02 -#define SEA_mmDIG_CLOCK_PATTERN 0x1c03 -#define SEA_mmDIG0_DIG_CLOCK_PATTERN 0x1c03 -#define SEA_mmDIG1_DIG_CLOCK_PATTERN 0x1f03 -#define SEA_mmDIG2_DIG_CLOCK_PATTERN 0x4203 -#define SEA_mmDIG3_DIG_CLOCK_PATTERN 0x4503 -#define SEA_mmDIG4_DIG_CLOCK_PATTERN 0x4803 -#define SEA_mmDIG5_DIG_CLOCK_PATTERN 0x4b03 -#define SEA_mmDIG6_DIG_CLOCK_PATTERN 0x4e03 -#define SEA_mmDIG_TEST_PATTERN 0x1c04 -#define SEA_mmDIG0_DIG_TEST_PATTERN 0x1c04 -#define SEA_mmDIG1_DIG_TEST_PATTERN 0x1f04 -#define SEA_mmDIG2_DIG_TEST_PATTERN 0x4204 -#define SEA_mmDIG3_DIG_TEST_PATTERN 0x4504 -#define SEA_mmDIG4_DIG_TEST_PATTERN 0x4804 -#define SEA_mmDIG5_DIG_TEST_PATTERN 0x4b04 -#define SEA_mmDIG6_DIG_TEST_PATTERN 0x4e04 -#define SEA_mmDIG_RANDOM_PATTERN_SEED 0x1c05 -#define SEA_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05 -#define SEA_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05 -#define SEA_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 -#define SEA_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 -#define SEA_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 -#define SEA_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05 -#define SEA_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05 -#define SEA_mmDIG_FIFO_STATUS 0x1c0a -#define SEA_mmDIG0_DIG_FIFO_STATUS 0x1c0a -#define SEA_mmDIG1_DIG_FIFO_STATUS 0x1f0a -#define SEA_mmDIG2_DIG_FIFO_STATUS 0x420a -#define SEA_mmDIG3_DIG_FIFO_STATUS 0x450a -#define SEA_mmDIG4_DIG_FIFO_STATUS 0x480a -#define SEA_mmDIG5_DIG_FIFO_STATUS 0x4b0a -#define SEA_mmDIG6_DIG_FIFO_STATUS 0x4e0a -#define SEA_mmDIG_DISPCLK_SWITCH_CNTL 0x1c08 -#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08 -#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08 -#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 -#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 -#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 -#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08 -#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08 -#define SEA_mmDIG_DISPCLK_SWITCH_STATUS 0x1c09 -#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09 -#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09 -#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 -#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 -#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 -#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09 -#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09 -#define SEA_mmHDMI_CONTROL 0x1c0c -#define SEA_mmDIG0_HDMI_CONTROL 0x1c0c -#define SEA_mmDIG1_HDMI_CONTROL 0x1f0c -#define SEA_mmDIG2_HDMI_CONTROL 0x420c -#define SEA_mmDIG3_HDMI_CONTROL 0x450c -#define SEA_mmDIG4_HDMI_CONTROL 0x480c -#define SEA_mmDIG5_HDMI_CONTROL 0x4b0c -#define SEA_mmDIG6_HDMI_CONTROL 0x4e0c -#define SEA_mmHDMI_STATUS 0x1c0d -#define SEA_mmDIG0_HDMI_STATUS 0x1c0d -#define SEA_mmDIG1_HDMI_STATUS 0x1f0d -#define SEA_mmDIG2_HDMI_STATUS 0x420d -#define SEA_mmDIG3_HDMI_STATUS 0x450d -#define SEA_mmDIG4_HDMI_STATUS 0x480d -#define SEA_mmDIG5_HDMI_STATUS 0x4b0d -#define SEA_mmDIG6_HDMI_STATUS 0x4e0d -#define SEA_mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e -#define SEA_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e -#define SEA_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e -#define SEA_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e -#define SEA_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e -#define SEA_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e -#define SEA_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e -#define SEA_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e -#define SEA_mmHDMI_ACR_PACKET_CONTROL 0x1c0f -#define SEA_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f -#define SEA_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f -#define SEA_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f -#define SEA_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f -#define SEA_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f -#define SEA_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f -#define SEA_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f -#define SEA_mmHDMI_VBI_PACKET_CONTROL 0x1c10 -#define SEA_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10 -#define SEA_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10 -#define SEA_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 -#define SEA_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 -#define SEA_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 -#define SEA_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10 -#define SEA_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10 -#define SEA_mmHDMI_INFOFRAME_CONTROL0 0x1c11 -#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11 -#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11 -#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 -#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 -#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 -#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11 -#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11 -#define SEA_mmHDMI_INFOFRAME_CONTROL1 0x1c12 -#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12 -#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12 -#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 -#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 -#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 -#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12 -#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12 -#define SEA_mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13 -#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13 -#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13 -#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 -#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 -#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 -#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13 -#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13 -#define SEA_mmAFMT_INTERRUPT_STATUS 0x1c14 -#define SEA_mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14 -#define SEA_mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14 -#define SEA_mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 -#define SEA_mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 -#define SEA_mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 -#define SEA_mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14 -#define SEA_mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14 -#define SEA_mmHDMI_GC 0x1c16 -#define SEA_mmDIG0_HDMI_GC 0x1c16 -#define SEA_mmDIG1_HDMI_GC 0x1f16 -#define SEA_mmDIG2_HDMI_GC 0x4216 -#define SEA_mmDIG3_HDMI_GC 0x4516 -#define SEA_mmDIG4_HDMI_GC 0x4816 -#define SEA_mmDIG5_HDMI_GC 0x4b16 -#define SEA_mmDIG6_HDMI_GC 0x4e16 -#define SEA_mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17 -#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17 -#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17 -#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 -#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 -#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 -#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17 -#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17 -#define SEA_mmAFMT_ISRC1_0 0x1c18 -#define SEA_mmDIG0_AFMT_ISRC1_0 0x1c18 -#define SEA_mmDIG1_AFMT_ISRC1_0 0x1f18 -#define SEA_mmDIG2_AFMT_ISRC1_0 0x4218 -#define SEA_mmDIG3_AFMT_ISRC1_0 0x4518 -#define SEA_mmDIG4_AFMT_ISRC1_0 0x4818 -#define SEA_mmDIG5_AFMT_ISRC1_0 0x4b18 -#define SEA_mmDIG6_AFMT_ISRC1_0 0x4e18 -#define SEA_mmAFMT_ISRC1_1 0x1c19 -#define SEA_mmDIG0_AFMT_ISRC1_1 0x1c19 -#define SEA_mmDIG1_AFMT_ISRC1_1 0x1f19 -#define SEA_mmDIG2_AFMT_ISRC1_1 0x4219 -#define SEA_mmDIG3_AFMT_ISRC1_1 0x4519 -#define SEA_mmDIG4_AFMT_ISRC1_1 0x4819 -#define SEA_mmDIG5_AFMT_ISRC1_1 0x4b19 -#define SEA_mmDIG6_AFMT_ISRC1_1 0x4e19 -#define SEA_mmAFMT_ISRC1_2 0x1c1a -#define SEA_mmDIG0_AFMT_ISRC1_2 0x1c1a -#define SEA_mmDIG1_AFMT_ISRC1_2 0x1f1a -#define SEA_mmDIG2_AFMT_ISRC1_2 0x421a -#define SEA_mmDIG3_AFMT_ISRC1_2 0x451a -#define SEA_mmDIG4_AFMT_ISRC1_2 0x481a -#define SEA_mmDIG5_AFMT_ISRC1_2 0x4b1a -#define SEA_mmDIG6_AFMT_ISRC1_2 0x4e1a -#define SEA_mmAFMT_ISRC1_3 0x1c1b -#define SEA_mmDIG0_AFMT_ISRC1_3 0x1c1b -#define SEA_mmDIG1_AFMT_ISRC1_3 0x1f1b -#define SEA_mmDIG2_AFMT_ISRC1_3 0x421b -#define SEA_mmDIG3_AFMT_ISRC1_3 0x451b -#define SEA_mmDIG4_AFMT_ISRC1_3 0x481b -#define SEA_mmDIG5_AFMT_ISRC1_3 0x4b1b -#define SEA_mmDIG6_AFMT_ISRC1_3 0x4e1b -#define SEA_mmAFMT_ISRC1_4 0x1c1c -#define SEA_mmDIG0_AFMT_ISRC1_4 0x1c1c -#define SEA_mmDIG1_AFMT_ISRC1_4 0x1f1c -#define SEA_mmDIG2_AFMT_ISRC1_4 0x421c -#define SEA_mmDIG3_AFMT_ISRC1_4 0x451c -#define SEA_mmDIG4_AFMT_ISRC1_4 0x481c -#define SEA_mmDIG5_AFMT_ISRC1_4 0x4b1c -#define SEA_mmDIG6_AFMT_ISRC1_4 0x4e1c -#define SEA_mmAFMT_ISRC2_0 0x1c1d -#define SEA_mmDIG0_AFMT_ISRC2_0 0x1c1d -#define SEA_mmDIG1_AFMT_ISRC2_0 0x1f1d -#define SEA_mmDIG2_AFMT_ISRC2_0 0x421d -#define SEA_mmDIG3_AFMT_ISRC2_0 0x451d -#define SEA_mmDIG4_AFMT_ISRC2_0 0x481d -#define SEA_mmDIG5_AFMT_ISRC2_0 0x4b1d -#define SEA_mmDIG6_AFMT_ISRC2_0 0x4e1d -#define SEA_mmAFMT_ISRC2_1 0x1c1e -#define SEA_mmDIG0_AFMT_ISRC2_1 0x1c1e -#define SEA_mmDIG1_AFMT_ISRC2_1 0x1f1e -#define SEA_mmDIG2_AFMT_ISRC2_1 0x421e -#define SEA_mmDIG3_AFMT_ISRC2_1 0x451e -#define SEA_mmDIG4_AFMT_ISRC2_1 0x481e -#define SEA_mmDIG5_AFMT_ISRC2_1 0x4b1e -#define SEA_mmDIG6_AFMT_ISRC2_1 0x4e1e -#define SEA_mmAFMT_ISRC2_2 0x1c1f -#define SEA_mmDIG0_AFMT_ISRC2_2 0x1c1f -#define SEA_mmDIG1_AFMT_ISRC2_2 0x1f1f -#define SEA_mmDIG2_AFMT_ISRC2_2 0x421f -#define SEA_mmDIG3_AFMT_ISRC2_2 0x451f -#define SEA_mmDIG4_AFMT_ISRC2_2 0x481f -#define SEA_mmDIG5_AFMT_ISRC2_2 0x4b1f -#define SEA_mmDIG6_AFMT_ISRC2_2 0x4e1f -#define SEA_mmAFMT_ISRC2_3 0x1c20 -#define SEA_mmDIG0_AFMT_ISRC2_3 0x1c20 -#define SEA_mmDIG1_AFMT_ISRC2_3 0x1f20 -#define SEA_mmDIG2_AFMT_ISRC2_3 0x4220 -#define SEA_mmDIG3_AFMT_ISRC2_3 0x4520 -#define SEA_mmDIG4_AFMT_ISRC2_3 0x4820 -#define SEA_mmDIG5_AFMT_ISRC2_3 0x4b20 -#define SEA_mmDIG6_AFMT_ISRC2_3 0x4e20 -#define SEA_mmAFMT_AVI_INFO0 0x1c21 -#define SEA_mmDIG0_AFMT_AVI_INFO0 0x1c21 -#define SEA_mmDIG1_AFMT_AVI_INFO0 0x1f21 -#define SEA_mmDIG2_AFMT_AVI_INFO0 0x4221 -#define SEA_mmDIG3_AFMT_AVI_INFO0 0x4521 -#define SEA_mmDIG4_AFMT_AVI_INFO0 0x4821 -#define SEA_mmDIG5_AFMT_AVI_INFO0 0x4b21 -#define SEA_mmDIG6_AFMT_AVI_INFO0 0x4e21 -#define SEA_mmAFMT_AVI_INFO1 0x1c22 -#define SEA_mmDIG0_AFMT_AVI_INFO1 0x1c22 -#define SEA_mmDIG1_AFMT_AVI_INFO1 0x1f22 -#define SEA_mmDIG2_AFMT_AVI_INFO1 0x4222 -#define SEA_mmDIG3_AFMT_AVI_INFO1 0x4522 -#define SEA_mmDIG4_AFMT_AVI_INFO1 0x4822 -#define SEA_mmDIG5_AFMT_AVI_INFO1 0x4b22 -#define SEA_mmDIG6_AFMT_AVI_INFO1 0x4e22 -#define SEA_mmAFMT_AVI_INFO2 0x1c23 -#define SEA_mmDIG0_AFMT_AVI_INFO2 0x1c23 -#define SEA_mmDIG1_AFMT_AVI_INFO2 0x1f23 -#define SEA_mmDIG2_AFMT_AVI_INFO2 0x4223 -#define SEA_mmDIG3_AFMT_AVI_INFO2 0x4523 -#define SEA_mmDIG4_AFMT_AVI_INFO2 0x4823 -#define SEA_mmDIG5_AFMT_AVI_INFO2 0x4b23 -#define SEA_mmDIG6_AFMT_AVI_INFO2 0x4e23 -#define SEA_mmAFMT_AVI_INFO3 0x1c24 -#define SEA_mmDIG0_AFMT_AVI_INFO3 0x1c24 -#define SEA_mmDIG1_AFMT_AVI_INFO3 0x1f24 -#define SEA_mmDIG2_AFMT_AVI_INFO3 0x4224 -#define SEA_mmDIG3_AFMT_AVI_INFO3 0x4524 -#define SEA_mmDIG4_AFMT_AVI_INFO3 0x4824 -#define SEA_mmDIG5_AFMT_AVI_INFO3 0x4b24 -#define SEA_mmDIG6_AFMT_AVI_INFO3 0x4e24 -#define SEA_mmAFMT_MPEG_INFO0 0x1c25 -#define SEA_mmDIG0_AFMT_MPEG_INFO0 0x1c25 -#define SEA_mmDIG1_AFMT_MPEG_INFO0 0x1f25 -#define SEA_mmDIG2_AFMT_MPEG_INFO0 0x4225 -#define SEA_mmDIG3_AFMT_MPEG_INFO0 0x4525 -#define SEA_mmDIG4_AFMT_MPEG_INFO0 0x4825 -#define SEA_mmDIG5_AFMT_MPEG_INFO0 0x4b25 -#define SEA_mmDIG6_AFMT_MPEG_INFO0 0x4e25 -#define SEA_mmAFMT_MPEG_INFO1 0x1c26 -#define SEA_mmDIG0_AFMT_MPEG_INFO1 0x1c26 -#define SEA_mmDIG1_AFMT_MPEG_INFO1 0x1f26 -#define SEA_mmDIG2_AFMT_MPEG_INFO1 0x4226 -#define SEA_mmDIG3_AFMT_MPEG_INFO1 0x4526 -#define SEA_mmDIG4_AFMT_MPEG_INFO1 0x4826 -#define SEA_mmDIG5_AFMT_MPEG_INFO1 0x4b26 -#define SEA_mmDIG6_AFMT_MPEG_INFO1 0x4e26 -#define SEA_mmAFMT_GENERIC_HDR 0x1c27 -#define SEA_mmDIG0_AFMT_GENERIC_HDR 0x1c27 -#define SEA_mmDIG1_AFMT_GENERIC_HDR 0x1f27 -#define SEA_mmDIG2_AFMT_GENERIC_HDR 0x4227 -#define SEA_mmDIG3_AFMT_GENERIC_HDR 0x4527 -#define SEA_mmDIG4_AFMT_GENERIC_HDR 0x4827 -#define SEA_mmDIG5_AFMT_GENERIC_HDR 0x4b27 -#define SEA_mmDIG6_AFMT_GENERIC_HDR 0x4e27 -#define SEA_mmAFMT_GENERIC_0 0x1c28 -#define SEA_mmDIG0_AFMT_GENERIC_0 0x1c28 -#define SEA_mmDIG1_AFMT_GENERIC_0 0x1f28 -#define SEA_mmDIG2_AFMT_GENERIC_0 0x4228 -#define SEA_mmDIG3_AFMT_GENERIC_0 0x4528 -#define SEA_mmDIG4_AFMT_GENERIC_0 0x4828 -#define SEA_mmDIG5_AFMT_GENERIC_0 0x4b28 -#define SEA_mmDIG6_AFMT_GENERIC_0 0x4e28 -#define SEA_mmAFMT_GENERIC_1 0x1c29 -#define SEA_mmDIG0_AFMT_GENERIC_1 0x1c29 -#define SEA_mmDIG1_AFMT_GENERIC_1 0x1f29 -#define SEA_mmDIG2_AFMT_GENERIC_1 0x4229 -#define SEA_mmDIG3_AFMT_GENERIC_1 0x4529 -#define SEA_mmDIG4_AFMT_GENERIC_1 0x4829 -#define SEA_mmDIG5_AFMT_GENERIC_1 0x4b29 -#define SEA_mmDIG6_AFMT_GENERIC_1 0x4e29 -#define SEA_mmAFMT_GENERIC_2 0x1c2a -#define SEA_mmDIG0_AFMT_GENERIC_2 0x1c2a -#define SEA_mmDIG1_AFMT_GENERIC_2 0x1f2a -#define SEA_mmDIG2_AFMT_GENERIC_2 0x422a -#define SEA_mmDIG3_AFMT_GENERIC_2 0x452a -#define SEA_mmDIG4_AFMT_GENERIC_2 0x482a -#define SEA_mmDIG5_AFMT_GENERIC_2 0x4b2a -#define SEA_mmDIG6_AFMT_GENERIC_2 0x4e2a -#define SEA_mmAFMT_GENERIC_3 0x1c2b -#define SEA_mmDIG0_AFMT_GENERIC_3 0x1c2b -#define SEA_mmDIG1_AFMT_GENERIC_3 0x1f2b -#define SEA_mmDIG2_AFMT_GENERIC_3 0x422b -#define SEA_mmDIG3_AFMT_GENERIC_3 0x452b -#define SEA_mmDIG4_AFMT_GENERIC_3 0x482b -#define SEA_mmDIG5_AFMT_GENERIC_3 0x4b2b -#define SEA_mmDIG6_AFMT_GENERIC_3 0x4e2b -#define SEA_mmAFMT_GENERIC_4 0x1c2c -#define SEA_mmDIG0_AFMT_GENERIC_4 0x1c2c -#define SEA_mmDIG1_AFMT_GENERIC_4 0x1f2c -#define SEA_mmDIG2_AFMT_GENERIC_4 0x422c -#define SEA_mmDIG3_AFMT_GENERIC_4 0x452c -#define SEA_mmDIG4_AFMT_GENERIC_4 0x482c -#define SEA_mmDIG5_AFMT_GENERIC_4 0x4b2c -#define SEA_mmDIG6_AFMT_GENERIC_4 0x4e2c -#define SEA_mmAFMT_GENERIC_5 0x1c2d -#define SEA_mmDIG0_AFMT_GENERIC_5 0x1c2d -#define SEA_mmDIG1_AFMT_GENERIC_5 0x1f2d -#define SEA_mmDIG2_AFMT_GENERIC_5 0x422d -#define SEA_mmDIG3_AFMT_GENERIC_5 0x452d -#define SEA_mmDIG4_AFMT_GENERIC_5 0x482d -#define SEA_mmDIG5_AFMT_GENERIC_5 0x4b2d -#define SEA_mmDIG6_AFMT_GENERIC_5 0x4e2d -#define SEA_mmAFMT_GENERIC_6 0x1c2e -#define SEA_mmDIG0_AFMT_GENERIC_6 0x1c2e -#define SEA_mmDIG1_AFMT_GENERIC_6 0x1f2e -#define SEA_mmDIG2_AFMT_GENERIC_6 0x422e -#define SEA_mmDIG3_AFMT_GENERIC_6 0x452e -#define SEA_mmDIG4_AFMT_GENERIC_6 0x482e -#define SEA_mmDIG5_AFMT_GENERIC_6 0x4b2e -#define SEA_mmDIG6_AFMT_GENERIC_6 0x4e2e -#define SEA_mmAFMT_GENERIC_7 0x1c2f -#define SEA_mmDIG0_AFMT_GENERIC_7 0x1c2f -#define SEA_mmDIG1_AFMT_GENERIC_7 0x1f2f -#define SEA_mmDIG2_AFMT_GENERIC_7 0x422f -#define SEA_mmDIG3_AFMT_GENERIC_7 0x452f -#define SEA_mmDIG4_AFMT_GENERIC_7 0x482f -#define SEA_mmDIG5_AFMT_GENERIC_7 0x4b2f -#define SEA_mmDIG6_AFMT_GENERIC_7 0x4e2f -#define SEA_mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30 -#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30 -#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30 -#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 -#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 -#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 -#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30 -#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30 -#define SEA_mmHDMI_ACR_32_0 0x1c37 -#define SEA_mmDIG0_HDMI_ACR_32_0 0x1c37 -#define SEA_mmDIG1_HDMI_ACR_32_0 0x1f37 -#define SEA_mmDIG2_HDMI_ACR_32_0 0x4237 -#define SEA_mmDIG3_HDMI_ACR_32_0 0x4537 -#define SEA_mmDIG4_HDMI_ACR_32_0 0x4837 -#define SEA_mmDIG5_HDMI_ACR_32_0 0x4b37 -#define SEA_mmDIG6_HDMI_ACR_32_0 0x4e37 -#define SEA_mmHDMI_ACR_32_1 0x1c38 -#define SEA_mmDIG0_HDMI_ACR_32_1 0x1c38 -#define SEA_mmDIG1_HDMI_ACR_32_1 0x1f38 -#define SEA_mmDIG2_HDMI_ACR_32_1 0x4238 -#define SEA_mmDIG3_HDMI_ACR_32_1 0x4538 -#define SEA_mmDIG4_HDMI_ACR_32_1 0x4838 -#define SEA_mmDIG5_HDMI_ACR_32_1 0x4b38 -#define SEA_mmDIG6_HDMI_ACR_32_1 0x4e38 -#define SEA_mmHDMI_ACR_44_0 0x1c39 -#define SEA_mmDIG0_HDMI_ACR_44_0 0x1c39 -#define SEA_mmDIG1_HDMI_ACR_44_0 0x1f39 -#define SEA_mmDIG2_HDMI_ACR_44_0 0x4239 -#define SEA_mmDIG3_HDMI_ACR_44_0 0x4539 -#define SEA_mmDIG4_HDMI_ACR_44_0 0x4839 -#define SEA_mmDIG5_HDMI_ACR_44_0 0x4b39 -#define SEA_mmDIG6_HDMI_ACR_44_0 0x4e39 -#define SEA_mmHDMI_ACR_44_1 0x1c3a -#define SEA_mmDIG0_HDMI_ACR_44_1 0x1c3a -#define SEA_mmDIG1_HDMI_ACR_44_1 0x1f3a -#define SEA_mmDIG2_HDMI_ACR_44_1 0x423a -#define SEA_mmDIG3_HDMI_ACR_44_1 0x453a -#define SEA_mmDIG4_HDMI_ACR_44_1 0x483a -#define SEA_mmDIG5_HDMI_ACR_44_1 0x4b3a -#define SEA_mmDIG6_HDMI_ACR_44_1 0x4e3a -#define SEA_mmHDMI_ACR_48_0 0x1c3b -#define SEA_mmDIG0_HDMI_ACR_48_0 0x1c3b -#define SEA_mmDIG1_HDMI_ACR_48_0 0x1f3b -#define SEA_mmDIG2_HDMI_ACR_48_0 0x423b -#define SEA_mmDIG3_HDMI_ACR_48_0 0x453b -#define SEA_mmDIG4_HDMI_ACR_48_0 0x483b -#define SEA_mmDIG5_HDMI_ACR_48_0 0x4b3b -#define SEA_mmDIG6_HDMI_ACR_48_0 0x4e3b -#define SEA_mmHDMI_ACR_48_1 0x1c3c -#define SEA_mmDIG0_HDMI_ACR_48_1 0x1c3c -#define SEA_mmDIG1_HDMI_ACR_48_1 0x1f3c -#define SEA_mmDIG2_HDMI_ACR_48_1 0x423c -#define SEA_mmDIG3_HDMI_ACR_48_1 0x453c -#define SEA_mmDIG4_HDMI_ACR_48_1 0x483c -#define SEA_mmDIG5_HDMI_ACR_48_1 0x4b3c -#define SEA_mmDIG6_HDMI_ACR_48_1 0x4e3c -#define SEA_mmHDMI_ACR_STATUS_0 0x1c3d -#define SEA_mmDIG0_HDMI_ACR_STATUS_0 0x1c3d -#define SEA_mmDIG1_HDMI_ACR_STATUS_0 0x1f3d -#define SEA_mmDIG2_HDMI_ACR_STATUS_0 0x423d -#define SEA_mmDIG3_HDMI_ACR_STATUS_0 0x453d -#define SEA_mmDIG4_HDMI_ACR_STATUS_0 0x483d -#define SEA_mmDIG5_HDMI_ACR_STATUS_0 0x4b3d -#define SEA_mmDIG6_HDMI_ACR_STATUS_0 0x4e3d -#define SEA_mmHDMI_ACR_STATUS_1 0x1c3e -#define SEA_mmDIG0_HDMI_ACR_STATUS_1 0x1c3e -#define SEA_mmDIG1_HDMI_ACR_STATUS_1 0x1f3e -#define SEA_mmDIG2_HDMI_ACR_STATUS_1 0x423e -#define SEA_mmDIG3_HDMI_ACR_STATUS_1 0x453e -#define SEA_mmDIG4_HDMI_ACR_STATUS_1 0x483e -#define SEA_mmDIG5_HDMI_ACR_STATUS_1 0x4b3e -#define SEA_mmDIG6_HDMI_ACR_STATUS_1 0x4e3e -#define SEA_mmAFMT_AUDIO_INFO0 0x1c3f -#define SEA_mmDIG0_AFMT_AUDIO_INFO0 0x1c3f -#define SEA_mmDIG1_AFMT_AUDIO_INFO0 0x1f3f -#define SEA_mmDIG2_AFMT_AUDIO_INFO0 0x423f -#define SEA_mmDIG3_AFMT_AUDIO_INFO0 0x453f -#define SEA_mmDIG4_AFMT_AUDIO_INFO0 0x483f -#define SEA_mmDIG5_AFMT_AUDIO_INFO0 0x4b3f -#define SEA_mmDIG6_AFMT_AUDIO_INFO0 0x4e3f -#define SEA_mmAFMT_AUDIO_INFO1 0x1c40 -#define SEA_mmDIG0_AFMT_AUDIO_INFO1 0x1c40 -#define SEA_mmDIG1_AFMT_AUDIO_INFO1 0x1f40 -#define SEA_mmDIG2_AFMT_AUDIO_INFO1 0x4240 -#define SEA_mmDIG3_AFMT_AUDIO_INFO1 0x4540 -#define SEA_mmDIG4_AFMT_AUDIO_INFO1 0x4840 -#define SEA_mmDIG5_AFMT_AUDIO_INFO1 0x4b40 -#define SEA_mmDIG6_AFMT_AUDIO_INFO1 0x4e40 -#define SEA_mmAFMT_60958_0 0x1c41 -#define SEA_mmDIG0_AFMT_60958_0 0x1c41 -#define SEA_mmDIG1_AFMT_60958_0 0x1f41 -#define SEA_mmDIG2_AFMT_60958_0 0x4241 -#define SEA_mmDIG3_AFMT_60958_0 0x4541 -#define SEA_mmDIG4_AFMT_60958_0 0x4841 -#define SEA_mmDIG5_AFMT_60958_0 0x4b41 -#define SEA_mmDIG6_AFMT_60958_0 0x4e41 -#define SEA_mmAFMT_60958_1 0x1c42 -#define SEA_mmDIG0_AFMT_60958_1 0x1c42 -#define SEA_mmDIG1_AFMT_60958_1 0x1f42 -#define SEA_mmDIG2_AFMT_60958_1 0x4242 -#define SEA_mmDIG3_AFMT_60958_1 0x4542 -#define SEA_mmDIG4_AFMT_60958_1 0x4842 -#define SEA_mmDIG5_AFMT_60958_1 0x4b42 -#define SEA_mmDIG6_AFMT_60958_1 0x4e42 -#define SEA_mmAFMT_AUDIO_CRC_CONTROL 0x1c43 -#define SEA_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43 -#define SEA_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43 -#define SEA_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 -#define SEA_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 -#define SEA_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 -#define SEA_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43 -#define SEA_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43 -#define SEA_mmAFMT_RAMP_CONTROL0 0x1c44 -#define SEA_mmDIG0_AFMT_RAMP_CONTROL0 0x1c44 -#define SEA_mmDIG1_AFMT_RAMP_CONTROL0 0x1f44 -#define SEA_mmDIG2_AFMT_RAMP_CONTROL0 0x4244 -#define SEA_mmDIG3_AFMT_RAMP_CONTROL0 0x4544 -#define SEA_mmDIG4_AFMT_RAMP_CONTROL0 0x4844 -#define SEA_mmDIG5_AFMT_RAMP_CONTROL0 0x4b44 -#define SEA_mmDIG6_AFMT_RAMP_CONTROL0 0x4e44 -#define SEA_mmAFMT_RAMP_CONTROL1 0x1c45 -#define SEA_mmDIG0_AFMT_RAMP_CONTROL1 0x1c45 -#define SEA_mmDIG1_AFMT_RAMP_CONTROL1 0x1f45 -#define SEA_mmDIG2_AFMT_RAMP_CONTROL1 0x4245 -#define SEA_mmDIG3_AFMT_RAMP_CONTROL1 0x4545 -#define SEA_mmDIG4_AFMT_RAMP_CONTROL1 0x4845 -#define SEA_mmDIG5_AFMT_RAMP_CONTROL1 0x4b45 -#define SEA_mmDIG6_AFMT_RAMP_CONTROL1 0x4e45 -#define SEA_mmAFMT_RAMP_CONTROL2 0x1c46 -#define SEA_mmDIG0_AFMT_RAMP_CONTROL2 0x1c46 -#define SEA_mmDIG1_AFMT_RAMP_CONTROL2 0x1f46 -#define SEA_mmDIG2_AFMT_RAMP_CONTROL2 0x4246 -#define SEA_mmDIG3_AFMT_RAMP_CONTROL2 0x4546 -#define SEA_mmDIG4_AFMT_RAMP_CONTROL2 0x4846 -#define SEA_mmDIG5_AFMT_RAMP_CONTROL2 0x4b46 -#define SEA_mmDIG6_AFMT_RAMP_CONTROL2 0x4e46 -#define SEA_mmAFMT_RAMP_CONTROL3 0x1c47 -#define SEA_mmDIG0_AFMT_RAMP_CONTROL3 0x1c47 -#define SEA_mmDIG1_AFMT_RAMP_CONTROL3 0x1f47 -#define SEA_mmDIG2_AFMT_RAMP_CONTROL3 0x4247 -#define SEA_mmDIG3_AFMT_RAMP_CONTROL3 0x4547 -#define SEA_mmDIG4_AFMT_RAMP_CONTROL3 0x4847 -#define SEA_mmDIG5_AFMT_RAMP_CONTROL3 0x4b47 -#define SEA_mmDIG6_AFMT_RAMP_CONTROL3 0x4e47 -#define SEA_mmAFMT_60958_2 0x1c48 -#define SEA_mmDIG0_AFMT_60958_2 0x1c48 -#define SEA_mmDIG1_AFMT_60958_2 0x1f48 -#define SEA_mmDIG2_AFMT_60958_2 0x4248 -#define SEA_mmDIG3_AFMT_60958_2 0x4548 -#define SEA_mmDIG4_AFMT_60958_2 0x4848 -#define SEA_mmDIG5_AFMT_60958_2 0x4b48 -#define SEA_mmDIG6_AFMT_60958_2 0x4e48 -#define SEA_mmAFMT_AUDIO_CRC_RESULT 0x1c49 -#define SEA_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49 -#define SEA_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49 -#define SEA_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 -#define SEA_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 -#define SEA_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 -#define SEA_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49 -#define SEA_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49 -#define SEA_mmAFMT_STATUS 0x1c4a -#define SEA_mmDIG0_AFMT_STATUS 0x1c4a -#define SEA_mmDIG1_AFMT_STATUS 0x1f4a -#define SEA_mmDIG2_AFMT_STATUS 0x424a -#define SEA_mmDIG3_AFMT_STATUS 0x454a -#define SEA_mmDIG4_AFMT_STATUS 0x484a -#define SEA_mmDIG5_AFMT_STATUS 0x4b4a -#define SEA_mmDIG6_AFMT_STATUS 0x4e4a -#define SEA_mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b -#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b -#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b -#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b -#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b -#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b -#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b -#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b -#define SEA_mmAFMT_VBI_PACKET_CONTROL 0x1c4c -#define SEA_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c -#define SEA_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c -#define SEA_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c -#define SEA_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c -#define SEA_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c -#define SEA_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c -#define SEA_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c -#define SEA_mmAFMT_INFOFRAME_CONTROL0 0x1c4d -#define SEA_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d -#define SEA_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d -#define SEA_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d -#define SEA_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d -#define SEA_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d -#define SEA_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d -#define SEA_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d -#define SEA_mmAFMT_AUDIO_SRC_CONTROL 0x1c4f -#define SEA_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f -#define SEA_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f -#define SEA_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f -#define SEA_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f -#define SEA_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f -#define SEA_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f -#define SEA_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f -#define SEA_mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52 -#define SEA_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52 -#define SEA_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52 -#define SEA_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 -#define SEA_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 -#define SEA_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 -#define SEA_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52 -#define SEA_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52 -#define SEA_mmDIG_BE_CNTL 0x1c50 -#define SEA_mmDIG0_DIG_BE_CNTL 0x1c50 -#define SEA_mmDIG1_DIG_BE_CNTL 0x1f50 -#define SEA_mmDIG2_DIG_BE_CNTL 0x4250 -#define SEA_mmDIG3_DIG_BE_CNTL 0x4550 -#define SEA_mmDIG4_DIG_BE_CNTL 0x4850 -#define SEA_mmDIG5_DIG_BE_CNTL 0x4b50 -#define SEA_mmDIG6_DIG_BE_CNTL 0x4e50 -#define SEA_mmDIG_BE_EN_CNTL 0x1c51 -#define SEA_mmDIG0_DIG_BE_EN_CNTL 0x1c51 -#define SEA_mmDIG1_DIG_BE_EN_CNTL 0x1f51 -#define SEA_mmDIG2_DIG_BE_EN_CNTL 0x4251 -#define SEA_mmDIG3_DIG_BE_EN_CNTL 0x4551 -#define SEA_mmDIG4_DIG_BE_EN_CNTL 0x4851 -#define SEA_mmDIG5_DIG_BE_EN_CNTL 0x4b51 -#define SEA_mmDIG6_DIG_BE_EN_CNTL 0x4e51 -#define SEA_mmTMDS_CNTL 0x1c7c -#define SEA_mmDIG0_TMDS_CNTL 0x1c7c -#define SEA_mmDIG1_TMDS_CNTL 0x1f7c -#define SEA_mmDIG2_TMDS_CNTL 0x427c -#define SEA_mmDIG3_TMDS_CNTL 0x457c -#define SEA_mmDIG4_TMDS_CNTL 0x487c -#define SEA_mmDIG5_TMDS_CNTL 0x4b7c -#define SEA_mmDIG6_TMDS_CNTL 0x4e7c -#define SEA_mmTMDS_CONTROL_CHAR 0x1c7d -#define SEA_mmDIG0_TMDS_CONTROL_CHAR 0x1c7d -#define SEA_mmDIG1_TMDS_CONTROL_CHAR 0x1f7d -#define SEA_mmDIG2_TMDS_CONTROL_CHAR 0x427d -#define SEA_mmDIG3_TMDS_CONTROL_CHAR 0x457d -#define SEA_mmDIG4_TMDS_CONTROL_CHAR 0x487d -#define SEA_mmDIG5_TMDS_CONTROL_CHAR 0x4b7d -#define SEA_mmDIG6_TMDS_CONTROL_CHAR 0x4e7d -#define SEA_mmTMDS_CONTROL0_FEEDBACK 0x1c7e -#define SEA_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e -#define SEA_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e -#define SEA_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e -#define SEA_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e -#define SEA_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e -#define SEA_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e -#define SEA_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e -#define SEA_mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f -#define SEA_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f -#define SEA_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f -#define SEA_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f -#define SEA_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f -#define SEA_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f -#define SEA_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f -#define SEA_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f -#define SEA_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 -#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 -#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80 -#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 -#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 -#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 -#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80 -#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80 -#define SEA_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 -#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 -#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81 -#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 -#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 -#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 -#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81 -#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81 -#define SEA_mmTMDS_DEBUG 0x1c82 -#define SEA_mmDIG0_TMDS_DEBUG 0x1c82 -#define SEA_mmDIG1_TMDS_DEBUG 0x1f82 -#define SEA_mmDIG2_TMDS_DEBUG 0x4282 -#define SEA_mmDIG3_TMDS_DEBUG 0x4582 -#define SEA_mmDIG4_TMDS_DEBUG 0x4882 -#define SEA_mmDIG5_TMDS_DEBUG 0x4b82 -#define SEA_mmDIG6_TMDS_DEBUG 0x4e82 -#define SEA_mmTMDS_CTL_BITS 0x1c83 -#define SEA_mmDIG0_TMDS_CTL_BITS 0x1c83 -#define SEA_mmDIG1_TMDS_CTL_BITS 0x1f83 -#define SEA_mmDIG2_TMDS_CTL_BITS 0x4283 -#define SEA_mmDIG3_TMDS_CTL_BITS 0x4583 -#define SEA_mmDIG4_TMDS_CTL_BITS 0x4883 -#define SEA_mmDIG5_TMDS_CTL_BITS 0x4b83 -#define SEA_mmDIG6_TMDS_CTL_BITS 0x4e83 -#define SEA_mmTMDS_DCBALANCER_CONTROL 0x1c84 -#define SEA_mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 -#define SEA_mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 -#define SEA_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 -#define SEA_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 -#define SEA_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 -#define SEA_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 -#define SEA_mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84 -#define SEA_mmTMDS_CTL0_1_GEN_CNTL 0x1c86 -#define SEA_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 -#define SEA_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86 -#define SEA_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 -#define SEA_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 -#define SEA_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 -#define SEA_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86 -#define SEA_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86 -#define SEA_mmTMDS_CTL2_3_GEN_CNTL 0x1c87 -#define SEA_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87 -#define SEA_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87 -#define SEA_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 -#define SEA_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 -#define SEA_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 -#define SEA_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87 -#define SEA_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87 -#define SEA_mmLVDS_DATA_CNTL 0x1c8c -#define SEA_mmDIG0_LVDS_DATA_CNTL 0x1c8c -#define SEA_mmDIG1_LVDS_DATA_CNTL 0x1f8c -#define SEA_mmDIG2_LVDS_DATA_CNTL 0x428c -#define SEA_mmDIG3_LVDS_DATA_CNTL 0x458c -#define SEA_mmDIG4_LVDS_DATA_CNTL 0x488c -#define SEA_mmDIG5_LVDS_DATA_CNTL 0x4b8c -#define SEA_mmDIG6_LVDS_DATA_CNTL 0x4e8c -#define SEA_mmDIG_LANE_ENABLE 0x1c8d -#define SEA_mmDIG0_DIG_LANE_ENABLE 0x1c8d -#define SEA_mmDIG1_DIG_LANE_ENABLE 0x1f8d -#define SEA_mmDIG2_DIG_LANE_ENABLE 0x428d -#define SEA_mmDIG3_DIG_LANE_ENABLE 0x458d -#define SEA_mmDIG4_DIG_LANE_ENABLE 0x488d -#define SEA_mmDIG5_DIG_LANE_ENABLE 0x4b8d -#define SEA_mmDIG6_DIG_LANE_ENABLE 0x4e8d -#define SEA_mmDOUT_SCRATCH0 0x1844 -#define SEA_mmDOUT_SCRATCH1 0x1845 -#define SEA_mmDOUT_SCRATCH2 0x1846 -#define SEA_mmDOUT_SCRATCH3 0x1847 -#define SEA_mmDOUT_SCRATCH4 0x1848 -#define SEA_mmDOUT_SCRATCH5 0x1849 -#define SEA_mmDOUT_SCRATCH6 0x184a -#define SEA_mmDOUT_SCRATCH7 0x184b -#define SEA_mmDOUT_DCE_VCE_CONTROL 0x18ff -#define SEA_mmDC_HPD1_INT_STATUS 0x1807 -#define SEA_mmDC_HPD1_INT_CONTROL 0x1808 -#define SEA_mmDC_HPD1_CONTROL 0x1809 -#define SEA_mmDC_HPD2_INT_STATUS 0x180a -#define SEA_mmDC_HPD2_INT_CONTROL 0x180b -#define SEA_mmDC_HPD2_CONTROL 0x180c -#define SEA_mmDC_HPD3_INT_STATUS 0x180d -#define SEA_mmDC_HPD3_INT_CONTROL 0x180e -#define SEA_mmDC_HPD3_CONTROL 0x180f -#define SEA_mmDC_HPD4_INT_STATUS 0x1810 -#define SEA_mmDC_HPD4_INT_CONTROL 0x1811 -#define SEA_mmDC_HPD4_CONTROL 0x1812 -#define SEA_mmDC_HPD5_INT_STATUS 0x1813 -#define SEA_mmDC_HPD5_INT_CONTROL 0x1814 -#define SEA_mmDC_HPD5_CONTROL 0x1815 -#define SEA_mmDC_HPD6_INT_STATUS 0x1816 -#define SEA_mmDC_HPD6_INT_CONTROL 0x1817 -#define SEA_mmDC_HPD6_CONTROL 0x1818 -#define SEA_mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 -#define SEA_mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 -#define SEA_mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 -#define SEA_mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 -#define SEA_mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 -#define SEA_mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 -#define SEA_mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc -#define SEA_mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd -#define SEA_mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be -#define SEA_mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc -#define SEA_mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd -#define SEA_mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe -#define SEA_mmDC_I2C_CONTROL 0x1819 -#define SEA_mmDC_I2C_ARBITRATION 0x181a -#define SEA_mmDC_I2C_INTERRUPT_CONTROL 0x181b -#define SEA_mmDC_I2C_SW_STATUS 0x181c -#define SEA_mmDC_I2C_DDC1_HW_STATUS 0x181d -#define SEA_mmDC_I2C_DDC2_HW_STATUS 0x181e -#define SEA_mmDC_I2C_DDC3_HW_STATUS 0x181f -#define SEA_mmDC_I2C_DDC4_HW_STATUS 0x1820 -#define SEA_mmDC_I2C_DDC5_HW_STATUS 0x1821 -#define SEA_mmDC_I2C_DDC6_HW_STATUS 0x1822 -#define SEA_mmDC_I2C_DDC1_SPEED 0x1823 -#define SEA_mmDC_I2C_DDC1_SETUP 0x1824 -#define SEA_mmDC_I2C_DDC2_SPEED 0x1825 -#define SEA_mmDC_I2C_DDC2_SETUP 0x1826 -#define SEA_mmDC_I2C_DDC3_SPEED 0x1827 -#define SEA_mmDC_I2C_DDC3_SETUP 0x1828 -#define SEA_mmDC_I2C_DDC4_SPEED 0x1829 -#define SEA_mmDC_I2C_DDC4_SETUP 0x182a -#define SEA_mmDC_I2C_DDC5_SPEED 0x182b -#define SEA_mmDC_I2C_DDC5_SETUP 0x182c -#define SEA_mmDC_I2C_DDC6_SPEED 0x182d -#define SEA_mmDC_I2C_DDC6_SETUP 0x182e -#define SEA_mmDC_I2C_TRANSACTION0 0x182f -#define SEA_mmDC_I2C_TRANSACTION1 0x1830 -#define SEA_mmDC_I2C_TRANSACTION2 0x1831 -#define SEA_mmDC_I2C_TRANSACTION3 0x1832 -#define SEA_mmDC_I2C_DATA 0x1833 -#define SEA_mmGENERIC_I2C_CONTROL 0x1834 -#define SEA_mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 -#define SEA_mmGENERIC_I2C_STATUS 0x1836 -#define SEA_mmGENERIC_I2C_SPEED 0x1837 -#define SEA_mmGENERIC_I2C_SETUP 0x1838 -#define SEA_mmGENERIC_I2C_TRANSACTION 0x1839 -#define SEA_mmGENERIC_I2C_DATA 0x183a -#define SEA_mmGENERIC_I2C_PIN_SELECTION 0x183b -#define SEA_mmGENERIC_I2C_PIN_DEBUG 0x183c -#define SEA_mmDISP_INTERRUPT_STATUS 0x183d -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2 -#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3 -#define SEA_mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 -#define SEA_mmDISP_TIMER_CONTROL 0x1842 -#define SEA_mmDC_I2C_DDCVGA_HW_STATUS 0x1855 -#define SEA_mmDC_I2C_DDCVGA_SPEED 0x1856 -#define SEA_mmDC_I2C_DDCVGA_SETUP 0x1857 -#define SEA_mmDC_I2C_EDID_DETECT_CTRL 0x186f -#define SEA_mmDISPOUT_STEREOSYNC_SEL 0x18bf -#define SEA_mmDOUT_TEST_DEBUG_INDEX 0x184d -#define SEA_mmDOUT_TEST_DEBUG_DATA 0x184e -#define SEA_ixDP_AUX1_DEBUG_A 0x10 -#define SEA_ixDP_AUX1_DEBUG_B 0x11 -#define SEA_ixDP_AUX1_DEBUG_C 0x12 -#define SEA_ixDP_AUX1_DEBUG_D 0x13 -#define SEA_ixDP_AUX1_DEBUG_E 0x14 -#define SEA_ixDP_AUX1_DEBUG_F 0x15 -#define SEA_ixDP_AUX1_DEBUG_G 0x16 -#define SEA_ixDP_AUX1_DEBUG_H 0x17 -#define SEA_ixDP_AUX1_DEBUG_I 0x18 -#define SEA_ixDP_AUX1_DEBUG_J 0x19 -#define SEA_ixDP_AUX1_DEBUG_K 0x1a -#define SEA_ixDP_AUX1_DEBUG_L 0x1b -#define SEA_ixDP_AUX1_DEBUG_M 0x1c -#define SEA_ixDP_AUX1_DEBUG_N 0x1d -#define SEA_ixDP_AUX1_DEBUG_O 0x1e -#define SEA_ixDP_AUX1_DEBUG_P 0x1f -#define SEA_ixDP_AUX1_DEBUG_Q 0x90 -#define SEA_ixDP_AUX2_DEBUG_A 0x20 -#define SEA_ixDP_AUX2_DEBUG_B 0x21 -#define SEA_ixDP_AUX2_DEBUG_C 0x22 -#define SEA_ixDP_AUX2_DEBUG_D 0x23 -#define SEA_ixDP_AUX2_DEBUG_E 0x24 -#define SEA_ixDP_AUX2_DEBUG_F 0x25 -#define SEA_ixDP_AUX2_DEBUG_G 0x26 -#define SEA_ixDP_AUX2_DEBUG_H 0x27 -#define SEA_ixDP_AUX2_DEBUG_I 0x28 -#define SEA_ixDP_AUX2_DEBUG_J 0x29 -#define SEA_ixDP_AUX2_DEBUG_K 0x2a -#define SEA_ixDP_AUX2_DEBUG_L 0x2b -#define SEA_ixDP_AUX2_DEBUG_M 0x2c -#define SEA_ixDP_AUX2_DEBUG_N 0x2d -#define SEA_ixDP_AUX2_DEBUG_O 0x2e -#define SEA_ixDP_AUX2_DEBUG_P 0x2f -#define SEA_ixDP_AUX2_DEBUG_Q 0x91 -#define SEA_ixDP_AUX3_DEBUG_A 0x30 -#define SEA_ixDP_AUX3_DEBUG_B 0x31 -#define SEA_ixDP_AUX3_DEBUG_C 0x32 -#define SEA_ixDP_AUX3_DEBUG_D 0x33 -#define SEA_ixDP_AUX3_DEBUG_E 0x34 -#define SEA_ixDP_AUX3_DEBUG_F 0x35 -#define SEA_ixDP_AUX3_DEBUG_G 0x36 -#define SEA_ixDP_AUX3_DEBUG_H 0x37 -#define SEA_ixDP_AUX3_DEBUG_I 0x38 -#define SEA_ixDP_AUX3_DEBUG_J 0x39 -#define SEA_ixDP_AUX3_DEBUG_K 0x3a -#define SEA_ixDP_AUX3_DEBUG_L 0x3b -#define SEA_ixDP_AUX3_DEBUG_M 0x3c -#define SEA_ixDP_AUX3_DEBUG_N 0x3d -#define SEA_ixDP_AUX3_DEBUG_O 0x3e -#define SEA_ixDP_AUX3_DEBUG_P 0x3f -#define SEA_ixDP_AUX3_DEBUG_Q 0x92 -#define SEA_ixDP_AUX4_DEBUG_A 0x40 -#define SEA_ixDP_AUX4_DEBUG_B 0x41 -#define SEA_ixDP_AUX4_DEBUG_C 0x42 -#define SEA_ixDP_AUX4_DEBUG_D 0x43 -#define SEA_ixDP_AUX4_DEBUG_E 0x44 -#define SEA_ixDP_AUX4_DEBUG_F 0x45 -#define SEA_ixDP_AUX4_DEBUG_G 0x46 -#define SEA_ixDP_AUX4_DEBUG_H 0x47 -#define SEA_ixDP_AUX4_DEBUG_I 0x48 -#define SEA_ixDP_AUX4_DEBUG_J 0x49 -#define SEA_ixDP_AUX4_DEBUG_K 0x4a -#define SEA_ixDP_AUX4_DEBUG_L 0x4b -#define SEA_ixDP_AUX4_DEBUG_M 0x4c -#define SEA_ixDP_AUX4_DEBUG_N 0x4d -#define SEA_ixDP_AUX4_DEBUG_O 0x4e -#define SEA_ixDP_AUX4_DEBUG_P 0x4f -#define SEA_ixDP_AUX4_DEBUG_Q 0x93 -#define SEA_ixDP_AUX5_DEBUG_A 0x70 -#define SEA_ixDP_AUX5_DEBUG_B 0x71 -#define SEA_ixDP_AUX5_DEBUG_C 0x72 -#define SEA_ixDP_AUX5_DEBUG_D 0x73 -#define SEA_ixDP_AUX5_DEBUG_E 0x74 -#define SEA_ixDP_AUX5_DEBUG_F 0x75 -#define SEA_ixDP_AUX5_DEBUG_G 0x76 -#define SEA_ixDP_AUX5_DEBUG_H 0x77 -#define SEA_ixDP_AUX5_DEBUG_I 0x78 -#define SEA_ixDP_AUX5_DEBUG_J 0x79 -#define SEA_ixDP_AUX5_DEBUG_K 0x7a -#define SEA_ixDP_AUX5_DEBUG_L 0x7b -#define SEA_ixDP_AUX5_DEBUG_M 0x7c -#define SEA_ixDP_AUX5_DEBUG_N 0x7d -#define SEA_ixDP_AUX5_DEBUG_O 0x7f -#define SEA_ixDP_AUX5_DEBUG_P 0x94 -#define SEA_ixDP_AUX5_DEBUG_Q 0x95 -#define SEA_ixDP_AUX6_DEBUG_A 0x80 -#define SEA_ixDP_AUX6_DEBUG_B 0x81 -#define SEA_ixDP_AUX6_DEBUG_C 0x82 -#define SEA_ixDP_AUX6_DEBUG_D 0x83 -#define SEA_ixDP_AUX6_DEBUG_E 0x84 -#define SEA_ixDP_AUX6_DEBUG_F 0x85 -#define SEA_ixDP_AUX6_DEBUG_G 0x86 -#define SEA_ixDP_AUX6_DEBUG_H 0x87 -#define SEA_ixDP_AUX6_DEBUG_I 0x88 -#define SEA_ixDP_AUX6_DEBUG_J 0x89 -#define SEA_ixDP_AUX6_DEBUG_K 0x8a -#define SEA_ixDP_AUX6_DEBUG_L 0x8b -#define SEA_ixDP_AUX6_DEBUG_M 0x8c -#define SEA_ixDP_AUX6_DEBUG_N 0x8d -#define SEA_ixDP_AUX6_DEBUG_O 0x8f -#define SEA_ixDP_AUX6_DEBUG_P 0x96 -#define SEA_ixDP_AUX6_DEBUG_Q 0x97 -#define SEA_mmDMCU_CTRL 0x1600 -#define SEA_mmDMCU_STATUS 0x1601 -#define SEA_mmDMCU_PC_START_ADDR 0x1602 -#define SEA_mmDMCU_FW_START_ADDR 0x1603 -#define SEA_mmDMCU_FW_END_ADDR 0x1604 -#define SEA_mmDMCU_FW_ISR_START_ADDR 0x1605 -#define SEA_mmDMCU_FW_CS_HI 0x1606 -#define SEA_mmDMCU_FW_CS_LO 0x1607 -#define SEA_mmDMCU_RAM_ACCESS_CTRL 0x1608 -#define SEA_mmDMCU_ERAM_WR_CTRL 0x1609 -#define SEA_mmDMCU_ERAM_WR_DATA 0x160a -#define SEA_mmDMCU_ERAM_RD_CTRL 0x160b -#define SEA_mmDMCU_ERAM_RD_DATA 0x160c -#define SEA_mmDMCU_IRAM_WR_CTRL 0x160d -#define SEA_mmDMCU_IRAM_WR_DATA 0x160e -#define SEA_mmDMCU_IRAM_RD_CTRL 0x160f -#define SEA_mmDMCU_IRAM_RD_DATA 0x1610 -#define SEA_mmDMCU_EVENT_TRIGGER 0x1611 -#define SEA_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 -#define SEA_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 -#define SEA_mmDMCU_INTERRUPT_STATUS 0x1614 -#define SEA_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 -#define SEA_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 -#define SEA_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 -#define SEA_mmDC_DMCU_SCRATCH 0x1618 -#define SEA_mmDMCU_INT_CNT 0x1619 -#define SEA_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a -#define SEA_mmDMCU_UC_CLK_GATING_CNTL 0x161b -#define SEA_mmMASTER_COMM_DATA_REG1 0x161c -#define SEA_mmMASTER_COMM_DATA_REG2 0x161d -#define SEA_mmMASTER_COMM_DATA_REG3 0x161e -#define SEA_mmMASTER_COMM_CMD_REG 0x161f -#define SEA_mmMASTER_COMM_CNTL_REG 0x1620 -#define SEA_mmSLAVE_COMM_DATA_REG1 0x1621 -#define SEA_mmSLAVE_COMM_DATA_REG2 0x1622 -#define SEA_mmSLAVE_COMM_DATA_REG3 0x1623 -#define SEA_mmSLAVE_COMM_CMD_REG 0x1624 -#define SEA_mmSLAVE_COMM_CNTL_REG 0x1625 -#define SEA_mmDMCU_TEST_DEBUG_INDEX 0x1626 -#define SEA_mmDMCU_TEST_DEBUG_DATA 0x1627 -#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750 -#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751 -#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752 -#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759 -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e -#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f -#define SEA_mmDP_LINK_CNTL 0x1cc0 -#define SEA_mmDP0_DP_LINK_CNTL 0x1cc0 -#define SEA_mmDP1_DP_LINK_CNTL 0x1fc0 -#define SEA_mmDP2_DP_LINK_CNTL 0x42c0 -#define SEA_mmDP3_DP_LINK_CNTL 0x45c0 -#define SEA_mmDP4_DP_LINK_CNTL 0x48c0 -#define SEA_mmDP5_DP_LINK_CNTL 0x4bc0 -#define SEA_mmDP6_DP_LINK_CNTL 0x4ec0 -#define SEA_mmDP_PIXEL_FORMAT 0x1cc1 -#define SEA_mmDP0_DP_PIXEL_FORMAT 0x1cc1 -#define SEA_mmDP1_DP_PIXEL_FORMAT 0x1fc1 -#define SEA_mmDP2_DP_PIXEL_FORMAT 0x42c1 -#define SEA_mmDP3_DP_PIXEL_FORMAT 0x45c1 -#define SEA_mmDP4_DP_PIXEL_FORMAT 0x48c1 -#define SEA_mmDP5_DP_PIXEL_FORMAT 0x4bc1 -#define SEA_mmDP6_DP_PIXEL_FORMAT 0x4ec1 -#define SEA_mmDP_MSA_COLORIMETRY 0x1cda -#define SEA_mmDP0_DP_MSA_COLORIMETRY 0x1cda -#define SEA_mmDP1_DP_MSA_COLORIMETRY 0x1fda -#define SEA_mmDP2_DP_MSA_COLORIMETRY 0x42da -#define SEA_mmDP3_DP_MSA_COLORIMETRY 0x45da -#define SEA_mmDP4_DP_MSA_COLORIMETRY 0x48da -#define SEA_mmDP5_DP_MSA_COLORIMETRY 0x4bda -#define SEA_mmDP6_DP_MSA_COLORIMETRY 0x4eda -#define SEA_mmDP_CONFIG 0x1cc2 -#define SEA_mmDP0_DP_CONFIG 0x1cc2 -#define SEA_mmDP1_DP_CONFIG 0x1fc2 -#define SEA_mmDP2_DP_CONFIG 0x42c2 -#define SEA_mmDP3_DP_CONFIG 0x45c2 -#define SEA_mmDP4_DP_CONFIG 0x48c2 -#define SEA_mmDP5_DP_CONFIG 0x4bc2 -#define SEA_mmDP6_DP_CONFIG 0x4ec2 -#define SEA_mmDP_VID_STREAM_CNTL 0x1cc3 -#define SEA_mmDP0_DP_VID_STREAM_CNTL 0x1cc3 -#define SEA_mmDP1_DP_VID_STREAM_CNTL 0x1fc3 -#define SEA_mmDP2_DP_VID_STREAM_CNTL 0x42c3 -#define SEA_mmDP3_DP_VID_STREAM_CNTL 0x45c3 -#define SEA_mmDP4_DP_VID_STREAM_CNTL 0x48c3 -#define SEA_mmDP5_DP_VID_STREAM_CNTL 0x4bc3 -#define SEA_mmDP6_DP_VID_STREAM_CNTL 0x4ec3 -#define SEA_mmDP_STEER_FIFO 0x1cc4 -#define SEA_mmDP0_DP_STEER_FIFO 0x1cc4 -#define SEA_mmDP1_DP_STEER_FIFO 0x1fc4 -#define SEA_mmDP2_DP_STEER_FIFO 0x42c4 -#define SEA_mmDP3_DP_STEER_FIFO 0x45c4 -#define SEA_mmDP4_DP_STEER_FIFO 0x48c4 -#define SEA_mmDP5_DP_STEER_FIFO 0x4bc4 -#define SEA_mmDP6_DP_STEER_FIFO 0x4ec4 -#define SEA_mmDP_MSA_MISC 0x1cc5 -#define SEA_mmDP0_DP_MSA_MISC 0x1cc5 -#define SEA_mmDP1_DP_MSA_MISC 0x1fc5 -#define SEA_mmDP2_DP_MSA_MISC 0x42c5 -#define SEA_mmDP3_DP_MSA_MISC 0x45c5 -#define SEA_mmDP4_DP_MSA_MISC 0x48c5 -#define SEA_mmDP5_DP_MSA_MISC 0x4bc5 -#define SEA_mmDP6_DP_MSA_MISC 0x4ec5 -#define SEA_mmDP_VID_TIMING 0x1cc9 -#define SEA_mmDP0_DP_VID_TIMING 0x1cc9 -#define SEA_mmDP1_DP_VID_TIMING 0x1fc9 -#define SEA_mmDP2_DP_VID_TIMING 0x42c9 -#define SEA_mmDP3_DP_VID_TIMING 0x45c9 -#define SEA_mmDP4_DP_VID_TIMING 0x48c9 -#define SEA_mmDP5_DP_VID_TIMING 0x4bc9 -#define SEA_mmDP6_DP_VID_TIMING 0x4ec9 -#define SEA_mmDP_VID_N 0x1cca -#define SEA_mmDP0_DP_VID_N 0x1cca -#define SEA_mmDP1_DP_VID_N 0x1fca -#define SEA_mmDP2_DP_VID_N 0x42ca -#define SEA_mmDP3_DP_VID_N 0x45ca -#define SEA_mmDP4_DP_VID_N 0x48ca -#define SEA_mmDP5_DP_VID_N 0x4bca -#define SEA_mmDP6_DP_VID_N 0x4eca -#define SEA_mmDP_VID_M 0x1ccb -#define SEA_mmDP0_DP_VID_M 0x1ccb -#define SEA_mmDP1_DP_VID_M 0x1fcb -#define SEA_mmDP2_DP_VID_M 0x42cb -#define SEA_mmDP3_DP_VID_M 0x45cb -#define SEA_mmDP4_DP_VID_M 0x48cb -#define SEA_mmDP5_DP_VID_M 0x4bcb -#define SEA_mmDP6_DP_VID_M 0x4ecb -#define SEA_mmDP_LINK_FRAMING_CNTL 0x1ccc -#define SEA_mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc -#define SEA_mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc -#define SEA_mmDP2_DP_LINK_FRAMING_CNTL 0x42cc -#define SEA_mmDP3_DP_LINK_FRAMING_CNTL 0x45cc -#define SEA_mmDP4_DP_LINK_FRAMING_CNTL 0x48cc -#define SEA_mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc -#define SEA_mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc -#define SEA_mmDP_HBR2_EYE_PATTERN 0x1cc8 -#define SEA_mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8 -#define SEA_mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8 -#define SEA_mmDP2_DP_HBR2_EYE_PATTERN 0x42c8 -#define SEA_mmDP3_DP_HBR2_EYE_PATTERN 0x45c8 -#define SEA_mmDP4_DP_HBR2_EYE_PATTERN 0x48c8 -#define SEA_mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8 -#define SEA_mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8 -#define SEA_mmDP_VID_MSA_VBID 0x1ccd -#define SEA_mmDP0_DP_VID_MSA_VBID 0x1ccd -#define SEA_mmDP1_DP_VID_MSA_VBID 0x1fcd -#define SEA_mmDP2_DP_VID_MSA_VBID 0x42cd -#define SEA_mmDP3_DP_VID_MSA_VBID 0x45cd -#define SEA_mmDP4_DP_VID_MSA_VBID 0x48cd -#define SEA_mmDP5_DP_VID_MSA_VBID 0x4bcd -#define SEA_mmDP6_DP_VID_MSA_VBID 0x4ecd -#define SEA_mmDP_VID_INTERRUPT_CNTL 0x1ccf -#define SEA_mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf -#define SEA_mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf -#define SEA_mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf -#define SEA_mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf -#define SEA_mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf -#define SEA_mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf -#define SEA_mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf -#define SEA_mmDP_DPHY_CNTL 0x1cd0 -#define SEA_mmDP0_DP_DPHY_CNTL 0x1cd0 -#define SEA_mmDP1_DP_DPHY_CNTL 0x1fd0 -#define SEA_mmDP2_DP_DPHY_CNTL 0x42d0 -#define SEA_mmDP3_DP_DPHY_CNTL 0x45d0 -#define SEA_mmDP4_DP_DPHY_CNTL 0x48d0 -#define SEA_mmDP5_DP_DPHY_CNTL 0x4bd0 -#define SEA_mmDP6_DP_DPHY_CNTL 0x4ed0 -#define SEA_mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 -#define SEA_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 -#define SEA_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1 -#define SEA_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 -#define SEA_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 -#define SEA_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 -#define SEA_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1 -#define SEA_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1 -#define SEA_mmDP_DPHY_SYM0 0x1cd2 -#define SEA_mmDP0_DP_DPHY_SYM0 0x1cd2 -#define SEA_mmDP1_DP_DPHY_SYM0 0x1fd2 -#define SEA_mmDP2_DP_DPHY_SYM0 0x42d2 -#define SEA_mmDP3_DP_DPHY_SYM0 0x45d2 -#define SEA_mmDP4_DP_DPHY_SYM0 0x48d2 -#define SEA_mmDP5_DP_DPHY_SYM0 0x4bd2 -#define SEA_mmDP6_DP_DPHY_SYM0 0x4ed2 -#define SEA_mmDP_DPHY_SYM1 0x1ce0 -#define SEA_mmDP0_DP_DPHY_SYM1 0x1ce0 -#define SEA_mmDP1_DP_DPHY_SYM1 0x1fe0 -#define SEA_mmDP2_DP_DPHY_SYM1 0x42e0 -#define SEA_mmDP3_DP_DPHY_SYM1 0x45e0 -#define SEA_mmDP4_DP_DPHY_SYM1 0x48e0 -#define SEA_mmDP5_DP_DPHY_SYM1 0x4be0 -#define SEA_mmDP6_DP_DPHY_SYM1 0x4ee0 -#define SEA_mmDP_DPHY_SYM2 0x1cdf -#define SEA_mmDP0_DP_DPHY_SYM2 0x1cdf -#define SEA_mmDP1_DP_DPHY_SYM2 0x1fdf -#define SEA_mmDP2_DP_DPHY_SYM2 0x42df -#define SEA_mmDP3_DP_DPHY_SYM2 0x45df -#define SEA_mmDP4_DP_DPHY_SYM2 0x48df -#define SEA_mmDP5_DP_DPHY_SYM2 0x4bdf -#define SEA_mmDP6_DP_DPHY_SYM2 0x4edf -#define SEA_mmDP_DPHY_8B10B_CNTL 0x1cd3 -#define SEA_mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3 -#define SEA_mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3 -#define SEA_mmDP2_DP_DPHY_8B10B_CNTL 0x42d3 -#define SEA_mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 -#define SEA_mmDP4_DP_DPHY_8B10B_CNTL 0x48d3 -#define SEA_mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3 -#define SEA_mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3 -#define SEA_mmDP_DPHY_PRBS_CNTL 0x1cd4 -#define SEA_mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 -#define SEA_mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 -#define SEA_mmDP2_DP_DPHY_PRBS_CNTL 0x42d4 -#define SEA_mmDP3_DP_DPHY_PRBS_CNTL 0x45d4 -#define SEA_mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 -#define SEA_mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 -#define SEA_mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 -#define SEA_mmDP_DPHY_CRC_EN 0x1cd6 -#define SEA_mmDP0_DP_DPHY_CRC_EN 0x1cd6 -#define SEA_mmDP1_DP_DPHY_CRC_EN 0x1fd6 -#define SEA_mmDP2_DP_DPHY_CRC_EN 0x42d6 -#define SEA_mmDP3_DP_DPHY_CRC_EN 0x45d6 -#define SEA_mmDP4_DP_DPHY_CRC_EN 0x48d6 -#define SEA_mmDP5_DP_DPHY_CRC_EN 0x4bd6 -#define SEA_mmDP6_DP_DPHY_CRC_EN 0x4ed6 -#define SEA_mmDP_DPHY_CRC_CNTL 0x1cd7 -#define SEA_mmDP0_DP_DPHY_CRC_CNTL 0x1cd7 -#define SEA_mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 -#define SEA_mmDP2_DP_DPHY_CRC_CNTL 0x42d7 -#define SEA_mmDP3_DP_DPHY_CRC_CNTL 0x45d7 -#define SEA_mmDP4_DP_DPHY_CRC_CNTL 0x48d7 -#define SEA_mmDP5_DP_DPHY_CRC_CNTL 0x4bd7 -#define SEA_mmDP6_DP_DPHY_CRC_CNTL 0x4ed7 -#define SEA_mmDP_DPHY_CRC_RESULT 0x1cd8 -#define SEA_mmDP0_DP_DPHY_CRC_RESULT 0x1cd8 -#define SEA_mmDP1_DP_DPHY_CRC_RESULT 0x1fd8 -#define SEA_mmDP2_DP_DPHY_CRC_RESULT 0x42d8 -#define SEA_mmDP3_DP_DPHY_CRC_RESULT 0x45d8 -#define SEA_mmDP4_DP_DPHY_CRC_RESULT 0x48d8 -#define SEA_mmDP5_DP_DPHY_CRC_RESULT 0x4bd8 -#define SEA_mmDP6_DP_DPHY_CRC_RESULT 0x4ed8 -#define SEA_mmDP_DPHY_CRC_MST_CNTL 0x1cc6 -#define SEA_mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6 -#define SEA_mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6 -#define SEA_mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6 -#define SEA_mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6 -#define SEA_mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6 -#define SEA_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6 -#define SEA_mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6 -#define SEA_mmDP_DPHY_CRC_MST_STATUS 0x1cc7 -#define SEA_mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7 -#define SEA_mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7 -#define SEA_mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7 -#define SEA_mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7 -#define SEA_mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7 -#define SEA_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7 -#define SEA_mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7 -#define SEA_mmDP_DPHY_FAST_TRAINING 0x1cce -#define SEA_mmDP0_DP_DPHY_FAST_TRAINING 0x1cce -#define SEA_mmDP1_DP_DPHY_FAST_TRAINING 0x1fce -#define SEA_mmDP2_DP_DPHY_FAST_TRAINING 0x42ce -#define SEA_mmDP3_DP_DPHY_FAST_TRAINING 0x45ce -#define SEA_mmDP4_DP_DPHY_FAST_TRAINING 0x48ce -#define SEA_mmDP5_DP_DPHY_FAST_TRAINING 0x4bce -#define SEA_mmDP6_DP_DPHY_FAST_TRAINING 0x4ece -#define SEA_mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9 -#define SEA_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9 -#define SEA_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9 -#define SEA_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9 -#define SEA_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9 -#define SEA_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9 -#define SEA_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9 -#define SEA_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9 -#define SEA_mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea -#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea -#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea -#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea -#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea -#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea -#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea -#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea -#define SEA_mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb -#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb -#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb -#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb -#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb -#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb -#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb -#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb -#define SEA_mmDP_SEC_CNTL 0x1ca0 -#define SEA_mmDP0_DP_SEC_CNTL 0x1ca0 -#define SEA_mmDP1_DP_SEC_CNTL 0x1fa0 -#define SEA_mmDP2_DP_SEC_CNTL 0x42a0 -#define SEA_mmDP3_DP_SEC_CNTL 0x45a0 -#define SEA_mmDP4_DP_SEC_CNTL 0x48a0 -#define SEA_mmDP5_DP_SEC_CNTL 0x4ba0 -#define SEA_mmDP6_DP_SEC_CNTL 0x4ea0 -#define SEA_mmDP_SEC_CNTL1 0x1cab -#define SEA_mmDP0_DP_SEC_CNTL1 0x1cab -#define SEA_mmDP1_DP_SEC_CNTL1 0x1fab -#define SEA_mmDP2_DP_SEC_CNTL1 0x42ab -#define SEA_mmDP3_DP_SEC_CNTL1 0x45ab -#define SEA_mmDP4_DP_SEC_CNTL1 0x48ab -#define SEA_mmDP5_DP_SEC_CNTL1 0x4bab -#define SEA_mmDP6_DP_SEC_CNTL1 0x4eab -#define SEA_mmDP_SEC_FRAMING1 0x1ca1 -#define SEA_mmDP0_DP_SEC_FRAMING1 0x1ca1 -#define SEA_mmDP1_DP_SEC_FRAMING1 0x1fa1 -#define SEA_mmDP2_DP_SEC_FRAMING1 0x42a1 -#define SEA_mmDP3_DP_SEC_FRAMING1 0x45a1 -#define SEA_mmDP4_DP_SEC_FRAMING1 0x48a1 -#define SEA_mmDP5_DP_SEC_FRAMING1 0x4ba1 -#define SEA_mmDP6_DP_SEC_FRAMING1 0x4ea1 -#define SEA_mmDP_SEC_FRAMING2 0x1ca2 -#define SEA_mmDP0_DP_SEC_FRAMING2 0x1ca2 -#define SEA_mmDP1_DP_SEC_FRAMING2 0x1fa2 -#define SEA_mmDP2_DP_SEC_FRAMING2 0x42a2 -#define SEA_mmDP3_DP_SEC_FRAMING2 0x45a2 -#define SEA_mmDP4_DP_SEC_FRAMING2 0x48a2 -#define SEA_mmDP5_DP_SEC_FRAMING2 0x4ba2 -#define SEA_mmDP6_DP_SEC_FRAMING2 0x4ea2 -#define SEA_mmDP_SEC_FRAMING3 0x1ca3 -#define SEA_mmDP0_DP_SEC_FRAMING3 0x1ca3 -#define SEA_mmDP1_DP_SEC_FRAMING3 0x1fa3 -#define SEA_mmDP2_DP_SEC_FRAMING3 0x42a3 -#define SEA_mmDP3_DP_SEC_FRAMING3 0x45a3 -#define SEA_mmDP4_DP_SEC_FRAMING3 0x48a3 -#define SEA_mmDP5_DP_SEC_FRAMING3 0x4ba3 -#define SEA_mmDP6_DP_SEC_FRAMING3 0x4ea3 -#define SEA_mmDP_SEC_FRAMING4 0x1ca4 -#define SEA_mmDP0_DP_SEC_FRAMING4 0x1ca4 -#define SEA_mmDP1_DP_SEC_FRAMING4 0x1fa4 -#define SEA_mmDP2_DP_SEC_FRAMING4 0x42a4 -#define SEA_mmDP3_DP_SEC_FRAMING4 0x45a4 -#define SEA_mmDP4_DP_SEC_FRAMING4 0x48a4 -#define SEA_mmDP5_DP_SEC_FRAMING4 0x4ba4 -#define SEA_mmDP6_DP_SEC_FRAMING4 0x4ea4 -#define SEA_mmDP_SEC_AUD_N 0x1ca5 -#define SEA_mmDP0_DP_SEC_AUD_N 0x1ca5 -#define SEA_mmDP1_DP_SEC_AUD_N 0x1fa5 -#define SEA_mmDP2_DP_SEC_AUD_N 0x42a5 -#define SEA_mmDP3_DP_SEC_AUD_N 0x45a5 -#define SEA_mmDP4_DP_SEC_AUD_N 0x48a5 -#define SEA_mmDP5_DP_SEC_AUD_N 0x4ba5 -#define SEA_mmDP6_DP_SEC_AUD_N 0x4ea5 -#define SEA_mmDP_SEC_AUD_N_READBACK 0x1ca6 -#define SEA_mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6 -#define SEA_mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6 -#define SEA_mmDP2_DP_SEC_AUD_N_READBACK 0x42a6 -#define SEA_mmDP3_DP_SEC_AUD_N_READBACK 0x45a6 -#define SEA_mmDP4_DP_SEC_AUD_N_READBACK 0x48a6 -#define SEA_mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6 -#define SEA_mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6 -#define SEA_mmDP_SEC_AUD_M 0x1ca7 -#define SEA_mmDP0_DP_SEC_AUD_M 0x1ca7 -#define SEA_mmDP1_DP_SEC_AUD_M 0x1fa7 -#define SEA_mmDP2_DP_SEC_AUD_M 0x42a7 -#define SEA_mmDP3_DP_SEC_AUD_M 0x45a7 -#define SEA_mmDP4_DP_SEC_AUD_M 0x48a7 -#define SEA_mmDP5_DP_SEC_AUD_M 0x4ba7 -#define SEA_mmDP6_DP_SEC_AUD_M 0x4ea7 -#define SEA_mmDP_SEC_AUD_M_READBACK 0x1ca8 -#define SEA_mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8 -#define SEA_mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8 -#define SEA_mmDP2_DP_SEC_AUD_M_READBACK 0x42a8 -#define SEA_mmDP3_DP_SEC_AUD_M_READBACK 0x45a8 -#define SEA_mmDP4_DP_SEC_AUD_M_READBACK 0x48a8 -#define SEA_mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8 -#define SEA_mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8 -#define SEA_mmDP_SEC_TIMESTAMP 0x1ca9 -#define SEA_mmDP0_DP_SEC_TIMESTAMP 0x1ca9 -#define SEA_mmDP1_DP_SEC_TIMESTAMP 0x1fa9 -#define SEA_mmDP2_DP_SEC_TIMESTAMP 0x42a9 -#define SEA_mmDP3_DP_SEC_TIMESTAMP 0x45a9 -#define SEA_mmDP4_DP_SEC_TIMESTAMP 0x48a9 -#define SEA_mmDP5_DP_SEC_TIMESTAMP 0x4ba9 -#define SEA_mmDP6_DP_SEC_TIMESTAMP 0x4ea9 -#define SEA_mmDP_SEC_PACKET_CNTL 0x1caa -#define SEA_mmDP0_DP_SEC_PACKET_CNTL 0x1caa -#define SEA_mmDP1_DP_SEC_PACKET_CNTL 0x1faa -#define SEA_mmDP2_DP_SEC_PACKET_CNTL 0x42aa -#define SEA_mmDP3_DP_SEC_PACKET_CNTL 0x45aa -#define SEA_mmDP4_DP_SEC_PACKET_CNTL 0x48aa -#define SEA_mmDP5_DP_SEC_PACKET_CNTL 0x4baa -#define SEA_mmDP6_DP_SEC_PACKET_CNTL 0x4eaa -#define SEA_mmDP_MSE_RATE_CNTL 0x1ce1 -#define SEA_mmDP0_DP_MSE_RATE_CNTL 0x1ce1 -#define SEA_mmDP1_DP_MSE_RATE_CNTL 0x1fe1 -#define SEA_mmDP2_DP_MSE_RATE_CNTL 0x42e1 -#define SEA_mmDP3_DP_MSE_RATE_CNTL 0x45e1 -#define SEA_mmDP4_DP_MSE_RATE_CNTL 0x48e1 -#define SEA_mmDP5_DP_MSE_RATE_CNTL 0x4be1 -#define SEA_mmDP6_DP_MSE_RATE_CNTL 0x4ee1 -#define SEA_mmDP_MSE_RATE_UPDATE 0x1ce3 -#define SEA_mmDP0_DP_MSE_RATE_UPDATE 0x1ce3 -#define SEA_mmDP1_DP_MSE_RATE_UPDATE 0x1fe3 -#define SEA_mmDP2_DP_MSE_RATE_UPDATE 0x42e3 -#define SEA_mmDP3_DP_MSE_RATE_UPDATE 0x45e3 -#define SEA_mmDP4_DP_MSE_RATE_UPDATE 0x48e3 -#define SEA_mmDP5_DP_MSE_RATE_UPDATE 0x4be3 -#define SEA_mmDP6_DP_MSE_RATE_UPDATE 0x4ee3 -#define SEA_mmDP_MSE_SAT0 0x1ce4 -#define SEA_mmDP0_DP_MSE_SAT0 0x1ce4 -#define SEA_mmDP1_DP_MSE_SAT0 0x1fe4 -#define SEA_mmDP2_DP_MSE_SAT0 0x42e4 -#define SEA_mmDP3_DP_MSE_SAT0 0x45e4 -#define SEA_mmDP4_DP_MSE_SAT0 0x48e4 -#define SEA_mmDP5_DP_MSE_SAT0 0x4be4 -#define SEA_mmDP6_DP_MSE_SAT0 0x4ee4 -#define SEA_mmDP_MSE_SAT1 0x1ce5 -#define SEA_mmDP0_DP_MSE_SAT1 0x1ce5 -#define SEA_mmDP1_DP_MSE_SAT1 0x1fe5 -#define SEA_mmDP2_DP_MSE_SAT1 0x42e5 -#define SEA_mmDP3_DP_MSE_SAT1 0x45e5 -#define SEA_mmDP4_DP_MSE_SAT1 0x48e5 -#define SEA_mmDP5_DP_MSE_SAT1 0x4be5 -#define SEA_mmDP6_DP_MSE_SAT1 0x4ee5 -#define SEA_mmDP_MSE_SAT2 0x1ce6 -#define SEA_mmDP0_DP_MSE_SAT2 0x1ce6 -#define SEA_mmDP1_DP_MSE_SAT2 0x1fe6 -#define SEA_mmDP2_DP_MSE_SAT2 0x42e6 -#define SEA_mmDP3_DP_MSE_SAT2 0x45e6 -#define SEA_mmDP4_DP_MSE_SAT2 0x48e6 -#define SEA_mmDP5_DP_MSE_SAT2 0x4be6 -#define SEA_mmDP6_DP_MSE_SAT2 0x4ee6 -#define SEA_mmDP_MSE_SAT_UPDATE 0x1ce7 -#define SEA_mmDP0_DP_MSE_SAT_UPDATE 0x1ce7 -#define SEA_mmDP1_DP_MSE_SAT_UPDATE 0x1fe7 -#define SEA_mmDP2_DP_MSE_SAT_UPDATE 0x42e7 -#define SEA_mmDP3_DP_MSE_SAT_UPDATE 0x45e7 -#define SEA_mmDP4_DP_MSE_SAT_UPDATE 0x48e7 -#define SEA_mmDP5_DP_MSE_SAT_UPDATE 0x4be7 -#define SEA_mmDP6_DP_MSE_SAT_UPDATE 0x4ee7 -#define SEA_mmDP_MSE_LINK_TIMING 0x1ce8 -#define SEA_mmDP0_DP_MSE_LINK_TIMING 0x1ce8 -#define SEA_mmDP1_DP_MSE_LINK_TIMING 0x1fe8 -#define SEA_mmDP2_DP_MSE_LINK_TIMING 0x42e8 -#define SEA_mmDP3_DP_MSE_LINK_TIMING 0x45e8 -#define SEA_mmDP4_DP_MSE_LINK_TIMING 0x48e8 -#define SEA_mmDP5_DP_MSE_LINK_TIMING 0x4be8 -#define SEA_mmDP6_DP_MSE_LINK_TIMING 0x4ee8 -#define SEA_mmDP_MSE_MISC_CNTL 0x1cdb -#define SEA_mmDP0_DP_MSE_MISC_CNTL 0x1cdb -#define SEA_mmDP1_DP_MSE_MISC_CNTL 0x1fdb -#define SEA_mmDP2_DP_MSE_MISC_CNTL 0x42db -#define SEA_mmDP3_DP_MSE_MISC_CNTL 0x45db -#define SEA_mmDP4_DP_MSE_MISC_CNTL 0x48db -#define SEA_mmDP5_DP_MSE_MISC_CNTL 0x4bdb -#define SEA_mmDP6_DP_MSE_MISC_CNTL 0x4edb -#define SEA_mmDP_TEST_DEBUG_INDEX 0x1cfc -#define SEA_mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc -#define SEA_mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc -#define SEA_mmDP2_DP_TEST_DEBUG_INDEX 0x42fc -#define SEA_mmDP3_DP_TEST_DEBUG_INDEX 0x45fc -#define SEA_mmDP4_DP_TEST_DEBUG_INDEX 0x48fc -#define SEA_mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc -#define SEA_mmDP6_DP_TEST_DEBUG_INDEX 0x4efc -#define SEA_mmDP_TEST_DEBUG_DATA 0x1cfd -#define SEA_mmDP0_DP_TEST_DEBUG_DATA 0x1cfd -#define SEA_mmDP1_DP_TEST_DEBUG_DATA 0x1ffd -#define SEA_mmDP2_DP_TEST_DEBUG_DATA 0x42fd -#define SEA_mmDP3_DP_TEST_DEBUG_DATA 0x45fd -#define SEA_mmDP4_DP_TEST_DEBUG_DATA 0x48fd -#define SEA_mmDP5_DP_TEST_DEBUG_DATA 0x4bfd -#define SEA_mmDP6_DP_TEST_DEBUG_DATA 0x4efd -#define SEA_mmAUX_CONTROL 0x1880 -#define SEA_mmDP_AUX0_AUX_CONTROL 0x1880 -#define SEA_mmDP_AUX1_AUX_CONTROL 0x1894 -#define SEA_mmDP_AUX2_AUX_CONTROL 0x18a8 -#define SEA_mmDP_AUX3_AUX_CONTROL 0x18c0 -#define SEA_mmDP_AUX4_AUX_CONTROL 0x18d4 -#define SEA_mmDP_AUX5_AUX_CONTROL 0x18e8 -#define SEA_mmAUX_SW_CONTROL 0x1881 -#define SEA_mmDP_AUX0_AUX_SW_CONTROL 0x1881 -#define SEA_mmDP_AUX1_AUX_SW_CONTROL 0x1895 -#define SEA_mmDP_AUX2_AUX_SW_CONTROL 0x18a9 -#define SEA_mmDP_AUX3_AUX_SW_CONTROL 0x18c1 -#define SEA_mmDP_AUX4_AUX_SW_CONTROL 0x18d5 -#define SEA_mmDP_AUX5_AUX_SW_CONTROL 0x18e9 -#define SEA_mmAUX_ARB_CONTROL 0x1882 -#define SEA_mmDP_AUX0_AUX_ARB_CONTROL 0x1882 -#define SEA_mmDP_AUX1_AUX_ARB_CONTROL 0x1896 -#define SEA_mmDP_AUX2_AUX_ARB_CONTROL 0x18aa -#define SEA_mmDP_AUX3_AUX_ARB_CONTROL 0x18c2 -#define SEA_mmDP_AUX4_AUX_ARB_CONTROL 0x18d6 -#define SEA_mmDP_AUX5_AUX_ARB_CONTROL 0x18ea -#define SEA_mmAUX_INTERRUPT_CONTROL 0x1883 -#define SEA_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 -#define SEA_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 -#define SEA_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab -#define SEA_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3 -#define SEA_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7 -#define SEA_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb -#define SEA_mmAUX_SW_STATUS 0x1884 -#define SEA_mmDP_AUX0_AUX_SW_STATUS 0x1884 -#define SEA_mmDP_AUX1_AUX_SW_STATUS 0x1898 -#define SEA_mmDP_AUX2_AUX_SW_STATUS 0x18ac -#define SEA_mmDP_AUX3_AUX_SW_STATUS 0x18c4 -#define SEA_mmDP_AUX4_AUX_SW_STATUS 0x18d8 -#define SEA_mmDP_AUX5_AUX_SW_STATUS 0x18ec -#define SEA_mmAUX_LS_STATUS 0x1885 -#define SEA_mmDP_AUX0_AUX_LS_STATUS 0x1885 -#define SEA_mmDP_AUX1_AUX_LS_STATUS 0x1899 -#define SEA_mmDP_AUX2_AUX_LS_STATUS 0x18ad -#define SEA_mmDP_AUX3_AUX_LS_STATUS 0x18c5 -#define SEA_mmDP_AUX4_AUX_LS_STATUS 0x18d9 -#define SEA_mmDP_AUX5_AUX_LS_STATUS 0x18ed -#define SEA_mmAUX_SW_DATA 0x1886 -#define SEA_mmDP_AUX0_AUX_SW_DATA 0x1886 -#define SEA_mmDP_AUX1_AUX_SW_DATA 0x189a -#define SEA_mmDP_AUX2_AUX_SW_DATA 0x18ae -#define SEA_mmDP_AUX3_AUX_SW_DATA 0x18c6 -#define SEA_mmDP_AUX4_AUX_SW_DATA 0x18da -#define SEA_mmDP_AUX5_AUX_SW_DATA 0x18ee -#define SEA_mmAUX_LS_DATA 0x1887 -#define SEA_mmDP_AUX0_AUX_LS_DATA 0x1887 -#define SEA_mmDP_AUX1_AUX_LS_DATA 0x189b -#define SEA_mmDP_AUX2_AUX_LS_DATA 0x18af -#define SEA_mmDP_AUX3_AUX_LS_DATA 0x18c7 -#define SEA_mmDP_AUX4_AUX_LS_DATA 0x18db -#define SEA_mmDP_AUX5_AUX_LS_DATA 0x18ef -#define SEA_mmAUX_DPHY_TX_REF_CONTROL 0x1888 -#define SEA_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 -#define SEA_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c -#define SEA_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0 -#define SEA_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8 -#define SEA_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc -#define SEA_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0 -#define SEA_mmAUX_DPHY_TX_CONTROL 0x1889 -#define SEA_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 -#define SEA_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d -#define SEA_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1 -#define SEA_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9 -#define SEA_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd -#define SEA_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1 -#define SEA_mmAUX_DPHY_RX_CONTROL0 0x188a -#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a -#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e -#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2 -#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca -#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de -#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2 -#define SEA_mmAUX_DPHY_RX_CONTROL1 0x188b -#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b -#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f -#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3 -#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb -#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df -#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3 -#define SEA_mmAUX_DPHY_TX_STATUS 0x188c -#define SEA_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c -#define SEA_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0 -#define SEA_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4 -#define SEA_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc -#define SEA_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0 -#define SEA_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4 -#define SEA_mmAUX_DPHY_RX_STATUS 0x188d -#define SEA_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d -#define SEA_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1 -#define SEA_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5 -#define SEA_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd -#define SEA_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1 -#define SEA_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5 -#define SEA_mmAUX_GTC_SYNC_CONTROL 0x188e -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6 -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6 -#define SEA_mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7 -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7 -#define SEA_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8 -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0 -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8 -#define SEA_mmAUX_GTC_SYNC_STATUS 0x1891 -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891 -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9 -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1 -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9 -#define SEA_mmAUX_GTC_SYNC_DATA 0x1892 -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892 -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2 -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa -#define SEA_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 -#define SEA_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 -#define SEA_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7 -#define SEA_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb -#define SEA_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3 -#define SEA_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7 -#define SEA_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb -#define SEA_mmDVO_ENABLE 0x1858 -#define SEA_mmDVO_SOURCE_SELECT 0x1859 -#define SEA_mmDVO_OUTPUT 0x185a -#define SEA_mmDVO_CONTROL 0x185b -#define SEA_mmDVO_CRC_EN 0x185c -#define SEA_mmDVO_CRC2_SIG_MASK 0x185d -#define SEA_mmDVO_CRC2_SIG_RESULT 0x185e -#define SEA_mmDVO_FIFO_ERROR_STATUS 0x185f -#define SEA_mmFBC_CNTL 0x16d0 -#define SEA_mmFBC_IDLE_MASK 0x16d1 -#define SEA_mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2 -#define SEA_mmFBC_START_STOP_DELAY 0x16d3 -#define SEA_mmFBC_COMP_CNTL 0x16d4 -#define SEA_mmFBC_COMP_MODE 0x16d5 -#define SEA_mmFBC_DEBUG0 0x16d6 -#define SEA_mmFBC_DEBUG1 0x16d7 -#define SEA_mmFBC_DEBUG2 0x16d8 -#define SEA_mmFBC_IND_LUT0 0x16d9 -#define SEA_mmFBC_IND_LUT1 0x16da -#define SEA_mmFBC_IND_LUT2 0x16db -#define SEA_mmFBC_IND_LUT3 0x16dc -#define SEA_mmFBC_IND_LUT4 0x16dd -#define SEA_mmFBC_IND_LUT5 0x16de -#define SEA_mmFBC_IND_LUT6 0x16df -#define SEA_mmFBC_IND_LUT7 0x16e0 -#define SEA_mmFBC_IND_LUT8 0x16e1 -#define SEA_mmFBC_IND_LUT9 0x16e2 -#define SEA_mmFBC_IND_LUT10 0x16e3 -#define SEA_mmFBC_IND_LUT11 0x16e4 -#define SEA_mmFBC_IND_LUT12 0x16e5 -#define SEA_mmFBC_IND_LUT13 0x16e6 -#define SEA_mmFBC_IND_LUT14 0x16e7 -#define SEA_mmFBC_IND_LUT15 0x16e8 -#define SEA_mmFBC_CSM_REGION_OFFSET_01 0x16e9 -#define SEA_mmFBC_CSM_REGION_OFFSET_23 0x16ea -#define SEA_mmFBC_CLIENT_REGION_MASK 0x16eb -#define SEA_mmFBC_DEBUG_COMP 0x16ec -#define SEA_mmFBC_DEBUG_CSR 0x16ed -#define SEA_mmFBC_DEBUG_CSR_RDATA 0x16ee -#define SEA_mmFBC_DEBUG_CSR_WDATA 0x16ef -#define SEA_mmFBC_DEBUG_CSR_RDATA_HI 0x16f6 -#define SEA_mmFBC_DEBUG_CSR_WDATA_HI 0x16f7 -#define SEA_mmFBC_MISC 0x16f0 -#define SEA_mmFBC_STATUS 0x16f1 -#define SEA_mmFBC_TEST_DEBUG_INDEX 0x16f4 -#define SEA_mmFBC_TEST_DEBUG_DATA 0x16f5 -#define SEA_mmFMT_CLAMP_COMPONENT_R 0x1be8 -#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 -#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8 -#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8 -#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8 -#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8 -#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8 -#define SEA_mmFMT_CLAMP_COMPONENT_G 0x1be9 -#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 -#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9 -#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9 -#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9 -#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9 -#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9 -#define SEA_mmFMT_CLAMP_COMPONENT_B 0x1bea -#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea -#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea -#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea -#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea -#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea -#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea -#define SEA_mmFMT_DYNAMIC_EXP_CNTL 0x1bed -#define SEA_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed -#define SEA_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed -#define SEA_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed -#define SEA_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed -#define SEA_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed -#define SEA_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed -#define SEA_mmFMT_CONTROL 0x1bee -#define SEA_mmFMT0_FMT_CONTROL 0x1bee -#define SEA_mmFMT1_FMT_CONTROL 0x1eee -#define SEA_mmFMT2_FMT_CONTROL 0x41ee -#define SEA_mmFMT3_FMT_CONTROL 0x44ee -#define SEA_mmFMT4_FMT_CONTROL 0x47ee -#define SEA_mmFMT5_FMT_CONTROL 0x4aee -#define SEA_mmFMT_FORCE_OUTPUT_CNTL 0x1bef -#define SEA_mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef -#define SEA_mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef -#define SEA_mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef -#define SEA_mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef -#define SEA_mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef -#define SEA_mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef -#define SEA_mmFMT_FORCE_DATA_0_1 0x1bf0 -#define SEA_mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 -#define SEA_mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0 -#define SEA_mmFMT2_FMT_FORCE_DATA_0_1 0x41f0 -#define SEA_mmFMT3_FMT_FORCE_DATA_0_1 0x44f0 -#define SEA_mmFMT4_FMT_FORCE_DATA_0_1 0x47f0 -#define SEA_mmFMT5_FMT_FORCE_DATA_0_1 0x4af0 -#define SEA_mmFMT_FORCE_DATA_2_3 0x1bf1 -#define SEA_mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 -#define SEA_mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1 -#define SEA_mmFMT2_FMT_FORCE_DATA_2_3 0x41f1 -#define SEA_mmFMT3_FMT_FORCE_DATA_2_3 0x44f1 -#define SEA_mmFMT4_FMT_FORCE_DATA_2_3 0x47f1 -#define SEA_mmFMT5_FMT_FORCE_DATA_2_3 0x4af1 -#define SEA_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 -#define SEA_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 -#define SEA_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2 -#define SEA_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2 -#define SEA_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2 -#define SEA_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2 -#define SEA_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2 -#define SEA_mmFMT_DITHER_RAND_R_SEED 0x1bf3 -#define SEA_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 -#define SEA_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3 -#define SEA_mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3 -#define SEA_mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3 -#define SEA_mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3 -#define SEA_mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3 -#define SEA_mmFMT_DITHER_RAND_G_SEED 0x1bf4 -#define SEA_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 -#define SEA_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4 -#define SEA_mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4 -#define SEA_mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4 -#define SEA_mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4 -#define SEA_mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4 -#define SEA_mmFMT_DITHER_RAND_B_SEED 0x1bf5 -#define SEA_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 -#define SEA_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5 -#define SEA_mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5 -#define SEA_mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5 -#define SEA_mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5 -#define SEA_mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5 -#define SEA_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6 -#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 -#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6 -#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6 -#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6 -#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7 -#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 -#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7 -#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7 -#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7 -#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8 -#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 -#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8 -#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8 -#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8 -#define SEA_mmFMT_CLAMP_CNTL 0x1bf9 -#define SEA_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 -#define SEA_mmFMT1_FMT_CLAMP_CNTL 0x1ef9 -#define SEA_mmFMT2_FMT_CLAMP_CNTL 0x41f9 -#define SEA_mmFMT3_FMT_CLAMP_CNTL 0x44f9 -#define SEA_mmFMT4_FMT_CLAMP_CNTL 0x47f9 -#define SEA_mmFMT5_FMT_CLAMP_CNTL 0x4af9 -#define SEA_mmFMT_CRC_CNTL 0x1bfa -#define SEA_mmFMT0_FMT_CRC_CNTL 0x1bfa -#define SEA_mmFMT1_FMT_CRC_CNTL 0x1efa -#define SEA_mmFMT2_FMT_CRC_CNTL 0x41fa -#define SEA_mmFMT3_FMT_CRC_CNTL 0x44fa -#define SEA_mmFMT4_FMT_CRC_CNTL 0x47fa -#define SEA_mmFMT5_FMT_CRC_CNTL 0x4afa -#define SEA_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb -#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb -#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb -#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb -#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb -#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc -#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc -#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc -#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc -#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc -#define SEA_mmFMT_CRC_SIG_RED_GREEN 0x1bfd -#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd -#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd -#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd -#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd -#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd -#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd -#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe -#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe -#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe -#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe -#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe -#define SEA_mmFMT_DEBUG_CNTL 0x1bff -#define SEA_mmFMT0_FMT_DEBUG_CNTL 0x1bff -#define SEA_mmFMT1_FMT_DEBUG_CNTL 0x1eff -#define SEA_mmFMT2_FMT_DEBUG_CNTL 0x41ff -#define SEA_mmFMT3_FMT_DEBUG_CNTL 0x44ff -#define SEA_mmFMT4_FMT_DEBUG_CNTL 0x47ff -#define SEA_mmFMT5_FMT_DEBUG_CNTL 0x4aff -#define SEA_mmFMT_TEST_DEBUG_INDEX 0x1beb -#define SEA_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb -#define SEA_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb -#define SEA_mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb -#define SEA_mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb -#define SEA_mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb -#define SEA_mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb -#define SEA_mmFMT_TEST_DEBUG_DATA 0x1bec -#define SEA_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec -#define SEA_mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec -#define SEA_mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec -#define SEA_mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec -#define SEA_mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec -#define SEA_mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec -#define SEA_ixFMT_DEBUG0 0x1 -#define SEA_ixFMT_DEBUG1 0x2 -#define SEA_ixFMT_DEBUG2 0x3 -#define SEA_ixFMT_DEBUG_ID 0x0 -#define SEA_mmLB_DATA_FORMAT 0x1ac0 -#define SEA_mmLB0_LB_DATA_FORMAT 0x1ac0 -#define SEA_mmLB1_LB_DATA_FORMAT 0x1dc0 -#define SEA_mmLB2_LB_DATA_FORMAT 0x40c0 -#define SEA_mmLB3_LB_DATA_FORMAT 0x43c0 -#define SEA_mmLB4_LB_DATA_FORMAT 0x46c0 -#define SEA_mmLB5_LB_DATA_FORMAT 0x49c0 -#define SEA_mmLB_MEMORY_CTRL 0x1ac1 -#define SEA_mmLB0_LB_MEMORY_CTRL 0x1ac1 -#define SEA_mmLB1_LB_MEMORY_CTRL 0x1dc1 -#define SEA_mmLB2_LB_MEMORY_CTRL 0x40c1 -#define SEA_mmLB3_LB_MEMORY_CTRL 0x43c1 -#define SEA_mmLB4_LB_MEMORY_CTRL 0x46c1 -#define SEA_mmLB5_LB_MEMORY_CTRL 0x49c1 -#define SEA_mmLB_MEMORY_SIZE_STATUS 0x1ac2 -#define SEA_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 -#define SEA_mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2 -#define SEA_mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2 -#define SEA_mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2 -#define SEA_mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2 -#define SEA_mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2 -#define SEA_mmLB_DESKTOP_HEIGHT 0x1ac3 -#define SEA_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 -#define SEA_mmLB1_LB_DESKTOP_HEIGHT 0x1dc3 -#define SEA_mmLB2_LB_DESKTOP_HEIGHT 0x40c3 -#define SEA_mmLB3_LB_DESKTOP_HEIGHT 0x43c3 -#define SEA_mmLB4_LB_DESKTOP_HEIGHT 0x46c3 -#define SEA_mmLB5_LB_DESKTOP_HEIGHT 0x49c3 -#define SEA_mmLB_VLINE_START_END 0x1ac4 -#define SEA_mmLB0_LB_VLINE_START_END 0x1ac4 -#define SEA_mmLB1_LB_VLINE_START_END 0x1dc4 -#define SEA_mmLB2_LB_VLINE_START_END 0x40c4 -#define SEA_mmLB3_LB_VLINE_START_END 0x43c4 -#define SEA_mmLB4_LB_VLINE_START_END 0x46c4 -#define SEA_mmLB5_LB_VLINE_START_END 0x49c4 -#define SEA_mmLB_VLINE2_START_END 0x1ac5 -#define SEA_mmLB0_LB_VLINE2_START_END 0x1ac5 -#define SEA_mmLB1_LB_VLINE2_START_END 0x1dc5 -#define SEA_mmLB2_LB_VLINE2_START_END 0x40c5 -#define SEA_mmLB3_LB_VLINE2_START_END 0x43c5 -#define SEA_mmLB4_LB_VLINE2_START_END 0x46c5 -#define SEA_mmLB5_LB_VLINE2_START_END 0x49c5 -#define SEA_mmLB_V_COUNTER 0x1ac6 -#define SEA_mmLB0_LB_V_COUNTER 0x1ac6 -#define SEA_mmLB1_LB_V_COUNTER 0x1dc6 -#define SEA_mmLB2_LB_V_COUNTER 0x40c6 -#define SEA_mmLB3_LB_V_COUNTER 0x43c6 -#define SEA_mmLB4_LB_V_COUNTER 0x46c6 -#define SEA_mmLB5_LB_V_COUNTER 0x49c6 -#define SEA_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 -#define SEA_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 -#define SEA_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7 -#define SEA_mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7 -#define SEA_mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7 -#define SEA_mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7 -#define SEA_mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7 -#define SEA_mmLB_INTERRUPT_MASK 0x1ac8 -#define SEA_mmLB0_LB_INTERRUPT_MASK 0x1ac8 -#define SEA_mmLB1_LB_INTERRUPT_MASK 0x1dc8 -#define SEA_mmLB2_LB_INTERRUPT_MASK 0x40c8 -#define SEA_mmLB3_LB_INTERRUPT_MASK 0x43c8 -#define SEA_mmLB4_LB_INTERRUPT_MASK 0x46c8 -#define SEA_mmLB5_LB_INTERRUPT_MASK 0x49c8 -#define SEA_mmLB_VLINE_STATUS 0x1ac9 -#define SEA_mmLB0_LB_VLINE_STATUS 0x1ac9 -#define SEA_mmLB1_LB_VLINE_STATUS 0x1dc9 -#define SEA_mmLB2_LB_VLINE_STATUS 0x40c9 -#define SEA_mmLB3_LB_VLINE_STATUS 0x43c9 -#define SEA_mmLB4_LB_VLINE_STATUS 0x46c9 -#define SEA_mmLB5_LB_VLINE_STATUS 0x49c9 -#define SEA_mmLB_VLINE2_STATUS 0x1aca -#define SEA_mmLB0_LB_VLINE2_STATUS 0x1aca -#define SEA_mmLB1_LB_VLINE2_STATUS 0x1dca -#define SEA_mmLB2_LB_VLINE2_STATUS 0x40ca -#define SEA_mmLB3_LB_VLINE2_STATUS 0x43ca -#define SEA_mmLB4_LB_VLINE2_STATUS 0x46ca -#define SEA_mmLB5_LB_VLINE2_STATUS 0x49ca -#define SEA_mmLB_VBLANK_STATUS 0x1acb -#define SEA_mmLB0_LB_VBLANK_STATUS 0x1acb -#define SEA_mmLB1_LB_VBLANK_STATUS 0x1dcb -#define SEA_mmLB2_LB_VBLANK_STATUS 0x40cb -#define SEA_mmLB3_LB_VBLANK_STATUS 0x43cb -#define SEA_mmLB4_LB_VBLANK_STATUS 0x46cb -#define SEA_mmLB5_LB_VBLANK_STATUS 0x49cb -#define SEA_mmLB_SYNC_RESET_SEL 0x1acc -#define SEA_mmLB0_LB_SYNC_RESET_SEL 0x1acc -#define SEA_mmLB1_LB_SYNC_RESET_SEL 0x1dcc -#define SEA_mmLB2_LB_SYNC_RESET_SEL 0x40cc -#define SEA_mmLB3_LB_SYNC_RESET_SEL 0x43cc -#define SEA_mmLB4_LB_SYNC_RESET_SEL 0x46cc -#define SEA_mmLB5_LB_SYNC_RESET_SEL 0x49cc -#define SEA_mmLB_BLACK_KEYER_R_CR 0x1acd -#define SEA_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd -#define SEA_mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd -#define SEA_mmLB2_LB_BLACK_KEYER_R_CR 0x40cd -#define SEA_mmLB3_LB_BLACK_KEYER_R_CR 0x43cd -#define SEA_mmLB4_LB_BLACK_KEYER_R_CR 0x46cd -#define SEA_mmLB5_LB_BLACK_KEYER_R_CR 0x49cd -#define SEA_mmLB_BLACK_KEYER_G_Y 0x1ace -#define SEA_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace -#define SEA_mmLB1_LB_BLACK_KEYER_G_Y 0x1dce -#define SEA_mmLB2_LB_BLACK_KEYER_G_Y 0x40ce -#define SEA_mmLB3_LB_BLACK_KEYER_G_Y 0x43ce -#define SEA_mmLB4_LB_BLACK_KEYER_G_Y 0x46ce -#define SEA_mmLB5_LB_BLACK_KEYER_G_Y 0x49ce -#define SEA_mmLB_BLACK_KEYER_B_CB 0x1acf -#define SEA_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf -#define SEA_mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf -#define SEA_mmLB2_LB_BLACK_KEYER_B_CB 0x40cf -#define SEA_mmLB3_LB_BLACK_KEYER_B_CB 0x43cf -#define SEA_mmLB4_LB_BLACK_KEYER_B_CB 0x46cf -#define SEA_mmLB5_LB_BLACK_KEYER_B_CB 0x49cf -#define SEA_mmLB_KEYER_COLOR_CTRL 0x1ad0 -#define SEA_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 -#define SEA_mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0 -#define SEA_mmLB2_LB_KEYER_COLOR_CTRL 0x40d0 -#define SEA_mmLB3_LB_KEYER_COLOR_CTRL 0x43d0 -#define SEA_mmLB4_LB_KEYER_COLOR_CTRL 0x46d0 -#define SEA_mmLB5_LB_KEYER_COLOR_CTRL 0x49d0 -#define SEA_mmLB_KEYER_COLOR_R_CR 0x1ad1 -#define SEA_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 -#define SEA_mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1 -#define SEA_mmLB2_LB_KEYER_COLOR_R_CR 0x40d1 -#define SEA_mmLB3_LB_KEYER_COLOR_R_CR 0x43d1 -#define SEA_mmLB4_LB_KEYER_COLOR_R_CR 0x46d1 -#define SEA_mmLB5_LB_KEYER_COLOR_R_CR 0x49d1 -#define SEA_mmLB_KEYER_COLOR_G_Y 0x1ad2 -#define SEA_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 -#define SEA_mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2 -#define SEA_mmLB2_LB_KEYER_COLOR_G_Y 0x40d2 -#define SEA_mmLB3_LB_KEYER_COLOR_G_Y 0x43d2 -#define SEA_mmLB4_LB_KEYER_COLOR_G_Y 0x46d2 -#define SEA_mmLB5_LB_KEYER_COLOR_G_Y 0x49d2 -#define SEA_mmLB_KEYER_COLOR_B_CB 0x1ad3 -#define SEA_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 -#define SEA_mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3 -#define SEA_mmLB2_LB_KEYER_COLOR_B_CB 0x40d3 -#define SEA_mmLB3_LB_KEYER_COLOR_B_CB 0x43d3 -#define SEA_mmLB4_LB_KEYER_COLOR_B_CB 0x46d3 -#define SEA_mmLB5_LB_KEYER_COLOR_B_CB 0x49d3 -#define SEA_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define SEA_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define SEA_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4 -#define SEA_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4 -#define SEA_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4 -#define SEA_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4 -#define SEA_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4 -#define SEA_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define SEA_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define SEA_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5 -#define SEA_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5 -#define SEA_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5 -#define SEA_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5 -#define SEA_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5 -#define SEA_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define SEA_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define SEA_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6 -#define SEA_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6 -#define SEA_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6 -#define SEA_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6 -#define SEA_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6 -#define SEA_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 -#define SEA_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 -#define SEA_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7 -#define SEA_mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7 -#define SEA_mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7 -#define SEA_mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7 -#define SEA_mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7 -#define SEA_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 -#define SEA_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 -#define SEA_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8 -#define SEA_mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8 -#define SEA_mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8 -#define SEA_mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8 -#define SEA_mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8 -#define SEA_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 -#define SEA_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 -#define SEA_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9 -#define SEA_mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9 -#define SEA_mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9 -#define SEA_mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9 -#define SEA_mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9 -#define SEA_mmLB_BUFFER_STATUS 0x1ada -#define SEA_mmLB0_LB_BUFFER_STATUS 0x1ada -#define SEA_mmLB1_LB_BUFFER_STATUS 0x1dda -#define SEA_mmLB2_LB_BUFFER_STATUS 0x40da -#define SEA_mmLB3_LB_BUFFER_STATUS 0x43da -#define SEA_mmLB4_LB_BUFFER_STATUS 0x46da -#define SEA_mmLB5_LB_BUFFER_STATUS 0x49da -#define SEA_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define SEA_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define SEA_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc -#define SEA_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc -#define SEA_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc -#define SEA_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc -#define SEA_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc -#define SEA_mmMVP_AFR_FLIP_MODE 0x1ae0 -#define SEA_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 -#define SEA_mmLB1_MVP_AFR_FLIP_MODE 0x1de0 -#define SEA_mmLB2_MVP_AFR_FLIP_MODE 0x40e0 -#define SEA_mmLB3_MVP_AFR_FLIP_MODE 0x43e0 -#define SEA_mmLB4_MVP_AFR_FLIP_MODE 0x46e0 -#define SEA_mmLB5_MVP_AFR_FLIP_MODE 0x49e0 -#define SEA_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define SEA_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define SEA_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1 -#define SEA_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 -#define SEA_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1 -#define SEA_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1 -#define SEA_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1 -#define SEA_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define SEA_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define SEA_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2 -#define SEA_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2 -#define SEA_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2 -#define SEA_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2 -#define SEA_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2 -#define SEA_mmDC_MVP_LB_CONTROL 0x1ae3 -#define SEA_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 -#define SEA_mmLB1_DC_MVP_LB_CONTROL 0x1de3 -#define SEA_mmLB2_DC_MVP_LB_CONTROL 0x40e3 -#define SEA_mmLB3_DC_MVP_LB_CONTROL 0x43e3 -#define SEA_mmLB4_DC_MVP_LB_CONTROL 0x46e3 -#define SEA_mmLB5_DC_MVP_LB_CONTROL 0x49e3 -#define SEA_mmLB_DEBUG 0x1ae4 -#define SEA_mmLB0_LB_DEBUG 0x1ae4 -#define SEA_mmLB1_LB_DEBUG 0x1de4 -#define SEA_mmLB2_LB_DEBUG 0x40e4 -#define SEA_mmLB3_LB_DEBUG 0x43e4 -#define SEA_mmLB4_LB_DEBUG 0x46e4 -#define SEA_mmLB5_LB_DEBUG 0x49e4 -#define SEA_mmLB_DEBUG2 0x1ae5 -#define SEA_mmLB0_LB_DEBUG2 0x1ae5 -#define SEA_mmLB1_LB_DEBUG2 0x1de5 -#define SEA_mmLB2_LB_DEBUG2 0x40e5 -#define SEA_mmLB3_LB_DEBUG2 0x43e5 -#define SEA_mmLB4_LB_DEBUG2 0x46e5 -#define SEA_mmLB5_LB_DEBUG2 0x49e5 -#define SEA_mmLB_DEBUG3 0x1ae6 -#define SEA_mmLB0_LB_DEBUG3 0x1ae6 -#define SEA_mmLB1_LB_DEBUG3 0x1de6 -#define SEA_mmLB2_LB_DEBUG3 0x40e6 -#define SEA_mmLB3_LB_DEBUG3 0x43e6 -#define SEA_mmLB4_LB_DEBUG3 0x46e6 -#define SEA_mmLB5_LB_DEBUG3 0x49e6 -#define SEA_mmLB_TEST_DEBUG_INDEX 0x1afe -#define SEA_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe -#define SEA_mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe -#define SEA_mmLB2_LB_TEST_DEBUG_INDEX 0x40fe -#define SEA_mmLB3_LB_TEST_DEBUG_INDEX 0x43fe -#define SEA_mmLB4_LB_TEST_DEBUG_INDEX 0x46fe -#define SEA_mmLB5_LB_TEST_DEBUG_INDEX 0x49fe -#define SEA_mmLB_TEST_DEBUG_DATA 0x1aff -#define SEA_mmLB0_LB_TEST_DEBUG_DATA 0x1aff -#define SEA_mmLB1_LB_TEST_DEBUG_DATA 0x1dff -#define SEA_mmLB2_LB_TEST_DEBUG_DATA 0x40ff -#define SEA_mmLB3_LB_TEST_DEBUG_DATA 0x43ff -#define SEA_mmLB4_LB_TEST_DEBUG_DATA 0x46ff -#define SEA_mmLB5_LB_TEST_DEBUG_DATA 0x49ff -#define SEA_mmMVP_CONTROL1 0x1680 -#define SEA_mmMVP_CONTROL2 0x1681 -#define SEA_mmMVP_FIFO_CONTROL 0x1682 -#define SEA_mmMVP_FIFO_STATUS 0x1683 -#define SEA_mmMVP_SLAVE_STATUS 0x1684 -#define SEA_mmMVP_INBAND_CNTL_CAP 0x1685 -#define SEA_mmMVP_BLACK_KEYER 0x1686 -#define SEA_mmMVP_CRC_CNTL 0x1687 -#define SEA_mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 -#define SEA_mmMVP_CRC_RESULT_RED 0x1689 -#define SEA_mmMVP_CONTROL3 0x168a -#define SEA_mmMVP_RECEIVE_CNT_CNTL1 0x168b -#define SEA_mmMVP_RECEIVE_CNT_CNTL2 0x168c -#define SEA_mmMVP_DEBUG 0x168f -#define SEA_mmMVP_TEST_DEBUG_INDEX 0x168d -#define SEA_mmMVP_TEST_DEBUG_DATA 0x168e -#define SEA_ixMVP_DEBUG_12 0xc -#define SEA_ixMVP_DEBUG_13 0xd -#define SEA_ixMVP_DEBUG_14 0xe -#define SEA_ixMVP_DEBUG_15 0xf -#define SEA_ixMVP_DEBUG_16 0x10 -#define SEA_ixMVP_DEBUG_17 0x11 -#define SEA_mmSCL_COEF_RAM_SELECT 0x1b40 -#define SEA_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 -#define SEA_mmSCL1_SCL_COEF_RAM_SELECT 0x1e40 -#define SEA_mmSCL2_SCL_COEF_RAM_SELECT 0x4140 -#define SEA_mmSCL3_SCL_COEF_RAM_SELECT 0x4440 -#define SEA_mmSCL4_SCL_COEF_RAM_SELECT 0x4740 -#define SEA_mmSCL5_SCL_COEF_RAM_SELECT 0x4a40 -#define SEA_mmSCL_COEF_RAM_TAP_DATA 0x1b41 -#define SEA_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 -#define SEA_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41 -#define SEA_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 -#define SEA_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 -#define SEA_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 -#define SEA_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 -#define SEA_mmSCL_MODE 0x1b42 -#define SEA_mmSCL0_SCL_MODE 0x1b42 -#define SEA_mmSCL1_SCL_MODE 0x1e42 -#define SEA_mmSCL2_SCL_MODE 0x4142 -#define SEA_mmSCL3_SCL_MODE 0x4442 -#define SEA_mmSCL4_SCL_MODE 0x4742 -#define SEA_mmSCL5_SCL_MODE 0x4a42 -#define SEA_mmSCL_TAP_CONTROL 0x1b43 -#define SEA_mmSCL0_SCL_TAP_CONTROL 0x1b43 -#define SEA_mmSCL1_SCL_TAP_CONTROL 0x1e43 -#define SEA_mmSCL2_SCL_TAP_CONTROL 0x4143 -#define SEA_mmSCL3_SCL_TAP_CONTROL 0x4443 -#define SEA_mmSCL4_SCL_TAP_CONTROL 0x4743 -#define SEA_mmSCL5_SCL_TAP_CONTROL 0x4a43 -#define SEA_mmSCL_CONTROL 0x1b44 -#define SEA_mmSCL0_SCL_CONTROL 0x1b44 -#define SEA_mmSCL1_SCL_CONTROL 0x1e44 -#define SEA_mmSCL2_SCL_CONTROL 0x4144 -#define SEA_mmSCL3_SCL_CONTROL 0x4444 -#define SEA_mmSCL4_SCL_CONTROL 0x4744 -#define SEA_mmSCL5_SCL_CONTROL 0x4a44 -#define SEA_mmSCL_BYPASS_CONTROL 0x1b45 -#define SEA_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 -#define SEA_mmSCL1_SCL_BYPASS_CONTROL 0x1e45 -#define SEA_mmSCL2_SCL_BYPASS_CONTROL 0x4145 -#define SEA_mmSCL3_SCL_BYPASS_CONTROL 0x4445 -#define SEA_mmSCL4_SCL_BYPASS_CONTROL 0x4745 -#define SEA_mmSCL5_SCL_BYPASS_CONTROL 0x4a45 -#define SEA_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define SEA_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define SEA_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46 -#define SEA_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 -#define SEA_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 -#define SEA_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 -#define SEA_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46 -#define SEA_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define SEA_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define SEA_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47 -#define SEA_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 -#define SEA_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 -#define SEA_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 -#define SEA_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47 -#define SEA_mmSCL_HORZ_FILTER_CONTROL 0x1b48 -#define SEA_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 -#define SEA_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48 -#define SEA_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148 -#define SEA_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448 -#define SEA_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748 -#define SEA_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48 -#define SEA_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define SEA_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define SEA_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49 -#define SEA_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 -#define SEA_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449 -#define SEA_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749 -#define SEA_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49 -#define SEA_mmSCL_HORZ_FILTER_INIT 0x1b4a -#define SEA_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a -#define SEA_mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a -#define SEA_mmSCL2_SCL_HORZ_FILTER_INIT 0x414a -#define SEA_mmSCL3_SCL_HORZ_FILTER_INIT 0x444a -#define SEA_mmSCL4_SCL_HORZ_FILTER_INIT 0x474a -#define SEA_mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a -#define SEA_mmSCL_VERT_FILTER_CONTROL 0x1b4b -#define SEA_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b -#define SEA_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b -#define SEA_mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b -#define SEA_mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b -#define SEA_mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b -#define SEA_mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b -#define SEA_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define SEA_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define SEA_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c -#define SEA_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c -#define SEA_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c -#define SEA_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c -#define SEA_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c -#define SEA_mmSCL_VERT_FILTER_INIT 0x1b4d -#define SEA_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d -#define SEA_mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d -#define SEA_mmSCL2_SCL_VERT_FILTER_INIT 0x414d -#define SEA_mmSCL3_SCL_VERT_FILTER_INIT 0x444d -#define SEA_mmSCL4_SCL_VERT_FILTER_INIT 0x474d -#define SEA_mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d -#define SEA_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e -#define SEA_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e -#define SEA_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e -#define SEA_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e -#define SEA_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e -#define SEA_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e -#define SEA_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e -#define SEA_mmSCL_ROUND_OFFSET 0x1b4f -#define SEA_mmSCL0_SCL_ROUND_OFFSET 0x1b4f -#define SEA_mmSCL1_SCL_ROUND_OFFSET 0x1e4f -#define SEA_mmSCL2_SCL_ROUND_OFFSET 0x414f -#define SEA_mmSCL3_SCL_ROUND_OFFSET 0x444f -#define SEA_mmSCL4_SCL_ROUND_OFFSET 0x474f -#define SEA_mmSCL5_SCL_ROUND_OFFSET 0x4a4f -#define SEA_mmSCL_UPDATE 0x1b51 -#define SEA_mmSCL0_SCL_UPDATE 0x1b51 -#define SEA_mmSCL1_SCL_UPDATE 0x1e51 -#define SEA_mmSCL2_SCL_UPDATE 0x4151 -#define SEA_mmSCL3_SCL_UPDATE 0x4451 -#define SEA_mmSCL4_SCL_UPDATE 0x4751 -#define SEA_mmSCL5_SCL_UPDATE 0x4a51 -#define SEA_mmSCL_F_SHARP_CONTROL 0x1b53 -#define SEA_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 -#define SEA_mmSCL1_SCL_F_SHARP_CONTROL 0x1e53 -#define SEA_mmSCL2_SCL_F_SHARP_CONTROL 0x4153 -#define SEA_mmSCL3_SCL_F_SHARP_CONTROL 0x4453 -#define SEA_mmSCL4_SCL_F_SHARP_CONTROL 0x4753 -#define SEA_mmSCL5_SCL_F_SHARP_CONTROL 0x4a53 -#define SEA_mmSCL_ALU_CONTROL 0x1b54 -#define SEA_mmSCL0_SCL_ALU_CONTROL 0x1b54 -#define SEA_mmSCL1_SCL_ALU_CONTROL 0x1e54 -#define SEA_mmSCL2_SCL_ALU_CONTROL 0x4154 -#define SEA_mmSCL3_SCL_ALU_CONTROL 0x4454 -#define SEA_mmSCL4_SCL_ALU_CONTROL 0x4754 -#define SEA_mmSCL5_SCL_ALU_CONTROL 0x4a54 -#define SEA_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define SEA_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define SEA_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55 -#define SEA_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 -#define SEA_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 -#define SEA_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 -#define SEA_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55 -#define SEA_mmVIEWPORT_START 0x1b5c -#define SEA_mmSCL0_VIEWPORT_START 0x1b5c -#define SEA_mmSCL1_VIEWPORT_START 0x1e5c -#define SEA_mmSCL2_VIEWPORT_START 0x415c -#define SEA_mmSCL3_VIEWPORT_START 0x445c -#define SEA_mmSCL4_VIEWPORT_START 0x475c -#define SEA_mmSCL5_VIEWPORT_START 0x4a5c -#define SEA_mmVIEWPORT_SIZE 0x1b5d -#define SEA_mmSCL0_VIEWPORT_SIZE 0x1b5d -#define SEA_mmSCL1_VIEWPORT_SIZE 0x1e5d -#define SEA_mmSCL2_VIEWPORT_SIZE 0x415d -#define SEA_mmSCL3_VIEWPORT_SIZE 0x445d -#define SEA_mmSCL4_VIEWPORT_SIZE 0x475d -#define SEA_mmSCL5_VIEWPORT_SIZE 0x4a5d -#define SEA_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define SEA_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define SEA_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e -#define SEA_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e -#define SEA_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e -#define SEA_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e -#define SEA_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e -#define SEA_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define SEA_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define SEA_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f -#define SEA_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f -#define SEA_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f -#define SEA_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f -#define SEA_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f -#define SEA_mmSCL_MODE_CHANGE_DET1 0x1b60 -#define SEA_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 -#define SEA_mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60 -#define SEA_mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 -#define SEA_mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 -#define SEA_mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 -#define SEA_mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60 -#define SEA_mmSCL_MODE_CHANGE_DET2 0x1b61 -#define SEA_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 -#define SEA_mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61 -#define SEA_mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 -#define SEA_mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 -#define SEA_mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 -#define SEA_mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61 -#define SEA_mmSCL_MODE_CHANGE_DET3 0x1b62 -#define SEA_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 -#define SEA_mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62 -#define SEA_mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 -#define SEA_mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 -#define SEA_mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 -#define SEA_mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62 -#define SEA_mmSCL_MODE_CHANGE_MASK 0x1b63 -#define SEA_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 -#define SEA_mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63 -#define SEA_mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 -#define SEA_mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 -#define SEA_mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 -#define SEA_mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63 -#define SEA_mmSCL_DEBUG2 0x1b69 -#define SEA_mmSCL0_SCL_DEBUG2 0x1b69 -#define SEA_mmSCL1_SCL_DEBUG2 0x1e69 -#define SEA_mmSCL2_SCL_DEBUG2 0x4169 -#define SEA_mmSCL3_SCL_DEBUG2 0x4469 -#define SEA_mmSCL4_SCL_DEBUG2 0x4769 -#define SEA_mmSCL5_SCL_DEBUG2 0x4a69 -#define SEA_mmSCL_DEBUG 0x1b6a -#define SEA_mmSCL0_SCL_DEBUG 0x1b6a -#define SEA_mmSCL1_SCL_DEBUG 0x1e6a -#define SEA_mmSCL2_SCL_DEBUG 0x416a -#define SEA_mmSCL3_SCL_DEBUG 0x446a -#define SEA_mmSCL4_SCL_DEBUG 0x476a -#define SEA_mmSCL5_SCL_DEBUG 0x4a6a -#define SEA_mmSCL_TEST_DEBUG_INDEX 0x1b6b -#define SEA_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b -#define SEA_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b -#define SEA_mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b -#define SEA_mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b -#define SEA_mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b -#define SEA_mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b -#define SEA_mmSCL_TEST_DEBUG_DATA 0x1b6c -#define SEA_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c -#define SEA_mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c -#define SEA_mmSCL2_SCL_TEST_DEBUG_DATA 0x416c -#define SEA_mmSCL3_SCL_TEST_DEBUG_DATA 0x446c -#define SEA_mmSCL4_SCL_TEST_DEBUG_DATA 0x476c -#define SEA_mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c -#define SEA_mmGENMO_WT 0xf0 -#define SEA_mmGENMO_RD 0xf3 -#define SEA_mmGENENB 0xf0 -#define SEA_mmGENFC_WT 0xee -#define SEA_mmVGA0_GENFC_WT 0xee -#define SEA_mmVGA1_GENFC_WT 0xf6 -#define SEA_mmGENFC_RD 0xf2 -#define SEA_mmGENS0 0xf0 -#define SEA_mmGENS1 0xee -#define SEA_mmVGA0_GENS1 0xee -#define SEA_mmVGA1_GENS1 0xf6 -#define SEA_mmDAC_DATA 0xf2 -#define SEA_mmDAC_MASK 0xf1 -#define SEA_mmDAC_R_INDEX 0xf1 -#define SEA_mmDAC_W_INDEX 0xf2 -#define SEA_mmSEQ8_IDX 0xf1 -#define SEA_mmSEQ8_DATA 0xf1 -#define SEA_ixSEQ00 0x0 -#define SEA_ixSEQ01 0x1 -#define SEA_ixSEQ02 0x2 -#define SEA_ixSEQ03 0x3 -#define SEA_ixSEQ04 0x4 -#define SEA_mmCRTC8_IDX 0xed -#define SEA_mmVGA0_CRTC8_IDX 0xed -#define SEA_mmVGA1_CRTC8_IDX 0xf5 -#define SEA_mmCRTC8_DATA 0xed -#define SEA_mmVGA0_CRTC8_DATA 0xed -#define SEA_mmVGA1_CRTC8_DATA 0xf5 -#define SEA_ixCRT00 0x0 -#define SEA_ixCRT01 0x1 -#define SEA_ixCRT02 0x2 -#define SEA_ixCRT03 0x3 -#define SEA_ixCRT04 0x4 -#define SEA_ixCRT05 0x5 -#define SEA_ixCRT06 0x6 -#define SEA_ixCRT07 0x7 -#define SEA_ixCRT08 0x8 -#define SEA_ixCRT09 0x9 -#define SEA_ixCRT0A 0xa -#define SEA_ixCRT0B 0xb -#define SEA_ixCRT0C 0xc -#define SEA_ixCRT0D 0xd -#define SEA_ixCRT0E 0xe -#define SEA_ixCRT0F 0xf -#define SEA_ixCRT10 0x10 -#define SEA_ixCRT11 0x11 -#define SEA_ixCRT12 0x12 -#define SEA_ixCRT13 0x13 -#define SEA_ixCRT14 0x14 -#define SEA_ixCRT15 0x15 -#define SEA_ixCRT16 0x16 -#define SEA_ixCRT17 0x17 -#define SEA_ixCRT18 0x18 -#define SEA_ixCRT1E 0x1e -#define SEA_ixCRT1F 0x1f -#define SEA_ixCRT22 0x22 -#define SEA_mmGRPH8_IDX 0xf3 -#define SEA_mmGRPH8_DATA 0xf3 -#define SEA_ixGRA00 0x0 -#define SEA_ixGRA01 0x1 -#define SEA_ixGRA02 0x2 -#define SEA_ixGRA03 0x3 -#define SEA_ixGRA04 0x4 -#define SEA_ixGRA05 0x5 -#define SEA_ixGRA06 0x6 -#define SEA_ixGRA07 0x7 -#define SEA_ixGRA08 0x8 -#define SEA_mmATTRX 0xf0 -#define SEA_mmATTRDW 0xf0 -#define SEA_mmATTRDR 0xf0 -#define SEA_ixATTR00 0x0 -#define SEA_ixATTR01 0x1 -#define SEA_ixATTR02 0x2 -#define SEA_ixATTR03 0x3 -#define SEA_ixATTR04 0x4 -#define SEA_ixATTR05 0x5 -#define SEA_ixATTR06 0x6 -#define SEA_ixATTR07 0x7 -#define SEA_ixATTR08 0x8 -#define SEA_ixATTR09 0x9 -#define SEA_ixATTR0A 0xa -#define SEA_ixATTR0B 0xb -#define SEA_ixATTR0C 0xc -#define SEA_ixATTR0D 0xd -#define SEA_ixATTR0E 0xe -#define SEA_ixATTR0F 0xf -#define SEA_ixATTR10 0x10 -#define SEA_ixATTR11 0x11 -#define SEA_ixATTR12 0x12 -#define SEA_ixATTR13 0x13 -#define SEA_ixATTR14 0x14 -#define SEA_mmVGA_RENDER_CONTROL 0xc0 -#define SEA_mmVGA_SOURCE_SELECT 0xfc -#define SEA_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 -#define SEA_mmVGA_MODE_CONTROL 0xc2 -#define SEA_mmVGA_SURFACE_PITCH_SELECT 0xc3 -#define SEA_mmVGA_MEMORY_BASE_ADDRESS 0xc4 -#define SEA_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 -#define SEA_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 -#define SEA_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 -#define SEA_mmVGA_HDP_CONTROL 0xca -#define SEA_mmVGA_CACHE_CONTROL 0xcb -#define SEA_mmD1VGA_CONTROL 0xcc -#define SEA_mmD2VGA_CONTROL 0xce -#define SEA_mmD3VGA_CONTROL 0xf8 -#define SEA_mmD4VGA_CONTROL 0xf9 -#define SEA_mmD5VGA_CONTROL 0xfa -#define SEA_mmD6VGA_CONTROL 0xfb -#define SEA_mmVGA_HW_DEBUG 0xcf -#define SEA_mmVGA_STATUS 0xd0 -#define SEA_mmVGA_INTERRUPT_CONTROL 0xd1 -#define SEA_mmVGA_STATUS_CLEAR 0xd2 -#define SEA_mmVGA_INTERRUPT_STATUS 0xd3 -#define SEA_mmVGA_MAIN_CONTROL 0xd4 -#define SEA_mmVGA_TEST_CONTROL 0xd5 -#define SEA_mmVGA_DEBUG_READBACK_INDEX 0xd6 -#define SEA_mmVGA_DEBUG_READBACK_DATA 0xd7 -#define SEA_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 -#define SEA_mmVGA_MEM_READ_PAGE_ADDR 0x13 -#define SEA_mmVGA_TEST_DEBUG_INDEX 0xc5 -#define SEA_mmVGA_TEST_DEBUG_DATA 0xc7 -#define SEA_ixVGADCC_DBG_DCCIF_C 0x7e -#define SEA_mmBPHYC_DAC_MACRO_CNTL 0x19fd -#define SEA_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe -#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30 -#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 -#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 -#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 -#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30 -#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31 -#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 -#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 -#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 -#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31 -#define SEA_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 -#define SEA_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 -#define SEA_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32 -#define SEA_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132 -#define SEA_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432 -#define SEA_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732 -#define SEA_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32 -#define SEA_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 -#define SEA_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 -#define SEA_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33 -#define SEA_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 -#define SEA_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 -#define SEA_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 -#define SEA_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33 -#define SEA_mmDPG_PIPE_DPM_CONTROL 0x1b34 -#define SEA_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 -#define SEA_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34 -#define SEA_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 -#define SEA_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 -#define SEA_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 -#define SEA_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34 -#define SEA_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 -#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 -#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35 -#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 -#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 -#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 -#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35 -#define SEA_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define SEA_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define SEA_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36 -#define SEA_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 -#define SEA_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 -#define SEA_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 -#define SEA_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36 -#define SEA_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37 -#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 -#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 -#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 -#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37 -#define SEA_mmDPG_REPEATER_PROGRAM 0x1b3a -#define SEA_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a -#define SEA_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a -#define SEA_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a -#define SEA_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a -#define SEA_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a -#define SEA_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a -#define SEA_mmDPG_HW_DEBUG_A 0x1b3b -#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b -#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b -#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b -#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b -#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b -#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b -#define SEA_mmDPG_HW_DEBUG_B 0x1b3c -#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c -#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c -#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c -#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c -#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c -#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c -#define SEA_mmDPG_TEST_DEBUG_INDEX 0x1b38 -#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 -#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38 -#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 -#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 -#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 -#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38 -#define SEA_mmDPG_TEST_DEBUG_DATA 0x1b39 -#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 -#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39 -#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 -#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 -#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 -#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39 -#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 -#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 -#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 -#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 -#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2 -#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3 -#define SEA_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5 -#define SEA_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6 -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7 -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8 -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9 -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd -#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de -#define SEA_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4 -#define SEA_mmAZALIA_F0_CODEC_DEBUG 0x17df -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6 -#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7 -#define SEA_mmGLOBAL_CAPABILITIES 0x0 -#define SEA_mmMINOR_VERSION 0x0 -#define SEA_mmMAJOR_VERSION 0x0 -#define SEA_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 -#define SEA_mmINPUT_PAYLOAD_CAPABILITY 0x1 -#define SEA_mmGLOBAL_CONTROL 0x2 -#define SEA_mmWAKE_ENABLE 0x3 -#define SEA_mmSTATE_CHANGE_STATUS 0x3 -#define SEA_mmGLOBAL_STATUS 0x4 -#define SEA_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -#define SEA_mmINTERRUPT_CONTROL 0x8 -#define SEA_mmINTERRUPT_STATUS 0x9 -#define SEA_mmWALL_CLOCK_COUNTER 0xc -#define SEA_mmSTREAM_SYNCHRONIZATION 0xe -#define SEA_mmCORB_LOWER_BASE_ADDRESS 0x10 -#define SEA_mmCORB_UPPER_BASE_ADDRESS 0x11 -#define SEA_mmCORB_WRITE_POINTER 0x12 -#define SEA_mmCORB_READ_POINTER 0x12 -#define SEA_mmCORB_CONTROL 0x13 -#define SEA_mmCORB_STATUS 0x13 -#define SEA_mmCORB_SIZE 0x13 -#define SEA_mmRIRB_LOWER_BASE_ADDRESS 0x14 -#define SEA_mmRIRB_UPPER_BASE_ADDRESS 0x15 -#define SEA_mmRIRB_WRITE_POINTER 0x16 -#define SEA_mmRESPONSE_INTERRUPT_COUNT 0x16 -#define SEA_mmRIRB_CONTROL 0x17 -#define SEA_mmRIRB_STATUS 0x17 -#define SEA_mmRIRB_SIZE 0x17 -#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 -#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define SEA_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 -#define SEA_mmIMMEDIATE_COMMAND_STATUS 0x1a -#define SEA_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c -#define SEA_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d -#define SEA_mmWALL_CLOCK_COUNTER_ALIAS 0x80c -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 -#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 -#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 -#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 -#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 -#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c -#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 -#define SEA_ixAUDIO_DESCRIPTOR0 0x1 -#define SEA_ixAUDIO_DESCRIPTOR1 0x2 -#define SEA_ixAUDIO_DESCRIPTOR2 0x3 -#define SEA_ixAUDIO_DESCRIPTOR3 0x4 -#define SEA_ixAUDIO_DESCRIPTOR4 0x5 -#define SEA_ixAUDIO_DESCRIPTOR5 0x6 -#define SEA_ixAUDIO_DESCRIPTOR6 0x7 -#define SEA_ixAUDIO_DESCRIPTOR7 0x8 -#define SEA_ixAUDIO_DESCRIPTOR8 0x9 -#define SEA_ixAUDIO_DESCRIPTOR9 0xa -#define SEA_ixAUDIO_DESCRIPTOR10 0xb -#define SEA_ixAUDIO_DESCRIPTOR11 0xc -#define SEA_ixAUDIO_DESCRIPTOR12 0xd -#define SEA_ixAUDIO_DESCRIPTOR13 0xe -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 -#define SEA_ixSINK_DESCRIPTION0 0x5 -#define SEA_ixSINK_DESCRIPTION1 0x6 -#define SEA_ixSINK_DESCRIPTION2 0x7 -#define SEA_ixSINK_DESCRIPTION3 0x8 -#define SEA_ixSINK_DESCRIPTION4 0x9 -#define SEA_ixSINK_DESCRIPTION5 0xa -#define SEA_ixSINK_DESCRIPTION6 0xb -#define SEA_ixSINK_DESCRIPTION7 0xc -#define SEA_ixSINK_DESCRIPTION8 0xd -#define SEA_ixSINK_DESCRIPTION9 0xe -#define SEA_ixSINK_DESCRIPTION10 0xf -#define SEA_ixSINK_DESCRIPTION11 0x10 -#define SEA_ixSINK_DESCRIPTION12 0x11 -#define SEA_ixSINK_DESCRIPTION13 0x12 -#define SEA_ixSINK_DESCRIPTION14 0x13 -#define SEA_ixSINK_DESCRIPTION15 0x14 -#define SEA_ixSINK_DESCRIPTION16 0x15 -#define SEA_ixSINK_DESCRIPTION17 0x16 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 -#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 -#define SEA_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 -#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 -#define SEA_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9 -#define SEA_mmAZALIA_AUDIO_DTO 0x17ba -#define SEA_mmAZALIA_AUDIO_DTO_CONTROL 0x17bb -#define SEA_mmAZALIA_SCLK_CONTROL 0x17bc -#define SEA_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd -#define SEA_mmAZALIA_DATA_DMA_CONTROL 0x17be -#define SEA_mmAZALIA_BDL_DMA_CONTROL 0x17bf -#define SEA_mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 -#define SEA_mmAZALIA_CORB_DMA_CONTROL 0x17c1 -#define SEA_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9 -#define SEA_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca -#define SEA_mmAZALIA_GLOBAL_CAPABILITIES 0x17cb -#define SEA_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc -#define SEA_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd -#define SEA_mmAZALIA_CONTROLLER_DEBUG 0x17cf -#define SEA_mmAZALIA_CRC0_CONTROL0 0x17ae -#define SEA_mmAZALIA_CRC0_CONTROL1 0x17af -#define SEA_mmAZALIA_CRC0_CONTROL2 0x17b0 -#define SEA_mmAZALIA_CRC0_CONTROL3 0x17b1 -#define SEA_mmAZALIA_CRC0_RESULT 0x17b2 -#define SEA_ixAZALIA_CRC0_CHANNEL0 0x0 -#define SEA_ixAZALIA_CRC0_CHANNEL1 0x1 -#define SEA_ixAZALIA_CRC0_CHANNEL2 0x2 -#define SEA_ixAZALIA_CRC0_CHANNEL3 0x3 -#define SEA_ixAZALIA_CRC0_CHANNEL4 0x4 -#define SEA_ixAZALIA_CRC0_CHANNEL5 0x5 -#define SEA_ixAZALIA_CRC0_CHANNEL6 0x6 -#define SEA_ixAZALIA_CRC0_CHANNEL7 0x7 -#define SEA_mmAZALIA_CRC1_CONTROL0 0x17b3 -#define SEA_mmAZALIA_CRC1_CONTROL1 0x17b4 -#define SEA_mmAZALIA_CRC1_CONTROL2 0x17b5 -#define SEA_mmAZALIA_CRC1_CONTROL3 0x17b6 -#define SEA_mmAZALIA_CRC1_RESULT 0x17b7 -#define SEA_ixAZALIA_CRC1_CHANNEL0 0x0 -#define SEA_ixAZALIA_CRC1_CHANNEL1 0x1 -#define SEA_ixAZALIA_CRC1_CHANNEL2 0x2 -#define SEA_ixAZALIA_CRC1_CHANNEL3 0x3 -#define SEA_ixAZALIA_CRC1_CHANNEL4 0x4 -#define SEA_ixAZALIA_CRC1_CHANNEL5 0x5 -#define SEA_ixAZALIA_CRC1_CHANNEL6 0x6 -#define SEA_ixAZALIA_CRC1_CHANNEL7 0x7 -#define SEA_mmAZ_TEST_DEBUG_INDEX 0x17d0 -#define SEA_mmAZ_TEST_DEBUG_DATA 0x17d1 -#define SEA_mmAZALIA_STREAM_INDEX 0x17e8 -#define SEA_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8 -#define SEA_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec -#define SEA_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0 -#define SEA_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4 -#define SEA_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8 -#define SEA_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc -#define SEA_mmAZALIA_STREAM_DATA 0x17e9 -#define SEA_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9 -#define SEA_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed -#define SEA_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1 -#define SEA_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5 -#define SEA_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9 -#define SEA_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd -#define SEA_ixAZALIA_FIFO_SIZE_CONTROL 0x0 -#define SEA_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 -#define SEA_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 -#define SEA_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 -#define SEA_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 -#define SEA_ixAZALIA_STREAM_DEBUG 0x5 -#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 -#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 -#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 -#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c -#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 -#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 -#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e -#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4 -#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 -#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 -#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 -#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d -#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 -#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 -#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f -#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd -#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe -#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 -#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 -#define SEA_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 -#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 -#define SEA_mmBLND_CONTROL 0x1b6d -#define SEA_mmBLND0_BLND_CONTROL 0x1b6d -#define SEA_mmBLND1_BLND_CONTROL 0x1e6d -#define SEA_mmBLND2_BLND_CONTROL 0x416d -#define SEA_mmBLND3_BLND_CONTROL 0x446d -#define SEA_mmBLND4_BLND_CONTROL 0x476d -#define SEA_mmBLND5_BLND_CONTROL 0x4a6d -#define SEA_mmSM_CONTROL2 0x1b6e -#define SEA_mmBLND0_SM_CONTROL2 0x1b6e -#define SEA_mmBLND1_SM_CONTROL2 0x1e6e -#define SEA_mmBLND2_SM_CONTROL2 0x416e -#define SEA_mmBLND3_SM_CONTROL2 0x446e -#define SEA_mmBLND4_SM_CONTROL2 0x476e -#define SEA_mmBLND5_SM_CONTROL2 0x4a6e -#define SEA_mmPTI_CONTROL 0x1b6f -#define SEA_mmBLND0_PTI_CONTROL 0x1b6f -#define SEA_mmBLND1_PTI_CONTROL 0x1e6f -#define SEA_mmBLND2_PTI_CONTROL 0x416f -#define SEA_mmBLND3_PTI_CONTROL 0x446f -#define SEA_mmBLND4_PTI_CONTROL 0x476f -#define SEA_mmBLND5_PTI_CONTROL 0x4a6f -#define SEA_mmBLND_UPDATE 0x1b70 -#define SEA_mmBLND0_BLND_UPDATE 0x1b70 -#define SEA_mmBLND1_BLND_UPDATE 0x1e70 -#define SEA_mmBLND2_BLND_UPDATE 0x4170 -#define SEA_mmBLND3_BLND_UPDATE 0x4470 -#define SEA_mmBLND4_BLND_UPDATE 0x4770 -#define SEA_mmBLND5_BLND_UPDATE 0x4a70 -#define SEA_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 -#define SEA_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 -#define SEA_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71 -#define SEA_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171 -#define SEA_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471 -#define SEA_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771 -#define SEA_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71 -#define SEA_mmBLND_V_UPDATE_LOCK 0x1b73 -#define SEA_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 -#define SEA_mmBLND1_BLND_V_UPDATE_LOCK 0x1e73 -#define SEA_mmBLND2_BLND_V_UPDATE_LOCK 0x4173 -#define SEA_mmBLND3_BLND_V_UPDATE_LOCK 0x4473 -#define SEA_mmBLND4_BLND_V_UPDATE_LOCK 0x4773 -#define SEA_mmBLND5_BLND_V_UPDATE_LOCK 0x4a73 -#define SEA_mmBLND_REG_UPDATE_STATUS 0x1b77 -#define SEA_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 -#define SEA_mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77 -#define SEA_mmBLND2_BLND_REG_UPDATE_STATUS 0x4177 -#define SEA_mmBLND3_BLND_REG_UPDATE_STATUS 0x4477 -#define SEA_mmBLND4_BLND_REG_UPDATE_STATUS 0x4777 -#define SEA_mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77 -#define SEA_mmBLND_DEBUG 0x1b74 -#define SEA_mmBLND0_BLND_DEBUG 0x1b74 -#define SEA_mmBLND1_BLND_DEBUG 0x1e74 -#define SEA_mmBLND2_BLND_DEBUG 0x4174 -#define SEA_mmBLND3_BLND_DEBUG 0x4474 -#define SEA_mmBLND4_BLND_DEBUG 0x4774 -#define SEA_mmBLND5_BLND_DEBUG 0x4a74 -#define SEA_mmBLND_TEST_DEBUG_INDEX 0x1b75 -#define SEA_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 -#define SEA_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75 -#define SEA_mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175 -#define SEA_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475 -#define SEA_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775 -#define SEA_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75 -#define SEA_mmBLND_TEST_DEBUG_DATA 0x1b76 -#define SEA_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 -#define SEA_mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76 -#define SEA_mmBLND2_BLND_TEST_DEBUG_DATA 0x4176 -#define SEA_mmBLND3_BLND_TEST_DEBUG_DATA 0x4476 -#define SEA_mmBLND4_BLND_TEST_DEBUG_DATA 0x4776 -#define SEA_mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76 -#define SEA_mmSI_ENABLE 0x4c00 -#define SEA_mmSI_EC_CONFIG 0x4c01 -#define SEA_mmCNV_MODE 0x4c02 -#define SEA_mmCNV_WINDOW_START 0x4c03 -#define SEA_mmCNV_WINDOW_SIZE 0x4c04 -#define SEA_mmCNV_UPDATE 0x4c05 -#define SEA_mmCNV_SOURCE_SIZE 0x4c06 -#define SEA_mmCNV_CSC_CONTROL 0x4c07 -#define SEA_mmCNV_CSC_C11_C12 0x4c08 -#define SEA_mmCNV_CSC_C13_C14 0x4c09 -#define SEA_mmCNV_CSC_C21_C22 0x4c0a -#define SEA_mmCNV_CSC_C23_C24 0x4c0b -#define SEA_mmCNV_CSC_C31_C32 0x4c0c -#define SEA_mmCNV_CSC_C33_C34 0x4c0d -#define SEA_mmCNV_CSC_ROUND_OFFSET_R 0x4c0e -#define SEA_mmCNV_CSC_ROUND_OFFSET_G 0x4c0f -#define SEA_mmCNV_CSC_ROUND_OFFSET_B 0x4c10 -#define SEA_mmCNV_CSC_CLAMP_R 0x4c11 -#define SEA_mmCNV_CSC_CLAMP_G 0x4c12 -#define SEA_mmCNV_CSC_CLAMP_B 0x4c13 -#define SEA_mmCNV_TEST_CNTL 0x4c14 -#define SEA_mmCNV_TEST_CRC_RED 0x4c15 -#define SEA_mmCNV_TEST_CRC_GREEN 0x4c16 -#define SEA_mmCNV_TEST_CRC_BLUE 0x4c17 -#define SEA_mmSI_DEBUG_CTRL 0x4c18 -#define SEA_mmSI_DBG_MODE 0x4c1b -#define SEA_mmSI_HARD_DEBUG 0x4c1c -#define SEA_mmCNV_TEST_DEBUG_INDEX 0x4c19 -#define SEA_mmCNV_TEST_DEBUG_DATA 0x4c1a -#define SEA_mmSISCL_COEF_RAM_SELECT 0x4c20 -#define SEA_mmSISCL_COEF_RAM_TAP_DATA 0x4c21 -#define SEA_mmSISCL_MODE 0x4c22 -#define SEA_mmSISCL_TAP_CONTROL 0x4c23 -#define SEA_mmSISCL_DEST_SIZE 0x4c24 -#define SEA_mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25 -#define SEA_mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26 -#define SEA_mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27 -#define SEA_mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28 -#define SEA_mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29 -#define SEA_mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a -#define SEA_mmSISCL_ROUND_OFFSET 0x4c2b -#define SEA_mmSISCL_CLAMP 0x4c2c -#define SEA_mmSISCL_OVERFLOW_STATUS 0x4c2d -#define SEA_mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e -#define SEA_mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f -#define SEA_mmSISCL_TEST_CNTL 0x4c30 -#define SEA_mmSISCL_TEST_CRC_RED 0x4c31 -#define SEA_mmSISCL_TEST_CRC_GREEN 0x4c32 -#define SEA_mmSISCL_TEST_CRC_BLUE 0x4c33 -#define SEA_mmSISCL_BACKPRESSURE_CNT_EN 0x4c36 -#define SEA_mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37 -#define SEA_mmSISCL_TEST_DEBUG_INDEX 0x4c34 -#define SEA_mmSISCL_TEST_DEBUG_DATA 0x4c35 -#define SEA_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 -#define SEA_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 -#define SEA_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 -#define SEA_mmXDMA_INTERRUPT 0x3e3 -#define SEA_mmXDMA_CLOCK_GATING_CNTL 0x3e4 -#define SEA_mmXDMA_MEM_POWER_CNTL 0x3e6 -#define SEA_mmXDMA_IF_BIF_STATUS 0x3e7 -#define SEA_mmXDMA_PERF_MEAS_STATUS 0x3e8 -#define SEA_mmXDMA_IF_STATUS 0x3e9 -#define SEA_mmXDMA_TEST_DEBUG_INDEX 0x3ea -#define SEA_mmXDMA_TEST_DEBUG_DATA 0x3eb -#define SEA_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 -#define SEA_mmXDMA_PG_CONTROL 0x3f9 -#define SEA_mmXDMA_PG_WDATA 0x3fa -#define SEA_mmXDMA_PG_STATUS 0x3fb -#define SEA_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc -#define SEA_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd #endif /* DCE_8_0_D_H */ diff --git a/headers/private/graphics/radeon_hd/vol_reg.h b/headers/private/graphics/radeon_hd/vol_reg.h index 46e585f9d4..d1d1221ad8 100644 --- a/headers/private/graphics/radeon_hd/vol_reg.h +++ b/headers/private/graphics/radeon_hd/vol_reg.h @@ -21,7330 +21,12 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +/* This header has been modified from its original version: + * it has been formatted to contain only what Haiku needs. */ + #ifndef DCE_10_0_D_H #define DCE_10_0_D_H -#define VOL_mmPIPE0_PG_CONFIG 0x2c0 -#define VOL_mmPIPE0_PG_ENABLE 0x2c1 -#define VOL_mmPIPE0_PG_STATUS 0x2c2 -#define VOL_mmPIPE1_PG_CONFIG 0x2c3 -#define VOL_mmPIPE1_PG_ENABLE 0x2c4 -#define VOL_mmPIPE1_PG_STATUS 0x2c5 -#define VOL_mmPIPE2_PG_CONFIG 0x2c6 -#define VOL_mmPIPE2_PG_ENABLE 0x2c7 -#define VOL_mmPIPE2_PG_STATUS 0x2c8 -#define VOL_mmPIPE3_PG_CONFIG 0x2c9 -#define VOL_mmPIPE3_PG_ENABLE 0x2ca -#define VOL_mmPIPE3_PG_STATUS 0x2cb -#define VOL_mmPIPE4_PG_CONFIG 0x2cc -#define VOL_mmPIPE4_PG_ENABLE 0x2cd -#define VOL_mmPIPE4_PG_STATUS 0x2ce -#define VOL_mmPIPE5_PG_CONFIG 0x2cf -#define VOL_mmPIPE5_PG_ENABLE 0x2d0 -#define VOL_mmPIPE5_PG_STATUS 0x2d1 -#define VOL_mmDC_IP_REQUEST_CNTL 0x2d2 -#define VOL_mmDC_PGFSM_CONFIG_REG 0x2d3 -#define VOL_mmDC_PGFSM_WRITE_REG 0x2d4 -#define VOL_mmDC_PGCNTL_STATUS_REG 0x2d5 -#define VOL_mmDCPG_TEST_DEBUG_INDEX 0x2d6 -#define VOL_mmDCPG_TEST_DEBUG_DATA 0x2d7 -#define VOL_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 -#define VOL_mmBL1_PWM_USER_LEVEL 0x1629 -#define VOL_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a -#define VOL_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b -#define VOL_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c -#define VOL_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d -#define VOL_mmBL1_PWM_ABM_CNTL 0x162e -#define VOL_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f -#define VOL_mmBL1_PWM_GRP2_REG_LOCK 0x1630 -#define VOL_mmDC_ABM1_CNTL 0x1638 -#define VOL_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 -#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a -#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b -#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c -#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d -#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e -#define VOL_mmDC_ABM1_ACE_THRES_12 0x163f -#define VOL_mmDC_ABM1_ACE_THRES_34 0x1640 -#define VOL_mmDC_ABM1_ACE_CNTL_MISC 0x1641 -#define VOL_mmDC_ABM1_DEBUG_MISC 0x1649 -#define VOL_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a -#define VOL_mmDC_ABM1_HG_MISC_CTRL 0x164b -#define VOL_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c -#define VOL_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d -#define VOL_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e -#define VOL_mmDC_ABM1_LS_PIXEL_COUNT 0x164f -#define VOL_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 -#define VOL_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 -#define VOL_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 -#define VOL_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 -#define VOL_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 -#define VOL_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 -#define VOL_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 -#define VOL_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 -#define VOL_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 -#define VOL_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 -#define VOL_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a -#define VOL_mmDC_ABM1_HG_RESULT_1 0x165b -#define VOL_mmDC_ABM1_HG_RESULT_2 0x165c -#define VOL_mmDC_ABM1_HG_RESULT_3 0x165d -#define VOL_mmDC_ABM1_HG_RESULT_4 0x165e -#define VOL_mmDC_ABM1_HG_RESULT_5 0x165f -#define VOL_mmDC_ABM1_HG_RESULT_6 0x1660 -#define VOL_mmDC_ABM1_HG_RESULT_7 0x1661 -#define VOL_mmDC_ABM1_HG_RESULT_8 0x1662 -#define VOL_mmDC_ABM1_HG_RESULT_9 0x1663 -#define VOL_mmDC_ABM1_HG_RESULT_10 0x1664 -#define VOL_mmDC_ABM1_HG_RESULT_11 0x1665 -#define VOL_mmDC_ABM1_HG_RESULT_12 0x1666 -#define VOL_mmDC_ABM1_HG_RESULT_13 0x1667 -#define VOL_mmDC_ABM1_HG_RESULT_14 0x1668 -#define VOL_mmDC_ABM1_HG_RESULT_15 0x1669 -#define VOL_mmDC_ABM1_HG_RESULT_16 0x166a -#define VOL_mmDC_ABM1_HG_RESULT_17 0x166b -#define VOL_mmDC_ABM1_HG_RESULT_18 0x166c -#define VOL_mmDC_ABM1_HG_RESULT_19 0x166d -#define VOL_mmDC_ABM1_HG_RESULT_20 0x166e -#define VOL_mmDC_ABM1_HG_RESULT_21 0x166f -#define VOL_mmDC_ABM1_HG_RESULT_22 0x1670 -#define VOL_mmDC_ABM1_HG_RESULT_23 0x1671 -#define VOL_mmDC_ABM1_HG_RESULT_24 0x1672 -#define VOL_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b -#define VOL_mmDC_ABM1_BL_MASTER_LOCK 0x169c -#define VOL_mmABM_TEST_DEBUG_INDEX 0x169e -#define VOL_mmABM_TEST_DEBUG_DATA 0x169f -#define VOL_mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c -#define VOL_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c -#define VOL_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1d7c -#define VOL_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x1f7c -#define VOL_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x417c -#define VOL_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x437c -#define VOL_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x457c -#define VOL_mmCRTC6_CRTC_DCFE_CLOCK_CONTROL 0x477c -#define VOL_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d -#define VOL_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d -#define VOL_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d -#define VOL_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d -#define VOL_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d -#define VOL_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d -#define VOL_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d -#define VOL_mmCRTC6_CRTC_H_BLANK_EARLY_NUM 0x477d -#define VOL_mmDCFE_DBG_SEL 0x1b7e -#define VOL_mmCRTC0_DCFE_DBG_SEL 0x1b7e -#define VOL_mmCRTC1_DCFE_DBG_SEL 0x1d7e -#define VOL_mmCRTC2_DCFE_DBG_SEL 0x1f7e -#define VOL_mmCRTC3_DCFE_DBG_SEL 0x417e -#define VOL_mmCRTC4_DCFE_DBG_SEL 0x437e -#define VOL_mmCRTC5_DCFE_DBG_SEL 0x457e -#define VOL_mmCRTC6_DCFE_DBG_SEL 0x477e -#define VOL_mmDCFE_MEM_PWR_CTRL 0x1b7f -#define VOL_mmCRTC0_DCFE_MEM_PWR_CTRL 0x1b7f -#define VOL_mmCRTC1_DCFE_MEM_PWR_CTRL 0x1d7f -#define VOL_mmCRTC2_DCFE_MEM_PWR_CTRL 0x1f7f -#define VOL_mmCRTC3_DCFE_MEM_PWR_CTRL 0x417f -#define VOL_mmCRTC4_DCFE_MEM_PWR_CTRL 0x437f -#define VOL_mmCRTC5_DCFE_MEM_PWR_CTRL 0x457f -#define VOL_mmCRTC6_DCFE_MEM_PWR_CTRL 0x477f -#define VOL_mmDCFE_MEM_PWR_CTRL2 0x1bb8 -#define VOL_mmCRTC0_DCFE_MEM_PWR_CTRL2 0x1bb8 -#define VOL_mmCRTC1_DCFE_MEM_PWR_CTRL2 0x1db8 -#define VOL_mmCRTC2_DCFE_MEM_PWR_CTRL2 0x1fb8 -#define VOL_mmCRTC3_DCFE_MEM_PWR_CTRL2 0x41b8 -#define VOL_mmCRTC4_DCFE_MEM_PWR_CTRL2 0x43b8 -#define VOL_mmCRTC5_DCFE_MEM_PWR_CTRL2 0x45b8 -#define VOL_mmCRTC6_DCFE_MEM_PWR_CTRL2 0x47b8 -#define VOL_mmDCFE_MEM_PWR_STATUS 0x1bb9 -#define VOL_mmCRTC0_DCFE_MEM_PWR_STATUS 0x1bb9 -#define VOL_mmCRTC1_DCFE_MEM_PWR_STATUS 0x1db9 -#define VOL_mmCRTC2_DCFE_MEM_PWR_STATUS 0x1fb9 -#define VOL_mmCRTC3_DCFE_MEM_PWR_STATUS 0x41b9 -#define VOL_mmCRTC4_DCFE_MEM_PWR_STATUS 0x43b9 -#define VOL_mmCRTC5_DCFE_MEM_PWR_STATUS 0x45b9 -#define VOL_mmCRTC6_DCFE_MEM_PWR_STATUS 0x47b9 -#define VOL_mmCRTC_H_TOTAL 0x1b80 -#define VOL_mmCRTC0_CRTC_H_TOTAL 0x1b80 -#define VOL_mmCRTC1_CRTC_H_TOTAL 0x1d80 -#define VOL_mmCRTC2_CRTC_H_TOTAL 0x1f80 -#define VOL_mmCRTC3_CRTC_H_TOTAL 0x4180 -#define VOL_mmCRTC4_CRTC_H_TOTAL 0x4380 -#define VOL_mmCRTC5_CRTC_H_TOTAL 0x4580 -#define VOL_mmCRTC6_CRTC_H_TOTAL 0x4780 -#define VOL_mmCRTC_H_BLANK_START_END 0x1b81 -#define VOL_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 -#define VOL_mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 -#define VOL_mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 -#define VOL_mmCRTC3_CRTC_H_BLANK_START_END 0x4181 -#define VOL_mmCRTC4_CRTC_H_BLANK_START_END 0x4381 -#define VOL_mmCRTC5_CRTC_H_BLANK_START_END 0x4581 -#define VOL_mmCRTC6_CRTC_H_BLANK_START_END 0x4781 -#define VOL_mmCRTC_H_SYNC_A 0x1b82 -#define VOL_mmCRTC0_CRTC_H_SYNC_A 0x1b82 -#define VOL_mmCRTC1_CRTC_H_SYNC_A 0x1d82 -#define VOL_mmCRTC2_CRTC_H_SYNC_A 0x1f82 -#define VOL_mmCRTC3_CRTC_H_SYNC_A 0x4182 -#define VOL_mmCRTC4_CRTC_H_SYNC_A 0x4382 -#define VOL_mmCRTC5_CRTC_H_SYNC_A 0x4582 -#define VOL_mmCRTC6_CRTC_H_SYNC_A 0x4782 -#define VOL_mmCRTC_H_SYNC_A_CNTL 0x1b83 -#define VOL_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 -#define VOL_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 -#define VOL_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 -#define VOL_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 -#define VOL_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 -#define VOL_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 -#define VOL_mmCRTC6_CRTC_H_SYNC_A_CNTL 0x4783 -#define VOL_mmCRTC_H_SYNC_B 0x1b84 -#define VOL_mmCRTC0_CRTC_H_SYNC_B 0x1b84 -#define VOL_mmCRTC1_CRTC_H_SYNC_B 0x1d84 -#define VOL_mmCRTC2_CRTC_H_SYNC_B 0x1f84 -#define VOL_mmCRTC3_CRTC_H_SYNC_B 0x4184 -#define VOL_mmCRTC4_CRTC_H_SYNC_B 0x4384 -#define VOL_mmCRTC5_CRTC_H_SYNC_B 0x4584 -#define VOL_mmCRTC6_CRTC_H_SYNC_B 0x4784 -#define VOL_mmCRTC_H_SYNC_B_CNTL 0x1b85 -#define VOL_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 -#define VOL_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 -#define VOL_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 -#define VOL_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 -#define VOL_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 -#define VOL_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 -#define VOL_mmCRTC6_CRTC_H_SYNC_B_CNTL 0x4785 -#define VOL_mmCRTC_VBI_END 0x1b86 -#define VOL_mmCRTC0_CRTC_VBI_END 0x1b86 -#define VOL_mmCRTC1_CRTC_VBI_END 0x1d86 -#define VOL_mmCRTC2_CRTC_VBI_END 0x1f86 -#define VOL_mmCRTC3_CRTC_VBI_END 0x4186 -#define VOL_mmCRTC4_CRTC_VBI_END 0x4386 -#define VOL_mmCRTC5_CRTC_VBI_END 0x4586 -#define VOL_mmCRTC6_CRTC_VBI_END 0x4786 -#define VOL_mmCRTC_V_TOTAL 0x1b87 -#define VOL_mmCRTC0_CRTC_V_TOTAL 0x1b87 -#define VOL_mmCRTC1_CRTC_V_TOTAL 0x1d87 -#define VOL_mmCRTC2_CRTC_V_TOTAL 0x1f87 -#define VOL_mmCRTC3_CRTC_V_TOTAL 0x4187 -#define VOL_mmCRTC4_CRTC_V_TOTAL 0x4387 -#define VOL_mmCRTC5_CRTC_V_TOTAL 0x4587 -#define VOL_mmCRTC6_CRTC_V_TOTAL 0x4787 -#define VOL_mmCRTC_V_TOTAL_MIN 0x1b88 -#define VOL_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 -#define VOL_mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 -#define VOL_mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 -#define VOL_mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 -#define VOL_mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 -#define VOL_mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 -#define VOL_mmCRTC6_CRTC_V_TOTAL_MIN 0x4788 -#define VOL_mmCRTC_V_TOTAL_MAX 0x1b89 -#define VOL_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 -#define VOL_mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 -#define VOL_mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 -#define VOL_mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 -#define VOL_mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 -#define VOL_mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 -#define VOL_mmCRTC6_CRTC_V_TOTAL_MAX 0x4789 -#define VOL_mmCRTC_V_TOTAL_CONTROL 0x1b8a -#define VOL_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a -#define VOL_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a -#define VOL_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a -#define VOL_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a -#define VOL_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a -#define VOL_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a -#define VOL_mmCRTC6_CRTC_V_TOTAL_CONTROL 0x478a -#define VOL_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b -#define VOL_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b -#define VOL_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b -#define VOL_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b -#define VOL_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b -#define VOL_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b -#define VOL_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b -#define VOL_mmCRTC6_CRTC_V_TOTAL_INT_STATUS 0x478b -#define VOL_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define VOL_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c -#define VOL_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c -#define VOL_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c -#define VOL_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c -#define VOL_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c -#define VOL_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c -#define VOL_mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS 0x478c -#define VOL_mmCRTC_V_BLANK_START_END 0x1b8d -#define VOL_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d -#define VOL_mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d -#define VOL_mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d -#define VOL_mmCRTC3_CRTC_V_BLANK_START_END 0x418d -#define VOL_mmCRTC4_CRTC_V_BLANK_START_END 0x438d -#define VOL_mmCRTC5_CRTC_V_BLANK_START_END 0x458d -#define VOL_mmCRTC6_CRTC_V_BLANK_START_END 0x478d -#define VOL_mmCRTC_V_SYNC_A 0x1b8e -#define VOL_mmCRTC0_CRTC_V_SYNC_A 0x1b8e -#define VOL_mmCRTC1_CRTC_V_SYNC_A 0x1d8e -#define VOL_mmCRTC2_CRTC_V_SYNC_A 0x1f8e -#define VOL_mmCRTC3_CRTC_V_SYNC_A 0x418e -#define VOL_mmCRTC4_CRTC_V_SYNC_A 0x438e -#define VOL_mmCRTC5_CRTC_V_SYNC_A 0x458e -#define VOL_mmCRTC6_CRTC_V_SYNC_A 0x478e -#define VOL_mmCRTC_V_SYNC_A_CNTL 0x1b8f -#define VOL_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f -#define VOL_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f -#define VOL_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f -#define VOL_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f -#define VOL_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f -#define VOL_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f -#define VOL_mmCRTC6_CRTC_V_SYNC_A_CNTL 0x478f -#define VOL_mmCRTC_V_SYNC_B 0x1b90 -#define VOL_mmCRTC0_CRTC_V_SYNC_B 0x1b90 -#define VOL_mmCRTC1_CRTC_V_SYNC_B 0x1d90 -#define VOL_mmCRTC2_CRTC_V_SYNC_B 0x1f90 -#define VOL_mmCRTC3_CRTC_V_SYNC_B 0x4190 -#define VOL_mmCRTC4_CRTC_V_SYNC_B 0x4390 -#define VOL_mmCRTC5_CRTC_V_SYNC_B 0x4590 -#define VOL_mmCRTC6_CRTC_V_SYNC_B 0x4790 -#define VOL_mmCRTC_V_SYNC_B_CNTL 0x1b91 -#define VOL_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 -#define VOL_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 -#define VOL_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 -#define VOL_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 -#define VOL_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 -#define VOL_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 -#define VOL_mmCRTC6_CRTC_V_SYNC_B_CNTL 0x4791 -#define VOL_mmCRTC_DTMTEST_CNTL 0x1b92 -#define VOL_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 -#define VOL_mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 -#define VOL_mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 -#define VOL_mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 -#define VOL_mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 -#define VOL_mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 -#define VOL_mmCRTC6_CRTC_DTMTEST_CNTL 0x4792 -#define VOL_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define VOL_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 -#define VOL_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 -#define VOL_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 -#define VOL_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 -#define VOL_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 -#define VOL_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 -#define VOL_mmCRTC6_CRTC_DTMTEST_STATUS_POSITION 0x4793 -#define VOL_mmCRTC_TRIGA_CNTL 0x1b94 -#define VOL_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 -#define VOL_mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 -#define VOL_mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 -#define VOL_mmCRTC3_CRTC_TRIGA_CNTL 0x4194 -#define VOL_mmCRTC4_CRTC_TRIGA_CNTL 0x4394 -#define VOL_mmCRTC5_CRTC_TRIGA_CNTL 0x4594 -#define VOL_mmCRTC6_CRTC_TRIGA_CNTL 0x4794 -#define VOL_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define VOL_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 -#define VOL_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 -#define VOL_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 -#define VOL_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 -#define VOL_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 -#define VOL_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 -#define VOL_mmCRTC6_CRTC_TRIGA_MANUAL_TRIG 0x4795 -#define VOL_mmCRTC_TRIGB_CNTL 0x1b96 -#define VOL_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 -#define VOL_mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 -#define VOL_mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 -#define VOL_mmCRTC3_CRTC_TRIGB_CNTL 0x4196 -#define VOL_mmCRTC4_CRTC_TRIGB_CNTL 0x4396 -#define VOL_mmCRTC5_CRTC_TRIGB_CNTL 0x4596 -#define VOL_mmCRTC6_CRTC_TRIGB_CNTL 0x4796 -#define VOL_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define VOL_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 -#define VOL_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 -#define VOL_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 -#define VOL_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 -#define VOL_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 -#define VOL_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 -#define VOL_mmCRTC6_CRTC_TRIGB_MANUAL_TRIG 0x4797 -#define VOL_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define VOL_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -#define VOL_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 -#define VOL_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 -#define VOL_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 -#define VOL_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 -#define VOL_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 -#define VOL_mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 -#define VOL_mmCRTC_FLOW_CONTROL 0x1b99 -#define VOL_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 -#define VOL_mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 -#define VOL_mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 -#define VOL_mmCRTC3_CRTC_FLOW_CONTROL 0x4199 -#define VOL_mmCRTC4_CRTC_FLOW_CONTROL 0x4399 -#define VOL_mmCRTC5_CRTC_FLOW_CONTROL 0x4599 -#define VOL_mmCRTC6_CRTC_FLOW_CONTROL 0x4799 -#define VOL_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a -#define VOL_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a -#define VOL_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a -#define VOL_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a -#define VOL_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a -#define VOL_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a -#define VOL_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a -#define VOL_mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE 0x479a -#define VOL_mmCRTC_AVSYNC_COUNTER 0x1b9b -#define VOL_mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b -#define VOL_mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b -#define VOL_mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b -#define VOL_mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b -#define VOL_mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b -#define VOL_mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b -#define VOL_mmCRTC6_CRTC_AVSYNC_COUNTER 0x479b -#define VOL_mmCRTC_CONTROL 0x1b9c -#define VOL_mmCRTC0_CRTC_CONTROL 0x1b9c -#define VOL_mmCRTC1_CRTC_CONTROL 0x1d9c -#define VOL_mmCRTC2_CRTC_CONTROL 0x1f9c -#define VOL_mmCRTC3_CRTC_CONTROL 0x419c -#define VOL_mmCRTC4_CRTC_CONTROL 0x439c -#define VOL_mmCRTC5_CRTC_CONTROL 0x459c -#define VOL_mmCRTC6_CRTC_CONTROL 0x479c -#define VOL_mmCRTC_BLANK_CONTROL 0x1b9d -#define VOL_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d -#define VOL_mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d -#define VOL_mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d -#define VOL_mmCRTC3_CRTC_BLANK_CONTROL 0x419d -#define VOL_mmCRTC4_CRTC_BLANK_CONTROL 0x439d -#define VOL_mmCRTC5_CRTC_BLANK_CONTROL 0x459d -#define VOL_mmCRTC6_CRTC_BLANK_CONTROL 0x479d -#define VOL_mmCRTC_INTERLACE_CONTROL 0x1b9e -#define VOL_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e -#define VOL_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e -#define VOL_mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e -#define VOL_mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e -#define VOL_mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e -#define VOL_mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e -#define VOL_mmCRTC6_CRTC_INTERLACE_CONTROL 0x479e -#define VOL_mmCRTC_INTERLACE_STATUS 0x1b9f -#define VOL_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f -#define VOL_mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f -#define VOL_mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f -#define VOL_mmCRTC3_CRTC_INTERLACE_STATUS 0x419f -#define VOL_mmCRTC4_CRTC_INTERLACE_STATUS 0x439f -#define VOL_mmCRTC5_CRTC_INTERLACE_STATUS 0x459f -#define VOL_mmCRTC6_CRTC_INTERLACE_STATUS 0x479f -#define VOL_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define VOL_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 -#define VOL_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 -#define VOL_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 -#define VOL_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 -#define VOL_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 -#define VOL_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 -#define VOL_mmCRTC6_CRTC_FIELD_INDICATION_CONTROL 0x47a0 -#define VOL_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define VOL_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 -#define VOL_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 -#define VOL_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 -#define VOL_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 -#define VOL_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 -#define VOL_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 -#define VOL_mmCRTC6_CRTC_PIXEL_DATA_READBACK0 0x47a1 -#define VOL_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define VOL_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 -#define VOL_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 -#define VOL_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 -#define VOL_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 -#define VOL_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 -#define VOL_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 -#define VOL_mmCRTC6_CRTC_PIXEL_DATA_READBACK1 0x47a2 -#define VOL_mmCRTC_STATUS 0x1ba3 -#define VOL_mmCRTC0_CRTC_STATUS 0x1ba3 -#define VOL_mmCRTC1_CRTC_STATUS 0x1da3 -#define VOL_mmCRTC2_CRTC_STATUS 0x1fa3 -#define VOL_mmCRTC3_CRTC_STATUS 0x41a3 -#define VOL_mmCRTC4_CRTC_STATUS 0x43a3 -#define VOL_mmCRTC5_CRTC_STATUS 0x45a3 -#define VOL_mmCRTC6_CRTC_STATUS 0x47a3 -#define VOL_mmCRTC_STATUS_POSITION 0x1ba4 -#define VOL_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 -#define VOL_mmCRTC1_CRTC_STATUS_POSITION 0x1da4 -#define VOL_mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 -#define VOL_mmCRTC3_CRTC_STATUS_POSITION 0x41a4 -#define VOL_mmCRTC4_CRTC_STATUS_POSITION 0x43a4 -#define VOL_mmCRTC5_CRTC_STATUS_POSITION 0x45a4 -#define VOL_mmCRTC6_CRTC_STATUS_POSITION 0x47a4 -#define VOL_mmCRTC_NOM_VERT_POSITION 0x1ba5 -#define VOL_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 -#define VOL_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 -#define VOL_mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 -#define VOL_mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 -#define VOL_mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 -#define VOL_mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 -#define VOL_mmCRTC6_CRTC_NOM_VERT_POSITION 0x47a5 -#define VOL_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 -#define VOL_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 -#define VOL_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 -#define VOL_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 -#define VOL_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 -#define VOL_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 -#define VOL_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 -#define VOL_mmCRTC6_CRTC_STATUS_FRAME_COUNT 0x47a6 -#define VOL_mmCRTC_STATUS_VF_COUNT 0x1ba7 -#define VOL_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 -#define VOL_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 -#define VOL_mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 -#define VOL_mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 -#define VOL_mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 -#define VOL_mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 -#define VOL_mmCRTC6_CRTC_STATUS_VF_COUNT 0x47a7 -#define VOL_mmCRTC_STATUS_HV_COUNT 0x1ba8 -#define VOL_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 -#define VOL_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 -#define VOL_mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 -#define VOL_mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 -#define VOL_mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 -#define VOL_mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 -#define VOL_mmCRTC6_CRTC_STATUS_HV_COUNT 0x47a8 -#define VOL_mmCRTC_COUNT_CONTROL 0x1ba9 -#define VOL_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 -#define VOL_mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 -#define VOL_mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 -#define VOL_mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 -#define VOL_mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 -#define VOL_mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 -#define VOL_mmCRTC6_CRTC_COUNT_CONTROL 0x47a9 -#define VOL_mmCRTC_COUNT_RESET 0x1baa -#define VOL_mmCRTC0_CRTC_COUNT_RESET 0x1baa -#define VOL_mmCRTC1_CRTC_COUNT_RESET 0x1daa -#define VOL_mmCRTC2_CRTC_COUNT_RESET 0x1faa -#define VOL_mmCRTC3_CRTC_COUNT_RESET 0x41aa -#define VOL_mmCRTC4_CRTC_COUNT_RESET 0x43aa -#define VOL_mmCRTC5_CRTC_COUNT_RESET 0x45aa -#define VOL_mmCRTC6_CRTC_COUNT_RESET 0x47aa -#define VOL_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define VOL_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -#define VOL_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab -#define VOL_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab -#define VOL_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab -#define VOL_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab -#define VOL_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab -#define VOL_mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab -#define VOL_mmCRTC_VERT_SYNC_CONTROL 0x1bac -#define VOL_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac -#define VOL_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac -#define VOL_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac -#define VOL_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac -#define VOL_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac -#define VOL_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac -#define VOL_mmCRTC6_CRTC_VERT_SYNC_CONTROL 0x47ac -#define VOL_mmCRTC_STEREO_STATUS 0x1bad -#define VOL_mmCRTC0_CRTC_STEREO_STATUS 0x1bad -#define VOL_mmCRTC1_CRTC_STEREO_STATUS 0x1dad -#define VOL_mmCRTC2_CRTC_STEREO_STATUS 0x1fad -#define VOL_mmCRTC3_CRTC_STEREO_STATUS 0x41ad -#define VOL_mmCRTC4_CRTC_STEREO_STATUS 0x43ad -#define VOL_mmCRTC5_CRTC_STEREO_STATUS 0x45ad -#define VOL_mmCRTC6_CRTC_STEREO_STATUS 0x47ad -#define VOL_mmCRTC_STEREO_CONTROL 0x1bae -#define VOL_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae -#define VOL_mmCRTC1_CRTC_STEREO_CONTROL 0x1dae -#define VOL_mmCRTC2_CRTC_STEREO_CONTROL 0x1fae -#define VOL_mmCRTC3_CRTC_STEREO_CONTROL 0x41ae -#define VOL_mmCRTC4_CRTC_STEREO_CONTROL 0x43ae -#define VOL_mmCRTC5_CRTC_STEREO_CONTROL 0x45ae -#define VOL_mmCRTC6_CRTC_STEREO_CONTROL 0x47ae -#define VOL_mmCRTC_SNAPSHOT_STATUS 0x1baf -#define VOL_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf -#define VOL_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf -#define VOL_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf -#define VOL_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af -#define VOL_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af -#define VOL_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af -#define VOL_mmCRTC6_CRTC_SNAPSHOT_STATUS 0x47af -#define VOL_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 -#define VOL_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 -#define VOL_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 -#define VOL_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 -#define VOL_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 -#define VOL_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 -#define VOL_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 -#define VOL_mmCRTC6_CRTC_SNAPSHOT_CONTROL 0x47b0 -#define VOL_mmCRTC_SNAPSHOT_POSITION 0x1bb1 -#define VOL_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 -#define VOL_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 -#define VOL_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 -#define VOL_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 -#define VOL_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 -#define VOL_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 -#define VOL_mmCRTC6_CRTC_SNAPSHOT_POSITION 0x47b1 -#define VOL_mmCRTC_SNAPSHOT_FRAME 0x1bb2 -#define VOL_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 -#define VOL_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 -#define VOL_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 -#define VOL_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 -#define VOL_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 -#define VOL_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 -#define VOL_mmCRTC6_CRTC_SNAPSHOT_FRAME 0x47b2 -#define VOL_mmCRTC_START_LINE_CONTROL 0x1bb3 -#define VOL_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 -#define VOL_mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 -#define VOL_mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 -#define VOL_mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 -#define VOL_mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 -#define VOL_mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 -#define VOL_mmCRTC6_CRTC_START_LINE_CONTROL 0x47b3 -#define VOL_mmCRTC_INTERRUPT_CONTROL 0x1bb4 -#define VOL_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 -#define VOL_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 -#define VOL_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 -#define VOL_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 -#define VOL_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 -#define VOL_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 -#define VOL_mmCRTC6_CRTC_INTERRUPT_CONTROL 0x47b4 -#define VOL_mmCRTC_UPDATE_LOCK 0x1bb5 -#define VOL_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 -#define VOL_mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 -#define VOL_mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 -#define VOL_mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 -#define VOL_mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 -#define VOL_mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 -#define VOL_mmCRTC6_CRTC_UPDATE_LOCK 0x47b5 -#define VOL_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define VOL_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -#define VOL_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 -#define VOL_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 -#define VOL_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 -#define VOL_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 -#define VOL_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 -#define VOL_mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 -#define VOL_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define VOL_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -#define VOL_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 -#define VOL_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 -#define VOL_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 -#define VOL_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 -#define VOL_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 -#define VOL_mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 -#define VOL_mmCRTC_TEST_PATTERN_CONTROL 0x1bba -#define VOL_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba -#define VOL_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba -#define VOL_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba -#define VOL_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba -#define VOL_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba -#define VOL_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba -#define VOL_mmCRTC6_CRTC_TEST_PATTERN_CONTROL 0x47ba -#define VOL_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define VOL_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb -#define VOL_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb -#define VOL_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb -#define VOL_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb -#define VOL_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb -#define VOL_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb -#define VOL_mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS 0x47bb -#define VOL_mmCRTC_TEST_PATTERN_COLOR 0x1bbc -#define VOL_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc -#define VOL_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc -#define VOL_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc -#define VOL_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc -#define VOL_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc -#define VOL_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc -#define VOL_mmCRTC6_CRTC_TEST_PATTERN_COLOR 0x47bc -#define VOL_mmMASTER_UPDATE_LOCK 0x1bbd -#define VOL_mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd -#define VOL_mmCRTC1_MASTER_UPDATE_LOCK 0x1dbd -#define VOL_mmCRTC2_MASTER_UPDATE_LOCK 0x1fbd -#define VOL_mmCRTC3_MASTER_UPDATE_LOCK 0x41bd -#define VOL_mmCRTC4_MASTER_UPDATE_LOCK 0x43bd -#define VOL_mmCRTC5_MASTER_UPDATE_LOCK 0x45bd -#define VOL_mmCRTC6_MASTER_UPDATE_LOCK 0x47bd -#define VOL_mmMASTER_UPDATE_MODE 0x1bbe -#define VOL_mmCRTC0_MASTER_UPDATE_MODE 0x1bbe -#define VOL_mmCRTC1_MASTER_UPDATE_MODE 0x1dbe -#define VOL_mmCRTC2_MASTER_UPDATE_MODE 0x1fbe -#define VOL_mmCRTC3_MASTER_UPDATE_MODE 0x41be -#define VOL_mmCRTC4_MASTER_UPDATE_MODE 0x43be -#define VOL_mmCRTC5_MASTER_UPDATE_MODE 0x45be -#define VOL_mmCRTC6_MASTER_UPDATE_MODE 0x47be -#define VOL_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define VOL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -#define VOL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf -#define VOL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf -#define VOL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf -#define VOL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf -#define VOL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf -#define VOL_mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf -#define VOL_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define VOL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -#define VOL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 -#define VOL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 -#define VOL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 -#define VOL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 -#define VOL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 -#define VOL_mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 -#define VOL_mmCRTC_MVP_STATUS 0x1bc1 -#define VOL_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 -#define VOL_mmCRTC1_CRTC_MVP_STATUS 0x1dc1 -#define VOL_mmCRTC2_CRTC_MVP_STATUS 0x1fc1 -#define VOL_mmCRTC3_CRTC_MVP_STATUS 0x41c1 -#define VOL_mmCRTC4_CRTC_MVP_STATUS 0x43c1 -#define VOL_mmCRTC5_CRTC_MVP_STATUS 0x45c1 -#define VOL_mmCRTC6_CRTC_MVP_STATUS 0x47c1 -#define VOL_mmCRTC_MASTER_EN 0x1bc2 -#define VOL_mmCRTC0_CRTC_MASTER_EN 0x1bc2 -#define VOL_mmCRTC1_CRTC_MASTER_EN 0x1dc2 -#define VOL_mmCRTC2_CRTC_MASTER_EN 0x1fc2 -#define VOL_mmCRTC3_CRTC_MASTER_EN 0x41c2 -#define VOL_mmCRTC4_CRTC_MASTER_EN 0x43c2 -#define VOL_mmCRTC5_CRTC_MASTER_EN 0x45c2 -#define VOL_mmCRTC6_CRTC_MASTER_EN 0x47c2 -#define VOL_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define VOL_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -#define VOL_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 -#define VOL_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 -#define VOL_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 -#define VOL_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 -#define VOL_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 -#define VOL_mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 -#define VOL_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define VOL_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 -#define VOL_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 -#define VOL_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 -#define VOL_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 -#define VOL_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 -#define VOL_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 -#define VOL_mmCRTC6_CRTC_V_UPDATE_INT_STATUS 0x47c4 -#define VOL_mmCRTC_OVERSCAN_COLOR 0x1bc8 -#define VOL_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 -#define VOL_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 -#define VOL_mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 -#define VOL_mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 -#define VOL_mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 -#define VOL_mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 -#define VOL_mmCRTC6_CRTC_OVERSCAN_COLOR 0x47c8 -#define VOL_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define VOL_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 -#define VOL_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 -#define VOL_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 -#define VOL_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 -#define VOL_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 -#define VOL_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 -#define VOL_mmCRTC6_CRTC_OVERSCAN_COLOR_EXT 0x47c9 -#define VOL_mmCRTC_BLANK_DATA_COLOR 0x1bca -#define VOL_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca -#define VOL_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca -#define VOL_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca -#define VOL_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca -#define VOL_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca -#define VOL_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca -#define VOL_mmCRTC6_CRTC_BLANK_DATA_COLOR 0x47ca -#define VOL_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define VOL_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb -#define VOL_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb -#define VOL_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb -#define VOL_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb -#define VOL_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb -#define VOL_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb -#define VOL_mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT 0x47cb -#define VOL_mmCRTC_BLACK_COLOR 0x1bcc -#define VOL_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc -#define VOL_mmCRTC1_CRTC_BLACK_COLOR 0x1dcc -#define VOL_mmCRTC2_CRTC_BLACK_COLOR 0x1fcc -#define VOL_mmCRTC3_CRTC_BLACK_COLOR 0x41cc -#define VOL_mmCRTC4_CRTC_BLACK_COLOR 0x43cc -#define VOL_mmCRTC5_CRTC_BLACK_COLOR 0x45cc -#define VOL_mmCRTC6_CRTC_BLACK_COLOR 0x47cc -#define VOL_mmCRTC_BLACK_COLOR_EXT 0x1bcd -#define VOL_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd -#define VOL_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd -#define VOL_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd -#define VOL_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd -#define VOL_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd -#define VOL_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd -#define VOL_mmCRTC6_CRTC_BLACK_COLOR_EXT 0x47cd -#define VOL_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce -#define VOL_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf -#define VOL_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 -#define VOL_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 -#define VOL_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 -#define VOL_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 -#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 -#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 -#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 -#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 -#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 -#define VOL_mmCRTC_CRC_CNTL 0x1bd4 -#define VOL_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 -#define VOL_mmCRTC1_CRTC_CRC_CNTL 0x1dd4 -#define VOL_mmCRTC2_CRTC_CRC_CNTL 0x1fd4 -#define VOL_mmCRTC3_CRTC_CRC_CNTL 0x41d4 -#define VOL_mmCRTC4_CRTC_CRC_CNTL 0x43d4 -#define VOL_mmCRTC5_CRTC_CRC_CNTL 0x45d4 -#define VOL_mmCRTC6_CRTC_CRC_CNTL 0x47d4 -#define VOL_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define VOL_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -#define VOL_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 -#define VOL_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 -#define VOL_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 -#define VOL_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 -#define VOL_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 -#define VOL_mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 -#define VOL_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define VOL_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -#define VOL_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 -#define VOL_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 -#define VOL_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 -#define VOL_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 -#define VOL_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 -#define VOL_mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 -#define VOL_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define VOL_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -#define VOL_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 -#define VOL_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 -#define VOL_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 -#define VOL_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 -#define VOL_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 -#define VOL_mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 -#define VOL_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define VOL_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -#define VOL_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 -#define VOL_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 -#define VOL_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 -#define VOL_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 -#define VOL_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 -#define VOL_mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 -#define VOL_mmCRTC_CRC0_DATA_RG 0x1bd9 -#define VOL_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 -#define VOL_mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 -#define VOL_mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 -#define VOL_mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 -#define VOL_mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 -#define VOL_mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 -#define VOL_mmCRTC6_CRTC_CRC0_DATA_RG 0x47d9 -#define VOL_mmCRTC_CRC0_DATA_B 0x1bda -#define VOL_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda -#define VOL_mmCRTC1_CRTC_CRC0_DATA_B 0x1dda -#define VOL_mmCRTC2_CRTC_CRC0_DATA_B 0x1fda -#define VOL_mmCRTC3_CRTC_CRC0_DATA_B 0x41da -#define VOL_mmCRTC4_CRTC_CRC0_DATA_B 0x43da -#define VOL_mmCRTC5_CRTC_CRC0_DATA_B 0x45da -#define VOL_mmCRTC6_CRTC_CRC0_DATA_B 0x47da -#define VOL_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define VOL_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -#define VOL_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb -#define VOL_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb -#define VOL_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db -#define VOL_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db -#define VOL_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db -#define VOL_mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db -#define VOL_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define VOL_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -#define VOL_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc -#define VOL_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc -#define VOL_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc -#define VOL_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc -#define VOL_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc -#define VOL_mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc -#define VOL_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define VOL_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -#define VOL_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd -#define VOL_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd -#define VOL_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd -#define VOL_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd -#define VOL_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd -#define VOL_mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd -#define VOL_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define VOL_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -#define VOL_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde -#define VOL_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde -#define VOL_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de -#define VOL_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de -#define VOL_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de -#define VOL_mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de -#define VOL_mmCRTC_CRC1_DATA_RG 0x1bdf -#define VOL_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf -#define VOL_mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf -#define VOL_mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf -#define VOL_mmCRTC3_CRTC_CRC1_DATA_RG 0x41df -#define VOL_mmCRTC4_CRTC_CRC1_DATA_RG 0x43df -#define VOL_mmCRTC5_CRTC_CRC1_DATA_RG 0x45df -#define VOL_mmCRTC6_CRTC_CRC1_DATA_RG 0x47df -#define VOL_mmCRTC_CRC1_DATA_B 0x1be0 -#define VOL_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 -#define VOL_mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 -#define VOL_mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 -#define VOL_mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 -#define VOL_mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 -#define VOL_mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 -#define VOL_mmCRTC6_CRTC_CRC1_DATA_B 0x47e0 -#define VOL_mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 -#define VOL_mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 -#define VOL_mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 -#define VOL_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 -#define VOL_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 -#define VOL_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 -#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 -#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 -#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 -#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 -#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 -#define VOL_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define VOL_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 -#define VOL_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 -#define VOL_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 -#define VOL_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 -#define VOL_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 -#define VOL_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 -#define VOL_mmCRTC6_CRTC_STATIC_SCREEN_CONTROL 0x47e7 -#define VOL_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define VOL_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 -#define VOL_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 -#define VOL_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 -#define VOL_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 -#define VOL_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 -#define VOL_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 -#define VOL_mmCRTC6_CRTC_3D_STRUCTURE_CONTROL 0x4778 -#define VOL_mmCRTC_GSL_VSYNC_GAP 0x1b79 -#define VOL_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 -#define VOL_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 -#define VOL_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 -#define VOL_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 -#define VOL_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 -#define VOL_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 -#define VOL_mmCRTC6_CRTC_GSL_VSYNC_GAP 0x4779 -#define VOL_mmCRTC_GSL_WINDOW 0x1b7a -#define VOL_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a -#define VOL_mmCRTC1_CRTC_GSL_WINDOW 0x1d7a -#define VOL_mmCRTC2_CRTC_GSL_WINDOW 0x1f7a -#define VOL_mmCRTC3_CRTC_GSL_WINDOW 0x417a -#define VOL_mmCRTC4_CRTC_GSL_WINDOW 0x437a -#define VOL_mmCRTC5_CRTC_GSL_WINDOW 0x457a -#define VOL_mmCRTC6_CRTC_GSL_WINDOW 0x477a -#define VOL_mmCRTC_GSL_CONTROL 0x1b7b -#define VOL_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b -#define VOL_mmCRTC1_CRTC_GSL_CONTROL 0x1d7b -#define VOL_mmCRTC2_CRTC_GSL_CONTROL 0x1f7b -#define VOL_mmCRTC3_CRTC_GSL_CONTROL 0x417b -#define VOL_mmCRTC4_CRTC_GSL_CONTROL 0x437b -#define VOL_mmCRTC5_CRTC_GSL_CONTROL 0x457b -#define VOL_mmCRTC6_CRTC_GSL_CONTROL 0x477b -#define VOL_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 -#define VOL_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 -#define VOL_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 -#define VOL_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 -#define VOL_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 -#define VOL_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 -#define VOL_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 -#define VOL_mmCRTC6_CRTC_TEST_DEBUG_INDEX 0x47c6 -#define VOL_mmCRTC_TEST_DEBUG_DATA 0x1bc7 -#define VOL_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 -#define VOL_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 -#define VOL_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 -#define VOL_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 -#define VOL_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 -#define VOL_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 -#define VOL_mmCRTC6_CRTC_TEST_DEBUG_DATA 0x47c7 -#define VOL_mmDAC_ENABLE 0x16aa -#define VOL_mmDAC_SOURCE_SELECT 0x16ab -#define VOL_mmDAC_CRC_EN 0x16ac -#define VOL_mmDAC_CRC_CONTROL 0x16ad -#define VOL_mmDAC_CRC_SIG_RGB_MASK 0x16ae -#define VOL_mmDAC_CRC_SIG_CONTROL_MASK 0x16af -#define VOL_mmDAC_CRC_SIG_RGB 0x16b0 -#define VOL_mmDAC_CRC_SIG_CONTROL 0x16b1 -#define VOL_mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 -#define VOL_mmDAC_STEREOSYNC_SELECT 0x16b3 -#define VOL_mmDAC_AUTODETECT_CONTROL 0x16b4 -#define VOL_mmDAC_AUTODETECT_CONTROL2 0x16b5 -#define VOL_mmDAC_AUTODETECT_CONTROL3 0x16b6 -#define VOL_mmDAC_AUTODETECT_STATUS 0x16b7 -#define VOL_mmDAC_AUTODETECT_INT_CONTROL 0x16b8 -#define VOL_mmDAC_FORCE_OUTPUT_CNTL 0x16b9 -#define VOL_mmDAC_FORCE_DATA 0x16ba -#define VOL_mmDAC_POWERDOWN 0x16bb -#define VOL_mmDAC_CONTROL 0x16bc -#define VOL_mmDAC_COMPARATOR_ENABLE 0x16bd -#define VOL_mmDAC_COMPARATOR_OUTPUT 0x16be -#define VOL_mmDAC_PWR_CNTL 0x16bf -#define VOL_mmDAC_DFT_CONFIG 0x16c0 -#define VOL_mmDAC_FIFO_STATUS 0x16c1 -#define VOL_mmDAC_TEST_DEBUG_INDEX 0x16c2 -#define VOL_mmDAC_TEST_DEBUG_DATA 0x16c3 -#define VOL_mmPERFCOUNTER_CNTL 0x170 -#define VOL_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 -#define VOL_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 -#define VOL_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 -#define VOL_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 -#define VOL_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 -#define VOL_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 -#define VOL_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 -#define VOL_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 -#define VOL_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 -#define VOL_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 -#define VOL_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 -#define VOL_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 -#define VOL_mmPERFCOUNTER_STATE 0x171 -#define VOL_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 -#define VOL_mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 -#define VOL_mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 -#define VOL_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 -#define VOL_mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 -#define VOL_mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 -#define VOL_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 -#define VOL_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 -#define VOL_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 -#define VOL_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 -#define VOL_mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 -#define VOL_mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 -#define VOL_mmPERFMON_CNTL 0x173 -#define VOL_mmDC_PERFMON0_PERFMON_CNTL 0x173 -#define VOL_mmDC_PERFMON1_PERFMON_CNTL 0x367 -#define VOL_mmDC_PERFMON2_PERFMON_CNTL 0x18cb -#define VOL_mmDC_PERFMON3_PERFMON_CNTL 0x1b27 -#define VOL_mmDC_PERFMON4_PERFMON_CNTL 0x1d27 -#define VOL_mmDC_PERFMON5_PERFMON_CNTL 0x1f27 -#define VOL_mmDC_PERFMON6_PERFMON_CNTL 0x4127 -#define VOL_mmDC_PERFMON7_PERFMON_CNTL 0x4327 -#define VOL_mmDC_PERFMON8_PERFMON_CNTL 0x4527 -#define VOL_mmDC_PERFMON9_PERFMON_CNTL 0x4727 -#define VOL_mmDC_PERFMON10_PERFMON_CNTL 0x59a3 -#define VOL_mmDC_PERFMON11_PERFMON_CNTL 0x5f6b -#define VOL_mmPERFMON_CNTL2 0x17a -#define VOL_mmDC_PERFMON0_PERFMON_CNTL2 0x17a -#define VOL_mmDC_PERFMON1_PERFMON_CNTL2 0x36e -#define VOL_mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 -#define VOL_mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e -#define VOL_mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e -#define VOL_mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e -#define VOL_mmDC_PERFMON6_PERFMON_CNTL2 0x412e -#define VOL_mmDC_PERFMON7_PERFMON_CNTL2 0x432e -#define VOL_mmDC_PERFMON8_PERFMON_CNTL2 0x452e -#define VOL_mmDC_PERFMON9_PERFMON_CNTL2 0x472e -#define VOL_mmDC_PERFMON10_PERFMON_CNTL2 0x59aa -#define VOL_mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 -#define VOL_mmPERFMON_CVALUE_INT_MISC 0x172 -#define VOL_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 -#define VOL_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 -#define VOL_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca -#define VOL_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 -#define VOL_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 -#define VOL_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 -#define VOL_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 -#define VOL_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 -#define VOL_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 -#define VOL_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 -#define VOL_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 -#define VOL_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a -#define VOL_mmPERFMON_CVALUE_LOW 0x174 -#define VOL_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 -#define VOL_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 -#define VOL_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc -#define VOL_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 -#define VOL_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 -#define VOL_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 -#define VOL_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 -#define VOL_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 -#define VOL_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 -#define VOL_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 -#define VOL_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 -#define VOL_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c -#define VOL_mmPERFMON_HI 0x175 -#define VOL_mmDC_PERFMON0_PERFMON_HI 0x175 -#define VOL_mmDC_PERFMON1_PERFMON_HI 0x369 -#define VOL_mmDC_PERFMON2_PERFMON_HI 0x18cd -#define VOL_mmDC_PERFMON3_PERFMON_HI 0x1b29 -#define VOL_mmDC_PERFMON4_PERFMON_HI 0x1d29 -#define VOL_mmDC_PERFMON5_PERFMON_HI 0x1f29 -#define VOL_mmDC_PERFMON6_PERFMON_HI 0x4129 -#define VOL_mmDC_PERFMON7_PERFMON_HI 0x4329 -#define VOL_mmDC_PERFMON8_PERFMON_HI 0x4529 -#define VOL_mmDC_PERFMON9_PERFMON_HI 0x4729 -#define VOL_mmDC_PERFMON10_PERFMON_HI 0x59a5 -#define VOL_mmDC_PERFMON11_PERFMON_HI 0x5f6d -#define VOL_mmPERFMON_LOW 0x176 -#define VOL_mmDC_PERFMON0_PERFMON_LOW 0x176 -#define VOL_mmDC_PERFMON1_PERFMON_LOW 0x36a -#define VOL_mmDC_PERFMON2_PERFMON_LOW 0x18ce -#define VOL_mmDC_PERFMON3_PERFMON_LOW 0x1b2a -#define VOL_mmDC_PERFMON4_PERFMON_LOW 0x1d2a -#define VOL_mmDC_PERFMON5_PERFMON_LOW 0x1f2a -#define VOL_mmDC_PERFMON6_PERFMON_LOW 0x412a -#define VOL_mmDC_PERFMON7_PERFMON_LOW 0x432a -#define VOL_mmDC_PERFMON8_PERFMON_LOW 0x452a -#define VOL_mmDC_PERFMON9_PERFMON_LOW 0x472a -#define VOL_mmDC_PERFMON10_PERFMON_LOW 0x59a6 -#define VOL_mmDC_PERFMON11_PERFMON_LOW 0x5f6e -#define VOL_mmPERFMON_TEST_DEBUG_INDEX 0x177 -#define VOL_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 -#define VOL_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b -#define VOL_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf -#define VOL_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b -#define VOL_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b -#define VOL_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b -#define VOL_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b -#define VOL_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b -#define VOL_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b -#define VOL_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b -#define VOL_mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 -#define VOL_mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f -#define VOL_mmPERFMON_TEST_DEBUG_DATA 0x178 -#define VOL_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 -#define VOL_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c -#define VOL_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 -#define VOL_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c -#define VOL_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c -#define VOL_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c -#define VOL_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c -#define VOL_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c -#define VOL_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c -#define VOL_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c -#define VOL_mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 -#define VOL_mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 -#define VOL_mmREFCLK_CNTL 0x109 -#define VOL_mmDCCG_CBUS_WRCMD_DELAY 0x110 -#define VOL_mmDPREFCLK_CNTL 0x118 -#define VOL_mmAVSYNC_COUNTER_WRITE 0x12a -#define VOL_mmAVSYNC_COUNTER_CONTROL 0x12b -#define VOL_mmAVSYNC_COUNTER_READ 0x12f -#define VOL_mmDCCG_GTC_CNTL 0x120 -#define VOL_mmDCCG_GTC_DTO_INCR 0x121 -#define VOL_mmDCCG_GTC_DTO_MODULO 0x122 -#define VOL_mmDCCG_GTC_CURRENT 0x123 -#define VOL_mmDCCG_DS_DTO_INCR 0x113 -#define VOL_mmDCCG_DS_DTO_MODULO 0x114 -#define VOL_mmDCCG_DS_CNTL 0x115 -#define VOL_mmDCCG_DS_HW_CAL_INTERVAL 0x116 -#define VOL_mmDCCG_DS_DEBUG_CNTL 0x112 -#define VOL_mmDMCU_SMU_INTERRUPT_CNTL 0x12c -#define VOL_mmSMU_CONTROL 0x12d -#define VOL_mmSMU_INTERRUPT_CONTROL 0x12e -#define VOL_mmDAC_CLK_ENABLE 0x128 -#define VOL_mmDVO_CLK_ENABLE 0x129 -#define VOL_mmDCCG_GATE_DISABLE_CNTL 0x134 -#define VOL_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 -#define VOL_mmSCLK_CGTT_BLK_CTRL_REG 0x136 -#define VOL_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 -#define VOL_mmREFCLK_CGTT_BLK_CTRL_REG 0x10b -#define VOL_mmDCCG_CAC_STATUS 0x137 -#define VOL_mmPIXCLK1_RESYNC_CNTL 0x138 -#define VOL_mmPIXCLK2_RESYNC_CNTL 0x139 -#define VOL_mmPIXCLK0_RESYNC_CNTL 0x13a -#define VOL_mmMICROSECOND_TIME_BASE_DIV 0x13b -#define VOL_mmDCCG_DISP_CNTL_REG 0x13f -#define VOL_mmMILLISECOND_TIME_BASE_DIV 0x130 -#define VOL_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 -#define VOL_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 -#define VOL_mmDCCG_PERFMON_CNTL 0x133 -#define VOL_mmDCCG_PERFMON_CNTL2 0x10e -#define VOL_mmCRTC0_PIXEL_RATE_CNTL 0x140 -#define VOL_mmDP_DTO0_PHASE 0x141 -#define VOL_mmDP_DTO0_MODULO 0x142 -#define VOL_mmCRTC1_PIXEL_RATE_CNTL 0x144 -#define VOL_mmDP_DTO1_PHASE 0x145 -#define VOL_mmDP_DTO1_MODULO 0x146 -#define VOL_mmCRTC2_PIXEL_RATE_CNTL 0x148 -#define VOL_mmDP_DTO2_PHASE 0x149 -#define VOL_mmDP_DTO2_MODULO 0x14a -#define VOL_mmCRTC3_PIXEL_RATE_CNTL 0x14c -#define VOL_mmDP_DTO3_PHASE 0x14d -#define VOL_mmDP_DTO3_MODULO 0x14e -#define VOL_mmCRTC4_PIXEL_RATE_CNTL 0x150 -#define VOL_mmDP_DTO4_PHASE 0x151 -#define VOL_mmDP_DTO4_MODULO 0x152 -#define VOL_mmCRTC5_PIXEL_RATE_CNTL 0x154 -#define VOL_mmDP_DTO5_PHASE 0x155 -#define VOL_mmDP_DTO5_MODULO 0x156 -#define VOL_mmDCCG_SOFT_RESET 0x15f -#define VOL_mmSYMCLKA_CLOCK_ENABLE 0x160 -#define VOL_mmSYMCLKB_CLOCK_ENABLE 0x161 -#define VOL_mmSYMCLKC_CLOCK_ENABLE 0x162 -#define VOL_mmSYMCLKD_CLOCK_ENABLE 0x163 -#define VOL_mmSYMCLKE_CLOCK_ENABLE 0x164 -#define VOL_mmSYMCLKF_CLOCK_ENABLE 0x165 -#define VOL_mmDPDBG_CLK_FORCE_CONTROL 0x10d -#define VOL_mmDVOACLKD_CNTL 0x168 -#define VOL_mmDVOACLKC_MVP_CNTL 0x169 -#define VOL_mmDVOACLKC_CNTL 0x16a -#define VOL_mmDCCG_AUDIO_DTO_SOURCE 0x16b -#define VOL_mmDCCG_AUDIO_DTO0_PHASE 0x16c -#define VOL_mmDCCG_AUDIO_DTO0_MODULE 0x16d -#define VOL_mmDCCG_AUDIO_DTO1_PHASE 0x16e -#define VOL_mmDCCG_AUDIO_DTO1_MODULE 0x16f -#define VOL_mmDCCG_TEST_DEBUG_INDEX 0x17c -#define VOL_mmDCCG_TEST_DEBUG_DATA 0x17d -#define VOL_mmDCCG_TEST_CLK_SEL 0x17e -#define VOL_mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 -#define VOL_mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa -#define VOL_mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb -#define VOL_mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc -#define VOL_mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd -#define VOL_mmCPLL_MACRO_CNTL_RESERVED10 0x5fda -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe -#define VOL_mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb -#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb -#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 -#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 -#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff -#define VOL_mmPLL_MACRO_CNTL_RESERVED0 0x1700 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 -#define VOL_mmPLL_MACRO_CNTL_RESERVED1 0x1701 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 -#define VOL_mmPLL_MACRO_CNTL_RESERVED2 0x1702 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 -#define VOL_mmPLL_MACRO_CNTL_RESERVED3 0x1703 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 -#define VOL_mmPLL_MACRO_CNTL_RESERVED4 0x1704 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 -#define VOL_mmPLL_MACRO_CNTL_RESERVED5 0x1705 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 -#define VOL_mmPLL_MACRO_CNTL_RESERVED6 0x1706 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a -#define VOL_mmPLL_MACRO_CNTL_RESERVED7 0x1707 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b -#define VOL_mmPLL_MACRO_CNTL_RESERVED8 0x1708 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c -#define VOL_mmPLL_MACRO_CNTL_RESERVED9 0x1709 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d -#define VOL_mmPLL_MACRO_CNTL_RESERVED10 0x170a -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e -#define VOL_mmPLL_MACRO_CNTL_RESERVED11 0x170b -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f -#define VOL_mmPLL_MACRO_CNTL_RESERVED12 0x170c -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 -#define VOL_mmPLL_MACRO_CNTL_RESERVED13 0x170d -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 -#define VOL_mmPLL_MACRO_CNTL_RESERVED14 0x170e -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 -#define VOL_mmPLL_MACRO_CNTL_RESERVED15 0x170f -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 -#define VOL_mmPLL_MACRO_CNTL_RESERVED16 0x1710 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 -#define VOL_mmPLL_MACRO_CNTL_RESERVED17 0x1711 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 -#define VOL_mmPLL_MACRO_CNTL_RESERVED18 0x1712 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 -#define VOL_mmPLL_MACRO_CNTL_RESERVED19 0x1713 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 -#define VOL_mmPLL_MACRO_CNTL_RESERVED20 0x1714 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 -#define VOL_mmPLL_MACRO_CNTL_RESERVED21 0x1715 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 -#define VOL_mmPLL_MACRO_CNTL_RESERVED22 0x1716 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a -#define VOL_mmPLL_MACRO_CNTL_RESERVED23 0x1717 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b -#define VOL_mmPLL_MACRO_CNTL_RESERVED24 0x1718 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c -#define VOL_mmPLL_MACRO_CNTL_RESERVED25 0x1719 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d -#define VOL_mmPLL_MACRO_CNTL_RESERVED26 0x171a -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e -#define VOL_mmPLL_MACRO_CNTL_RESERVED27 0x171b -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f -#define VOL_mmPLL_MACRO_CNTL_RESERVED28 0x171c -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 -#define VOL_mmPLL_MACRO_CNTL_RESERVED29 0x171d -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 -#define VOL_mmPLL_MACRO_CNTL_RESERVED30 0x171e -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 -#define VOL_mmPLL_MACRO_CNTL_RESERVED31 0x171f -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 -#define VOL_mmPLL_MACRO_CNTL_RESERVED32 0x1720 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 -#define VOL_mmPLL_MACRO_CNTL_RESERVED33 0x1721 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 -#define VOL_mmPLL_MACRO_CNTL_RESERVED34 0x1722 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 -#define VOL_mmPLL_MACRO_CNTL_RESERVED35 0x1723 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 -#define VOL_mmPLL_MACRO_CNTL_RESERVED36 0x1724 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 -#define VOL_mmPLL_MACRO_CNTL_RESERVED37 0x1725 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 -#define VOL_mmPLL_MACRO_CNTL_RESERVED38 0x1726 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a -#define VOL_mmPLL_MACRO_CNTL_RESERVED39 0x1727 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b -#define VOL_mmPLL_MACRO_CNTL_RESERVED40 0x1728 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c -#define VOL_mmPLL_MACRO_CNTL_RESERVED41 0x1729 -#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 -#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 -#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d -#define VOL_mmDENTIST_DISPCLK_CNTL 0x124 -#define VOL_mmDCDEBUG_BUS_CLK1_SEL 0x16c4 -#define VOL_mmDCDEBUG_BUS_CLK2_SEL 0x16c5 -#define VOL_mmDCDEBUG_BUS_CLK3_SEL 0x16c6 -#define VOL_mmDCDEBUG_BUS_CLK4_SEL 0x16c7 -#define VOL_mmDCDEBUG_BUS_CLK5_SEL 0x16c8 -#define VOL_mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 -#define VOL_mmDCDEBUG_OUT_CNTL 0x16ca -#define VOL_mmDCDEBUG_OUT_DATA 0x16cb -#define VOL_mmDMIF_ADDR_CONFIG 0x2f5 -#define VOL_mmDMIF_CONTROL 0x2f6 -#define VOL_mmDMIF_STATUS 0x2f7 -#define VOL_mmDMIF_HW_DEBUG 0x2f8 -#define VOL_mmDMIF_ARBITRATION_CONTROL 0x2f9 -#define VOL_mmPIPE0_ARBITRATION_CONTROL3 0x2fa -#define VOL_mmPIPE1_ARBITRATION_CONTROL3 0x2fb -#define VOL_mmPIPE2_ARBITRATION_CONTROL3 0x2fc -#define VOL_mmPIPE3_ARBITRATION_CONTROL3 0x2fd -#define VOL_mmPIPE4_ARBITRATION_CONTROL3 0x2fe -#define VOL_mmPIPE5_ARBITRATION_CONTROL3 0x2ff -#define VOL_mmPIPE6_ARBITRATION_CONTROL3 0x32a -#define VOL_mmPIPE7_ARBITRATION_CONTROL3 0x32b -#define VOL_mmDMIF_P_VMID 0x300 -#define VOL_mmDMIF_URG_OVERRIDE 0x329 -#define VOL_mmDMIF_TEST_DEBUG_INDEX 0x301 -#define VOL_mmDMIF_TEST_DEBUG_DATA 0x302 -#define VOL_ixDMIF_DEBUG02_CORE0 0x2 -#define VOL_ixDMIF_DEBUG02_CORE1 0xa -#define VOL_mmDMIF_ADDR_CALC 0x303 -#define VOL_mmDMIF_STATUS2 0x304 -#define VOL_mmPIPE0_MAX_REQUESTS 0x305 -#define VOL_mmPIPE1_MAX_REQUESTS 0x306 -#define VOL_mmPIPE2_MAX_REQUESTS 0x307 -#define VOL_mmPIPE3_MAX_REQUESTS 0x308 -#define VOL_mmPIPE4_MAX_REQUESTS 0x309 -#define VOL_mmPIPE5_MAX_REQUESTS 0x30a -#define VOL_mmPIPE6_MAX_REQUESTS 0x32c -#define VOL_mmPIPE7_MAX_REQUESTS 0x32d -#define VOL_mmLOW_POWER_TILING_CONTROL 0x30b -#define VOL_mmMCIF_CONTROL 0x30c -#define VOL_mmMCIF_WRITE_COMBINE_CONTROL 0x30d -#define VOL_mmMCIF_TEST_DEBUG_INDEX 0x30e -#define VOL_mmMCIF_TEST_DEBUG_DATA 0x30f -#define VOL_ixIDDCCIF02_DBG_DCCIF_C 0x9 -#define VOL_ixIDDCCIF04_DBG_DCCIF_E 0xb -#define VOL_ixIDDCCIF05_DBG_DCCIF_F 0xc -#define VOL_mmMCIF_VMID 0x310 -#define VOL_mmMCIF_MEM_CONTROL 0x311 -#define VOL_mmCC_DC_PIPE_DIS 0x312 -#define VOL_mmMC_DC_INTERFACE_NACK_STATUS 0x313 -#define VOL_mmRBBMIF_TIMEOUT 0x314 -#define VOL_mmRBBMIF_STATUS 0x315 -#define VOL_mmRBBMIF_TIMEOUT_DIS 0x316 -#define VOL_mmRBBMIF_STATUS_FLAG 0x327 -#define VOL_mmDCI_MEM_PWR_STATUS 0x317 -#define VOL_mmDCI_MEM_PWR_STATUS2 0x318 -#define VOL_mmDCI_CLK_CNTL 0x319 -#define VOL_mmDCI_MEM_PWR_CNTL 0x31b -#define VOL_mmDCI_MEM_PWR_CNTL2 0x31c -#define VOL_mmDCI_MEM_PWR_CNTL3 0x31d -#define VOL_mmDCI_SOFT_RESET 0x328 -#define VOL_mmDCI_TEST_DEBUG_INDEX 0x31e -#define VOL_mmDCI_TEST_DEBUG_DATA 0x31f -#define VOL_mmDCI_DEBUG_CONFIG 0x320 -#define VOL_mmPIPE0_DMIF_BUFFER_CONTROL 0x321 -#define VOL_mmPIPE1_DMIF_BUFFER_CONTROL 0x322 -#define VOL_mmPIPE2_DMIF_BUFFER_CONTROL 0x323 -#define VOL_mmPIPE3_DMIF_BUFFER_CONTROL 0x324 -#define VOL_mmPIPE4_DMIF_BUFFER_CONTROL 0x325 -#define VOL_mmPIPE5_DMIF_BUFFER_CONTROL 0x326 -#define VOL_mmDC_GENERICA 0x4800 -#define VOL_mmDC_GENERICB 0x4801 -#define VOL_mmDC_PAD_EXTERN_SIG 0x4802 -#define VOL_mmDC_REF_CLK_CNTL 0x4803 -#define VOL_mmDC_GPIO_DEBUG 0x4804 -#define VOL_mmUNIPHYA_LINK_CNTL 0x4805 -#define VOL_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 -#define VOL_mmUNIPHYB_LINK_CNTL 0x4807 -#define VOL_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 -#define VOL_mmUNIPHYC_LINK_CNTL 0x4809 -#define VOL_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a -#define VOL_mmUNIPHYD_LINK_CNTL 0x480b -#define VOL_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c -#define VOL_mmUNIPHYE_LINK_CNTL 0x480d -#define VOL_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e -#define VOL_mmUNIPHYF_LINK_CNTL 0x480f -#define VOL_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 -#define VOL_mmUNIPHYG_LINK_CNTL 0x4811 -#define VOL_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 -#define VOL_mmUNIPHY_IMPCAL_LINKA 0x4838 -#define VOL_mmUNIPHY_IMPCAL_LINKB 0x4839 -#define VOL_mmUNIPHY_IMPCAL_LINKC 0x483f -#define VOL_mmUNIPHY_IMPCAL_LINKD 0x4840 -#define VOL_mmUNIPHY_IMPCAL_LINKE 0x4843 -#define VOL_mmUNIPHY_IMPCAL_LINKF 0x4844 -#define VOL_mmUNIPHY_IMPCAL_PERIOD 0x483a -#define VOL_mmAUXP_IMPCAL 0x483b -#define VOL_mmAUXN_IMPCAL 0x483c -#define VOL_mmDCIO_IMPCAL_CNTL 0x483d -#define VOL_mmUNIPHY_IMPCAL_PSW_AB 0x483e -#define VOL_mmDCIO_IMPCAL_CNTL_CD 0x4841 -#define VOL_mmUNIPHY_IMPCAL_PSW_CD 0x4842 -#define VOL_mmDCIO_IMPCAL_CNTL_EF 0x4845 -#define VOL_mmUNIPHY_IMPCAL_PSW_EF 0x4846 -#define VOL_mmDCIO_WRCMD_DELAY 0x4816 -#define VOL_mmDC_PINSTRAPS 0x4818 -#define VOL_mmDC_DVODATA_CONFIG 0x481a -#define VOL_mmLVTMA_PWRSEQ_CNTL 0x481b -#define VOL_mmLVTMA_PWRSEQ_STATE 0x481c -#define VOL_mmLVTMA_PWRSEQ_REF_DIV 0x481d -#define VOL_mmLVTMA_PWRSEQ_DELAY1 0x481e -#define VOL_mmLVTMA_PWRSEQ_DELAY2 0x481f -#define VOL_mmBL_PWM_CNTL 0x4820 -#define VOL_mmBL_PWM_CNTL2 0x4821 -#define VOL_mmBL_PWM_PERIOD_CNTL 0x4822 -#define VOL_mmBL_PWM_GRP1_REG_LOCK 0x4823 -#define VOL_mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 -#define VOL_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 -#define VOL_mmDCIO_GSL0_CNTL 0x4826 -#define VOL_mmDCIO_GSL1_CNTL 0x4827 -#define VOL_mmDCIO_GSL2_CNTL 0x4828 -#define VOL_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 -#define VOL_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a -#define VOL_mmDC_GPU_TIMER_READ 0x482b -#define VOL_mmDC_GPU_TIMER_READ_CNTL 0x482c -#define VOL_mmDCIO_CLOCK_CNTL 0x482d -#define VOL_mmDCIO_DEBUG 0x482f -#define VOL_mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 -#define VOL_mmDBG_OUT_CNTL 0x4834 -#define VOL_mmDCIO_DEBUG_CONFIG 0x4835 -#define VOL_mmDCIO_SOFT_RESET 0x4836 -#define VOL_mmDCIO_DPHY_SEL 0x4837 -#define VOL_mmDCIO_TEST_DEBUG_INDEX 0x4831 -#define VOL_mmDCIO_TEST_DEBUG_DATA 0x4832 -#define VOL_ixDCIO_DEBUG1 0x1 -#define VOL_ixDCIO_DEBUG2 0x2 -#define VOL_ixDCIO_DEBUG3 0x3 -#define VOL_ixDCIO_DEBUG4 0x4 -#define VOL_ixDCIO_DEBUG5 0x5 -#define VOL_ixDCIO_DEBUG6 0x6 -#define VOL_ixDCIO_DEBUG7 0x7 -#define VOL_ixDCIO_DEBUG8 0x8 -#define VOL_ixDCIO_DEBUG9 0x9 -#define VOL_ixDCIO_DEBUGA 0xa -#define VOL_ixDCIO_DEBUGB 0xb -#define VOL_ixDCIO_DEBUGC 0xc -#define VOL_ixDCIO_DEBUGD 0xd -#define VOL_ixDCIO_DEBUGE 0xe -#define VOL_ixDCIO_DEBUGF 0xf -#define VOL_ixDCIO_DEBUG10 0x10 -#define VOL_ixDCIO_DEBUG11 0x11 -#define VOL_ixDCIO_DEBUG12 0x12 -#define VOL_ixDCIO_DEBUG13 0x13 -#define VOL_ixDCIO_DEBUG14 0x14 -#define VOL_ixDCIO_DEBUG15 0x15 -#define VOL_ixDCIO_DEBUG16 0x16 -#define VOL_ixDCIO_DEBUG_ID 0x0 -#define VOL_mmDC_GPIO_GENERIC_MASK 0x4860 -#define VOL_mmDC_GPIO_GENERIC_A 0x4861 -#define VOL_mmDC_GPIO_GENERIC_EN 0x4862 -#define VOL_mmDC_GPIO_GENERIC_Y 0x4863 -#define VOL_mmDC_GPIO_DVODATA_MASK 0x4864 -#define VOL_mmDC_GPIO_DVODATA_A 0x4865 -#define VOL_mmDC_GPIO_DVODATA_EN 0x4866 -#define VOL_mmDC_GPIO_DVODATA_Y 0x4867 -#define VOL_mmDC_GPIO_DDC1_MASK 0x4868 -#define VOL_mmDC_GPIO_DDC1_A 0x4869 -#define VOL_mmDC_GPIO_DDC1_EN 0x486a -#define VOL_mmDC_GPIO_DDC1_Y 0x486b -#define VOL_mmDC_GPIO_DDC2_MASK 0x486c -#define VOL_mmDC_GPIO_DDC2_A 0x486d -#define VOL_mmDC_GPIO_DDC2_EN 0x486e -#define VOL_mmDC_GPIO_DDC2_Y 0x486f -#define VOL_mmDC_GPIO_DDC3_MASK 0x4870 -#define VOL_mmDC_GPIO_DDC3_A 0x4871 -#define VOL_mmDC_GPIO_DDC3_EN 0x4872 -#define VOL_mmDC_GPIO_DDC3_Y 0x4873 -#define VOL_mmDC_GPIO_DDC4_MASK 0x4874 -#define VOL_mmDC_GPIO_DDC4_A 0x4875 -#define VOL_mmDC_GPIO_DDC4_EN 0x4876 -#define VOL_mmDC_GPIO_DDC4_Y 0x4877 -#define VOL_mmDC_GPIO_DDC5_MASK 0x4878 -#define VOL_mmDC_GPIO_DDC5_A 0x4879 -#define VOL_mmDC_GPIO_DDC5_EN 0x487a -#define VOL_mmDC_GPIO_DDC5_Y 0x487b -#define VOL_mmDC_GPIO_DDC6_MASK 0x487c -#define VOL_mmDC_GPIO_DDC6_A 0x487d -#define VOL_mmDC_GPIO_DDC6_EN 0x487e -#define VOL_mmDC_GPIO_DDC6_Y 0x487f -#define VOL_mmDC_GPIO_DDCVGA_MASK 0x4880 -#define VOL_mmDC_GPIO_DDCVGA_A 0x4881 -#define VOL_mmDC_GPIO_DDCVGA_EN 0x4882 -#define VOL_mmDC_GPIO_DDCVGA_Y 0x4883 -#define VOL_mmDC_GPIO_SYNCA_MASK 0x4884 -#define VOL_mmDC_GPIO_SYNCA_A 0x4885 -#define VOL_mmDC_GPIO_SYNCA_EN 0x4886 -#define VOL_mmDC_GPIO_SYNCA_Y 0x4887 -#define VOL_mmDC_GPIO_GENLK_MASK 0x4888 -#define VOL_mmDC_GPIO_GENLK_A 0x4889 -#define VOL_mmDC_GPIO_GENLK_EN 0x488a -#define VOL_mmDC_GPIO_GENLK_Y 0x488b -#define VOL_mmDC_GPIO_HPD_MASK 0x488c #define VOL_mmDC_GPIO_HPD_A 0x488d -#define VOL_mmDC_GPIO_HPD_EN 0x488e -#define VOL_mmDC_GPIO_HPD_Y 0x488f -#define VOL_mmDC_GPIO_PWRSEQ_MASK 0x4890 -#define VOL_mmDC_GPIO_PWRSEQ_A 0x4891 -#define VOL_mmDC_GPIO_PWRSEQ_EN 0x4892 -#define VOL_mmDC_GPIO_PWRSEQ_Y 0x4893 -#define VOL_mmDC_GPIO_PAD_STRENGTH_1 0x4894 -#define VOL_mmDC_GPIO_PAD_STRENGTH_2 0x4895 -#define VOL_mmPHY_AUX_CNTL 0x4897 -#define VOL_mmDC_GPIO_I2CPAD_A 0x4899 -#define VOL_mmDC_GPIO_I2CPAD_EN 0x489a -#define VOL_mmDC_GPIO_I2CPAD_Y 0x489b -#define VOL_mmDC_GPIO_I2CPAD_STRENGTH 0x489c -#define VOL_mmDVO_STRENGTH_CONTROL 0x489d -#define VOL_mmDVO_VREF_CONTROL 0x489e -#define VOL_mmDVO_SKEW_ADJUST 0x489f -#define VOL_mmDAC_MACRO_CNTL_RESERVED0 0x48b8 -#define VOL_mmDAC_MACRO_CNTL_RESERVED1 0x48b9 -#define VOL_mmDAC_MACRO_CNTL_RESERVED2 0x48ba -#define VOL_mmDAC_MACRO_CNTL_RESERVED3 0x48bb -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e -#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df -#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df -#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff -#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f -#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f -#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f -#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f -#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe -#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff -#define VOL_mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a -#define VOL_mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b -#define VOL_mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c -#define VOL_mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d -#define VOL_mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e -#define VOL_mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f -#define VOL_mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED18 0x5daa -#define VOL_mmDPHY_MACRO_CNTL_RESERVED19 0x5dab -#define VOL_mmDPHY_MACRO_CNTL_RESERVED20 0x5dac -#define VOL_mmDPHY_MACRO_CNTL_RESERVED21 0x5dad -#define VOL_mmDPHY_MACRO_CNTL_RESERVED22 0x5dae -#define VOL_mmDPHY_MACRO_CNTL_RESERVED23 0x5daf -#define VOL_mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED34 0x5dba -#define VOL_mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb -#define VOL_mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc -#define VOL_mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd -#define VOL_mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe -#define VOL_mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf -#define VOL_mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED50 0x5dca -#define VOL_mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb -#define VOL_mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc -#define VOL_mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd -#define VOL_mmDPHY_MACRO_CNTL_RESERVED54 0x5dce -#define VOL_mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf -#define VOL_mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 -#define VOL_mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 -#define VOL_mmGRPH_ENABLE 0x1a00 -#define VOL_mmDCP0_GRPH_ENABLE 0x1a00 -#define VOL_mmDCP1_GRPH_ENABLE 0x1c00 -#define VOL_mmDCP2_GRPH_ENABLE 0x1e00 -#define VOL_mmDCP3_GRPH_ENABLE 0x4000 -#define VOL_mmDCP4_GRPH_ENABLE 0x4200 -#define VOL_mmDCP5_GRPH_ENABLE 0x4400 -#define VOL_mmGRPH_CONTROL 0x1a01 -#define VOL_mmDCP0_GRPH_CONTROL 0x1a01 -#define VOL_mmDCP1_GRPH_CONTROL 0x1c01 -#define VOL_mmDCP2_GRPH_CONTROL 0x1e01 -#define VOL_mmDCP3_GRPH_CONTROL 0x4001 -#define VOL_mmDCP4_GRPH_CONTROL 0x4201 -#define VOL_mmDCP5_GRPH_CONTROL 0x4401 -#define VOL_mmGRPH_LUT_10BIT_BYPASS 0x1a02 -#define VOL_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 -#define VOL_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 -#define VOL_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 -#define VOL_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 -#define VOL_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 -#define VOL_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 -#define VOL_mmGRPH_SWAP_CNTL 0x1a03 -#define VOL_mmDCP0_GRPH_SWAP_CNTL 0x1a03 -#define VOL_mmDCP1_GRPH_SWAP_CNTL 0x1c03 -#define VOL_mmDCP2_GRPH_SWAP_CNTL 0x1e03 -#define VOL_mmDCP3_GRPH_SWAP_CNTL 0x4003 -#define VOL_mmDCP4_GRPH_SWAP_CNTL 0x4203 -#define VOL_mmDCP5_GRPH_SWAP_CNTL 0x4403 -#define VOL_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define VOL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -#define VOL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 -#define VOL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 -#define VOL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 -#define VOL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 -#define VOL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 -#define VOL_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define VOL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -#define VOL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 -#define VOL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 -#define VOL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 -#define VOL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 -#define VOL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 -#define VOL_mmGRPH_PITCH 0x1a06 -#define VOL_mmDCP0_GRPH_PITCH 0x1a06 -#define VOL_mmDCP1_GRPH_PITCH 0x1c06 -#define VOL_mmDCP2_GRPH_PITCH 0x1e06 -#define VOL_mmDCP3_GRPH_PITCH 0x4006 -#define VOL_mmDCP4_GRPH_PITCH 0x4206 -#define VOL_mmDCP5_GRPH_PITCH 0x4406 -#define VOL_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define VOL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -#define VOL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 -#define VOL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 -#define VOL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 -#define VOL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 -#define VOL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 -#define VOL_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define VOL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -#define VOL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 -#define VOL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 -#define VOL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 -#define VOL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 -#define VOL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 -#define VOL_mmGRPH_SURFACE_OFFSET_X 0x1a09 -#define VOL_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 -#define VOL_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 -#define VOL_mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 -#define VOL_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 -#define VOL_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 -#define VOL_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 -#define VOL_mmGRPH_SURFACE_OFFSET_Y 0x1a0a -#define VOL_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a -#define VOL_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a -#define VOL_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a -#define VOL_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a -#define VOL_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a -#define VOL_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a -#define VOL_mmGRPH_X_START 0x1a0b -#define VOL_mmDCP0_GRPH_X_START 0x1a0b -#define VOL_mmDCP1_GRPH_X_START 0x1c0b -#define VOL_mmDCP2_GRPH_X_START 0x1e0b -#define VOL_mmDCP3_GRPH_X_START 0x400b -#define VOL_mmDCP4_GRPH_X_START 0x420b -#define VOL_mmDCP5_GRPH_X_START 0x440b -#define VOL_mmGRPH_Y_START 0x1a0c -#define VOL_mmDCP0_GRPH_Y_START 0x1a0c -#define VOL_mmDCP1_GRPH_Y_START 0x1c0c -#define VOL_mmDCP2_GRPH_Y_START 0x1e0c -#define VOL_mmDCP3_GRPH_Y_START 0x400c -#define VOL_mmDCP4_GRPH_Y_START 0x420c -#define VOL_mmDCP5_GRPH_Y_START 0x440c -#define VOL_mmGRPH_X_END 0x1a0d -#define VOL_mmDCP0_GRPH_X_END 0x1a0d -#define VOL_mmDCP1_GRPH_X_END 0x1c0d -#define VOL_mmDCP2_GRPH_X_END 0x1e0d -#define VOL_mmDCP3_GRPH_X_END 0x400d -#define VOL_mmDCP4_GRPH_X_END 0x420d -#define VOL_mmDCP5_GRPH_X_END 0x440d -#define VOL_mmGRPH_Y_END 0x1a0e -#define VOL_mmDCP0_GRPH_Y_END 0x1a0e -#define VOL_mmDCP1_GRPH_Y_END 0x1c0e -#define VOL_mmDCP2_GRPH_Y_END 0x1e0e -#define VOL_mmDCP3_GRPH_Y_END 0x400e -#define VOL_mmDCP4_GRPH_Y_END 0x420e -#define VOL_mmDCP5_GRPH_Y_END 0x440e -#define VOL_mmINPUT_GAMMA_CONTROL 0x1a10 -#define VOL_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 -#define VOL_mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 -#define VOL_mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 -#define VOL_mmDCP3_INPUT_GAMMA_CONTROL 0x4010 -#define VOL_mmDCP4_INPUT_GAMMA_CONTROL 0x4210 -#define VOL_mmDCP5_INPUT_GAMMA_CONTROL 0x4410 -#define VOL_mmGRPH_UPDATE 0x1a11 -#define VOL_mmDCP0_GRPH_UPDATE 0x1a11 -#define VOL_mmDCP1_GRPH_UPDATE 0x1c11 -#define VOL_mmDCP2_GRPH_UPDATE 0x1e11 -#define VOL_mmDCP3_GRPH_UPDATE 0x4011 -#define VOL_mmDCP4_GRPH_UPDATE 0x4211 -#define VOL_mmDCP5_GRPH_UPDATE 0x4411 -#define VOL_mmGRPH_FLIP_CONTROL 0x1a12 -#define VOL_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 -#define VOL_mmDCP1_GRPH_FLIP_CONTROL 0x1c12 -#define VOL_mmDCP2_GRPH_FLIP_CONTROL 0x1e12 -#define VOL_mmDCP3_GRPH_FLIP_CONTROL 0x4012 -#define VOL_mmDCP4_GRPH_FLIP_CONTROL 0x4212 -#define VOL_mmDCP5_GRPH_FLIP_CONTROL 0x4412 -#define VOL_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define VOL_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 -#define VOL_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 -#define VOL_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 -#define VOL_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 -#define VOL_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 -#define VOL_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 -#define VOL_mmGRPH_DFQ_CONTROL 0x1a14 -#define VOL_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 -#define VOL_mmDCP1_GRPH_DFQ_CONTROL 0x1c14 -#define VOL_mmDCP2_GRPH_DFQ_CONTROL 0x1e14 -#define VOL_mmDCP3_GRPH_DFQ_CONTROL 0x4014 -#define VOL_mmDCP4_GRPH_DFQ_CONTROL 0x4214 -#define VOL_mmDCP5_GRPH_DFQ_CONTROL 0x4414 -#define VOL_mmGRPH_DFQ_STATUS 0x1a15 -#define VOL_mmDCP0_GRPH_DFQ_STATUS 0x1a15 -#define VOL_mmDCP1_GRPH_DFQ_STATUS 0x1c15 -#define VOL_mmDCP2_GRPH_DFQ_STATUS 0x1e15 -#define VOL_mmDCP3_GRPH_DFQ_STATUS 0x4015 -#define VOL_mmDCP4_GRPH_DFQ_STATUS 0x4215 -#define VOL_mmDCP5_GRPH_DFQ_STATUS 0x4415 -#define VOL_mmGRPH_INTERRUPT_STATUS 0x1a16 -#define VOL_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 -#define VOL_mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 -#define VOL_mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 -#define VOL_mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 -#define VOL_mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 -#define VOL_mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 -#define VOL_mmGRPH_INTERRUPT_CONTROL 0x1a17 -#define VOL_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 -#define VOL_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 -#define VOL_mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 -#define VOL_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 -#define VOL_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 -#define VOL_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 -#define VOL_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define VOL_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -#define VOL_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 -#define VOL_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 -#define VOL_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 -#define VOL_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 -#define VOL_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 -#define VOL_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define VOL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -#define VOL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 -#define VOL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 -#define VOL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 -#define VOL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 -#define VOL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 -#define VOL_mmGRPH_COMPRESS_PITCH 0x1a1a -#define VOL_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a -#define VOL_mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a -#define VOL_mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a -#define VOL_mmDCP3_GRPH_COMPRESS_PITCH 0x401a -#define VOL_mmDCP4_GRPH_COMPRESS_PITCH 0x421a -#define VOL_mmDCP5_GRPH_COMPRESS_PITCH 0x441a -#define VOL_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define VOL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -#define VOL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b -#define VOL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b -#define VOL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b -#define VOL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b -#define VOL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b -#define VOL_mmOVL_ENABLE 0x1a1c -#define VOL_mmDCP0_OVL_ENABLE 0x1a1c -#define VOL_mmDCP1_OVL_ENABLE 0x1c1c -#define VOL_mmDCP2_OVL_ENABLE 0x1e1c -#define VOL_mmDCP3_OVL_ENABLE 0x401c -#define VOL_mmDCP4_OVL_ENABLE 0x421c -#define VOL_mmDCP5_OVL_ENABLE 0x441c -#define VOL_mmOVL_CONTROL1 0x1a1d -#define VOL_mmDCP0_OVL_CONTROL1 0x1a1d -#define VOL_mmDCP1_OVL_CONTROL1 0x1c1d -#define VOL_mmDCP2_OVL_CONTROL1 0x1e1d -#define VOL_mmDCP3_OVL_CONTROL1 0x401d -#define VOL_mmDCP4_OVL_CONTROL1 0x421d -#define VOL_mmDCP5_OVL_CONTROL1 0x441d -#define VOL_mmOVL_CONTROL2 0x1a1e -#define VOL_mmDCP0_OVL_CONTROL2 0x1a1e -#define VOL_mmDCP1_OVL_CONTROL2 0x1c1e -#define VOL_mmDCP2_OVL_CONTROL2 0x1e1e -#define VOL_mmDCP3_OVL_CONTROL2 0x401e -#define VOL_mmDCP4_OVL_CONTROL2 0x421e -#define VOL_mmDCP5_OVL_CONTROL2 0x441e -#define VOL_mmOVL_SWAP_CNTL 0x1a1f -#define VOL_mmDCP0_OVL_SWAP_CNTL 0x1a1f -#define VOL_mmDCP1_OVL_SWAP_CNTL 0x1c1f -#define VOL_mmDCP2_OVL_SWAP_CNTL 0x1e1f -#define VOL_mmDCP3_OVL_SWAP_CNTL 0x401f -#define VOL_mmDCP4_OVL_SWAP_CNTL 0x421f -#define VOL_mmDCP5_OVL_SWAP_CNTL 0x441f -#define VOL_mmOVL_SURFACE_ADDRESS 0x1a20 -#define VOL_mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 -#define VOL_mmDCP1_OVL_SURFACE_ADDRESS 0x1c20 -#define VOL_mmDCP2_OVL_SURFACE_ADDRESS 0x1e20 -#define VOL_mmDCP3_OVL_SURFACE_ADDRESS 0x4020 -#define VOL_mmDCP4_OVL_SURFACE_ADDRESS 0x4220 -#define VOL_mmDCP5_OVL_SURFACE_ADDRESS 0x4420 -#define VOL_mmOVL_PITCH 0x1a21 -#define VOL_mmDCP0_OVL_PITCH 0x1a21 -#define VOL_mmDCP1_OVL_PITCH 0x1c21 -#define VOL_mmDCP2_OVL_PITCH 0x1e21 -#define VOL_mmDCP3_OVL_PITCH 0x4021 -#define VOL_mmDCP4_OVL_PITCH 0x4221 -#define VOL_mmDCP5_OVL_PITCH 0x4421 -#define VOL_mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 -#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 -#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1c22 -#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x1e22 -#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4022 -#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4222 -#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4422 -#define VOL_mmOVL_SURFACE_OFFSET_X 0x1a23 -#define VOL_mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 -#define VOL_mmDCP1_OVL_SURFACE_OFFSET_X 0x1c23 -#define VOL_mmDCP2_OVL_SURFACE_OFFSET_X 0x1e23 -#define VOL_mmDCP3_OVL_SURFACE_OFFSET_X 0x4023 -#define VOL_mmDCP4_OVL_SURFACE_OFFSET_X 0x4223 -#define VOL_mmDCP5_OVL_SURFACE_OFFSET_X 0x4423 -#define VOL_mmOVL_SURFACE_OFFSET_Y 0x1a24 -#define VOL_mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 -#define VOL_mmDCP1_OVL_SURFACE_OFFSET_Y 0x1c24 -#define VOL_mmDCP2_OVL_SURFACE_OFFSET_Y 0x1e24 -#define VOL_mmDCP3_OVL_SURFACE_OFFSET_Y 0x4024 -#define VOL_mmDCP4_OVL_SURFACE_OFFSET_Y 0x4224 -#define VOL_mmDCP5_OVL_SURFACE_OFFSET_Y 0x4424 -#define VOL_mmOVL_START 0x1a25 -#define VOL_mmDCP0_OVL_START 0x1a25 -#define VOL_mmDCP1_OVL_START 0x1c25 -#define VOL_mmDCP2_OVL_START 0x1e25 -#define VOL_mmDCP3_OVL_START 0x4025 -#define VOL_mmDCP4_OVL_START 0x4225 -#define VOL_mmDCP5_OVL_START 0x4425 -#define VOL_mmOVL_END 0x1a26 -#define VOL_mmDCP0_OVL_END 0x1a26 -#define VOL_mmDCP1_OVL_END 0x1c26 -#define VOL_mmDCP2_OVL_END 0x1e26 -#define VOL_mmDCP3_OVL_END 0x4026 -#define VOL_mmDCP4_OVL_END 0x4226 -#define VOL_mmDCP5_OVL_END 0x4426 -#define VOL_mmOVL_UPDATE 0x1a27 -#define VOL_mmDCP0_OVL_UPDATE 0x1a27 -#define VOL_mmDCP1_OVL_UPDATE 0x1c27 -#define VOL_mmDCP2_OVL_UPDATE 0x1e27 -#define VOL_mmDCP3_OVL_UPDATE 0x4027 -#define VOL_mmDCP4_OVL_UPDATE 0x4227 -#define VOL_mmDCP5_OVL_UPDATE 0x4427 -#define VOL_mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 -#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 -#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1c28 -#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x1e28 -#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4028 -#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4228 -#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4428 -#define VOL_mmOVL_DFQ_CONTROL 0x1a29 -#define VOL_mmDCP0_OVL_DFQ_CONTROL 0x1a29 -#define VOL_mmDCP1_OVL_DFQ_CONTROL 0x1c29 -#define VOL_mmDCP2_OVL_DFQ_CONTROL 0x1e29 -#define VOL_mmDCP3_OVL_DFQ_CONTROL 0x4029 -#define VOL_mmDCP4_OVL_DFQ_CONTROL 0x4229 -#define VOL_mmDCP5_OVL_DFQ_CONTROL 0x4429 -#define VOL_mmOVL_DFQ_STATUS 0x1a2a -#define VOL_mmDCP0_OVL_DFQ_STATUS 0x1a2a -#define VOL_mmDCP1_OVL_DFQ_STATUS 0x1c2a -#define VOL_mmDCP2_OVL_DFQ_STATUS 0x1e2a -#define VOL_mmDCP3_OVL_DFQ_STATUS 0x402a -#define VOL_mmDCP4_OVL_DFQ_STATUS 0x422a -#define VOL_mmDCP5_OVL_DFQ_STATUS 0x442a -#define VOL_mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1c2b -#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1e2b -#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b -#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x422b -#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x442b -#define VOL_mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c -#define VOL_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c -#define VOL_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1c2c -#define VOL_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x1e2c -#define VOL_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x402c -#define VOL_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x422c -#define VOL_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x442c -#define VOL_mmPRESCALE_GRPH_CONTROL 0x1a2d -#define VOL_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d -#define VOL_mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d -#define VOL_mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d -#define VOL_mmDCP3_PRESCALE_GRPH_CONTROL 0x402d -#define VOL_mmDCP4_PRESCALE_GRPH_CONTROL 0x422d -#define VOL_mmDCP5_PRESCALE_GRPH_CONTROL 0x442d -#define VOL_mmPRESCALE_VALUES_GRPH_R 0x1a2e -#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e -#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e -#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e -#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e -#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e -#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e -#define VOL_mmPRESCALE_VALUES_GRPH_G 0x1a2f -#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f -#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f -#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f -#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f -#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f -#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f -#define VOL_mmPRESCALE_VALUES_GRPH_B 0x1a30 -#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 -#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 -#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 -#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 -#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 -#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 -#define VOL_mmPRESCALE_OVL_CONTROL 0x1a31 -#define VOL_mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 -#define VOL_mmDCP1_PRESCALE_OVL_CONTROL 0x1c31 -#define VOL_mmDCP2_PRESCALE_OVL_CONTROL 0x1e31 -#define VOL_mmDCP3_PRESCALE_OVL_CONTROL 0x4031 -#define VOL_mmDCP4_PRESCALE_OVL_CONTROL 0x4231 -#define VOL_mmDCP5_PRESCALE_OVL_CONTROL 0x4431 -#define VOL_mmPRESCALE_VALUES_OVL_CB 0x1a32 -#define VOL_mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 -#define VOL_mmDCP1_PRESCALE_VALUES_OVL_CB 0x1c32 -#define VOL_mmDCP2_PRESCALE_VALUES_OVL_CB 0x1e32 -#define VOL_mmDCP3_PRESCALE_VALUES_OVL_CB 0x4032 -#define VOL_mmDCP4_PRESCALE_VALUES_OVL_CB 0x4232 -#define VOL_mmDCP5_PRESCALE_VALUES_OVL_CB 0x4432 -#define VOL_mmPRESCALE_VALUES_OVL_Y 0x1a33 -#define VOL_mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 -#define VOL_mmDCP1_PRESCALE_VALUES_OVL_Y 0x1c33 -#define VOL_mmDCP2_PRESCALE_VALUES_OVL_Y 0x1e33 -#define VOL_mmDCP3_PRESCALE_VALUES_OVL_Y 0x4033 -#define VOL_mmDCP4_PRESCALE_VALUES_OVL_Y 0x4233 -#define VOL_mmDCP5_PRESCALE_VALUES_OVL_Y 0x4433 -#define VOL_mmPRESCALE_VALUES_OVL_CR 0x1a34 -#define VOL_mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 -#define VOL_mmDCP1_PRESCALE_VALUES_OVL_CR 0x1c34 -#define VOL_mmDCP2_PRESCALE_VALUES_OVL_CR 0x1e34 -#define VOL_mmDCP3_PRESCALE_VALUES_OVL_CR 0x4034 -#define VOL_mmDCP4_PRESCALE_VALUES_OVL_CR 0x4234 -#define VOL_mmDCP5_PRESCALE_VALUES_OVL_CR 0x4434 -#define VOL_mmINPUT_CSC_CONTROL 0x1a35 -#define VOL_mmDCP0_INPUT_CSC_CONTROL 0x1a35 -#define VOL_mmDCP1_INPUT_CSC_CONTROL 0x1c35 -#define VOL_mmDCP2_INPUT_CSC_CONTROL 0x1e35 -#define VOL_mmDCP3_INPUT_CSC_CONTROL 0x4035 -#define VOL_mmDCP4_INPUT_CSC_CONTROL 0x4235 -#define VOL_mmDCP5_INPUT_CSC_CONTROL 0x4435 -#define VOL_mmINPUT_CSC_C11_C12 0x1a36 -#define VOL_mmDCP0_INPUT_CSC_C11_C12 0x1a36 -#define VOL_mmDCP1_INPUT_CSC_C11_C12 0x1c36 -#define VOL_mmDCP2_INPUT_CSC_C11_C12 0x1e36 -#define VOL_mmDCP3_INPUT_CSC_C11_C12 0x4036 -#define VOL_mmDCP4_INPUT_CSC_C11_C12 0x4236 -#define VOL_mmDCP5_INPUT_CSC_C11_C12 0x4436 -#define VOL_mmINPUT_CSC_C13_C14 0x1a37 -#define VOL_mmDCP0_INPUT_CSC_C13_C14 0x1a37 -#define VOL_mmDCP1_INPUT_CSC_C13_C14 0x1c37 -#define VOL_mmDCP2_INPUT_CSC_C13_C14 0x1e37 -#define VOL_mmDCP3_INPUT_CSC_C13_C14 0x4037 -#define VOL_mmDCP4_INPUT_CSC_C13_C14 0x4237 -#define VOL_mmDCP5_INPUT_CSC_C13_C14 0x4437 -#define VOL_mmINPUT_CSC_C21_C22 0x1a38 -#define VOL_mmDCP0_INPUT_CSC_C21_C22 0x1a38 -#define VOL_mmDCP1_INPUT_CSC_C21_C22 0x1c38 -#define VOL_mmDCP2_INPUT_CSC_C21_C22 0x1e38 -#define VOL_mmDCP3_INPUT_CSC_C21_C22 0x4038 -#define VOL_mmDCP4_INPUT_CSC_C21_C22 0x4238 -#define VOL_mmDCP5_INPUT_CSC_C21_C22 0x4438 -#define VOL_mmINPUT_CSC_C23_C24 0x1a39 -#define VOL_mmDCP0_INPUT_CSC_C23_C24 0x1a39 -#define VOL_mmDCP1_INPUT_CSC_C23_C24 0x1c39 -#define VOL_mmDCP2_INPUT_CSC_C23_C24 0x1e39 -#define VOL_mmDCP3_INPUT_CSC_C23_C24 0x4039 -#define VOL_mmDCP4_INPUT_CSC_C23_C24 0x4239 -#define VOL_mmDCP5_INPUT_CSC_C23_C24 0x4439 -#define VOL_mmINPUT_CSC_C31_C32 0x1a3a -#define VOL_mmDCP0_INPUT_CSC_C31_C32 0x1a3a -#define VOL_mmDCP1_INPUT_CSC_C31_C32 0x1c3a -#define VOL_mmDCP2_INPUT_CSC_C31_C32 0x1e3a -#define VOL_mmDCP3_INPUT_CSC_C31_C32 0x403a -#define VOL_mmDCP4_INPUT_CSC_C31_C32 0x423a -#define VOL_mmDCP5_INPUT_CSC_C31_C32 0x443a -#define VOL_mmINPUT_CSC_C33_C34 0x1a3b -#define VOL_mmDCP0_INPUT_CSC_C33_C34 0x1a3b -#define VOL_mmDCP1_INPUT_CSC_C33_C34 0x1c3b -#define VOL_mmDCP2_INPUT_CSC_C33_C34 0x1e3b -#define VOL_mmDCP3_INPUT_CSC_C33_C34 0x403b -#define VOL_mmDCP4_INPUT_CSC_C33_C34 0x423b -#define VOL_mmDCP5_INPUT_CSC_C33_C34 0x443b -#define VOL_mmOUTPUT_CSC_CONTROL 0x1a3c -#define VOL_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c -#define VOL_mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c -#define VOL_mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c -#define VOL_mmDCP3_OUTPUT_CSC_CONTROL 0x403c -#define VOL_mmDCP4_OUTPUT_CSC_CONTROL 0x423c -#define VOL_mmDCP5_OUTPUT_CSC_CONTROL 0x443c -#define VOL_mmOUTPUT_CSC_C11_C12 0x1a3d -#define VOL_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d -#define VOL_mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d -#define VOL_mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d -#define VOL_mmDCP3_OUTPUT_CSC_C11_C12 0x403d -#define VOL_mmDCP4_OUTPUT_CSC_C11_C12 0x423d -#define VOL_mmDCP5_OUTPUT_CSC_C11_C12 0x443d -#define VOL_mmOUTPUT_CSC_C13_C14 0x1a3e -#define VOL_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e -#define VOL_mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e -#define VOL_mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e -#define VOL_mmDCP3_OUTPUT_CSC_C13_C14 0x403e -#define VOL_mmDCP4_OUTPUT_CSC_C13_C14 0x423e -#define VOL_mmDCP5_OUTPUT_CSC_C13_C14 0x443e -#define VOL_mmOUTPUT_CSC_C21_C22 0x1a3f -#define VOL_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f -#define VOL_mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f -#define VOL_mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f -#define VOL_mmDCP3_OUTPUT_CSC_C21_C22 0x403f -#define VOL_mmDCP4_OUTPUT_CSC_C21_C22 0x423f -#define VOL_mmDCP5_OUTPUT_CSC_C21_C22 0x443f -#define VOL_mmOUTPUT_CSC_C23_C24 0x1a40 -#define VOL_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 -#define VOL_mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 -#define VOL_mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 -#define VOL_mmDCP3_OUTPUT_CSC_C23_C24 0x4040 -#define VOL_mmDCP4_OUTPUT_CSC_C23_C24 0x4240 -#define VOL_mmDCP5_OUTPUT_CSC_C23_C24 0x4440 -#define VOL_mmOUTPUT_CSC_C31_C32 0x1a41 -#define VOL_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 -#define VOL_mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 -#define VOL_mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 -#define VOL_mmDCP3_OUTPUT_CSC_C31_C32 0x4041 -#define VOL_mmDCP4_OUTPUT_CSC_C31_C32 0x4241 -#define VOL_mmDCP5_OUTPUT_CSC_C31_C32 0x4441 -#define VOL_mmOUTPUT_CSC_C33_C34 0x1a42 -#define VOL_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 -#define VOL_mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 -#define VOL_mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 -#define VOL_mmDCP3_OUTPUT_CSC_C33_C34 0x4042 -#define VOL_mmDCP4_OUTPUT_CSC_C33_C34 0x4242 -#define VOL_mmDCP5_OUTPUT_CSC_C33_C34 0x4442 -#define VOL_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 -#define VOL_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 -#define VOL_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 -#define VOL_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 -#define VOL_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 -#define VOL_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 -#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 -#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 -#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 -#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 -#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 -#define VOL_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 -#define VOL_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a -#define VOL_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b -#define VOL_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c -#define VOL_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d -#define VOL_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e -#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e -#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e -#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e -#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e -#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e -#define VOL_mmDENORM_CONTROL 0x1a50 -#define VOL_mmDCP0_DENORM_CONTROL 0x1a50 -#define VOL_mmDCP1_DENORM_CONTROL 0x1c50 -#define VOL_mmDCP2_DENORM_CONTROL 0x1e50 -#define VOL_mmDCP3_DENORM_CONTROL 0x4050 -#define VOL_mmDCP4_DENORM_CONTROL 0x4250 -#define VOL_mmDCP5_DENORM_CONTROL 0x4450 -#define VOL_mmOUT_ROUND_CONTROL 0x1a51 -#define VOL_mmDCP0_OUT_ROUND_CONTROL 0x1a51 -#define VOL_mmDCP1_OUT_ROUND_CONTROL 0x1c51 -#define VOL_mmDCP2_OUT_ROUND_CONTROL 0x1e51 -#define VOL_mmDCP3_OUT_ROUND_CONTROL 0x4051 -#define VOL_mmDCP4_OUT_ROUND_CONTROL 0x4251 -#define VOL_mmDCP5_OUT_ROUND_CONTROL 0x4451 -#define VOL_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 -#define VOL_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 -#define VOL_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 -#define VOL_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 -#define VOL_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 -#define VOL_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 -#define VOL_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 -#define VOL_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c -#define VOL_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c -#define VOL_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c -#define VOL_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c -#define VOL_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c -#define VOL_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c -#define VOL_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c -#define VOL_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d -#define VOL_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d -#define VOL_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d -#define VOL_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d -#define VOL_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d -#define VOL_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d -#define VOL_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d -#define VOL_mmKEY_CONTROL 0x1a53 -#define VOL_mmDCP0_KEY_CONTROL 0x1a53 -#define VOL_mmDCP1_KEY_CONTROL 0x1c53 -#define VOL_mmDCP2_KEY_CONTROL 0x1e53 -#define VOL_mmDCP3_KEY_CONTROL 0x4053 -#define VOL_mmDCP4_KEY_CONTROL 0x4253 -#define VOL_mmDCP5_KEY_CONTROL 0x4453 -#define VOL_mmKEY_RANGE_ALPHA 0x1a54 -#define VOL_mmDCP0_KEY_RANGE_ALPHA 0x1a54 -#define VOL_mmDCP1_KEY_RANGE_ALPHA 0x1c54 -#define VOL_mmDCP2_KEY_RANGE_ALPHA 0x1e54 -#define VOL_mmDCP3_KEY_RANGE_ALPHA 0x4054 -#define VOL_mmDCP4_KEY_RANGE_ALPHA 0x4254 -#define VOL_mmDCP5_KEY_RANGE_ALPHA 0x4454 -#define VOL_mmKEY_RANGE_RED 0x1a55 -#define VOL_mmDCP0_KEY_RANGE_RED 0x1a55 -#define VOL_mmDCP1_KEY_RANGE_RED 0x1c55 -#define VOL_mmDCP2_KEY_RANGE_RED 0x1e55 -#define VOL_mmDCP3_KEY_RANGE_RED 0x4055 -#define VOL_mmDCP4_KEY_RANGE_RED 0x4255 -#define VOL_mmDCP5_KEY_RANGE_RED 0x4455 -#define VOL_mmKEY_RANGE_GREEN 0x1a56 -#define VOL_mmDCP0_KEY_RANGE_GREEN 0x1a56 -#define VOL_mmDCP1_KEY_RANGE_GREEN 0x1c56 -#define VOL_mmDCP2_KEY_RANGE_GREEN 0x1e56 -#define VOL_mmDCP3_KEY_RANGE_GREEN 0x4056 -#define VOL_mmDCP4_KEY_RANGE_GREEN 0x4256 -#define VOL_mmDCP5_KEY_RANGE_GREEN 0x4456 -#define VOL_mmKEY_RANGE_BLUE 0x1a57 -#define VOL_mmDCP0_KEY_RANGE_BLUE 0x1a57 -#define VOL_mmDCP1_KEY_RANGE_BLUE 0x1c57 -#define VOL_mmDCP2_KEY_RANGE_BLUE 0x1e57 -#define VOL_mmDCP3_KEY_RANGE_BLUE 0x4057 -#define VOL_mmDCP4_KEY_RANGE_BLUE 0x4257 -#define VOL_mmDCP5_KEY_RANGE_BLUE 0x4457 -#define VOL_mmDEGAMMA_CONTROL 0x1a58 -#define VOL_mmDCP0_DEGAMMA_CONTROL 0x1a58 -#define VOL_mmDCP1_DEGAMMA_CONTROL 0x1c58 -#define VOL_mmDCP2_DEGAMMA_CONTROL 0x1e58 -#define VOL_mmDCP3_DEGAMMA_CONTROL 0x4058 -#define VOL_mmDCP4_DEGAMMA_CONTROL 0x4258 -#define VOL_mmDCP5_DEGAMMA_CONTROL 0x4458 -#define VOL_mmGAMUT_REMAP_CONTROL 0x1a59 -#define VOL_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 -#define VOL_mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 -#define VOL_mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 -#define VOL_mmDCP3_GAMUT_REMAP_CONTROL 0x4059 -#define VOL_mmDCP4_GAMUT_REMAP_CONTROL 0x4259 -#define VOL_mmDCP5_GAMUT_REMAP_CONTROL 0x4459 -#define VOL_mmGAMUT_REMAP_C11_C12 0x1a5a -#define VOL_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a -#define VOL_mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a -#define VOL_mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a -#define VOL_mmDCP3_GAMUT_REMAP_C11_C12 0x405a -#define VOL_mmDCP4_GAMUT_REMAP_C11_C12 0x425a -#define VOL_mmDCP5_GAMUT_REMAP_C11_C12 0x445a -#define VOL_mmGAMUT_REMAP_C13_C14 0x1a5b -#define VOL_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b -#define VOL_mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b -#define VOL_mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b -#define VOL_mmDCP3_GAMUT_REMAP_C13_C14 0x405b -#define VOL_mmDCP4_GAMUT_REMAP_C13_C14 0x425b -#define VOL_mmDCP5_GAMUT_REMAP_C13_C14 0x445b -#define VOL_mmGAMUT_REMAP_C21_C22 0x1a5c -#define VOL_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c -#define VOL_mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c -#define VOL_mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c -#define VOL_mmDCP3_GAMUT_REMAP_C21_C22 0x405c -#define VOL_mmDCP4_GAMUT_REMAP_C21_C22 0x425c -#define VOL_mmDCP5_GAMUT_REMAP_C21_C22 0x445c -#define VOL_mmGAMUT_REMAP_C23_C24 0x1a5d -#define VOL_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d -#define VOL_mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d -#define VOL_mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d -#define VOL_mmDCP3_GAMUT_REMAP_C23_C24 0x405d -#define VOL_mmDCP4_GAMUT_REMAP_C23_C24 0x425d -#define VOL_mmDCP5_GAMUT_REMAP_C23_C24 0x445d -#define VOL_mmGAMUT_REMAP_C31_C32 0x1a5e -#define VOL_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e -#define VOL_mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e -#define VOL_mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e -#define VOL_mmDCP3_GAMUT_REMAP_C31_C32 0x405e -#define VOL_mmDCP4_GAMUT_REMAP_C31_C32 0x425e -#define VOL_mmDCP5_GAMUT_REMAP_C31_C32 0x445e -#define VOL_mmGAMUT_REMAP_C33_C34 0x1a5f -#define VOL_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f -#define VOL_mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f -#define VOL_mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f -#define VOL_mmDCP3_GAMUT_REMAP_C33_C34 0x405f -#define VOL_mmDCP4_GAMUT_REMAP_C33_C34 0x425f -#define VOL_mmDCP5_GAMUT_REMAP_C33_C34 0x445f -#define VOL_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 -#define VOL_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 -#define VOL_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 -#define VOL_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 -#define VOL_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 -#define VOL_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 -#define VOL_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 -#define VOL_mmDCP_RANDOM_SEEDS 0x1a61 -#define VOL_mmDCP0_DCP_RANDOM_SEEDS 0x1a61 -#define VOL_mmDCP1_DCP_RANDOM_SEEDS 0x1c61 -#define VOL_mmDCP2_DCP_RANDOM_SEEDS 0x1e61 -#define VOL_mmDCP3_DCP_RANDOM_SEEDS 0x4061 -#define VOL_mmDCP4_DCP_RANDOM_SEEDS 0x4261 -#define VOL_mmDCP5_DCP_RANDOM_SEEDS 0x4461 -#define VOL_mmDCP_FP_CONVERTED_FIELD 0x1a65 -#define VOL_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 -#define VOL_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 -#define VOL_mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 -#define VOL_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 -#define VOL_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 -#define VOL_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 -#define VOL_mmCUR_CONTROL 0x1a66 -#define VOL_mmDCP0_CUR_CONTROL 0x1a66 -#define VOL_mmDCP1_CUR_CONTROL 0x1c66 -#define VOL_mmDCP2_CUR_CONTROL 0x1e66 -#define VOL_mmDCP3_CUR_CONTROL 0x4066 -#define VOL_mmDCP4_CUR_CONTROL 0x4266 -#define VOL_mmDCP5_CUR_CONTROL 0x4466 -#define VOL_mmCUR_SURFACE_ADDRESS 0x1a67 -#define VOL_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 -#define VOL_mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 -#define VOL_mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 -#define VOL_mmDCP3_CUR_SURFACE_ADDRESS 0x4067 -#define VOL_mmDCP4_CUR_SURFACE_ADDRESS 0x4267 -#define VOL_mmDCP5_CUR_SURFACE_ADDRESS 0x4467 -#define VOL_mmCUR_SIZE 0x1a68 -#define VOL_mmDCP0_CUR_SIZE 0x1a68 -#define VOL_mmDCP1_CUR_SIZE 0x1c68 -#define VOL_mmDCP2_CUR_SIZE 0x1e68 -#define VOL_mmDCP3_CUR_SIZE 0x4068 -#define VOL_mmDCP4_CUR_SIZE 0x4268 -#define VOL_mmDCP5_CUR_SIZE 0x4468 -#define VOL_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define VOL_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 -#define VOL_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 -#define VOL_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 -#define VOL_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 -#define VOL_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 -#define VOL_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 -#define VOL_mmCUR_POSITION 0x1a6a -#define VOL_mmDCP0_CUR_POSITION 0x1a6a -#define VOL_mmDCP1_CUR_POSITION 0x1c6a -#define VOL_mmDCP2_CUR_POSITION 0x1e6a -#define VOL_mmDCP3_CUR_POSITION 0x406a -#define VOL_mmDCP4_CUR_POSITION 0x426a -#define VOL_mmDCP5_CUR_POSITION 0x446a -#define VOL_mmCUR_HOT_SPOT 0x1a6b -#define VOL_mmDCP0_CUR_HOT_SPOT 0x1a6b -#define VOL_mmDCP1_CUR_HOT_SPOT 0x1c6b -#define VOL_mmDCP2_CUR_HOT_SPOT 0x1e6b -#define VOL_mmDCP3_CUR_HOT_SPOT 0x406b -#define VOL_mmDCP4_CUR_HOT_SPOT 0x426b -#define VOL_mmDCP5_CUR_HOT_SPOT 0x446b -#define VOL_mmCUR_COLOR1 0x1a6c -#define VOL_mmDCP0_CUR_COLOR1 0x1a6c -#define VOL_mmDCP1_CUR_COLOR1 0x1c6c -#define VOL_mmDCP2_CUR_COLOR1 0x1e6c -#define VOL_mmDCP3_CUR_COLOR1 0x406c -#define VOL_mmDCP4_CUR_COLOR1 0x426c -#define VOL_mmDCP5_CUR_COLOR1 0x446c -#define VOL_mmCUR_COLOR2 0x1a6d -#define VOL_mmDCP0_CUR_COLOR2 0x1a6d -#define VOL_mmDCP1_CUR_COLOR2 0x1c6d -#define VOL_mmDCP2_CUR_COLOR2 0x1e6d -#define VOL_mmDCP3_CUR_COLOR2 0x406d -#define VOL_mmDCP4_CUR_COLOR2 0x426d -#define VOL_mmDCP5_CUR_COLOR2 0x446d -#define VOL_mmCUR_UPDATE 0x1a6e -#define VOL_mmDCP0_CUR_UPDATE 0x1a6e -#define VOL_mmDCP1_CUR_UPDATE 0x1c6e -#define VOL_mmDCP2_CUR_UPDATE 0x1e6e -#define VOL_mmDCP3_CUR_UPDATE 0x406e -#define VOL_mmDCP4_CUR_UPDATE 0x426e -#define VOL_mmDCP5_CUR_UPDATE 0x446e -#define VOL_mmCUR_REQUEST_FILTER_CNTL 0x1a99 -#define VOL_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 -#define VOL_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 -#define VOL_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 -#define VOL_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 -#define VOL_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 -#define VOL_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 -#define VOL_mmCUR_STEREO_CONTROL 0x1a9a -#define VOL_mmDCP0_CUR_STEREO_CONTROL 0x1a9a -#define VOL_mmDCP1_CUR_STEREO_CONTROL 0x1c9a -#define VOL_mmDCP2_CUR_STEREO_CONTROL 0x1e9a -#define VOL_mmDCP3_CUR_STEREO_CONTROL 0x409a -#define VOL_mmDCP4_CUR_STEREO_CONTROL 0x429a -#define VOL_mmDCP5_CUR_STEREO_CONTROL 0x449a -#define VOL_mmDC_LUT_RW_MODE 0x1a78 -#define VOL_mmDCP0_DC_LUT_RW_MODE 0x1a78 -#define VOL_mmDCP1_DC_LUT_RW_MODE 0x1c78 -#define VOL_mmDCP2_DC_LUT_RW_MODE 0x1e78 -#define VOL_mmDCP3_DC_LUT_RW_MODE 0x4078 -#define VOL_mmDCP4_DC_LUT_RW_MODE 0x4278 -#define VOL_mmDCP5_DC_LUT_RW_MODE 0x4478 -#define VOL_mmDC_LUT_RW_INDEX 0x1a79 -#define VOL_mmDCP0_DC_LUT_RW_INDEX 0x1a79 -#define VOL_mmDCP1_DC_LUT_RW_INDEX 0x1c79 -#define VOL_mmDCP2_DC_LUT_RW_INDEX 0x1e79 -#define VOL_mmDCP3_DC_LUT_RW_INDEX 0x4079 -#define VOL_mmDCP4_DC_LUT_RW_INDEX 0x4279 -#define VOL_mmDCP5_DC_LUT_RW_INDEX 0x4479 -#define VOL_mmDC_LUT_SEQ_COLOR 0x1a7a -#define VOL_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a -#define VOL_mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a -#define VOL_mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a -#define VOL_mmDCP3_DC_LUT_SEQ_COLOR 0x407a -#define VOL_mmDCP4_DC_LUT_SEQ_COLOR 0x427a -#define VOL_mmDCP5_DC_LUT_SEQ_COLOR 0x447a -#define VOL_mmDC_LUT_PWL_DATA 0x1a7b -#define VOL_mmDCP0_DC_LUT_PWL_DATA 0x1a7b -#define VOL_mmDCP1_DC_LUT_PWL_DATA 0x1c7b -#define VOL_mmDCP2_DC_LUT_PWL_DATA 0x1e7b -#define VOL_mmDCP3_DC_LUT_PWL_DATA 0x407b -#define VOL_mmDCP4_DC_LUT_PWL_DATA 0x427b -#define VOL_mmDCP5_DC_LUT_PWL_DATA 0x447b -#define VOL_mmDC_LUT_30_COLOR 0x1a7c -#define VOL_mmDCP0_DC_LUT_30_COLOR 0x1a7c -#define VOL_mmDCP1_DC_LUT_30_COLOR 0x1c7c -#define VOL_mmDCP2_DC_LUT_30_COLOR 0x1e7c -#define VOL_mmDCP3_DC_LUT_30_COLOR 0x407c -#define VOL_mmDCP4_DC_LUT_30_COLOR 0x427c -#define VOL_mmDCP5_DC_LUT_30_COLOR 0x447c -#define VOL_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define VOL_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d -#define VOL_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d -#define VOL_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d -#define VOL_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d -#define VOL_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d -#define VOL_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d -#define VOL_mmDC_LUT_WRITE_EN_MASK 0x1a7e -#define VOL_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e -#define VOL_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e -#define VOL_mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e -#define VOL_mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e -#define VOL_mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e -#define VOL_mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e -#define VOL_mmDC_LUT_AUTOFILL 0x1a7f -#define VOL_mmDCP0_DC_LUT_AUTOFILL 0x1a7f -#define VOL_mmDCP1_DC_LUT_AUTOFILL 0x1c7f -#define VOL_mmDCP2_DC_LUT_AUTOFILL 0x1e7f -#define VOL_mmDCP3_DC_LUT_AUTOFILL 0x407f -#define VOL_mmDCP4_DC_LUT_AUTOFILL 0x427f -#define VOL_mmDCP5_DC_LUT_AUTOFILL 0x447f -#define VOL_mmDC_LUT_CONTROL 0x1a80 -#define VOL_mmDCP0_DC_LUT_CONTROL 0x1a80 -#define VOL_mmDCP1_DC_LUT_CONTROL 0x1c80 -#define VOL_mmDCP2_DC_LUT_CONTROL 0x1e80 -#define VOL_mmDCP3_DC_LUT_CONTROL 0x4080 -#define VOL_mmDCP4_DC_LUT_CONTROL 0x4280 -#define VOL_mmDCP5_DC_LUT_CONTROL 0x4480 -#define VOL_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 -#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 -#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 -#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 -#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 -#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 -#define VOL_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 -#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 -#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 -#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 -#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 -#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 -#define VOL_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 -#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 -#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 -#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 -#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 -#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 -#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 -#define VOL_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 -#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 -#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 -#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 -#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 -#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 -#define VOL_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 -#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 -#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 -#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 -#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 -#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 -#define VOL_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 -#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 -#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 -#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 -#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 -#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 -#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 -#define VOL_mmDCP_CRC_CONTROL 0x1a87 -#define VOL_mmDCP0_DCP_CRC_CONTROL 0x1a87 -#define VOL_mmDCP1_DCP_CRC_CONTROL 0x1c87 -#define VOL_mmDCP2_DCP_CRC_CONTROL 0x1e87 -#define VOL_mmDCP3_DCP_CRC_CONTROL 0x4087 -#define VOL_mmDCP4_DCP_CRC_CONTROL 0x4287 -#define VOL_mmDCP5_DCP_CRC_CONTROL 0x4487 -#define VOL_mmDCP_CRC_MASK 0x1a88 -#define VOL_mmDCP0_DCP_CRC_MASK 0x1a88 -#define VOL_mmDCP1_DCP_CRC_MASK 0x1c88 -#define VOL_mmDCP2_DCP_CRC_MASK 0x1e88 -#define VOL_mmDCP3_DCP_CRC_MASK 0x4088 -#define VOL_mmDCP4_DCP_CRC_MASK 0x4288 -#define VOL_mmDCP5_DCP_CRC_MASK 0x4488 -#define VOL_mmDCP_CRC_CURRENT 0x1a89 -#define VOL_mmDCP0_DCP_CRC_CURRENT 0x1a89 -#define VOL_mmDCP1_DCP_CRC_CURRENT 0x1c89 -#define VOL_mmDCP2_DCP_CRC_CURRENT 0x1e89 -#define VOL_mmDCP3_DCP_CRC_CURRENT 0x4089 -#define VOL_mmDCP4_DCP_CRC_CURRENT 0x4289 -#define VOL_mmDCP5_DCP_CRC_CURRENT 0x4489 -#define VOL_mmDCP_CRC_LAST 0x1a8b -#define VOL_mmDCP0_DCP_CRC_LAST 0x1a8b -#define VOL_mmDCP1_DCP_CRC_LAST 0x1c8b -#define VOL_mmDCP2_DCP_CRC_LAST 0x1e8b -#define VOL_mmDCP3_DCP_CRC_LAST 0x408b -#define VOL_mmDCP4_DCP_CRC_LAST 0x428b -#define VOL_mmDCP5_DCP_CRC_LAST 0x448b -#define VOL_mmDCP_DEBUG 0x1a8d -#define VOL_mmDCP0_DCP_DEBUG 0x1a8d -#define VOL_mmDCP1_DCP_DEBUG 0x1c8d -#define VOL_mmDCP2_DCP_DEBUG 0x1e8d -#define VOL_mmDCP3_DCP_DEBUG 0x408d -#define VOL_mmDCP4_DCP_DEBUG 0x428d -#define VOL_mmDCP5_DCP_DEBUG 0x448d -#define VOL_mmGRPH_FLIP_RATE_CNTL 0x1a8e -#define VOL_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e -#define VOL_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e -#define VOL_mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e -#define VOL_mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e -#define VOL_mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e -#define VOL_mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e -#define VOL_mmDCP_GSL_CONTROL 0x1a90 -#define VOL_mmDCP0_DCP_GSL_CONTROL 0x1a90 -#define VOL_mmDCP1_DCP_GSL_CONTROL 0x1c90 -#define VOL_mmDCP2_DCP_GSL_CONTROL 0x1e90 -#define VOL_mmDCP3_DCP_GSL_CONTROL 0x4090 -#define VOL_mmDCP4_DCP_GSL_CONTROL 0x4290 -#define VOL_mmDCP5_DCP_GSL_CONTROL 0x4490 -#define VOL_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define VOL_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -#define VOL_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 -#define VOL_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 -#define VOL_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 -#define VOL_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 -#define VOL_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 -#define VOL_mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -#define VOL_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -#define VOL_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1c92 -#define VOL_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x1e92 -#define VOL_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 -#define VOL_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4292 -#define VOL_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4492 -#define VOL_mmOVL_STEREOSYNC_FLIP 0x1a93 -#define VOL_mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 -#define VOL_mmDCP1_OVL_STEREOSYNC_FLIP 0x1c93 -#define VOL_mmDCP2_OVL_STEREOSYNC_FLIP 0x1e93 -#define VOL_mmDCP3_OVL_STEREOSYNC_FLIP 0x4093 -#define VOL_mmDCP4_OVL_STEREOSYNC_FLIP 0x4293 -#define VOL_mmDCP5_OVL_STEREOSYNC_FLIP 0x4493 -#define VOL_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -#define VOL_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -#define VOL_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c94 -#define VOL_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e94 -#define VOL_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 -#define VOL_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4294 -#define VOL_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4494 -#define VOL_mmDCP_TEST_DEBUG_INDEX 0x1a95 -#define VOL_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 -#define VOL_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 -#define VOL_mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 -#define VOL_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 -#define VOL_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 -#define VOL_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 -#define VOL_mmDCP_TEST_DEBUG_DATA 0x1a96 -#define VOL_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 -#define VOL_mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 -#define VOL_mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 -#define VOL_mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 -#define VOL_mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 -#define VOL_mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 -#define VOL_mmGRPH_STEREOSYNC_FLIP 0x1a97 -#define VOL_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 -#define VOL_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 -#define VOL_mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 -#define VOL_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 -#define VOL_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 -#define VOL_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 -#define VOL_mmDCP_DEBUG2 0x1a98 -#define VOL_mmDCP0_DCP_DEBUG2 0x1a98 -#define VOL_mmDCP1_DCP_DEBUG2 0x1c98 -#define VOL_mmDCP2_DCP_DEBUG2 0x1e98 -#define VOL_mmDCP3_DCP_DEBUG2 0x4098 -#define VOL_mmDCP4_DCP_DEBUG2 0x4298 -#define VOL_mmDCP5_DCP_DEBUG2 0x4498 -#define VOL_mmHW_ROTATION 0x1a9e -#define VOL_mmDCP0_HW_ROTATION 0x1a9e -#define VOL_mmDCP1_HW_ROTATION 0x1c9e -#define VOL_mmDCP2_HW_ROTATION 0x1e9e -#define VOL_mmDCP3_HW_ROTATION 0x409e -#define VOL_mmDCP4_HW_ROTATION 0x429e -#define VOL_mmDCP5_HW_ROTATION 0x449e -#define VOL_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define VOL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -#define VOL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f -#define VOL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f -#define VOL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f -#define VOL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f -#define VOL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f -#define VOL_mmREGAMMA_CONTROL 0x1aa0 -#define VOL_mmDCP0_REGAMMA_CONTROL 0x1aa0 -#define VOL_mmDCP1_REGAMMA_CONTROL 0x1ca0 -#define VOL_mmDCP2_REGAMMA_CONTROL 0x1ea0 -#define VOL_mmDCP3_REGAMMA_CONTROL 0x40a0 -#define VOL_mmDCP4_REGAMMA_CONTROL 0x42a0 -#define VOL_mmDCP5_REGAMMA_CONTROL 0x44a0 -#define VOL_mmREGAMMA_LUT_INDEX 0x1aa1 -#define VOL_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 -#define VOL_mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 -#define VOL_mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 -#define VOL_mmDCP3_REGAMMA_LUT_INDEX 0x40a1 -#define VOL_mmDCP4_REGAMMA_LUT_INDEX 0x42a1 -#define VOL_mmDCP5_REGAMMA_LUT_INDEX 0x44a1 -#define VOL_mmREGAMMA_LUT_DATA 0x1aa2 -#define VOL_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 -#define VOL_mmDCP1_REGAMMA_LUT_DATA 0x1ca2 -#define VOL_mmDCP2_REGAMMA_LUT_DATA 0x1ea2 -#define VOL_mmDCP3_REGAMMA_LUT_DATA 0x40a2 -#define VOL_mmDCP4_REGAMMA_LUT_DATA 0x42a2 -#define VOL_mmDCP5_REGAMMA_LUT_DATA 0x44a2 -#define VOL_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define VOL_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -#define VOL_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 -#define VOL_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 -#define VOL_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 -#define VOL_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 -#define VOL_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 -#define VOL_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 -#define VOL_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 -#define VOL_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 -#define VOL_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 -#define VOL_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 -#define VOL_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 -#define VOL_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 -#define VOL_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define VOL_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -#define VOL_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 -#define VOL_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 -#define VOL_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 -#define VOL_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 -#define VOL_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 -#define VOL_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define VOL_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 -#define VOL_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 -#define VOL_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 -#define VOL_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 -#define VOL_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 -#define VOL_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 -#define VOL_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define VOL_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 -#define VOL_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 -#define VOL_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 -#define VOL_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 -#define VOL_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 -#define VOL_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 -#define VOL_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 -#define VOL_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 -#define VOL_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa -#define VOL_mmREGAMMA_CNTLA_REGION_6_7 0x1aab -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab -#define VOL_mmREGAMMA_CNTLA_REGION_8_9 0x1aac -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac -#define VOL_mmREGAMMA_CNTLA_REGION_10_11 0x1aad -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad -#define VOL_mmREGAMMA_CNTLA_REGION_12_13 0x1aae -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae -#define VOL_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf -#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf -#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf -#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf -#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af -#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af -#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af -#define VOL_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 -#define VOL_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 -#define VOL_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 -#define VOL_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 -#define VOL_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 -#define VOL_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 -#define VOL_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 -#define VOL_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define VOL_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -#define VOL_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 -#define VOL_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 -#define VOL_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 -#define VOL_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 -#define VOL_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 -#define VOL_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define VOL_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 -#define VOL_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 -#define VOL_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 -#define VOL_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 -#define VOL_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 -#define VOL_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 -#define VOL_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define VOL_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 -#define VOL_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 -#define VOL_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 -#define VOL_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 -#define VOL_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 -#define VOL_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 -#define VOL_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 -#define VOL_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 -#define VOL_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 -#define VOL_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 -#define VOL_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 -#define VOL_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 -#define VOL_mmREGAMMA_CNTLB_REGION_12_13 0x1aba -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba -#define VOL_mmREGAMMA_CNTLB_REGION_14_15 0x1abb -#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb -#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb -#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb -#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb -#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb -#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb -#define VOL_mmALPHA_CONTROL 0x1abc -#define VOL_mmDCP0_ALPHA_CONTROL 0x1abc -#define VOL_mmDCP1_ALPHA_CONTROL 0x1cbc -#define VOL_mmDCP2_ALPHA_CONTROL 0x1ebc -#define VOL_mmDCP3_ALPHA_CONTROL 0x40bc -#define VOL_mmDCP4_ALPHA_CONTROL 0x42bc -#define VOL_mmDCP5_ALPHA_CONTROL 0x44bc -#define VOL_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define VOL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -#define VOL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd -#define VOL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd -#define VOL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd -#define VOL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd -#define VOL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd -#define VOL_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define VOL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -#define VOL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe -#define VOL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe -#define VOL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be -#define VOL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be -#define VOL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be -#define VOL_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define VOL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -#define VOL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf -#define VOL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf -#define VOL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf -#define VOL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf -#define VOL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf -#define VOL_mmDIG_FE_CNTL 0x4a00 -#define VOL_mmDIG0_DIG_FE_CNTL 0x4a00 -#define VOL_mmDIG1_DIG_FE_CNTL 0x4b00 -#define VOL_mmDIG2_DIG_FE_CNTL 0x4c00 -#define VOL_mmDIG3_DIG_FE_CNTL 0x4d00 -#define VOL_mmDIG4_DIG_FE_CNTL 0x4e00 -#define VOL_mmDIG5_DIG_FE_CNTL 0x4f00 -#define VOL_mmDIG6_DIG_FE_CNTL 0x5400 -#define VOL_mmDIG_OUTPUT_CRC_CNTL 0x4a01 -#define VOL_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 -#define VOL_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 -#define VOL_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 -#define VOL_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 -#define VOL_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 -#define VOL_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 -#define VOL_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 -#define VOL_mmDIG_OUTPUT_CRC_RESULT 0x4a02 -#define VOL_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 -#define VOL_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 -#define VOL_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 -#define VOL_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 -#define VOL_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 -#define VOL_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 -#define VOL_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 -#define VOL_mmDIG_CLOCK_PATTERN 0x4a03 -#define VOL_mmDIG0_DIG_CLOCK_PATTERN 0x4a03 -#define VOL_mmDIG1_DIG_CLOCK_PATTERN 0x4b03 -#define VOL_mmDIG2_DIG_CLOCK_PATTERN 0x4c03 -#define VOL_mmDIG3_DIG_CLOCK_PATTERN 0x4d03 -#define VOL_mmDIG4_DIG_CLOCK_PATTERN 0x4e03 -#define VOL_mmDIG5_DIG_CLOCK_PATTERN 0x4f03 -#define VOL_mmDIG6_DIG_CLOCK_PATTERN 0x5403 -#define VOL_mmDIG_TEST_PATTERN 0x4a04 -#define VOL_mmDIG0_DIG_TEST_PATTERN 0x4a04 -#define VOL_mmDIG1_DIG_TEST_PATTERN 0x4b04 -#define VOL_mmDIG2_DIG_TEST_PATTERN 0x4c04 -#define VOL_mmDIG3_DIG_TEST_PATTERN 0x4d04 -#define VOL_mmDIG4_DIG_TEST_PATTERN 0x4e04 -#define VOL_mmDIG5_DIG_TEST_PATTERN 0x4f04 -#define VOL_mmDIG6_DIG_TEST_PATTERN 0x5404 -#define VOL_mmDIG_RANDOM_PATTERN_SEED 0x4a05 -#define VOL_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 -#define VOL_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 -#define VOL_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 -#define VOL_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 -#define VOL_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 -#define VOL_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 -#define VOL_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 -#define VOL_mmDIG_FIFO_STATUS 0x4a06 -#define VOL_mmDIG0_DIG_FIFO_STATUS 0x4a06 -#define VOL_mmDIG1_DIG_FIFO_STATUS 0x4b06 -#define VOL_mmDIG2_DIG_FIFO_STATUS 0x4c06 -#define VOL_mmDIG3_DIG_FIFO_STATUS 0x4d06 -#define VOL_mmDIG4_DIG_FIFO_STATUS 0x4e06 -#define VOL_mmDIG5_DIG_FIFO_STATUS 0x4f06 -#define VOL_mmDIG6_DIG_FIFO_STATUS 0x5406 -#define VOL_mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 -#define VOL_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 -#define VOL_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 -#define VOL_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 -#define VOL_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 -#define VOL_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 -#define VOL_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 -#define VOL_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 -#define VOL_mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 -#define VOL_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 -#define VOL_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 -#define VOL_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 -#define VOL_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 -#define VOL_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 -#define VOL_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 -#define VOL_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 -#define VOL_mmHDMI_CONTROL 0x4a09 -#define VOL_mmDIG0_HDMI_CONTROL 0x4a09 -#define VOL_mmDIG1_HDMI_CONTROL 0x4b09 -#define VOL_mmDIG2_HDMI_CONTROL 0x4c09 -#define VOL_mmDIG3_HDMI_CONTROL 0x4d09 -#define VOL_mmDIG4_HDMI_CONTROL 0x4e09 -#define VOL_mmDIG5_HDMI_CONTROL 0x4f09 -#define VOL_mmDIG6_HDMI_CONTROL 0x5409 -#define VOL_mmHDMI_STATUS 0x4a0a -#define VOL_mmDIG0_HDMI_STATUS 0x4a0a -#define VOL_mmDIG1_HDMI_STATUS 0x4b0a -#define VOL_mmDIG2_HDMI_STATUS 0x4c0a -#define VOL_mmDIG3_HDMI_STATUS 0x4d0a -#define VOL_mmDIG4_HDMI_STATUS 0x4e0a -#define VOL_mmDIG5_HDMI_STATUS 0x4f0a -#define VOL_mmDIG6_HDMI_STATUS 0x540a -#define VOL_mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b -#define VOL_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b -#define VOL_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b -#define VOL_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b -#define VOL_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b -#define VOL_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b -#define VOL_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b -#define VOL_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b -#define VOL_mmHDMI_ACR_PACKET_CONTROL 0x4a0c -#define VOL_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c -#define VOL_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c -#define VOL_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c -#define VOL_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c -#define VOL_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c -#define VOL_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c -#define VOL_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c -#define VOL_mmHDMI_VBI_PACKET_CONTROL 0x4a0d -#define VOL_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d -#define VOL_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d -#define VOL_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d -#define VOL_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d -#define VOL_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d -#define VOL_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d -#define VOL_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d -#define VOL_mmHDMI_INFOFRAME_CONTROL0 0x4a0e -#define VOL_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e -#define VOL_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e -#define VOL_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e -#define VOL_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e -#define VOL_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e -#define VOL_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e -#define VOL_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e -#define VOL_mmHDMI_INFOFRAME_CONTROL1 0x4a0f -#define VOL_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f -#define VOL_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f -#define VOL_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f -#define VOL_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f -#define VOL_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f -#define VOL_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f -#define VOL_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f -#define VOL_mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 -#define VOL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 -#define VOL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 -#define VOL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 -#define VOL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 -#define VOL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 -#define VOL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 -#define VOL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 -#define VOL_mmAFMT_INTERRUPT_STATUS 0x4a11 -#define VOL_mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 -#define VOL_mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 -#define VOL_mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 -#define VOL_mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 -#define VOL_mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 -#define VOL_mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 -#define VOL_mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 -#define VOL_mmHDMI_GC 0x4a13 -#define VOL_mmDIG0_HDMI_GC 0x4a13 -#define VOL_mmDIG1_HDMI_GC 0x4b13 -#define VOL_mmDIG2_HDMI_GC 0x4c13 -#define VOL_mmDIG3_HDMI_GC 0x4d13 -#define VOL_mmDIG4_HDMI_GC 0x4e13 -#define VOL_mmDIG5_HDMI_GC 0x4f13 -#define VOL_mmDIG6_HDMI_GC 0x5413 -#define VOL_mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 -#define VOL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 -#define VOL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 -#define VOL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 -#define VOL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 -#define VOL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 -#define VOL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 -#define VOL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 -#define VOL_mmAFMT_ISRC1_0 0x4a15 -#define VOL_mmDIG0_AFMT_ISRC1_0 0x4a15 -#define VOL_mmDIG1_AFMT_ISRC1_0 0x4b15 -#define VOL_mmDIG2_AFMT_ISRC1_0 0x4c15 -#define VOL_mmDIG3_AFMT_ISRC1_0 0x4d15 -#define VOL_mmDIG4_AFMT_ISRC1_0 0x4e15 -#define VOL_mmDIG5_AFMT_ISRC1_0 0x4f15 -#define VOL_mmDIG6_AFMT_ISRC1_0 0x5415 -#define VOL_mmAFMT_ISRC1_1 0x4a16 -#define VOL_mmDIG0_AFMT_ISRC1_1 0x4a16 -#define VOL_mmDIG1_AFMT_ISRC1_1 0x4b16 -#define VOL_mmDIG2_AFMT_ISRC1_1 0x4c16 -#define VOL_mmDIG3_AFMT_ISRC1_1 0x4d16 -#define VOL_mmDIG4_AFMT_ISRC1_1 0x4e16 -#define VOL_mmDIG5_AFMT_ISRC1_1 0x4f16 -#define VOL_mmDIG6_AFMT_ISRC1_1 0x5416 -#define VOL_mmAFMT_ISRC1_2 0x4a17 -#define VOL_mmDIG0_AFMT_ISRC1_2 0x4a17 -#define VOL_mmDIG1_AFMT_ISRC1_2 0x4b17 -#define VOL_mmDIG2_AFMT_ISRC1_2 0x4c17 -#define VOL_mmDIG3_AFMT_ISRC1_2 0x4d17 -#define VOL_mmDIG4_AFMT_ISRC1_2 0x4e17 -#define VOL_mmDIG5_AFMT_ISRC1_2 0x4f17 -#define VOL_mmDIG6_AFMT_ISRC1_2 0x5417 -#define VOL_mmAFMT_ISRC1_3 0x4a18 -#define VOL_mmDIG0_AFMT_ISRC1_3 0x4a18 -#define VOL_mmDIG1_AFMT_ISRC1_3 0x4b18 -#define VOL_mmDIG2_AFMT_ISRC1_3 0x4c18 -#define VOL_mmDIG3_AFMT_ISRC1_3 0x4d18 -#define VOL_mmDIG4_AFMT_ISRC1_3 0x4e18 -#define VOL_mmDIG5_AFMT_ISRC1_3 0x4f18 -#define VOL_mmDIG6_AFMT_ISRC1_3 0x5418 -#define VOL_mmAFMT_ISRC1_4 0x4a19 -#define VOL_mmDIG0_AFMT_ISRC1_4 0x4a19 -#define VOL_mmDIG1_AFMT_ISRC1_4 0x4b19 -#define VOL_mmDIG2_AFMT_ISRC1_4 0x4c19 -#define VOL_mmDIG3_AFMT_ISRC1_4 0x4d19 -#define VOL_mmDIG4_AFMT_ISRC1_4 0x4e19 -#define VOL_mmDIG5_AFMT_ISRC1_4 0x4f19 -#define VOL_mmDIG6_AFMT_ISRC1_4 0x5419 -#define VOL_mmAFMT_ISRC2_0 0x4a1a -#define VOL_mmDIG0_AFMT_ISRC2_0 0x4a1a -#define VOL_mmDIG1_AFMT_ISRC2_0 0x4b1a -#define VOL_mmDIG2_AFMT_ISRC2_0 0x4c1a -#define VOL_mmDIG3_AFMT_ISRC2_0 0x4d1a -#define VOL_mmDIG4_AFMT_ISRC2_0 0x4e1a -#define VOL_mmDIG5_AFMT_ISRC2_0 0x4f1a -#define VOL_mmDIG6_AFMT_ISRC2_0 0x541a -#define VOL_mmAFMT_ISRC2_1 0x4a1b -#define VOL_mmDIG0_AFMT_ISRC2_1 0x4a1b -#define VOL_mmDIG1_AFMT_ISRC2_1 0x4b1b -#define VOL_mmDIG2_AFMT_ISRC2_1 0x4c1b -#define VOL_mmDIG3_AFMT_ISRC2_1 0x4d1b -#define VOL_mmDIG4_AFMT_ISRC2_1 0x4e1b -#define VOL_mmDIG5_AFMT_ISRC2_1 0x4f1b -#define VOL_mmDIG6_AFMT_ISRC2_1 0x541b -#define VOL_mmAFMT_ISRC2_2 0x4a1c -#define VOL_mmDIG0_AFMT_ISRC2_2 0x4a1c -#define VOL_mmDIG1_AFMT_ISRC2_2 0x4b1c -#define VOL_mmDIG2_AFMT_ISRC2_2 0x4c1c -#define VOL_mmDIG3_AFMT_ISRC2_2 0x4d1c -#define VOL_mmDIG4_AFMT_ISRC2_2 0x4e1c -#define VOL_mmDIG5_AFMT_ISRC2_2 0x4f1c -#define VOL_mmDIG6_AFMT_ISRC2_2 0x541c -#define VOL_mmAFMT_ISRC2_3 0x4a1d -#define VOL_mmDIG0_AFMT_ISRC2_3 0x4a1d -#define VOL_mmDIG1_AFMT_ISRC2_3 0x4b1d -#define VOL_mmDIG2_AFMT_ISRC2_3 0x4c1d -#define VOL_mmDIG3_AFMT_ISRC2_3 0x4d1d -#define VOL_mmDIG4_AFMT_ISRC2_3 0x4e1d -#define VOL_mmDIG5_AFMT_ISRC2_3 0x4f1d -#define VOL_mmDIG6_AFMT_ISRC2_3 0x541d -#define VOL_mmAFMT_AVI_INFO0 0x4a1e -#define VOL_mmDIG0_AFMT_AVI_INFO0 0x4a1e -#define VOL_mmDIG1_AFMT_AVI_INFO0 0x4b1e -#define VOL_mmDIG2_AFMT_AVI_INFO0 0x4c1e -#define VOL_mmDIG3_AFMT_AVI_INFO0 0x4d1e -#define VOL_mmDIG4_AFMT_AVI_INFO0 0x4e1e -#define VOL_mmDIG5_AFMT_AVI_INFO0 0x4f1e -#define VOL_mmDIG6_AFMT_AVI_INFO0 0x541e -#define VOL_mmAFMT_AVI_INFO1 0x4a1f -#define VOL_mmDIG0_AFMT_AVI_INFO1 0x4a1f -#define VOL_mmDIG1_AFMT_AVI_INFO1 0x4b1f -#define VOL_mmDIG2_AFMT_AVI_INFO1 0x4c1f -#define VOL_mmDIG3_AFMT_AVI_INFO1 0x4d1f -#define VOL_mmDIG4_AFMT_AVI_INFO1 0x4e1f -#define VOL_mmDIG5_AFMT_AVI_INFO1 0x4f1f -#define VOL_mmDIG6_AFMT_AVI_INFO1 0x541f -#define VOL_mmAFMT_AVI_INFO2 0x4a20 -#define VOL_mmDIG0_AFMT_AVI_INFO2 0x4a20 -#define VOL_mmDIG1_AFMT_AVI_INFO2 0x4b20 -#define VOL_mmDIG2_AFMT_AVI_INFO2 0x4c20 -#define VOL_mmDIG3_AFMT_AVI_INFO2 0x4d20 -#define VOL_mmDIG4_AFMT_AVI_INFO2 0x4e20 -#define VOL_mmDIG5_AFMT_AVI_INFO2 0x4f20 -#define VOL_mmDIG6_AFMT_AVI_INFO2 0x5420 -#define VOL_mmAFMT_AVI_INFO3 0x4a21 -#define VOL_mmDIG0_AFMT_AVI_INFO3 0x4a21 -#define VOL_mmDIG1_AFMT_AVI_INFO3 0x4b21 -#define VOL_mmDIG2_AFMT_AVI_INFO3 0x4c21 -#define VOL_mmDIG3_AFMT_AVI_INFO3 0x4d21 -#define VOL_mmDIG4_AFMT_AVI_INFO3 0x4e21 -#define VOL_mmDIG5_AFMT_AVI_INFO3 0x4f21 -#define VOL_mmDIG6_AFMT_AVI_INFO3 0x5421 -#define VOL_mmAFMT_MPEG_INFO0 0x4a22 -#define VOL_mmDIG0_AFMT_MPEG_INFO0 0x4a22 -#define VOL_mmDIG1_AFMT_MPEG_INFO0 0x4b22 -#define VOL_mmDIG2_AFMT_MPEG_INFO0 0x4c22 -#define VOL_mmDIG3_AFMT_MPEG_INFO0 0x4d22 -#define VOL_mmDIG4_AFMT_MPEG_INFO0 0x4e22 -#define VOL_mmDIG5_AFMT_MPEG_INFO0 0x4f22 -#define VOL_mmDIG6_AFMT_MPEG_INFO0 0x5422 -#define VOL_mmAFMT_MPEG_INFO1 0x4a23 -#define VOL_mmDIG0_AFMT_MPEG_INFO1 0x4a23 -#define VOL_mmDIG1_AFMT_MPEG_INFO1 0x4b23 -#define VOL_mmDIG2_AFMT_MPEG_INFO1 0x4c23 -#define VOL_mmDIG3_AFMT_MPEG_INFO1 0x4d23 -#define VOL_mmDIG4_AFMT_MPEG_INFO1 0x4e23 -#define VOL_mmDIG5_AFMT_MPEG_INFO1 0x4f23 -#define VOL_mmDIG6_AFMT_MPEG_INFO1 0x5423 -#define VOL_mmAFMT_GENERIC_HDR 0x4a24 -#define VOL_mmDIG0_AFMT_GENERIC_HDR 0x4a24 -#define VOL_mmDIG1_AFMT_GENERIC_HDR 0x4b24 -#define VOL_mmDIG2_AFMT_GENERIC_HDR 0x4c24 -#define VOL_mmDIG3_AFMT_GENERIC_HDR 0x4d24 -#define VOL_mmDIG4_AFMT_GENERIC_HDR 0x4e24 -#define VOL_mmDIG5_AFMT_GENERIC_HDR 0x4f24 -#define VOL_mmDIG6_AFMT_GENERIC_HDR 0x5424 -#define VOL_mmAFMT_GENERIC_0 0x4a25 -#define VOL_mmDIG0_AFMT_GENERIC_0 0x4a25 -#define VOL_mmDIG1_AFMT_GENERIC_0 0x4b25 -#define VOL_mmDIG2_AFMT_GENERIC_0 0x4c25 -#define VOL_mmDIG3_AFMT_GENERIC_0 0x4d25 -#define VOL_mmDIG4_AFMT_GENERIC_0 0x4e25 -#define VOL_mmDIG5_AFMT_GENERIC_0 0x4f25 -#define VOL_mmDIG6_AFMT_GENERIC_0 0x5425 -#define VOL_mmAFMT_GENERIC_1 0x4a26 -#define VOL_mmDIG0_AFMT_GENERIC_1 0x4a26 -#define VOL_mmDIG1_AFMT_GENERIC_1 0x4b26 -#define VOL_mmDIG2_AFMT_GENERIC_1 0x4c26 -#define VOL_mmDIG3_AFMT_GENERIC_1 0x4d26 -#define VOL_mmDIG4_AFMT_GENERIC_1 0x4e26 -#define VOL_mmDIG5_AFMT_GENERIC_1 0x4f26 -#define VOL_mmDIG6_AFMT_GENERIC_1 0x5426 -#define VOL_mmAFMT_GENERIC_2 0x4a27 -#define VOL_mmDIG0_AFMT_GENERIC_2 0x4a27 -#define VOL_mmDIG1_AFMT_GENERIC_2 0x4b27 -#define VOL_mmDIG2_AFMT_GENERIC_2 0x4c27 -#define VOL_mmDIG3_AFMT_GENERIC_2 0x4d27 -#define VOL_mmDIG4_AFMT_GENERIC_2 0x4e27 -#define VOL_mmDIG5_AFMT_GENERIC_2 0x4f27 -#define VOL_mmDIG6_AFMT_GENERIC_2 0x5427 -#define VOL_mmAFMT_GENERIC_3 0x4a28 -#define VOL_mmDIG0_AFMT_GENERIC_3 0x4a28 -#define VOL_mmDIG1_AFMT_GENERIC_3 0x4b28 -#define VOL_mmDIG2_AFMT_GENERIC_3 0x4c28 -#define VOL_mmDIG3_AFMT_GENERIC_3 0x4d28 -#define VOL_mmDIG4_AFMT_GENERIC_3 0x4e28 -#define VOL_mmDIG5_AFMT_GENERIC_3 0x4f28 -#define VOL_mmDIG6_AFMT_GENERIC_3 0x5428 -#define VOL_mmAFMT_GENERIC_4 0x4a29 -#define VOL_mmDIG0_AFMT_GENERIC_4 0x4a29 -#define VOL_mmDIG1_AFMT_GENERIC_4 0x4b29 -#define VOL_mmDIG2_AFMT_GENERIC_4 0x4c29 -#define VOL_mmDIG3_AFMT_GENERIC_4 0x4d29 -#define VOL_mmDIG4_AFMT_GENERIC_4 0x4e29 -#define VOL_mmDIG5_AFMT_GENERIC_4 0x4f29 -#define VOL_mmDIG6_AFMT_GENERIC_4 0x5429 -#define VOL_mmAFMT_GENERIC_5 0x4a2a -#define VOL_mmDIG0_AFMT_GENERIC_5 0x4a2a -#define VOL_mmDIG1_AFMT_GENERIC_5 0x4b2a -#define VOL_mmDIG2_AFMT_GENERIC_5 0x4c2a -#define VOL_mmDIG3_AFMT_GENERIC_5 0x4d2a -#define VOL_mmDIG4_AFMT_GENERIC_5 0x4e2a -#define VOL_mmDIG5_AFMT_GENERIC_5 0x4f2a -#define VOL_mmDIG6_AFMT_GENERIC_5 0x542a -#define VOL_mmAFMT_GENERIC_6 0x4a2b -#define VOL_mmDIG0_AFMT_GENERIC_6 0x4a2b -#define VOL_mmDIG1_AFMT_GENERIC_6 0x4b2b -#define VOL_mmDIG2_AFMT_GENERIC_6 0x4c2b -#define VOL_mmDIG3_AFMT_GENERIC_6 0x4d2b -#define VOL_mmDIG4_AFMT_GENERIC_6 0x4e2b -#define VOL_mmDIG5_AFMT_GENERIC_6 0x4f2b -#define VOL_mmDIG6_AFMT_GENERIC_6 0x542b -#define VOL_mmAFMT_GENERIC_7 0x4a2c -#define VOL_mmDIG0_AFMT_GENERIC_7 0x4a2c -#define VOL_mmDIG1_AFMT_GENERIC_7 0x4b2c -#define VOL_mmDIG2_AFMT_GENERIC_7 0x4c2c -#define VOL_mmDIG3_AFMT_GENERIC_7 0x4d2c -#define VOL_mmDIG4_AFMT_GENERIC_7 0x4e2c -#define VOL_mmDIG5_AFMT_GENERIC_7 0x4f2c -#define VOL_mmDIG6_AFMT_GENERIC_7 0x542c -#define VOL_mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d -#define VOL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d -#define VOL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d -#define VOL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d -#define VOL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d -#define VOL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d -#define VOL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d -#define VOL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d -#define VOL_mmHDMI_ACR_32_0 0x4a2e -#define VOL_mmDIG0_HDMI_ACR_32_0 0x4a2e -#define VOL_mmDIG1_HDMI_ACR_32_0 0x4b2e -#define VOL_mmDIG2_HDMI_ACR_32_0 0x4c2e -#define VOL_mmDIG3_HDMI_ACR_32_0 0x4d2e -#define VOL_mmDIG4_HDMI_ACR_32_0 0x4e2e -#define VOL_mmDIG5_HDMI_ACR_32_0 0x4f2e -#define VOL_mmDIG6_HDMI_ACR_32_0 0x542e -#define VOL_mmHDMI_ACR_32_1 0x4a2f -#define VOL_mmDIG0_HDMI_ACR_32_1 0x4a2f -#define VOL_mmDIG1_HDMI_ACR_32_1 0x4b2f -#define VOL_mmDIG2_HDMI_ACR_32_1 0x4c2f -#define VOL_mmDIG3_HDMI_ACR_32_1 0x4d2f -#define VOL_mmDIG4_HDMI_ACR_32_1 0x4e2f -#define VOL_mmDIG5_HDMI_ACR_32_1 0x4f2f -#define VOL_mmDIG6_HDMI_ACR_32_1 0x542f -#define VOL_mmHDMI_ACR_44_0 0x4a30 -#define VOL_mmDIG0_HDMI_ACR_44_0 0x4a30 -#define VOL_mmDIG1_HDMI_ACR_44_0 0x4b30 -#define VOL_mmDIG2_HDMI_ACR_44_0 0x4c30 -#define VOL_mmDIG3_HDMI_ACR_44_0 0x4d30 -#define VOL_mmDIG4_HDMI_ACR_44_0 0x4e30 -#define VOL_mmDIG5_HDMI_ACR_44_0 0x4f30 -#define VOL_mmDIG6_HDMI_ACR_44_0 0x5430 -#define VOL_mmHDMI_ACR_44_1 0x4a31 -#define VOL_mmDIG0_HDMI_ACR_44_1 0x4a31 -#define VOL_mmDIG1_HDMI_ACR_44_1 0x4b31 -#define VOL_mmDIG2_HDMI_ACR_44_1 0x4c31 -#define VOL_mmDIG3_HDMI_ACR_44_1 0x4d31 -#define VOL_mmDIG4_HDMI_ACR_44_1 0x4e31 -#define VOL_mmDIG5_HDMI_ACR_44_1 0x4f31 -#define VOL_mmDIG6_HDMI_ACR_44_1 0x5431 -#define VOL_mmHDMI_ACR_48_0 0x4a32 -#define VOL_mmDIG0_HDMI_ACR_48_0 0x4a32 -#define VOL_mmDIG1_HDMI_ACR_48_0 0x4b32 -#define VOL_mmDIG2_HDMI_ACR_48_0 0x4c32 -#define VOL_mmDIG3_HDMI_ACR_48_0 0x4d32 -#define VOL_mmDIG4_HDMI_ACR_48_0 0x4e32 -#define VOL_mmDIG5_HDMI_ACR_48_0 0x4f32 -#define VOL_mmDIG6_HDMI_ACR_48_0 0x5432 -#define VOL_mmHDMI_ACR_48_1 0x4a33 -#define VOL_mmDIG0_HDMI_ACR_48_1 0x4a33 -#define VOL_mmDIG1_HDMI_ACR_48_1 0x4b33 -#define VOL_mmDIG2_HDMI_ACR_48_1 0x4c33 -#define VOL_mmDIG3_HDMI_ACR_48_1 0x4d33 -#define VOL_mmDIG4_HDMI_ACR_48_1 0x4e33 -#define VOL_mmDIG5_HDMI_ACR_48_1 0x4f33 -#define VOL_mmDIG6_HDMI_ACR_48_1 0x5433 -#define VOL_mmHDMI_ACR_STATUS_0 0x4a34 -#define VOL_mmDIG0_HDMI_ACR_STATUS_0 0x4a34 -#define VOL_mmDIG1_HDMI_ACR_STATUS_0 0x4b34 -#define VOL_mmDIG2_HDMI_ACR_STATUS_0 0x4c34 -#define VOL_mmDIG3_HDMI_ACR_STATUS_0 0x4d34 -#define VOL_mmDIG4_HDMI_ACR_STATUS_0 0x4e34 -#define VOL_mmDIG5_HDMI_ACR_STATUS_0 0x4f34 -#define VOL_mmDIG6_HDMI_ACR_STATUS_0 0x5434 -#define VOL_mmHDMI_ACR_STATUS_1 0x4a35 -#define VOL_mmDIG0_HDMI_ACR_STATUS_1 0x4a35 -#define VOL_mmDIG1_HDMI_ACR_STATUS_1 0x4b35 -#define VOL_mmDIG2_HDMI_ACR_STATUS_1 0x4c35 -#define VOL_mmDIG3_HDMI_ACR_STATUS_1 0x4d35 -#define VOL_mmDIG4_HDMI_ACR_STATUS_1 0x4e35 -#define VOL_mmDIG5_HDMI_ACR_STATUS_1 0x4f35 -#define VOL_mmDIG6_HDMI_ACR_STATUS_1 0x5435 -#define VOL_mmAFMT_AUDIO_INFO0 0x4a36 -#define VOL_mmDIG0_AFMT_AUDIO_INFO0 0x4a36 -#define VOL_mmDIG1_AFMT_AUDIO_INFO0 0x4b36 -#define VOL_mmDIG2_AFMT_AUDIO_INFO0 0x4c36 -#define VOL_mmDIG3_AFMT_AUDIO_INFO0 0x4d36 -#define VOL_mmDIG4_AFMT_AUDIO_INFO0 0x4e36 -#define VOL_mmDIG5_AFMT_AUDIO_INFO0 0x4f36 -#define VOL_mmDIG6_AFMT_AUDIO_INFO0 0x5436 -#define VOL_mmAFMT_AUDIO_INFO1 0x4a37 -#define VOL_mmDIG0_AFMT_AUDIO_INFO1 0x4a37 -#define VOL_mmDIG1_AFMT_AUDIO_INFO1 0x4b37 -#define VOL_mmDIG2_AFMT_AUDIO_INFO1 0x4c37 -#define VOL_mmDIG3_AFMT_AUDIO_INFO1 0x4d37 -#define VOL_mmDIG4_AFMT_AUDIO_INFO1 0x4e37 -#define VOL_mmDIG5_AFMT_AUDIO_INFO1 0x4f37 -#define VOL_mmDIG6_AFMT_AUDIO_INFO1 0x5437 -#define VOL_mmAFMT_60958_0 0x4a38 -#define VOL_mmDIG0_AFMT_60958_0 0x4a38 -#define VOL_mmDIG1_AFMT_60958_0 0x4b38 -#define VOL_mmDIG2_AFMT_60958_0 0x4c38 -#define VOL_mmDIG3_AFMT_60958_0 0x4d38 -#define VOL_mmDIG4_AFMT_60958_0 0x4e38 -#define VOL_mmDIG5_AFMT_60958_0 0x4f38 -#define VOL_mmDIG6_AFMT_60958_0 0x5438 -#define VOL_mmAFMT_60958_1 0x4a39 -#define VOL_mmDIG0_AFMT_60958_1 0x4a39 -#define VOL_mmDIG1_AFMT_60958_1 0x4b39 -#define VOL_mmDIG2_AFMT_60958_1 0x4c39 -#define VOL_mmDIG3_AFMT_60958_1 0x4d39 -#define VOL_mmDIG4_AFMT_60958_1 0x4e39 -#define VOL_mmDIG5_AFMT_60958_1 0x4f39 -#define VOL_mmDIG6_AFMT_60958_1 0x5439 -#define VOL_mmAFMT_AUDIO_CRC_CONTROL 0x4a3a -#define VOL_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a -#define VOL_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a -#define VOL_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a -#define VOL_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a -#define VOL_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a -#define VOL_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a -#define VOL_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a -#define VOL_mmAFMT_RAMP_CONTROL0 0x4a3b -#define VOL_mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b -#define VOL_mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b -#define VOL_mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b -#define VOL_mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b -#define VOL_mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b -#define VOL_mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b -#define VOL_mmDIG6_AFMT_RAMP_CONTROL0 0x543b -#define VOL_mmAFMT_RAMP_CONTROL1 0x4a3c -#define VOL_mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c -#define VOL_mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c -#define VOL_mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c -#define VOL_mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c -#define VOL_mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c -#define VOL_mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c -#define VOL_mmDIG6_AFMT_RAMP_CONTROL1 0x543c -#define VOL_mmAFMT_RAMP_CONTROL2 0x4a3d -#define VOL_mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d -#define VOL_mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d -#define VOL_mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d -#define VOL_mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d -#define VOL_mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d -#define VOL_mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d -#define VOL_mmDIG6_AFMT_RAMP_CONTROL2 0x543d -#define VOL_mmAFMT_RAMP_CONTROL3 0x4a3e -#define VOL_mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e -#define VOL_mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e -#define VOL_mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e -#define VOL_mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e -#define VOL_mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e -#define VOL_mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e -#define VOL_mmDIG6_AFMT_RAMP_CONTROL3 0x543e -#define VOL_mmAFMT_60958_2 0x4a3f -#define VOL_mmDIG0_AFMT_60958_2 0x4a3f -#define VOL_mmDIG1_AFMT_60958_2 0x4b3f -#define VOL_mmDIG2_AFMT_60958_2 0x4c3f -#define VOL_mmDIG3_AFMT_60958_2 0x4d3f -#define VOL_mmDIG4_AFMT_60958_2 0x4e3f -#define VOL_mmDIG5_AFMT_60958_2 0x4f3f -#define VOL_mmDIG6_AFMT_60958_2 0x543f -#define VOL_mmAFMT_AUDIO_CRC_RESULT 0x4a40 -#define VOL_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 -#define VOL_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 -#define VOL_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 -#define VOL_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 -#define VOL_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 -#define VOL_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 -#define VOL_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 -#define VOL_mmAFMT_STATUS 0x4a41 -#define VOL_mmDIG0_AFMT_STATUS 0x4a41 -#define VOL_mmDIG1_AFMT_STATUS 0x4b41 -#define VOL_mmDIG2_AFMT_STATUS 0x4c41 -#define VOL_mmDIG3_AFMT_STATUS 0x4d41 -#define VOL_mmDIG4_AFMT_STATUS 0x4e41 -#define VOL_mmDIG5_AFMT_STATUS 0x4f41 -#define VOL_mmDIG6_AFMT_STATUS 0x5441 -#define VOL_mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 -#define VOL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 -#define VOL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 -#define VOL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 -#define VOL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 -#define VOL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 -#define VOL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 -#define VOL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 -#define VOL_mmAFMT_VBI_PACKET_CONTROL 0x4a43 -#define VOL_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 -#define VOL_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 -#define VOL_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 -#define VOL_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 -#define VOL_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 -#define VOL_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 -#define VOL_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 -#define VOL_mmAFMT_INFOFRAME_CONTROL0 0x4a44 -#define VOL_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 -#define VOL_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 -#define VOL_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 -#define VOL_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 -#define VOL_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 -#define VOL_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 -#define VOL_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 -#define VOL_mmAFMT_AUDIO_SRC_CONTROL 0x4a45 -#define VOL_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 -#define VOL_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 -#define VOL_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 -#define VOL_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 -#define VOL_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 -#define VOL_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 -#define VOL_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 -#define VOL_mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 -#define VOL_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 -#define VOL_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 -#define VOL_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 -#define VOL_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 -#define VOL_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 -#define VOL_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 -#define VOL_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 -#define VOL_mmDIG_BE_CNTL 0x4a47 -#define VOL_mmDIG0_DIG_BE_CNTL 0x4a47 -#define VOL_mmDIG1_DIG_BE_CNTL 0x4b47 -#define VOL_mmDIG2_DIG_BE_CNTL 0x4c47 -#define VOL_mmDIG3_DIG_BE_CNTL 0x4d47 -#define VOL_mmDIG4_DIG_BE_CNTL 0x4e47 -#define VOL_mmDIG5_DIG_BE_CNTL 0x4f47 -#define VOL_mmDIG6_DIG_BE_CNTL 0x5447 -#define VOL_mmDIG_BE_EN_CNTL 0x4a48 -#define VOL_mmDIG0_DIG_BE_EN_CNTL 0x4a48 -#define VOL_mmDIG1_DIG_BE_EN_CNTL 0x4b48 -#define VOL_mmDIG2_DIG_BE_EN_CNTL 0x4c48 -#define VOL_mmDIG3_DIG_BE_EN_CNTL 0x4d48 -#define VOL_mmDIG4_DIG_BE_EN_CNTL 0x4e48 -#define VOL_mmDIG5_DIG_BE_EN_CNTL 0x4f48 -#define VOL_mmDIG6_DIG_BE_EN_CNTL 0x5448 -#define VOL_mmTMDS_CNTL 0x4a6b -#define VOL_mmDIG0_TMDS_CNTL 0x4a6b -#define VOL_mmDIG1_TMDS_CNTL 0x4b6b -#define VOL_mmDIG2_TMDS_CNTL 0x4c6b -#define VOL_mmDIG3_TMDS_CNTL 0x4d6b -#define VOL_mmDIG4_TMDS_CNTL 0x4e6b -#define VOL_mmDIG5_TMDS_CNTL 0x4f6b -#define VOL_mmDIG6_TMDS_CNTL 0x546b -#define VOL_mmTMDS_CONTROL_CHAR 0x4a6c -#define VOL_mmDIG0_TMDS_CONTROL_CHAR 0x4a6c -#define VOL_mmDIG1_TMDS_CONTROL_CHAR 0x4b6c -#define VOL_mmDIG2_TMDS_CONTROL_CHAR 0x4c6c -#define VOL_mmDIG3_TMDS_CONTROL_CHAR 0x4d6c -#define VOL_mmDIG4_TMDS_CONTROL_CHAR 0x4e6c -#define VOL_mmDIG5_TMDS_CONTROL_CHAR 0x4f6c -#define VOL_mmDIG6_TMDS_CONTROL_CHAR 0x546c -#define VOL_mmTMDS_CONTROL0_FEEDBACK 0x4a6d -#define VOL_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d -#define VOL_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d -#define VOL_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d -#define VOL_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d -#define VOL_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d -#define VOL_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d -#define VOL_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d -#define VOL_mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e -#define VOL_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e -#define VOL_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e -#define VOL_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e -#define VOL_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e -#define VOL_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e -#define VOL_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e -#define VOL_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e -#define VOL_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f -#define VOL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f -#define VOL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f -#define VOL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f -#define VOL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f -#define VOL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f -#define VOL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f -#define VOL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f -#define VOL_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 -#define VOL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 -#define VOL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 -#define VOL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 -#define VOL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 -#define VOL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 -#define VOL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 -#define VOL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 -#define VOL_mmTMDS_DEBUG 0x4a71 -#define VOL_mmDIG0_TMDS_DEBUG 0x4a71 -#define VOL_mmDIG1_TMDS_DEBUG 0x4b71 -#define VOL_mmDIG2_TMDS_DEBUG 0x4c71 -#define VOL_mmDIG3_TMDS_DEBUG 0x4d71 -#define VOL_mmDIG4_TMDS_DEBUG 0x4e71 -#define VOL_mmDIG5_TMDS_DEBUG 0x4f71 -#define VOL_mmDIG6_TMDS_DEBUG 0x5471 -#define VOL_mmTMDS_CTL_BITS 0x4a72 -#define VOL_mmDIG0_TMDS_CTL_BITS 0x4a72 -#define VOL_mmDIG1_TMDS_CTL_BITS 0x4b72 -#define VOL_mmDIG2_TMDS_CTL_BITS 0x4c72 -#define VOL_mmDIG3_TMDS_CTL_BITS 0x4d72 -#define VOL_mmDIG4_TMDS_CTL_BITS 0x4e72 -#define VOL_mmDIG5_TMDS_CTL_BITS 0x4f72 -#define VOL_mmDIG6_TMDS_CTL_BITS 0x5472 -#define VOL_mmTMDS_DCBALANCER_CONTROL 0x4a73 -#define VOL_mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 -#define VOL_mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 -#define VOL_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 -#define VOL_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 -#define VOL_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 -#define VOL_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 -#define VOL_mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 -#define VOL_mmTMDS_CTL0_1_GEN_CNTL 0x4a75 -#define VOL_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 -#define VOL_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 -#define VOL_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 -#define VOL_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 -#define VOL_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 -#define VOL_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 -#define VOL_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 -#define VOL_mmTMDS_CTL2_3_GEN_CNTL 0x4a76 -#define VOL_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 -#define VOL_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 -#define VOL_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 -#define VOL_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 -#define VOL_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 -#define VOL_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 -#define VOL_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 -#define VOL_ixTMDS_DEBUG1 0x1 -#define VOL_ixTMDS_DEBUG2 0x2 -#define VOL_ixTMDS_DEBUG3 0x3 -#define VOL_ixTMDS_DEBUG7 0x4 -#define VOL_ixTMDS_DEBUG8 0x5 -#define VOL_ixTMDS_DEBUG9 0x6 -#define VOL_ixTMDS_DEBUG10 0x7 -#define VOL_ixTMDS_DEBUG11 0x8 -#define VOL_ixTMDS_DEBUG12 0x9 -#define VOL_ixTMDS_DEBUG13 0xa -#define VOL_mmLVDS_DATA_CNTL 0x4a78 -#define VOL_mmDIG0_LVDS_DATA_CNTL 0x4a78 -#define VOL_mmDIG1_LVDS_DATA_CNTL 0x4b78 -#define VOL_mmDIG2_LVDS_DATA_CNTL 0x4c78 -#define VOL_mmDIG3_LVDS_DATA_CNTL 0x4d78 -#define VOL_mmDIG4_LVDS_DATA_CNTL 0x4e78 -#define VOL_mmDIG5_LVDS_DATA_CNTL 0x4f78 -#define VOL_mmDIG6_LVDS_DATA_CNTL 0x5478 -#define VOL_mmDIG_LANE_ENABLE 0x4a79 -#define VOL_mmDIG0_DIG_LANE_ENABLE 0x4a79 -#define VOL_mmDIG1_DIG_LANE_ENABLE 0x4b79 -#define VOL_mmDIG2_DIG_LANE_ENABLE 0x4c79 -#define VOL_mmDIG3_DIG_LANE_ENABLE 0x4d79 -#define VOL_mmDIG4_DIG_LANE_ENABLE 0x4e79 -#define VOL_mmDIG5_DIG_LANE_ENABLE 0x4f79 -#define VOL_mmDIG6_DIG_LANE_ENABLE 0x5479 -#define VOL_mmDIG_TEST_DEBUG_INDEX 0x4a7a -#define VOL_mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a -#define VOL_mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a -#define VOL_mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a -#define VOL_mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a -#define VOL_mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a -#define VOL_mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a -#define VOL_mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a -#define VOL_mmDIG_TEST_DEBUG_DATA 0x4a7b -#define VOL_mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b -#define VOL_mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b -#define VOL_mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b -#define VOL_mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b -#define VOL_mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b -#define VOL_mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b -#define VOL_mmDIG6_DIG_TEST_DEBUG_DATA 0x547b -#define VOL_mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c -#define VOL_mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c -#define VOL_mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c -#define VOL_mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c -#define VOL_mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c -#define VOL_mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c -#define VOL_mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c -#define VOL_mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c -#define VOL_mmDIG_FE_TEST_DEBUG_DATA 0x4a7d -#define VOL_mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d -#define VOL_mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d -#define VOL_mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d -#define VOL_mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d -#define VOL_mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d -#define VOL_mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d -#define VOL_mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d -#define VOL_mmDMCU_CTRL 0x1600 -#define VOL_mmDMCU_STATUS 0x1601 -#define VOL_mmDMCU_PC_START_ADDR 0x1602 -#define VOL_mmDMCU_FW_START_ADDR 0x1603 -#define VOL_mmDMCU_FW_END_ADDR 0x1604 -#define VOL_mmDMCU_FW_ISR_START_ADDR 0x1605 -#define VOL_mmDMCU_FW_CS_HI 0x1606 -#define VOL_mmDMCU_FW_CS_LO 0x1607 -#define VOL_mmDMCU_RAM_ACCESS_CTRL 0x1608 -#define VOL_mmDMCU_ERAM_WR_CTRL 0x1609 -#define VOL_mmDMCU_ERAM_WR_DATA 0x160a -#define VOL_mmDMCU_ERAM_RD_CTRL 0x160b -#define VOL_mmDMCU_ERAM_RD_DATA 0x160c -#define VOL_mmDMCU_IRAM_WR_CTRL 0x160d -#define VOL_mmDMCU_IRAM_WR_DATA 0x160e -#define VOL_mmDMCU_IRAM_RD_CTRL 0x160f -#define VOL_mmDMCU_IRAM_RD_DATA 0x1610 -#define VOL_mmDMCU_EVENT_TRIGGER 0x1611 -#define VOL_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 -#define VOL_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 -#define VOL_mmDMCU_INTERRUPT_STATUS 0x1614 -#define VOL_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 -#define VOL_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 -#define VOL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 -#define VOL_mmDC_DMCU_SCRATCH 0x1618 -#define VOL_mmDMCU_INT_CNT 0x1619 -#define VOL_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a -#define VOL_mmDMCU_UC_CLK_GATING_CNTL 0x161b -#define VOL_mmMASTER_COMM_DATA_REG1 0x161c -#define VOL_mmMASTER_COMM_DATA_REG2 0x161d -#define VOL_mmMASTER_COMM_DATA_REG3 0x161e -#define VOL_mmMASTER_COMM_CMD_REG 0x161f -#define VOL_mmMASTER_COMM_CNTL_REG 0x1620 -#define VOL_mmSLAVE_COMM_DATA_REG1 0x1621 -#define VOL_mmSLAVE_COMM_DATA_REG2 0x1622 -#define VOL_mmSLAVE_COMM_DATA_REG3 0x1623 -#define VOL_mmSLAVE_COMM_CMD_REG 0x1624 -#define VOL_mmSLAVE_COMM_CNTL_REG 0x1625 -#define VOL_mmDMCU_TEST_DEBUG_INDEX 0x1626 -#define VOL_mmDMCU_TEST_DEBUG_DATA 0x1627 -#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 -#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 -#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 -#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 -#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x167c -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x167d -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x167e -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x167f -#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5 0x1633 -#define VOL_mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 -#define VOL_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 -#define VOL_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 -#define VOL_mmDP_LINK_CNTL 0x4aa0 -#define VOL_mmDP0_DP_LINK_CNTL 0x4aa0 -#define VOL_mmDP1_DP_LINK_CNTL 0x4ba0 -#define VOL_mmDP2_DP_LINK_CNTL 0x4ca0 -#define VOL_mmDP3_DP_LINK_CNTL 0x4da0 -#define VOL_mmDP4_DP_LINK_CNTL 0x4ea0 -#define VOL_mmDP5_DP_LINK_CNTL 0x4fa0 -#define VOL_mmDP6_DP_LINK_CNTL 0x54a0 -#define VOL_mmDP_PIXEL_FORMAT 0x4aa1 -#define VOL_mmDP0_DP_PIXEL_FORMAT 0x4aa1 -#define VOL_mmDP1_DP_PIXEL_FORMAT 0x4ba1 -#define VOL_mmDP2_DP_PIXEL_FORMAT 0x4ca1 -#define VOL_mmDP3_DP_PIXEL_FORMAT 0x4da1 -#define VOL_mmDP4_DP_PIXEL_FORMAT 0x4ea1 -#define VOL_mmDP5_DP_PIXEL_FORMAT 0x4fa1 -#define VOL_mmDP6_DP_PIXEL_FORMAT 0x54a1 -#define VOL_mmDP_MSA_COLORIMETRY 0x4aa2 -#define VOL_mmDP0_DP_MSA_COLORIMETRY 0x4aa2 -#define VOL_mmDP1_DP_MSA_COLORIMETRY 0x4ba2 -#define VOL_mmDP2_DP_MSA_COLORIMETRY 0x4ca2 -#define VOL_mmDP3_DP_MSA_COLORIMETRY 0x4da2 -#define VOL_mmDP4_DP_MSA_COLORIMETRY 0x4ea2 -#define VOL_mmDP5_DP_MSA_COLORIMETRY 0x4fa2 -#define VOL_mmDP6_DP_MSA_COLORIMETRY 0x54a2 -#define VOL_mmDP_CONFIG 0x4aa3 -#define VOL_mmDP0_DP_CONFIG 0x4aa3 -#define VOL_mmDP1_DP_CONFIG 0x4ba3 -#define VOL_mmDP2_DP_CONFIG 0x4ca3 -#define VOL_mmDP3_DP_CONFIG 0x4da3 -#define VOL_mmDP4_DP_CONFIG 0x4ea3 -#define VOL_mmDP5_DP_CONFIG 0x4fa3 -#define VOL_mmDP6_DP_CONFIG 0x54a3 -#define VOL_mmDP_VID_STREAM_CNTL 0x4aa4 -#define VOL_mmDP0_DP_VID_STREAM_CNTL 0x4aa4 -#define VOL_mmDP1_DP_VID_STREAM_CNTL 0x4ba4 -#define VOL_mmDP2_DP_VID_STREAM_CNTL 0x4ca4 -#define VOL_mmDP3_DP_VID_STREAM_CNTL 0x4da4 -#define VOL_mmDP4_DP_VID_STREAM_CNTL 0x4ea4 -#define VOL_mmDP5_DP_VID_STREAM_CNTL 0x4fa4 -#define VOL_mmDP6_DP_VID_STREAM_CNTL 0x54a4 -#define VOL_mmDP_STEER_FIFO 0x4aa5 -#define VOL_mmDP0_DP_STEER_FIFO 0x4aa5 -#define VOL_mmDP1_DP_STEER_FIFO 0x4ba5 -#define VOL_mmDP2_DP_STEER_FIFO 0x4ca5 -#define VOL_mmDP3_DP_STEER_FIFO 0x4da5 -#define VOL_mmDP4_DP_STEER_FIFO 0x4ea5 -#define VOL_mmDP5_DP_STEER_FIFO 0x4fa5 -#define VOL_mmDP6_DP_STEER_FIFO 0x54a5 -#define VOL_mmDP_MSA_MISC 0x4aa6 -#define VOL_mmDP0_DP_MSA_MISC 0x4aa6 -#define VOL_mmDP1_DP_MSA_MISC 0x4ba6 -#define VOL_mmDP2_DP_MSA_MISC 0x4ca6 -#define VOL_mmDP3_DP_MSA_MISC 0x4da6 -#define VOL_mmDP4_DP_MSA_MISC 0x4ea6 -#define VOL_mmDP5_DP_MSA_MISC 0x4fa6 -#define VOL_mmDP6_DP_MSA_MISC 0x54a6 -#define VOL_mmDP_VID_TIMING 0x4aa8 -#define VOL_mmDP0_DP_VID_TIMING 0x4aa8 -#define VOL_mmDP1_DP_VID_TIMING 0x4ba8 -#define VOL_mmDP2_DP_VID_TIMING 0x4ca8 -#define VOL_mmDP3_DP_VID_TIMING 0x4da8 -#define VOL_mmDP4_DP_VID_TIMING 0x4ea8 -#define VOL_mmDP5_DP_VID_TIMING 0x4fa8 -#define VOL_mmDP6_DP_VID_TIMING 0x54a8 -#define VOL_mmDP_VID_N 0x4aa9 -#define VOL_mmDP0_DP_VID_N 0x4aa9 -#define VOL_mmDP1_DP_VID_N 0x4ba9 -#define VOL_mmDP2_DP_VID_N 0x4ca9 -#define VOL_mmDP3_DP_VID_N 0x4da9 -#define VOL_mmDP4_DP_VID_N 0x4ea9 -#define VOL_mmDP5_DP_VID_N 0x4fa9 -#define VOL_mmDP6_DP_VID_N 0x54a9 -#define VOL_mmDP_VID_M 0x4aaa -#define VOL_mmDP0_DP_VID_M 0x4aaa -#define VOL_mmDP1_DP_VID_M 0x4baa -#define VOL_mmDP2_DP_VID_M 0x4caa -#define VOL_mmDP3_DP_VID_M 0x4daa -#define VOL_mmDP4_DP_VID_M 0x4eaa -#define VOL_mmDP5_DP_VID_M 0x4faa -#define VOL_mmDP6_DP_VID_M 0x54aa -#define VOL_mmDP_LINK_FRAMING_CNTL 0x4aab -#define VOL_mmDP0_DP_LINK_FRAMING_CNTL 0x4aab -#define VOL_mmDP1_DP_LINK_FRAMING_CNTL 0x4bab -#define VOL_mmDP2_DP_LINK_FRAMING_CNTL 0x4cab -#define VOL_mmDP3_DP_LINK_FRAMING_CNTL 0x4dab -#define VOL_mmDP4_DP_LINK_FRAMING_CNTL 0x4eab -#define VOL_mmDP5_DP_LINK_FRAMING_CNTL 0x4fab -#define VOL_mmDP6_DP_LINK_FRAMING_CNTL 0x54ab -#define VOL_mmDP_HBR2_EYE_PATTERN 0x4aac -#define VOL_mmDP0_DP_HBR2_EYE_PATTERN 0x4aac -#define VOL_mmDP1_DP_HBR2_EYE_PATTERN 0x4bac -#define VOL_mmDP2_DP_HBR2_EYE_PATTERN 0x4cac -#define VOL_mmDP3_DP_HBR2_EYE_PATTERN 0x4dac -#define VOL_mmDP4_DP_HBR2_EYE_PATTERN 0x4eac -#define VOL_mmDP5_DP_HBR2_EYE_PATTERN 0x4fac -#define VOL_mmDP6_DP_HBR2_EYE_PATTERN 0x54ac -#define VOL_mmDP_VID_MSA_VBID 0x4aad -#define VOL_mmDP0_DP_VID_MSA_VBID 0x4aad -#define VOL_mmDP1_DP_VID_MSA_VBID 0x4bad -#define VOL_mmDP2_DP_VID_MSA_VBID 0x4cad -#define VOL_mmDP3_DP_VID_MSA_VBID 0x4dad -#define VOL_mmDP4_DP_VID_MSA_VBID 0x4ead -#define VOL_mmDP5_DP_VID_MSA_VBID 0x4fad -#define VOL_mmDP6_DP_VID_MSA_VBID 0x54ad -#define VOL_mmDP_VID_INTERRUPT_CNTL 0x4aae -#define VOL_mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae -#define VOL_mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae -#define VOL_mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae -#define VOL_mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae -#define VOL_mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae -#define VOL_mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae -#define VOL_mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae -#define VOL_mmDP_DPHY_CNTL 0x4aaf -#define VOL_mmDP0_DP_DPHY_CNTL 0x4aaf -#define VOL_mmDP1_DP_DPHY_CNTL 0x4baf -#define VOL_mmDP2_DP_DPHY_CNTL 0x4caf -#define VOL_mmDP3_DP_DPHY_CNTL 0x4daf -#define VOL_mmDP4_DP_DPHY_CNTL 0x4eaf -#define VOL_mmDP5_DP_DPHY_CNTL 0x4faf -#define VOL_mmDP6_DP_DPHY_CNTL 0x54af -#define VOL_mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 -#define VOL_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 -#define VOL_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 -#define VOL_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 -#define VOL_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 -#define VOL_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 -#define VOL_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 -#define VOL_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 -#define VOL_mmDP_DPHY_SYM0 0x4ab1 -#define VOL_mmDP0_DP_DPHY_SYM0 0x4ab1 -#define VOL_mmDP1_DP_DPHY_SYM0 0x4bb1 -#define VOL_mmDP2_DP_DPHY_SYM0 0x4cb1 -#define VOL_mmDP3_DP_DPHY_SYM0 0x4db1 -#define VOL_mmDP4_DP_DPHY_SYM0 0x4eb1 -#define VOL_mmDP5_DP_DPHY_SYM0 0x4fb1 -#define VOL_mmDP6_DP_DPHY_SYM0 0x54b1 -#define VOL_mmDP_DPHY_SYM1 0x4ab2 -#define VOL_mmDP0_DP_DPHY_SYM1 0x4ab2 -#define VOL_mmDP1_DP_DPHY_SYM1 0x4bb2 -#define VOL_mmDP2_DP_DPHY_SYM1 0x4cb2 -#define VOL_mmDP3_DP_DPHY_SYM1 0x4db2 -#define VOL_mmDP4_DP_DPHY_SYM1 0x4eb2 -#define VOL_mmDP5_DP_DPHY_SYM1 0x4fb2 -#define VOL_mmDP6_DP_DPHY_SYM1 0x54b2 -#define VOL_mmDP_DPHY_SYM2 0x4ab3 -#define VOL_mmDP0_DP_DPHY_SYM2 0x4ab3 -#define VOL_mmDP1_DP_DPHY_SYM2 0x4bb3 -#define VOL_mmDP2_DP_DPHY_SYM2 0x4cb3 -#define VOL_mmDP3_DP_DPHY_SYM2 0x4db3 -#define VOL_mmDP4_DP_DPHY_SYM2 0x4eb3 -#define VOL_mmDP5_DP_DPHY_SYM2 0x4fb3 -#define VOL_mmDP6_DP_DPHY_SYM2 0x54b3 -#define VOL_mmDP_DPHY_8B10B_CNTL 0x4ab4 -#define VOL_mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 -#define VOL_mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 -#define VOL_mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 -#define VOL_mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 -#define VOL_mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 -#define VOL_mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 -#define VOL_mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 -#define VOL_mmDP_DPHY_PRBS_CNTL 0x4ab5 -#define VOL_mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 -#define VOL_mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 -#define VOL_mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 -#define VOL_mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 -#define VOL_mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 -#define VOL_mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 -#define VOL_mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 -#define VOL_mmDP_DPHY_CRC_EN 0x4ab7 -#define VOL_mmDP0_DP_DPHY_CRC_EN 0x4ab7 -#define VOL_mmDP1_DP_DPHY_CRC_EN 0x4bb7 -#define VOL_mmDP2_DP_DPHY_CRC_EN 0x4cb7 -#define VOL_mmDP3_DP_DPHY_CRC_EN 0x4db7 -#define VOL_mmDP4_DP_DPHY_CRC_EN 0x4eb7 -#define VOL_mmDP5_DP_DPHY_CRC_EN 0x4fb7 -#define VOL_mmDP6_DP_DPHY_CRC_EN 0x54b7 -#define VOL_mmDP_DPHY_CRC_CNTL 0x4ab8 -#define VOL_mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 -#define VOL_mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 -#define VOL_mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 -#define VOL_mmDP3_DP_DPHY_CRC_CNTL 0x4db8 -#define VOL_mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 -#define VOL_mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 -#define VOL_mmDP6_DP_DPHY_CRC_CNTL 0x54b8 -#define VOL_mmDP_DPHY_CRC_RESULT 0x4ab9 -#define VOL_mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 -#define VOL_mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 -#define VOL_mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 -#define VOL_mmDP3_DP_DPHY_CRC_RESULT 0x4db9 -#define VOL_mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 -#define VOL_mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 -#define VOL_mmDP6_DP_DPHY_CRC_RESULT 0x54b9 -#define VOL_mmDP_DPHY_CRC_MST_CNTL 0x4aba -#define VOL_mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba -#define VOL_mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba -#define VOL_mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba -#define VOL_mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba -#define VOL_mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba -#define VOL_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba -#define VOL_mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba -#define VOL_mmDP_DPHY_CRC_MST_STATUS 0x4abb -#define VOL_mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb -#define VOL_mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb -#define VOL_mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb -#define VOL_mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb -#define VOL_mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb -#define VOL_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb -#define VOL_mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb -#define VOL_mmDP_DPHY_FAST_TRAINING 0x4abc -#define VOL_mmDP0_DP_DPHY_FAST_TRAINING 0x4abc -#define VOL_mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc -#define VOL_mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc -#define VOL_mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc -#define VOL_mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc -#define VOL_mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc -#define VOL_mmDP6_DP_DPHY_FAST_TRAINING 0x54bc -#define VOL_mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd -#define VOL_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd -#define VOL_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd -#define VOL_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd -#define VOL_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd -#define VOL_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd -#define VOL_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd -#define VOL_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd -#define VOL_mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe -#define VOL_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe -#define VOL_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe -#define VOL_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe -#define VOL_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe -#define VOL_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe -#define VOL_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe -#define VOL_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be -#define VOL_mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf -#define VOL_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf -#define VOL_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf -#define VOL_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf -#define VOL_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf -#define VOL_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf -#define VOL_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf -#define VOL_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf -#define VOL_mmDP_SEC_CNTL 0x4ac3 -#define VOL_mmDP0_DP_SEC_CNTL 0x4ac3 -#define VOL_mmDP1_DP_SEC_CNTL 0x4bc3 -#define VOL_mmDP2_DP_SEC_CNTL 0x4cc3 -#define VOL_mmDP3_DP_SEC_CNTL 0x4dc3 -#define VOL_mmDP4_DP_SEC_CNTL 0x4ec3 -#define VOL_mmDP5_DP_SEC_CNTL 0x4fc3 -#define VOL_mmDP6_DP_SEC_CNTL 0x54c3 -#define VOL_mmDP_SEC_CNTL1 0x4ac4 -#define VOL_mmDP0_DP_SEC_CNTL1 0x4ac4 -#define VOL_mmDP1_DP_SEC_CNTL1 0x4bc4 -#define VOL_mmDP2_DP_SEC_CNTL1 0x4cc4 -#define VOL_mmDP3_DP_SEC_CNTL1 0x4dc4 -#define VOL_mmDP4_DP_SEC_CNTL1 0x4ec4 -#define VOL_mmDP5_DP_SEC_CNTL1 0x4fc4 -#define VOL_mmDP6_DP_SEC_CNTL1 0x54c4 -#define VOL_mmDP_SEC_FRAMING1 0x4ac5 -#define VOL_mmDP0_DP_SEC_FRAMING1 0x4ac5 -#define VOL_mmDP1_DP_SEC_FRAMING1 0x4bc5 -#define VOL_mmDP2_DP_SEC_FRAMING1 0x4cc5 -#define VOL_mmDP3_DP_SEC_FRAMING1 0x4dc5 -#define VOL_mmDP4_DP_SEC_FRAMING1 0x4ec5 -#define VOL_mmDP5_DP_SEC_FRAMING1 0x4fc5 -#define VOL_mmDP6_DP_SEC_FRAMING1 0x54c5 -#define VOL_mmDP_SEC_FRAMING2 0x4ac6 -#define VOL_mmDP0_DP_SEC_FRAMING2 0x4ac6 -#define VOL_mmDP1_DP_SEC_FRAMING2 0x4bc6 -#define VOL_mmDP2_DP_SEC_FRAMING2 0x4cc6 -#define VOL_mmDP3_DP_SEC_FRAMING2 0x4dc6 -#define VOL_mmDP4_DP_SEC_FRAMING2 0x4ec6 -#define VOL_mmDP5_DP_SEC_FRAMING2 0x4fc6 -#define VOL_mmDP6_DP_SEC_FRAMING2 0x54c6 -#define VOL_mmDP_SEC_FRAMING3 0x4ac7 -#define VOL_mmDP0_DP_SEC_FRAMING3 0x4ac7 -#define VOL_mmDP1_DP_SEC_FRAMING3 0x4bc7 -#define VOL_mmDP2_DP_SEC_FRAMING3 0x4cc7 -#define VOL_mmDP3_DP_SEC_FRAMING3 0x4dc7 -#define VOL_mmDP4_DP_SEC_FRAMING3 0x4ec7 -#define VOL_mmDP5_DP_SEC_FRAMING3 0x4fc7 -#define VOL_mmDP6_DP_SEC_FRAMING3 0x54c7 -#define VOL_mmDP_SEC_FRAMING4 0x4ac8 -#define VOL_mmDP0_DP_SEC_FRAMING4 0x4ac8 -#define VOL_mmDP1_DP_SEC_FRAMING4 0x4bc8 -#define VOL_mmDP2_DP_SEC_FRAMING4 0x4cc8 -#define VOL_mmDP3_DP_SEC_FRAMING4 0x4dc8 -#define VOL_mmDP4_DP_SEC_FRAMING4 0x4ec8 -#define VOL_mmDP5_DP_SEC_FRAMING4 0x4fc8 -#define VOL_mmDP6_DP_SEC_FRAMING4 0x54c8 -#define VOL_mmDP_SEC_AUD_N 0x4ac9 -#define VOL_mmDP0_DP_SEC_AUD_N 0x4ac9 -#define VOL_mmDP1_DP_SEC_AUD_N 0x4bc9 -#define VOL_mmDP2_DP_SEC_AUD_N 0x4cc9 -#define VOL_mmDP3_DP_SEC_AUD_N 0x4dc9 -#define VOL_mmDP4_DP_SEC_AUD_N 0x4ec9 -#define VOL_mmDP5_DP_SEC_AUD_N 0x4fc9 -#define VOL_mmDP6_DP_SEC_AUD_N 0x54c9 -#define VOL_mmDP_SEC_AUD_N_READBACK 0x4aca -#define VOL_mmDP0_DP_SEC_AUD_N_READBACK 0x4aca -#define VOL_mmDP1_DP_SEC_AUD_N_READBACK 0x4bca -#define VOL_mmDP2_DP_SEC_AUD_N_READBACK 0x4cca -#define VOL_mmDP3_DP_SEC_AUD_N_READBACK 0x4dca -#define VOL_mmDP4_DP_SEC_AUD_N_READBACK 0x4eca -#define VOL_mmDP5_DP_SEC_AUD_N_READBACK 0x4fca -#define VOL_mmDP6_DP_SEC_AUD_N_READBACK 0x54ca -#define VOL_mmDP_SEC_AUD_M 0x4acb -#define VOL_mmDP0_DP_SEC_AUD_M 0x4acb -#define VOL_mmDP1_DP_SEC_AUD_M 0x4bcb -#define VOL_mmDP2_DP_SEC_AUD_M 0x4ccb -#define VOL_mmDP3_DP_SEC_AUD_M 0x4dcb -#define VOL_mmDP4_DP_SEC_AUD_M 0x4ecb -#define VOL_mmDP5_DP_SEC_AUD_M 0x4fcb -#define VOL_mmDP6_DP_SEC_AUD_M 0x54cb -#define VOL_mmDP_SEC_AUD_M_READBACK 0x4acc -#define VOL_mmDP0_DP_SEC_AUD_M_READBACK 0x4acc -#define VOL_mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc -#define VOL_mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc -#define VOL_mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc -#define VOL_mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc -#define VOL_mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc -#define VOL_mmDP6_DP_SEC_AUD_M_READBACK 0x54cc -#define VOL_mmDP_SEC_TIMESTAMP 0x4acd -#define VOL_mmDP0_DP_SEC_TIMESTAMP 0x4acd -#define VOL_mmDP1_DP_SEC_TIMESTAMP 0x4bcd -#define VOL_mmDP2_DP_SEC_TIMESTAMP 0x4ccd -#define VOL_mmDP3_DP_SEC_TIMESTAMP 0x4dcd -#define VOL_mmDP4_DP_SEC_TIMESTAMP 0x4ecd -#define VOL_mmDP5_DP_SEC_TIMESTAMP 0x4fcd -#define VOL_mmDP6_DP_SEC_TIMESTAMP 0x54cd -#define VOL_mmDP_SEC_PACKET_CNTL 0x4ace -#define VOL_mmDP0_DP_SEC_PACKET_CNTL 0x4ace -#define VOL_mmDP1_DP_SEC_PACKET_CNTL 0x4bce -#define VOL_mmDP2_DP_SEC_PACKET_CNTL 0x4cce -#define VOL_mmDP3_DP_SEC_PACKET_CNTL 0x4dce -#define VOL_mmDP4_DP_SEC_PACKET_CNTL 0x4ece -#define VOL_mmDP5_DP_SEC_PACKET_CNTL 0x4fce -#define VOL_mmDP6_DP_SEC_PACKET_CNTL 0x54ce -#define VOL_mmDP_MSE_RATE_CNTL 0x4acf -#define VOL_mmDP0_DP_MSE_RATE_CNTL 0x4acf -#define VOL_mmDP1_DP_MSE_RATE_CNTL 0x4bcf -#define VOL_mmDP2_DP_MSE_RATE_CNTL 0x4ccf -#define VOL_mmDP3_DP_MSE_RATE_CNTL 0x4dcf -#define VOL_mmDP4_DP_MSE_RATE_CNTL 0x4ecf -#define VOL_mmDP5_DP_MSE_RATE_CNTL 0x4fcf -#define VOL_mmDP6_DP_MSE_RATE_CNTL 0x54cf -#define VOL_mmDP_MSE_RATE_UPDATE 0x4ad1 -#define VOL_mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 -#define VOL_mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 -#define VOL_mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 -#define VOL_mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 -#define VOL_mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 -#define VOL_mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 -#define VOL_mmDP6_DP_MSE_RATE_UPDATE 0x54d1 -#define VOL_mmDP_MSE_SAT0 0x4ad2 -#define VOL_mmDP0_DP_MSE_SAT0 0x4ad2 -#define VOL_mmDP1_DP_MSE_SAT0 0x4bd2 -#define VOL_mmDP2_DP_MSE_SAT0 0x4cd2 -#define VOL_mmDP3_DP_MSE_SAT0 0x4dd2 -#define VOL_mmDP4_DP_MSE_SAT0 0x4ed2 -#define VOL_mmDP5_DP_MSE_SAT0 0x4fd2 -#define VOL_mmDP6_DP_MSE_SAT0 0x54d2 -#define VOL_mmDP_MSE_SAT1 0x4ad3 -#define VOL_mmDP0_DP_MSE_SAT1 0x4ad3 -#define VOL_mmDP1_DP_MSE_SAT1 0x4bd3 -#define VOL_mmDP2_DP_MSE_SAT1 0x4cd3 -#define VOL_mmDP3_DP_MSE_SAT1 0x4dd3 -#define VOL_mmDP4_DP_MSE_SAT1 0x4ed3 -#define VOL_mmDP5_DP_MSE_SAT1 0x4fd3 -#define VOL_mmDP6_DP_MSE_SAT1 0x54d3 -#define VOL_mmDP_MSE_SAT2 0x4ad4 -#define VOL_mmDP0_DP_MSE_SAT2 0x4ad4 -#define VOL_mmDP1_DP_MSE_SAT2 0x4bd4 -#define VOL_mmDP2_DP_MSE_SAT2 0x4cd4 -#define VOL_mmDP3_DP_MSE_SAT2 0x4dd4 -#define VOL_mmDP4_DP_MSE_SAT2 0x4ed4 -#define VOL_mmDP5_DP_MSE_SAT2 0x4fd4 -#define VOL_mmDP6_DP_MSE_SAT2 0x54d4 -#define VOL_mmDP_MSE_SAT_UPDATE 0x4ad5 -#define VOL_mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 -#define VOL_mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 -#define VOL_mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 -#define VOL_mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 -#define VOL_mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 -#define VOL_mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 -#define VOL_mmDP6_DP_MSE_SAT_UPDATE 0x54d5 -#define VOL_mmDP_MSE_LINK_TIMING 0x4ad6 -#define VOL_mmDP0_DP_MSE_LINK_TIMING 0x4ad6 -#define VOL_mmDP1_DP_MSE_LINK_TIMING 0x4bd6 -#define VOL_mmDP2_DP_MSE_LINK_TIMING 0x4cd6 -#define VOL_mmDP3_DP_MSE_LINK_TIMING 0x4dd6 -#define VOL_mmDP4_DP_MSE_LINK_TIMING 0x4ed6 -#define VOL_mmDP5_DP_MSE_LINK_TIMING 0x4fd6 -#define VOL_mmDP6_DP_MSE_LINK_TIMING 0x54d6 -#define VOL_mmDP_MSE_MISC_CNTL 0x4ad7 -#define VOL_mmDP0_DP_MSE_MISC_CNTL 0x4ad7 -#define VOL_mmDP1_DP_MSE_MISC_CNTL 0x4bd7 -#define VOL_mmDP2_DP_MSE_MISC_CNTL 0x4cd7 -#define VOL_mmDP3_DP_MSE_MISC_CNTL 0x4dd7 -#define VOL_mmDP4_DP_MSE_MISC_CNTL 0x4ed7 -#define VOL_mmDP5_DP_MSE_MISC_CNTL 0x4fd7 -#define VOL_mmDP6_DP_MSE_MISC_CNTL 0x54d7 -#define VOL_mmDP_TEST_DEBUG_INDEX 0x4ad8 -#define VOL_mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 -#define VOL_mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 -#define VOL_mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 -#define VOL_mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 -#define VOL_mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 -#define VOL_mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 -#define VOL_mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 -#define VOL_mmDP_TEST_DEBUG_DATA 0x4ad9 -#define VOL_mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 -#define VOL_mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 -#define VOL_mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 -#define VOL_mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 -#define VOL_mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 -#define VOL_mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 -#define VOL_mmDP6_DP_TEST_DEBUG_DATA 0x54d9 -#define VOL_mmDP_FE_TEST_DEBUG_INDEX 0x4ada -#define VOL_mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada -#define VOL_mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda -#define VOL_mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda -#define VOL_mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda -#define VOL_mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda -#define VOL_mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda -#define VOL_mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da -#define VOL_mmDP_FE_TEST_DEBUG_DATA 0x4adb -#define VOL_mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb -#define VOL_mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb -#define VOL_mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb -#define VOL_mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb -#define VOL_mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb -#define VOL_mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb -#define VOL_mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db -#define VOL_mmAUX_CONTROL 0x5c00 -#define VOL_mmDP_AUX0_AUX_CONTROL 0x5c00 -#define VOL_mmDP_AUX1_AUX_CONTROL 0x5c1c -#define VOL_mmDP_AUX2_AUX_CONTROL 0x5c38 -#define VOL_mmDP_AUX3_AUX_CONTROL 0x5c54 -#define VOL_mmDP_AUX4_AUX_CONTROL 0x5c70 -#define VOL_mmDP_AUX5_AUX_CONTROL 0x5c8c -#define VOL_mmAUX_SW_CONTROL 0x5c01 -#define VOL_mmDP_AUX0_AUX_SW_CONTROL 0x5c01 -#define VOL_mmDP_AUX1_AUX_SW_CONTROL 0x5c1d -#define VOL_mmDP_AUX2_AUX_SW_CONTROL 0x5c39 -#define VOL_mmDP_AUX3_AUX_SW_CONTROL 0x5c55 -#define VOL_mmDP_AUX4_AUX_SW_CONTROL 0x5c71 -#define VOL_mmDP_AUX5_AUX_SW_CONTROL 0x5c8d -#define VOL_mmAUX_ARB_CONTROL 0x5c02 -#define VOL_mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 -#define VOL_mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e -#define VOL_mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a -#define VOL_mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 -#define VOL_mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 -#define VOL_mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e -#define VOL_mmAUX_INTERRUPT_CONTROL 0x5c03 -#define VOL_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 -#define VOL_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f -#define VOL_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b -#define VOL_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 -#define VOL_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 -#define VOL_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f -#define VOL_mmAUX_SW_STATUS 0x5c04 -#define VOL_mmDP_AUX0_AUX_SW_STATUS 0x5c04 -#define VOL_mmDP_AUX1_AUX_SW_STATUS 0x5c20 -#define VOL_mmDP_AUX2_AUX_SW_STATUS 0x5c3c -#define VOL_mmDP_AUX3_AUX_SW_STATUS 0x5c58 -#define VOL_mmDP_AUX4_AUX_SW_STATUS 0x5c74 -#define VOL_mmDP_AUX5_AUX_SW_STATUS 0x5c90 -#define VOL_mmAUX_LS_STATUS 0x5c05 -#define VOL_mmDP_AUX0_AUX_LS_STATUS 0x5c05 -#define VOL_mmDP_AUX1_AUX_LS_STATUS 0x5c21 -#define VOL_mmDP_AUX2_AUX_LS_STATUS 0x5c3d -#define VOL_mmDP_AUX3_AUX_LS_STATUS 0x5c59 -#define VOL_mmDP_AUX4_AUX_LS_STATUS 0x5c75 -#define VOL_mmDP_AUX5_AUX_LS_STATUS 0x5c91 -#define VOL_mmAUX_SW_DATA 0x5c06 -#define VOL_mmDP_AUX0_AUX_SW_DATA 0x5c06 -#define VOL_mmDP_AUX1_AUX_SW_DATA 0x5c22 -#define VOL_mmDP_AUX2_AUX_SW_DATA 0x5c3e -#define VOL_mmDP_AUX3_AUX_SW_DATA 0x5c5a -#define VOL_mmDP_AUX4_AUX_SW_DATA 0x5c76 -#define VOL_mmDP_AUX5_AUX_SW_DATA 0x5c92 -#define VOL_mmAUX_LS_DATA 0x5c07 -#define VOL_mmDP_AUX0_AUX_LS_DATA 0x5c07 -#define VOL_mmDP_AUX1_AUX_LS_DATA 0x5c23 -#define VOL_mmDP_AUX2_AUX_LS_DATA 0x5c3f -#define VOL_mmDP_AUX3_AUX_LS_DATA 0x5c5b -#define VOL_mmDP_AUX4_AUX_LS_DATA 0x5c77 -#define VOL_mmDP_AUX5_AUX_LS_DATA 0x5c93 -#define VOL_mmAUX_DPHY_TX_REF_CONTROL 0x5c08 -#define VOL_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 -#define VOL_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 -#define VOL_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 -#define VOL_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c -#define VOL_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 -#define VOL_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 -#define VOL_mmAUX_DPHY_TX_CONTROL 0x5c09 -#define VOL_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 -#define VOL_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 -#define VOL_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 -#define VOL_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d -#define VOL_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 -#define VOL_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 -#define VOL_mmAUX_DPHY_RX_CONTROL0 0x5c0a -#define VOL_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a -#define VOL_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 -#define VOL_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 -#define VOL_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e -#define VOL_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a -#define VOL_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 -#define VOL_mmAUX_DPHY_RX_CONTROL1 0x5c0b -#define VOL_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b -#define VOL_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 -#define VOL_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 -#define VOL_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f -#define VOL_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b -#define VOL_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 -#define VOL_mmAUX_DPHY_TX_STATUS 0x5c0c -#define VOL_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c -#define VOL_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 -#define VOL_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 -#define VOL_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 -#define VOL_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c -#define VOL_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 -#define VOL_mmAUX_DPHY_RX_STATUS 0x5c0d -#define VOL_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d -#define VOL_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 -#define VOL_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 -#define VOL_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 -#define VOL_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d -#define VOL_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 -#define VOL_mmAUX_GTC_SYNC_CONTROL 0x5c0e -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a -#define VOL_mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b -#define VOL_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c -#define VOL_mmAUX_GTC_SYNC_STATUS 0x5c11 -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d -#define VOL_mmAUX_GTC_SYNC_DATA 0x5c12 -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e -#define VOL_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 -#define VOL_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 -#define VOL_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f -#define VOL_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b -#define VOL_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 -#define VOL_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 -#define VOL_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f -#define VOL_mmAUX_TEST_DEBUG_INDEX 0x5c14 -#define VOL_mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 -#define VOL_mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 -#define VOL_mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c -#define VOL_mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 -#define VOL_mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 -#define VOL_mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 -#define VOL_mmAUX_TEST_DEBUG_DATA 0x5c15 -#define VOL_mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 -#define VOL_mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 -#define VOL_mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d -#define VOL_mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 -#define VOL_mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 -#define VOL_mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 -#define VOL_ixDP_AUX_DEBUG_A 0x10 -#define VOL_ixDP_AUX_DEBUG_B 0x11 -#define VOL_ixDP_AUX_DEBUG_C 0x12 -#define VOL_ixDP_AUX_DEBUG_D 0x13 -#define VOL_ixDP_AUX_DEBUG_E 0x14 -#define VOL_ixDP_AUX_DEBUG_F 0x15 -#define VOL_ixDP_AUX_DEBUG_G 0x16 -#define VOL_ixDP_AUX_DEBUG_H 0x17 -#define VOL_ixDP_AUX_DEBUG_I 0x18 -#define VOL_ixDP_AUX_DEBUG_J 0x19 -#define VOL_ixDP_AUX_DEBUG_K 0x1a -#define VOL_ixDP_AUX_DEBUG_L 0x1b -#define VOL_ixDP_AUX_DEBUG_M 0x1c -#define VOL_ixDP_AUX_DEBUG_N 0x1d -#define VOL_ixDP_AUX_DEBUG_O 0x1e -#define VOL_ixDP_AUX_DEBUG_P 0x1f -#define VOL_ixDP_AUX_DEBUG_Q 0x20 -#define VOL_mmDVO_ENABLE 0x16a0 -#define VOL_mmDVO_SOURCE_SELECT 0x16a1 -#define VOL_mmDVO_OUTPUT 0x16a2 -#define VOL_mmDVO_CONTROL 0x16a3 -#define VOL_mmDVO_CRC_EN 0x16a4 -#define VOL_mmDVO_CRC2_SIG_MASK 0x16a5 -#define VOL_mmDVO_CRC2_SIG_RESULT 0x16a6 -#define VOL_mmDVO_FIFO_ERROR_STATUS 0x16a7 -#define VOL_mmDVO_TEST_DEBUG_INDEX 0x16a8 -#define VOL_mmDVO_TEST_DEBUG_DATA 0x16a9 -#define VOL_mmFBC_CNTL 0x280 -#define VOL_mmFBC_IDLE_MASK 0x281 -#define VOL_mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 -#define VOL_mmFBC_START_STOP_DELAY 0x283 -#define VOL_mmFBC_COMP_CNTL 0x284 -#define VOL_mmFBC_COMP_MODE 0x285 -#define VOL_mmFBC_DEBUG0 0x286 -#define VOL_mmFBC_DEBUG1 0x287 -#define VOL_mmFBC_DEBUG2 0x288 -#define VOL_mmFBC_IND_LUT0 0x289 -#define VOL_mmFBC_IND_LUT1 0x28a -#define VOL_mmFBC_IND_LUT2 0x28b -#define VOL_mmFBC_IND_LUT3 0x28c -#define VOL_mmFBC_IND_LUT4 0x28d -#define VOL_mmFBC_IND_LUT5 0x28e -#define VOL_mmFBC_IND_LUT6 0x28f -#define VOL_mmFBC_IND_LUT7 0x290 -#define VOL_mmFBC_IND_LUT8 0x291 -#define VOL_mmFBC_IND_LUT9 0x292 -#define VOL_mmFBC_IND_LUT10 0x293 -#define VOL_mmFBC_IND_LUT11 0x294 -#define VOL_mmFBC_IND_LUT12 0x295 -#define VOL_mmFBC_IND_LUT13 0x296 -#define VOL_mmFBC_IND_LUT14 0x297 -#define VOL_mmFBC_IND_LUT15 0x298 -#define VOL_mmFBC_CSM_REGION_OFFSET_01 0x299 -#define VOL_mmFBC_CSM_REGION_OFFSET_23 0x29a -#define VOL_mmFBC_CLIENT_REGION_MASK 0x29b -#define VOL_mmFBC_DEBUG_COMP 0x29c -#define VOL_mmFBC_DEBUG_CSR 0x29d -#define VOL_mmFBC_DEBUG_CSR_RDATA 0x29e -#define VOL_mmFBC_DEBUG_CSR_WDATA 0x29f -#define VOL_mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 -#define VOL_mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 -#define VOL_mmFBC_MISC 0x2a2 -#define VOL_mmFBC_STATUS 0x2a3 -#define VOL_mmFBC_TEST_DEBUG_INDEX 0x2a4 -#define VOL_mmFBC_TEST_DEBUG_DATA 0x2a5 -#define VOL_mmFMT_CLAMP_COMPONENT_R 0x1be8 -#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 -#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 -#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 -#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 -#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 -#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 -#define VOL_mmFMT_CLAMP_COMPONENT_G 0x1be9 -#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 -#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 -#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 -#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 -#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 -#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 -#define VOL_mmFMT_CLAMP_COMPONENT_B 0x1bea -#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea -#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea -#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea -#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea -#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea -#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea -#define VOL_mmFMT_DYNAMIC_EXP_CNTL 0x1bed -#define VOL_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed -#define VOL_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded -#define VOL_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed -#define VOL_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed -#define VOL_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed -#define VOL_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed -#define VOL_mmFMT_CONTROL 0x1bee -#define VOL_mmFMT0_FMT_CONTROL 0x1bee -#define VOL_mmFMT1_FMT_CONTROL 0x1dee -#define VOL_mmFMT2_FMT_CONTROL 0x1fee -#define VOL_mmFMT3_FMT_CONTROL 0x41ee -#define VOL_mmFMT4_FMT_CONTROL 0x43ee -#define VOL_mmFMT5_FMT_CONTROL 0x45ee -#define VOL_mmFMT_FORCE_OUTPUT_CNTL 0x1bef -#define VOL_mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef -#define VOL_mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1def -#define VOL_mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x1fef -#define VOL_mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x41ef -#define VOL_mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x43ef -#define VOL_mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x45ef -#define VOL_mmFMT_FORCE_DATA_0_1 0x1bf0 -#define VOL_mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 -#define VOL_mmFMT1_FMT_FORCE_DATA_0_1 0x1df0 -#define VOL_mmFMT2_FMT_FORCE_DATA_0_1 0x1ff0 -#define VOL_mmFMT3_FMT_FORCE_DATA_0_1 0x41f0 -#define VOL_mmFMT4_FMT_FORCE_DATA_0_1 0x43f0 -#define VOL_mmFMT5_FMT_FORCE_DATA_0_1 0x45f0 -#define VOL_mmFMT_FORCE_DATA_2_3 0x1bf1 -#define VOL_mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 -#define VOL_mmFMT1_FMT_FORCE_DATA_2_3 0x1df1 -#define VOL_mmFMT2_FMT_FORCE_DATA_2_3 0x1ff1 -#define VOL_mmFMT3_FMT_FORCE_DATA_2_3 0x41f1 -#define VOL_mmFMT4_FMT_FORCE_DATA_2_3 0x43f1 -#define VOL_mmFMT5_FMT_FORCE_DATA_2_3 0x45f1 -#define VOL_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 -#define VOL_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 -#define VOL_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 -#define VOL_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 -#define VOL_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 -#define VOL_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 -#define VOL_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 -#define VOL_mmFMT_DITHER_RAND_R_SEED 0x1bf3 -#define VOL_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 -#define VOL_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 -#define VOL_mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 -#define VOL_mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 -#define VOL_mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 -#define VOL_mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 -#define VOL_mmFMT_DITHER_RAND_G_SEED 0x1bf4 -#define VOL_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 -#define VOL_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 -#define VOL_mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 -#define VOL_mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 -#define VOL_mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 -#define VOL_mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 -#define VOL_mmFMT_DITHER_RAND_B_SEED 0x1bf5 -#define VOL_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 -#define VOL_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 -#define VOL_mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 -#define VOL_mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 -#define VOL_mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 -#define VOL_mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 -#define VOL_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 -#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 -#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 -#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 -#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 -#define VOL_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 -#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 -#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 -#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 -#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 -#define VOL_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 -#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 -#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 -#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 -#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 -#define VOL_mmFMT_CLAMP_CNTL 0x1bf9 -#define VOL_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 -#define VOL_mmFMT1_FMT_CLAMP_CNTL 0x1df9 -#define VOL_mmFMT2_FMT_CLAMP_CNTL 0x1ff9 -#define VOL_mmFMT3_FMT_CLAMP_CNTL 0x41f9 -#define VOL_mmFMT4_FMT_CLAMP_CNTL 0x43f9 -#define VOL_mmFMT5_FMT_CLAMP_CNTL 0x45f9 -#define VOL_mmFMT_CRC_CNTL 0x1bfa -#define VOL_mmFMT0_FMT_CRC_CNTL 0x1bfa -#define VOL_mmFMT1_FMT_CRC_CNTL 0x1dfa -#define VOL_mmFMT2_FMT_CRC_CNTL 0x1ffa -#define VOL_mmFMT3_FMT_CRC_CNTL 0x41fa -#define VOL_mmFMT4_FMT_CRC_CNTL 0x43fa -#define VOL_mmFMT5_FMT_CRC_CNTL 0x45fa -#define VOL_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define VOL_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -#define VOL_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb -#define VOL_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb -#define VOL_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb -#define VOL_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb -#define VOL_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb -#define VOL_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define VOL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -#define VOL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc -#define VOL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc -#define VOL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc -#define VOL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc -#define VOL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc -#define VOL_mmFMT_CRC_SIG_RED_GREEN 0x1bfd -#define VOL_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd -#define VOL_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd -#define VOL_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd -#define VOL_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd -#define VOL_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd -#define VOL_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd -#define VOL_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define VOL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe -#define VOL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe -#define VOL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe -#define VOL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe -#define VOL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe -#define VOL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe -#define VOL_mmFMT_DEBUG_CNTL 0x1bff -#define VOL_mmFMT0_FMT_DEBUG_CNTL 0x1bff -#define VOL_mmFMT1_FMT_DEBUG_CNTL 0x1dff -#define VOL_mmFMT2_FMT_DEBUG_CNTL 0x1fff -#define VOL_mmFMT3_FMT_DEBUG_CNTL 0x41ff -#define VOL_mmFMT4_FMT_DEBUG_CNTL 0x43ff -#define VOL_mmFMT5_FMT_DEBUG_CNTL 0x45ff -#define VOL_mmFMT_TEST_DEBUG_INDEX 0x1beb -#define VOL_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb -#define VOL_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb -#define VOL_mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb -#define VOL_mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb -#define VOL_mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb -#define VOL_mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb -#define VOL_mmFMT_TEST_DEBUG_DATA 0x1bec -#define VOL_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec -#define VOL_mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec -#define VOL_mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec -#define VOL_mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec -#define VOL_mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec -#define VOL_mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec -#define VOL_ixFMT_DEBUG0 0x1 -#define VOL_ixFMT_DEBUG1 0x2 -#define VOL_ixFMT_DEBUG2 0x3 -#define VOL_ixFMT_DEBUG_ID 0x0 -#define VOL_mmLB_DATA_FORMAT 0x1ac0 -#define VOL_mmLB0_LB_DATA_FORMAT 0x1ac0 -#define VOL_mmLB1_LB_DATA_FORMAT 0x1cc0 -#define VOL_mmLB2_LB_DATA_FORMAT 0x1ec0 -#define VOL_mmLB3_LB_DATA_FORMAT 0x40c0 -#define VOL_mmLB4_LB_DATA_FORMAT 0x42c0 -#define VOL_mmLB5_LB_DATA_FORMAT 0x44c0 -#define VOL_mmLB_MEMORY_CTRL 0x1ac1 -#define VOL_mmLB0_LB_MEMORY_CTRL 0x1ac1 -#define VOL_mmLB1_LB_MEMORY_CTRL 0x1cc1 -#define VOL_mmLB2_LB_MEMORY_CTRL 0x1ec1 -#define VOL_mmLB3_LB_MEMORY_CTRL 0x40c1 -#define VOL_mmLB4_LB_MEMORY_CTRL 0x42c1 -#define VOL_mmLB5_LB_MEMORY_CTRL 0x44c1 -#define VOL_mmLB_MEMORY_SIZE_STATUS 0x1ac2 -#define VOL_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 -#define VOL_mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 -#define VOL_mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 -#define VOL_mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 -#define VOL_mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 -#define VOL_mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 -#define VOL_mmLB_DESKTOP_HEIGHT 0x1ac3 -#define VOL_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 -#define VOL_mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 -#define VOL_mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 -#define VOL_mmLB3_LB_DESKTOP_HEIGHT 0x40c3 -#define VOL_mmLB4_LB_DESKTOP_HEIGHT 0x42c3 -#define VOL_mmLB5_LB_DESKTOP_HEIGHT 0x44c3 -#define VOL_mmLB_VLINE_START_END 0x1ac4 -#define VOL_mmLB0_LB_VLINE_START_END 0x1ac4 -#define VOL_mmLB1_LB_VLINE_START_END 0x1cc4 -#define VOL_mmLB2_LB_VLINE_START_END 0x1ec4 -#define VOL_mmLB3_LB_VLINE_START_END 0x40c4 -#define VOL_mmLB4_LB_VLINE_START_END 0x42c4 -#define VOL_mmLB5_LB_VLINE_START_END 0x44c4 -#define VOL_mmLB_VLINE2_START_END 0x1ac5 -#define VOL_mmLB0_LB_VLINE2_START_END 0x1ac5 -#define VOL_mmLB1_LB_VLINE2_START_END 0x1cc5 -#define VOL_mmLB2_LB_VLINE2_START_END 0x1ec5 -#define VOL_mmLB3_LB_VLINE2_START_END 0x40c5 -#define VOL_mmLB4_LB_VLINE2_START_END 0x42c5 -#define VOL_mmLB5_LB_VLINE2_START_END 0x44c5 -#define VOL_mmLB_V_COUNTER 0x1ac6 -#define VOL_mmLB0_LB_V_COUNTER 0x1ac6 -#define VOL_mmLB1_LB_V_COUNTER 0x1cc6 -#define VOL_mmLB2_LB_V_COUNTER 0x1ec6 -#define VOL_mmLB3_LB_V_COUNTER 0x40c6 -#define VOL_mmLB4_LB_V_COUNTER 0x42c6 -#define VOL_mmLB5_LB_V_COUNTER 0x44c6 -#define VOL_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 -#define VOL_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 -#define VOL_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 -#define VOL_mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 -#define VOL_mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 -#define VOL_mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 -#define VOL_mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 -#define VOL_mmLB_INTERRUPT_MASK 0x1ac8 -#define VOL_mmLB0_LB_INTERRUPT_MASK 0x1ac8 -#define VOL_mmLB1_LB_INTERRUPT_MASK 0x1cc8 -#define VOL_mmLB2_LB_INTERRUPT_MASK 0x1ec8 -#define VOL_mmLB3_LB_INTERRUPT_MASK 0x40c8 -#define VOL_mmLB4_LB_INTERRUPT_MASK 0x42c8 -#define VOL_mmLB5_LB_INTERRUPT_MASK 0x44c8 -#define VOL_mmLB_VLINE_STATUS 0x1ac9 -#define VOL_mmLB0_LB_VLINE_STATUS 0x1ac9 -#define VOL_mmLB1_LB_VLINE_STATUS 0x1cc9 -#define VOL_mmLB2_LB_VLINE_STATUS 0x1ec9 -#define VOL_mmLB3_LB_VLINE_STATUS 0x40c9 -#define VOL_mmLB4_LB_VLINE_STATUS 0x42c9 -#define VOL_mmLB5_LB_VLINE_STATUS 0x44c9 -#define VOL_mmLB_VLINE2_STATUS 0x1aca -#define VOL_mmLB0_LB_VLINE2_STATUS 0x1aca -#define VOL_mmLB1_LB_VLINE2_STATUS 0x1cca -#define VOL_mmLB2_LB_VLINE2_STATUS 0x1eca -#define VOL_mmLB3_LB_VLINE2_STATUS 0x40ca -#define VOL_mmLB4_LB_VLINE2_STATUS 0x42ca -#define VOL_mmLB5_LB_VLINE2_STATUS 0x44ca -#define VOL_mmLB_VBLANK_STATUS 0x1acb -#define VOL_mmLB0_LB_VBLANK_STATUS 0x1acb -#define VOL_mmLB1_LB_VBLANK_STATUS 0x1ccb -#define VOL_mmLB2_LB_VBLANK_STATUS 0x1ecb -#define VOL_mmLB3_LB_VBLANK_STATUS 0x40cb -#define VOL_mmLB4_LB_VBLANK_STATUS 0x42cb -#define VOL_mmLB5_LB_VBLANK_STATUS 0x44cb -#define VOL_mmLB_SYNC_RESET_SEL 0x1acc -#define VOL_mmLB0_LB_SYNC_RESET_SEL 0x1acc -#define VOL_mmLB1_LB_SYNC_RESET_SEL 0x1ccc -#define VOL_mmLB2_LB_SYNC_RESET_SEL 0x1ecc -#define VOL_mmLB3_LB_SYNC_RESET_SEL 0x40cc -#define VOL_mmLB4_LB_SYNC_RESET_SEL 0x42cc -#define VOL_mmLB5_LB_SYNC_RESET_SEL 0x44cc -#define VOL_mmLB_BLACK_KEYER_R_CR 0x1acd -#define VOL_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd -#define VOL_mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd -#define VOL_mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd -#define VOL_mmLB3_LB_BLACK_KEYER_R_CR 0x40cd -#define VOL_mmLB4_LB_BLACK_KEYER_R_CR 0x42cd -#define VOL_mmLB5_LB_BLACK_KEYER_R_CR 0x44cd -#define VOL_mmLB_BLACK_KEYER_G_Y 0x1ace -#define VOL_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace -#define VOL_mmLB1_LB_BLACK_KEYER_G_Y 0x1cce -#define VOL_mmLB2_LB_BLACK_KEYER_G_Y 0x1ece -#define VOL_mmLB3_LB_BLACK_KEYER_G_Y 0x40ce -#define VOL_mmLB4_LB_BLACK_KEYER_G_Y 0x42ce -#define VOL_mmLB5_LB_BLACK_KEYER_G_Y 0x44ce -#define VOL_mmLB_BLACK_KEYER_B_CB 0x1acf -#define VOL_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf -#define VOL_mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf -#define VOL_mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf -#define VOL_mmLB3_LB_BLACK_KEYER_B_CB 0x40cf -#define VOL_mmLB4_LB_BLACK_KEYER_B_CB 0x42cf -#define VOL_mmLB5_LB_BLACK_KEYER_B_CB 0x44cf -#define VOL_mmLB_KEYER_COLOR_CTRL 0x1ad0 -#define VOL_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 -#define VOL_mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 -#define VOL_mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 -#define VOL_mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 -#define VOL_mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 -#define VOL_mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 -#define VOL_mmLB_KEYER_COLOR_R_CR 0x1ad1 -#define VOL_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 -#define VOL_mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 -#define VOL_mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 -#define VOL_mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 -#define VOL_mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 -#define VOL_mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 -#define VOL_mmLB_KEYER_COLOR_G_Y 0x1ad2 -#define VOL_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 -#define VOL_mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 -#define VOL_mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 -#define VOL_mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 -#define VOL_mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 -#define VOL_mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 -#define VOL_mmLB_KEYER_COLOR_B_CB 0x1ad3 -#define VOL_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 -#define VOL_mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 -#define VOL_mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 -#define VOL_mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 -#define VOL_mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 -#define VOL_mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 -#define VOL_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define VOL_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 -#define VOL_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 -#define VOL_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 -#define VOL_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 -#define VOL_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 -#define VOL_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 -#define VOL_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define VOL_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 -#define VOL_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 -#define VOL_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 -#define VOL_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 -#define VOL_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 -#define VOL_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 -#define VOL_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define VOL_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 -#define VOL_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 -#define VOL_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 -#define VOL_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 -#define VOL_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 -#define VOL_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 -#define VOL_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 -#define VOL_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 -#define VOL_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 -#define VOL_mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 -#define VOL_mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 -#define VOL_mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 -#define VOL_mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 -#define VOL_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 -#define VOL_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 -#define VOL_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 -#define VOL_mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 -#define VOL_mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 -#define VOL_mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 -#define VOL_mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 -#define VOL_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 -#define VOL_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 -#define VOL_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 -#define VOL_mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 -#define VOL_mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 -#define VOL_mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 -#define VOL_mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 -#define VOL_mmLB_BUFFER_STATUS 0x1ada -#define VOL_mmLB0_LB_BUFFER_STATUS 0x1ada -#define VOL_mmLB1_LB_BUFFER_STATUS 0x1cda -#define VOL_mmLB2_LB_BUFFER_STATUS 0x1eda -#define VOL_mmLB3_LB_BUFFER_STATUS 0x40da -#define VOL_mmLB4_LB_BUFFER_STATUS 0x42da -#define VOL_mmLB5_LB_BUFFER_STATUS 0x44da -#define VOL_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define VOL_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc -#define VOL_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc -#define VOL_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc -#define VOL_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc -#define VOL_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc -#define VOL_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc -#define VOL_mmMVP_AFR_FLIP_MODE 0x1ae0 -#define VOL_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 -#define VOL_mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 -#define VOL_mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 -#define VOL_mmLB3_MVP_AFR_FLIP_MODE 0x40e0 -#define VOL_mmLB4_MVP_AFR_FLIP_MODE 0x42e0 -#define VOL_mmLB5_MVP_AFR_FLIP_MODE 0x44e0 -#define VOL_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define VOL_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -#define VOL_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 -#define VOL_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 -#define VOL_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 -#define VOL_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 -#define VOL_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 -#define VOL_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define VOL_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 -#define VOL_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 -#define VOL_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 -#define VOL_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 -#define VOL_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 -#define VOL_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 -#define VOL_mmDC_MVP_LB_CONTROL 0x1ae3 -#define VOL_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 -#define VOL_mmLB1_DC_MVP_LB_CONTROL 0x1ce3 -#define VOL_mmLB2_DC_MVP_LB_CONTROL 0x1ee3 -#define VOL_mmLB3_DC_MVP_LB_CONTROL 0x40e3 -#define VOL_mmLB4_DC_MVP_LB_CONTROL 0x42e3 -#define VOL_mmLB5_DC_MVP_LB_CONTROL 0x44e3 -#define VOL_mmLB_DEBUG 0x1ae4 -#define VOL_mmLB0_LB_DEBUG 0x1ae4 -#define VOL_mmLB1_LB_DEBUG 0x1ce4 -#define VOL_mmLB2_LB_DEBUG 0x1ee4 -#define VOL_mmLB3_LB_DEBUG 0x40e4 -#define VOL_mmLB4_LB_DEBUG 0x42e4 -#define VOL_mmLB5_LB_DEBUG 0x44e4 -#define VOL_mmLB_DEBUG2 0x1ae5 -#define VOL_mmLB0_LB_DEBUG2 0x1ae5 -#define VOL_mmLB1_LB_DEBUG2 0x1ce5 -#define VOL_mmLB2_LB_DEBUG2 0x1ee5 -#define VOL_mmLB3_LB_DEBUG2 0x40e5 -#define VOL_mmLB4_LB_DEBUG2 0x42e5 -#define VOL_mmLB5_LB_DEBUG2 0x44e5 -#define VOL_mmLB_DEBUG3 0x1ae6 -#define VOL_mmLB0_LB_DEBUG3 0x1ae6 -#define VOL_mmLB1_LB_DEBUG3 0x1ce6 -#define VOL_mmLB2_LB_DEBUG3 0x1ee6 -#define VOL_mmLB3_LB_DEBUG3 0x40e6 -#define VOL_mmLB4_LB_DEBUG3 0x42e6 -#define VOL_mmLB5_LB_DEBUG3 0x44e6 -#define VOL_mmLB_TEST_DEBUG_INDEX 0x1afe -#define VOL_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe -#define VOL_mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe -#define VOL_mmLB2_LB_TEST_DEBUG_INDEX 0x1efe -#define VOL_mmLB3_LB_TEST_DEBUG_INDEX 0x40fe -#define VOL_mmLB4_LB_TEST_DEBUG_INDEX 0x42fe -#define VOL_mmLB5_LB_TEST_DEBUG_INDEX 0x44fe -#define VOL_mmLB_TEST_DEBUG_DATA 0x1aff -#define VOL_mmLB0_LB_TEST_DEBUG_DATA 0x1aff -#define VOL_mmLB1_LB_TEST_DEBUG_DATA 0x1cff -#define VOL_mmLB2_LB_TEST_DEBUG_DATA 0x1eff -#define VOL_mmLB3_LB_TEST_DEBUG_DATA 0x40ff -#define VOL_mmLB4_LB_TEST_DEBUG_DATA 0x42ff -#define VOL_mmLB5_LB_TEST_DEBUG_DATA 0x44ff -#define VOL_mmLBV_DATA_FORMAT 0x463c -#define VOL_mmLBV_MEMORY_CTRL 0x463d -#define VOL_mmLBV_MEMORY_SIZE_STATUS 0x463e -#define VOL_mmLBV_DESKTOP_HEIGHT 0x463f -#define VOL_mmLBV_VLINE_START_END 0x4640 -#define VOL_mmLBV_VLINE2_START_END 0x4641 -#define VOL_mmLBV_V_COUNTER 0x4642 -#define VOL_mmLBV_SNAPSHOT_V_COUNTER 0x4643 -#define VOL_mmLBV_V_COUNTER_CHROMA 0x4644 -#define VOL_mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 -#define VOL_mmLBV_INTERRUPT_MASK 0x4646 -#define VOL_mmLBV_VLINE_STATUS 0x4647 -#define VOL_mmLBV_VLINE2_STATUS 0x4648 -#define VOL_mmLBV_VBLANK_STATUS 0x4649 -#define VOL_mmLBV_SYNC_RESET_SEL 0x464a -#define VOL_mmLBV_BLACK_KEYER_R_CR 0x464b -#define VOL_mmLBV_BLACK_KEYER_G_Y 0x464c -#define VOL_mmLBV_BLACK_KEYER_B_CB 0x464d -#define VOL_mmLBV_KEYER_COLOR_CTRL 0x464e -#define VOL_mmLBV_KEYER_COLOR_R_CR 0x464f -#define VOL_mmLBV_KEYER_COLOR_G_Y 0x4650 -#define VOL_mmLBV_KEYER_COLOR_B_CB 0x4651 -#define VOL_mmLBV_KEYER_COLOR_REP_R_CR 0x4652 -#define VOL_mmLBV_KEYER_COLOR_REP_G_Y 0x4653 -#define VOL_mmLBV_KEYER_COLOR_REP_B_CB 0x4654 -#define VOL_mmLBV_BUFFER_LEVEL_STATUS 0x4655 -#define VOL_mmLBV_BUFFER_URGENCY_CTRL 0x4656 -#define VOL_mmLBV_BUFFER_URGENCY_STATUS 0x4657 -#define VOL_mmLBV_BUFFER_STATUS 0x4658 -#define VOL_mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 -#define VOL_mmLBV_DEBUG 0x465a -#define VOL_mmLBV_DEBUG2 0x465b -#define VOL_mmLBV_DEBUG3 0x465c -#define VOL_mmLBV_TEST_DEBUG_INDEX 0x4666 -#define VOL_mmLBV_TEST_DEBUG_DATA 0x4667 -#define VOL_mmMVP_CONTROL1 0x2ac -#define VOL_mmMVP_CONTROL2 0x2ad -#define VOL_mmMVP_FIFO_CONTROL 0x2ae -#define VOL_mmMVP_FIFO_STATUS 0x2af -#define VOL_mmMVP_SLAVE_STATUS 0x2b0 -#define VOL_mmMVP_INBAND_CNTL_CAP 0x2b1 -#define VOL_mmMVP_BLACK_KEYER 0x2b2 -#define VOL_mmMVP_CRC_CNTL 0x2b3 -#define VOL_mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 -#define VOL_mmMVP_CRC_RESULT_RED 0x2b5 -#define VOL_mmMVP_CONTROL3 0x2b6 -#define VOL_mmMVP_RECEIVE_CNT_CNTL1 0x2b7 -#define VOL_mmMVP_RECEIVE_CNT_CNTL2 0x2b8 -#define VOL_mmMVP_DEBUG 0x2bb -#define VOL_mmMVP_TEST_DEBUG_INDEX 0x2b9 -#define VOL_mmMVP_TEST_DEBUG_DATA 0x2ba -#define VOL_ixMVP_DEBUG_12 0xc -#define VOL_ixMVP_DEBUG_13 0xd -#define VOL_ixMVP_DEBUG_14 0xe -#define VOL_ixMVP_DEBUG_15 0xf -#define VOL_ixMVP_DEBUG_16 0x10 -#define VOL_ixMVP_DEBUG_17 0x11 -#define VOL_mmSCL_COEF_RAM_SELECT 0x1b40 -#define VOL_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 -#define VOL_mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 -#define VOL_mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 -#define VOL_mmSCL3_SCL_COEF_RAM_SELECT 0x4140 -#define VOL_mmSCL4_SCL_COEF_RAM_SELECT 0x4340 -#define VOL_mmSCL5_SCL_COEF_RAM_SELECT 0x4540 -#define VOL_mmSCL_COEF_RAM_TAP_DATA 0x1b41 -#define VOL_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 -#define VOL_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 -#define VOL_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 -#define VOL_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 -#define VOL_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 -#define VOL_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 -#define VOL_mmSCL_MODE 0x1b42 -#define VOL_mmSCL0_SCL_MODE 0x1b42 -#define VOL_mmSCL1_SCL_MODE 0x1d42 -#define VOL_mmSCL2_SCL_MODE 0x1f42 -#define VOL_mmSCL3_SCL_MODE 0x4142 -#define VOL_mmSCL4_SCL_MODE 0x4342 -#define VOL_mmSCL5_SCL_MODE 0x4542 -#define VOL_mmSCL_TAP_CONTROL 0x1b43 -#define VOL_mmSCL0_SCL_TAP_CONTROL 0x1b43 -#define VOL_mmSCL1_SCL_TAP_CONTROL 0x1d43 -#define VOL_mmSCL2_SCL_TAP_CONTROL 0x1f43 -#define VOL_mmSCL3_SCL_TAP_CONTROL 0x4143 -#define VOL_mmSCL4_SCL_TAP_CONTROL 0x4343 -#define VOL_mmSCL5_SCL_TAP_CONTROL 0x4543 -#define VOL_mmSCL_CONTROL 0x1b44 -#define VOL_mmSCL0_SCL_CONTROL 0x1b44 -#define VOL_mmSCL1_SCL_CONTROL 0x1d44 -#define VOL_mmSCL2_SCL_CONTROL 0x1f44 -#define VOL_mmSCL3_SCL_CONTROL 0x4144 -#define VOL_mmSCL4_SCL_CONTROL 0x4344 -#define VOL_mmSCL5_SCL_CONTROL 0x4544 -#define VOL_mmSCL_BYPASS_CONTROL 0x1b45 -#define VOL_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 -#define VOL_mmSCL1_SCL_BYPASS_CONTROL 0x1d45 -#define VOL_mmSCL2_SCL_BYPASS_CONTROL 0x1f45 -#define VOL_mmSCL3_SCL_BYPASS_CONTROL 0x4145 -#define VOL_mmSCL4_SCL_BYPASS_CONTROL 0x4345 -#define VOL_mmSCL5_SCL_BYPASS_CONTROL 0x4545 -#define VOL_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define VOL_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 -#define VOL_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 -#define VOL_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 -#define VOL_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 -#define VOL_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 -#define VOL_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 -#define VOL_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define VOL_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 -#define VOL_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 -#define VOL_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 -#define VOL_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 -#define VOL_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 -#define VOL_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 -#define VOL_mmSCL_HORZ_FILTER_CONTROL 0x1b48 -#define VOL_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 -#define VOL_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 -#define VOL_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 -#define VOL_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 -#define VOL_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 -#define VOL_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 -#define VOL_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define VOL_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -#define VOL_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 -#define VOL_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 -#define VOL_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 -#define VOL_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 -#define VOL_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 -#define VOL_mmSCL_HORZ_FILTER_INIT 0x1b4a -#define VOL_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a -#define VOL_mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a -#define VOL_mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a -#define VOL_mmSCL3_SCL_HORZ_FILTER_INIT 0x414a -#define VOL_mmSCL4_SCL_HORZ_FILTER_INIT 0x434a -#define VOL_mmSCL5_SCL_HORZ_FILTER_INIT 0x454a -#define VOL_mmSCL_VERT_FILTER_CONTROL 0x1b4b -#define VOL_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b -#define VOL_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b -#define VOL_mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b -#define VOL_mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b -#define VOL_mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b -#define VOL_mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b -#define VOL_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define VOL_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c -#define VOL_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c -#define VOL_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c -#define VOL_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c -#define VOL_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c -#define VOL_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c -#define VOL_mmSCL_VERT_FILTER_INIT 0x1b4d -#define VOL_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d -#define VOL_mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d -#define VOL_mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d -#define VOL_mmSCL3_SCL_VERT_FILTER_INIT 0x414d -#define VOL_mmSCL4_SCL_VERT_FILTER_INIT 0x434d -#define VOL_mmSCL5_SCL_VERT_FILTER_INIT 0x454d -#define VOL_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e -#define VOL_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e -#define VOL_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e -#define VOL_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e -#define VOL_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e -#define VOL_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e -#define VOL_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e -#define VOL_mmSCL_ROUND_OFFSET 0x1b4f -#define VOL_mmSCL0_SCL_ROUND_OFFSET 0x1b4f -#define VOL_mmSCL1_SCL_ROUND_OFFSET 0x1d4f -#define VOL_mmSCL2_SCL_ROUND_OFFSET 0x1f4f -#define VOL_mmSCL3_SCL_ROUND_OFFSET 0x414f -#define VOL_mmSCL4_SCL_ROUND_OFFSET 0x434f -#define VOL_mmSCL5_SCL_ROUND_OFFSET 0x454f -#define VOL_mmSCL_UPDATE 0x1b51 -#define VOL_mmSCL0_SCL_UPDATE 0x1b51 -#define VOL_mmSCL1_SCL_UPDATE 0x1d51 -#define VOL_mmSCL2_SCL_UPDATE 0x1f51 -#define VOL_mmSCL3_SCL_UPDATE 0x4151 -#define VOL_mmSCL4_SCL_UPDATE 0x4351 -#define VOL_mmSCL5_SCL_UPDATE 0x4551 -#define VOL_mmSCL_F_SHARP_CONTROL 0x1b53 -#define VOL_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 -#define VOL_mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 -#define VOL_mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 -#define VOL_mmSCL3_SCL_F_SHARP_CONTROL 0x4153 -#define VOL_mmSCL4_SCL_F_SHARP_CONTROL 0x4353 -#define VOL_mmSCL5_SCL_F_SHARP_CONTROL 0x4553 -#define VOL_mmSCL_ALU_CONTROL 0x1b54 -#define VOL_mmSCL0_SCL_ALU_CONTROL 0x1b54 -#define VOL_mmSCL1_SCL_ALU_CONTROL 0x1d54 -#define VOL_mmSCL2_SCL_ALU_CONTROL 0x1f54 -#define VOL_mmSCL3_SCL_ALU_CONTROL 0x4154 -#define VOL_mmSCL4_SCL_ALU_CONTROL 0x4354 -#define VOL_mmSCL5_SCL_ALU_CONTROL 0x4554 -#define VOL_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define VOL_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -#define VOL_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 -#define VOL_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 -#define VOL_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 -#define VOL_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 -#define VOL_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 -#define VOL_mmVIEWPORT_START_SECONDARY 0x1b5b -#define VOL_mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b -#define VOL_mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b -#define VOL_mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b -#define VOL_mmSCL3_VIEWPORT_START_SECONDARY 0x415b -#define VOL_mmSCL4_VIEWPORT_START_SECONDARY 0x435b -#define VOL_mmSCL5_VIEWPORT_START_SECONDARY 0x455b -#define VOL_mmVIEWPORT_START 0x1b5c -#define VOL_mmSCL0_VIEWPORT_START 0x1b5c -#define VOL_mmSCL1_VIEWPORT_START 0x1d5c -#define VOL_mmSCL2_VIEWPORT_START 0x1f5c -#define VOL_mmSCL3_VIEWPORT_START 0x415c -#define VOL_mmSCL4_VIEWPORT_START 0x435c -#define VOL_mmSCL5_VIEWPORT_START 0x455c -#define VOL_mmVIEWPORT_SIZE 0x1b5d -#define VOL_mmSCL0_VIEWPORT_SIZE 0x1b5d -#define VOL_mmSCL1_VIEWPORT_SIZE 0x1d5d -#define VOL_mmSCL2_VIEWPORT_SIZE 0x1f5d -#define VOL_mmSCL3_VIEWPORT_SIZE 0x415d -#define VOL_mmSCL4_VIEWPORT_SIZE 0x435d -#define VOL_mmSCL5_VIEWPORT_SIZE 0x455d -#define VOL_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define VOL_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e -#define VOL_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e -#define VOL_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e -#define VOL_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e -#define VOL_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e -#define VOL_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e -#define VOL_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define VOL_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f -#define VOL_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f -#define VOL_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f -#define VOL_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f -#define VOL_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f -#define VOL_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f -#define VOL_mmSCL_MODE_CHANGE_DET1 0x1b60 -#define VOL_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 -#define VOL_mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 -#define VOL_mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 -#define VOL_mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 -#define VOL_mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 -#define VOL_mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 -#define VOL_mmSCL_MODE_CHANGE_DET2 0x1b61 -#define VOL_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 -#define VOL_mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 -#define VOL_mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 -#define VOL_mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 -#define VOL_mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 -#define VOL_mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 -#define VOL_mmSCL_MODE_CHANGE_DET3 0x1b62 -#define VOL_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 -#define VOL_mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 -#define VOL_mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 -#define VOL_mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 -#define VOL_mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 -#define VOL_mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 -#define VOL_mmSCL_MODE_CHANGE_MASK 0x1b63 -#define VOL_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 -#define VOL_mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 -#define VOL_mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 -#define VOL_mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 -#define VOL_mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 -#define VOL_mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 -#define VOL_mmSCL_DEBUG2 0x1b69 -#define VOL_mmSCL0_SCL_DEBUG2 0x1b69 -#define VOL_mmSCL1_SCL_DEBUG2 0x1d69 -#define VOL_mmSCL2_SCL_DEBUG2 0x1f69 -#define VOL_mmSCL3_SCL_DEBUG2 0x4169 -#define VOL_mmSCL4_SCL_DEBUG2 0x4369 -#define VOL_mmSCL5_SCL_DEBUG2 0x4569 -#define VOL_mmSCL_DEBUG 0x1b6a -#define VOL_mmSCL0_SCL_DEBUG 0x1b6a -#define VOL_mmSCL1_SCL_DEBUG 0x1d6a -#define VOL_mmSCL2_SCL_DEBUG 0x1f6a -#define VOL_mmSCL3_SCL_DEBUG 0x416a -#define VOL_mmSCL4_SCL_DEBUG 0x436a -#define VOL_mmSCL5_SCL_DEBUG 0x456a -#define VOL_mmSCL_TEST_DEBUG_INDEX 0x1b6b -#define VOL_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b -#define VOL_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b -#define VOL_mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b -#define VOL_mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b -#define VOL_mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b -#define VOL_mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b -#define VOL_mmSCL_TEST_DEBUG_DATA 0x1b6c -#define VOL_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c -#define VOL_mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c -#define VOL_mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c -#define VOL_mmSCL3_SCL_TEST_DEBUG_DATA 0x416c -#define VOL_mmSCL4_SCL_TEST_DEBUG_DATA 0x436c -#define VOL_mmSCL5_SCL_TEST_DEBUG_DATA 0x456c -#define VOL_mmSCLV_COEF_RAM_SELECT 0x4670 -#define VOL_mmSCLV_COEF_RAM_TAP_DATA 0x4671 -#define VOL_mmSCLV_MODE 0x4672 -#define VOL_mmSCLV_TAP_CONTROL 0x4673 -#define VOL_mmSCLV_CONTROL 0x4674 -#define VOL_mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 -#define VOL_mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 -#define VOL_mmSCLV_HORZ_FILTER_CONTROL 0x4677 -#define VOL_mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 -#define VOL_mmSCLV_HORZ_FILTER_INIT 0x4679 -#define VOL_mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a -#define VOL_mmSCLV_HORZ_FILTER_INIT_C 0x467b -#define VOL_mmSCLV_VERT_FILTER_CONTROL 0x467c -#define VOL_mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d -#define VOL_mmSCLV_VERT_FILTER_INIT 0x467e -#define VOL_mmSCLV_VERT_FILTER_INIT_BOT 0x467f -#define VOL_mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 -#define VOL_mmSCLV_VERT_FILTER_INIT_C 0x4681 -#define VOL_mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 -#define VOL_mmSCLV_ROUND_OFFSET 0x4683 -#define VOL_mmSCLV_UPDATE 0x4684 -#define VOL_mmSCLV_ALU_CONTROL 0x4685 -#define VOL_mmSCLV_VIEWPORT_START 0x4686 -#define VOL_mmSCLV_VIEWPORT_START_SECONDARY 0x4687 -#define VOL_mmSCLV_VIEWPORT_SIZE 0x4688 -#define VOL_mmSCLV_VIEWPORT_START_C 0x4689 -#define VOL_mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a -#define VOL_mmSCLV_VIEWPORT_SIZE_C 0x468b -#define VOL_mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c -#define VOL_mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d -#define VOL_mmSCLV_MODE_CHANGE_DET1 0x468e -#define VOL_mmSCLV_MODE_CHANGE_DET2 0x468f -#define VOL_mmSCLV_MODE_CHANGE_DET3 0x4690 -#define VOL_mmSCLV_MODE_CHANGE_MASK 0x4691 -#define VOL_mmSCLV_DEBUG2 0x4692 -#define VOL_mmSCLV_DEBUG 0x4693 -#define VOL_mmSCLV_TEST_DEBUG_INDEX 0x4694 -#define VOL_mmSCLV_TEST_DEBUG_DATA 0x4695 -#define VOL_mmCOL_MAN_UPDATE 0x46a4 -#define VOL_mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 -#define VOL_mmINPUT_CSC_C11_C12_A 0x46a6 -#define VOL_mmINPUT_CSC_C13_C14_A 0x46a7 -#define VOL_mmINPUT_CSC_C21_C22_A 0x46a8 -#define VOL_mmINPUT_CSC_C23_C24_A 0x46a9 -#define VOL_mmINPUT_CSC_C31_C32_A 0x46aa -#define VOL_mmINPUT_CSC_C33_C34_A 0x46ab -#define VOL_mmINPUT_CSC_C11_C12_B 0x46ac -#define VOL_mmINPUT_CSC_C13_C14_B 0x46ad -#define VOL_mmINPUT_CSC_C21_C22_B 0x46ae -#define VOL_mmINPUT_CSC_C23_C24_B 0x46af -#define VOL_mmINPUT_CSC_C31_C32_B 0x46b0 -#define VOL_mmINPUT_CSC_C33_C34_B 0x46b1 -#define VOL_mmPRESCALE_CONTROL 0x46b2 -#define VOL_mmPRESCALE_VALUES_R 0x46b3 -#define VOL_mmPRESCALE_VALUES_G 0x46b4 -#define VOL_mmPRESCALE_VALUES_B 0x46b5 -#define VOL_mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 -#define VOL_mmOUTPUT_CSC_C11_C12_A 0x46b7 -#define VOL_mmOUTPUT_CSC_C13_C14_A 0x46b8 -#define VOL_mmOUTPUT_CSC_C21_C22_A 0x46b9 -#define VOL_mmOUTPUT_CSC_C23_C24_A 0x46ba -#define VOL_mmOUTPUT_CSC_C31_C32_A 0x46bb -#define VOL_mmOUTPUT_CSC_C33_C34_A 0x46bc -#define VOL_mmOUTPUT_CSC_C11_C12_B 0x46bd -#define VOL_mmOUTPUT_CSC_C13_C14_B 0x46be -#define VOL_mmOUTPUT_CSC_C21_C22_B 0x46bf -#define VOL_mmOUTPUT_CSC_C23_C24_B 0x46c0 -#define VOL_mmOUTPUT_CSC_C31_C32_B 0x46c1 -#define VOL_mmOUTPUT_CSC_C33_C34_B 0x46c2 -#define VOL_mmDENORM_CLAMP_CONTROL 0x46c3 -#define VOL_mmDENORM_CLAMP_RANGE_R_CR 0x46c4 -#define VOL_mmDENORM_CLAMP_RANGE_G_Y 0x46c5 -#define VOL_mmDENORM_CLAMP_RANGE_B_CB 0x46c6 -#define VOL_mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 -#define VOL_mmGAMMA_CORR_CONTROL 0x46c8 -#define VOL_mmGAMMA_CORR_LUT_INDEX 0x46c9 -#define VOL_mmGAMMA_CORR_LUT_DATA 0x46ca -#define VOL_mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb -#define VOL_mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc -#define VOL_mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd -#define VOL_mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce -#define VOL_mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf -#define VOL_mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 -#define VOL_mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 -#define VOL_mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 -#define VOL_mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 -#define VOL_mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da -#define VOL_mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db -#define VOL_mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc -#define VOL_mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd -#define VOL_mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de -#define VOL_mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df -#define VOL_mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 -#define VOL_mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 -#define VOL_mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 -#define VOL_mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 -#define VOL_mmCOL_MAN_TEST_DEBUG_INDEX 0x46e4 -#define VOL_mmCOL_MAN_TEST_DEBUG_DATA 0x46e5 -#define VOL_mmCOL_MAN_DEBUG_CONTROL 0x46e6 -#define VOL_mmUNP_GRPH_ENABLE 0x4600 -#define VOL_mmUNP_GRPH_CONTROL 0x4601 -#define VOL_mmUNP_GRPH_CONTROL_EXP 0x4603 -#define VOL_mmUNP_GRPH_SWAP_CNTL 0x4605 -#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 -#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 -#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 -#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 -#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a -#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b -#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c -#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d -#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e -#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f -#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 -#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 -#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 -#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 -#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 -#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 -#define VOL_mmUNP_GRPH_PITCH_L 0x4616 -#define VOL_mmUNP_GRPH_PITCH_C 0x4617 -#define VOL_mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 -#define VOL_mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 -#define VOL_mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a -#define VOL_mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b -#define VOL_mmUNP_GRPH_X_START_L 0x461c -#define VOL_mmUNP_GRPH_X_START_C 0x461d -#define VOL_mmUNP_GRPH_Y_START_L 0x461e -#define VOL_mmUNP_GRPH_Y_START_C 0x461f -#define VOL_mmUNP_GRPH_X_END_L 0x4620 -#define VOL_mmUNP_GRPH_X_END_C 0x4621 -#define VOL_mmUNP_GRPH_Y_END_L 0x4622 -#define VOL_mmUNP_GRPH_Y_END_C 0x4623 -#define VOL_mmUNP_GRPH_UPDATE 0x4624 -#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 -#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 -#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 -#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 -#define VOL_mmUNP_GRPH_DFQ_CONTROL 0x4629 -#define VOL_mmUNP_GRPH_DFQ_STATUS 0x462a -#define VOL_mmUNP_GRPH_INTERRUPT_STATUS 0x462b -#define VOL_mmUNP_GRPH_INTERRUPT_CONTROL 0x462c -#define VOL_mmUNP_GRPH_STEREOSYNC_FLIP 0x462e -#define VOL_mmUNP_GRPH_FLIP_RATE_CNTL 0x462f -#define VOL_mmUNP_CRC_CONTROL 0x4630 -#define VOL_mmUNP_CRC_MASK 0x4631 -#define VOL_mmUNP_CRC_CURRENT 0x4632 -#define VOL_mmUNP_CRC_LAST 0x4633 -#define VOL_mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 -#define VOL_mmUNP_HW_ROTATION 0x4635 -#define VOL_mmUNP_DEBUG 0x4636 -#define VOL_mmUNP_DEBUG2 0x4637 -#define VOL_mmUNP_TEST_DEBUG_INDEX 0x4638 -#define VOL_mmUNP_TEST_DEBUG_DATA 0x4639 -#define VOL_mmGENMO_WT 0xf0 -#define VOL_mmGENMO_RD 0xf3 -#define VOL_mmGENENB 0xf0 -#define VOL_mmGENFC_WT 0xee -#define VOL_mmVGA0_GENFC_WT 0xee -#define VOL_mmVGA1_GENFC_WT 0xf6 -#define VOL_mmGENFC_RD 0xf2 -#define VOL_mmGENS0 0xf0 -#define VOL_mmGENS1 0xee -#define VOL_mmVGA0_GENS1 0xee -#define VOL_mmVGA1_GENS1 0xf6 -#define VOL_mmDAC_DATA 0xf2 -#define VOL_mmDAC_MASK 0xf1 -#define VOL_mmDAC_R_INDEX 0xf1 -#define VOL_mmDAC_W_INDEX 0xf2 -#define VOL_mmSEQ8_IDX 0xf1 -#define VOL_mmSEQ8_DATA 0xf1 -#define VOL_ixSEQ00 0x0 -#define VOL_ixSEQ01 0x1 -#define VOL_ixSEQ02 0x2 -#define VOL_ixSEQ03 0x3 -#define VOL_ixSEQ04 0x4 -#define VOL_mmCRTC8_IDX 0xed -#define VOL_mmVGA0_CRTC8_IDX 0xed -#define VOL_mmVGA1_CRTC8_IDX 0xf5 -#define VOL_mmCRTC8_DATA 0xed -#define VOL_mmVGA0_CRTC8_DATA 0xed -#define VOL_mmVGA1_CRTC8_DATA 0xf5 -#define VOL_ixCRT00 0x0 -#define VOL_ixCRT01 0x1 -#define VOL_ixCRT02 0x2 -#define VOL_ixCRT03 0x3 -#define VOL_ixCRT04 0x4 -#define VOL_ixCRT05 0x5 -#define VOL_ixCRT06 0x6 -#define VOL_ixCRT07 0x7 -#define VOL_ixCRT08 0x8 -#define VOL_ixCRT09 0x9 -#define VOL_ixCRT0A 0xa -#define VOL_ixCRT0B 0xb -#define VOL_ixCRT0C 0xc -#define VOL_ixCRT0D 0xd -#define VOL_ixCRT0E 0xe -#define VOL_ixCRT0F 0xf -#define VOL_ixCRT10 0x10 -#define VOL_ixCRT11 0x11 -#define VOL_ixCRT12 0x12 -#define VOL_ixCRT13 0x13 -#define VOL_ixCRT14 0x14 -#define VOL_ixCRT15 0x15 -#define VOL_ixCRT16 0x16 -#define VOL_ixCRT17 0x17 -#define VOL_ixCRT18 0x18 -#define VOL_ixCRT1E 0x1e -#define VOL_ixCRT1F 0x1f -#define VOL_ixCRT22 0x22 -#define VOL_mmGRPH8_IDX 0xf3 -#define VOL_mmGRPH8_DATA 0xf3 -#define VOL_ixGRA00 0x0 -#define VOL_ixGRA01 0x1 -#define VOL_ixGRA02 0x2 -#define VOL_ixGRA03 0x3 -#define VOL_ixGRA04 0x4 -#define VOL_ixGRA05 0x5 -#define VOL_ixGRA06 0x6 -#define VOL_ixGRA07 0x7 -#define VOL_ixGRA08 0x8 -#define VOL_mmATTRX 0xf0 -#define VOL_mmATTRDW 0xf0 -#define VOL_mmATTRDR 0xf0 -#define VOL_ixATTR00 0x0 -#define VOL_ixATTR01 0x1 -#define VOL_ixATTR02 0x2 -#define VOL_ixATTR03 0x3 -#define VOL_ixATTR04 0x4 -#define VOL_ixATTR05 0x5 -#define VOL_ixATTR06 0x6 -#define VOL_ixATTR07 0x7 -#define VOL_ixATTR08 0x8 -#define VOL_ixATTR09 0x9 -#define VOL_ixATTR0A 0xa -#define VOL_ixATTR0B 0xb -#define VOL_ixATTR0C 0xc -#define VOL_ixATTR0D 0xd -#define VOL_ixATTR0E 0xe -#define VOL_ixATTR0F 0xf -#define VOL_ixATTR10 0x10 -#define VOL_ixATTR11 0x11 -#define VOL_ixATTR12 0x12 -#define VOL_ixATTR13 0x13 -#define VOL_ixATTR14 0x14 -#define VOL_mmVGA_RENDER_CONTROL 0xc0 -#define VOL_mmVGA_SOURCE_SELECT 0xfc -#define VOL_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 -#define VOL_mmVGA_MODE_CONTROL 0xc2 -#define VOL_mmVGA_SURFACE_PITCH_SELECT 0xc3 -#define VOL_mmVGA_MEMORY_BASE_ADDRESS 0xc4 -#define VOL_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 -#define VOL_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 -#define VOL_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 -#define VOL_mmVGA_HDP_CONTROL 0xca -#define VOL_mmVGA_CACHE_CONTROL 0xcb -#define VOL_mmD1VGA_CONTROL 0xcc -#define VOL_mmD2VGA_CONTROL 0xce -#define VOL_mmD3VGA_CONTROL 0xf8 -#define VOL_mmD4VGA_CONTROL 0xf9 -#define VOL_mmD5VGA_CONTROL 0xfa -#define VOL_mmD6VGA_CONTROL 0xfb -#define VOL_mmVGA_HW_DEBUG 0xcf -#define VOL_mmVGA_STATUS 0xd0 -#define VOL_mmVGA_INTERRUPT_CONTROL 0xd1 -#define VOL_mmVGA_STATUS_CLEAR 0xd2 -#define VOL_mmVGA_INTERRUPT_STATUS 0xd3 -#define VOL_mmVGA_MAIN_CONTROL 0xd4 -#define VOL_mmVGA_TEST_CONTROL 0xd5 -#define VOL_mmVGA_DEBUG_READBACK_INDEX 0xd6 -#define VOL_mmVGA_DEBUG_READBACK_DATA 0xd7 -#define VOL_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 -#define VOL_mmVGA_MEM_READ_PAGE_ADDR 0x13 -#define VOL_mmVGA_TEST_DEBUG_INDEX 0xc5 -#define VOL_mmVGA_TEST_DEBUG_DATA 0xc7 -#define VOL_ixVGADCC_DBG_DCCIF_C 0x7e -#define VOL_mmBPHYC_DAC_MACRO_CNTL 0x48b9 -#define VOL_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba -#define VOL_mmPLL_REF_DIV 0x1700 -#define VOL_mmBPHYC_PLL0_PLL_REF_DIV 0x1700 -#define VOL_mmBPHYC_PLL1_PLL_REF_DIV 0x172a -#define VOL_mmBPHYC_PLL2_PLL_REF_DIV 0x1754 -#define VOL_mmPLL_FB_DIV 0x1701 -#define VOL_mmBPHYC_PLL0_PLL_FB_DIV 0x1701 -#define VOL_mmBPHYC_PLL1_PLL_FB_DIV 0x172b -#define VOL_mmBPHYC_PLL2_PLL_FB_DIV 0x1755 -#define VOL_mmPLL_POST_DIV 0x1702 -#define VOL_mmBPHYC_PLL0_PLL_POST_DIV 0x1702 -#define VOL_mmBPHYC_PLL1_PLL_POST_DIV 0x172c -#define VOL_mmBPHYC_PLL2_PLL_POST_DIV 0x1756 -#define VOL_mmPLL_SS_AMOUNT_DSFRAC 0x1703 -#define VOL_mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 -#define VOL_mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d -#define VOL_mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 -#define VOL_mmPLL_SS_CNTL 0x1704 -#define VOL_mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 -#define VOL_mmBPHYC_PLL1_PLL_SS_CNTL 0x172e -#define VOL_mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 -#define VOL_mmPLL_DS_CNTL 0x1705 -#define VOL_mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 -#define VOL_mmBPHYC_PLL1_PLL_DS_CNTL 0x172f -#define VOL_mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 -#define VOL_mmPLL_IDCLK_CNTL 0x1706 -#define VOL_mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 -#define VOL_mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 -#define VOL_mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a -#define VOL_mmPLL_CNTL 0x1707 -#define VOL_mmBPHYC_PLL0_PLL_CNTL 0x1707 -#define VOL_mmBPHYC_PLL1_PLL_CNTL 0x1731 -#define VOL_mmBPHYC_PLL2_PLL_CNTL 0x175b -#define VOL_mmPLL_ANALOG 0x1708 -#define VOL_mmBPHYC_PLL0_PLL_ANALOG 0x1708 -#define VOL_mmBPHYC_PLL1_PLL_ANALOG 0x1732 -#define VOL_mmBPHYC_PLL2_PLL_ANALOG 0x175c -#define VOL_mmPLL_VREG_CNTL 0x1709 -#define VOL_mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 -#define VOL_mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 -#define VOL_mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d -#define VOL_mmPLL_UNLOCK_DETECT_CNTL 0x170a -#define VOL_mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a -#define VOL_mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 -#define VOL_mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e -#define VOL_mmPLL_DEBUG_CNTL 0x170b -#define VOL_mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b -#define VOL_mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 -#define VOL_mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f -#define VOL_mmPLL_UPDATE_LOCK 0x170c -#define VOL_mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c -#define VOL_mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 -#define VOL_mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 -#define VOL_mmPLL_UPDATE_CNTL 0x170d -#define VOL_mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d -#define VOL_mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 -#define VOL_mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 -#define VOL_mmPLL_XOR_LOCK 0x1710 -#define VOL_mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 -#define VOL_mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a -#define VOL_mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 -#define VOL_mmPLL_ANALOG_CNTL 0x1711 -#define VOL_mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 -#define VOL_mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b -#define VOL_mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 -#define VOL_mmVGA25_PPLL_REF_DIV 0x1712 -#define VOL_mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 -#define VOL_mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c -#define VOL_mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 -#define VOL_mmVGA28_PPLL_REF_DIV 0x1713 -#define VOL_mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 -#define VOL_mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d -#define VOL_mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 -#define VOL_mmVGA41_PPLL_REF_DIV 0x1714 -#define VOL_mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 -#define VOL_mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e -#define VOL_mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 -#define VOL_mmVGA25_PPLL_FB_DIV 0x1715 -#define VOL_mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 -#define VOL_mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f -#define VOL_mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 -#define VOL_mmVGA28_PPLL_FB_DIV 0x1716 -#define VOL_mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 -#define VOL_mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 -#define VOL_mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a -#define VOL_mmVGA41_PPLL_FB_DIV 0x1717 -#define VOL_mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 -#define VOL_mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 -#define VOL_mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b -#define VOL_mmVGA25_PPLL_POST_DIV 0x1718 -#define VOL_mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 -#define VOL_mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 -#define VOL_mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c -#define VOL_mmVGA28_PPLL_POST_DIV 0x1719 -#define VOL_mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 -#define VOL_mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 -#define VOL_mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d -#define VOL_mmVGA41_PPLL_POST_DIV 0x171a -#define VOL_mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a -#define VOL_mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 -#define VOL_mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e -#define VOL_mmVGA25_PPLL_ANALOG 0x171b -#define VOL_mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b -#define VOL_mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 -#define VOL_mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f -#define VOL_mmVGA28_PPLL_ANALOG 0x171c -#define VOL_mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c -#define VOL_mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 -#define VOL_mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 -#define VOL_mmVGA41_PPLL_ANALOG 0x171d -#define VOL_mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d -#define VOL_mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 -#define VOL_mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 -#define VOL_mmDISPPLL_BG_CNTL 0x171e -#define VOL_mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e -#define VOL_mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 -#define VOL_mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 -#define VOL_mmPPLL_DIV_UPDATE_DEBUG 0x171f -#define VOL_mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f -#define VOL_mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 -#define VOL_mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 -#define VOL_mmPPLL_STATUS_DEBUG 0x1720 -#define VOL_mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 -#define VOL_mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a -#define VOL_mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 -#define VOL_mmPPLL_DEBUG_MUX_CNTL 0x1721 -#define VOL_mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 -#define VOL_mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b -#define VOL_mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 -#define VOL_mmPPLL_SPARE0 0x1722 -#define VOL_mmBPHYC_PLL0_PPLL_SPARE0 0x1722 -#define VOL_mmBPHYC_PLL1_PPLL_SPARE0 0x174c -#define VOL_mmBPHYC_PLL2_PPLL_SPARE0 0x1776 -#define VOL_mmPPLL_SPARE1 0x1723 -#define VOL_mmBPHYC_PLL0_PPLL_SPARE1 0x1723 -#define VOL_mmBPHYC_PLL1_PPLL_SPARE1 0x174d -#define VOL_mmBPHYC_PLL2_PPLL_SPARE1 0x1777 -#define VOL_mmUNIPHY_TX_CONTROL1 0x48c0 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 -#define VOL_mmUNIPHY_TX_CONTROL2 0x48c1 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 -#define VOL_mmUNIPHY_TX_CONTROL3 0x48c2 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 -#define VOL_mmUNIPHY_TX_CONTROL4 0x48c3 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 -#define VOL_mmUNIPHY_POWER_CONTROL 0x48c4 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 -#define VOL_mmUNIPHY_PLL_FBDIV 0x48c5 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 -#define VOL_mmUNIPHY_PLL_CONTROL1 0x48c6 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 -#define VOL_mmUNIPHY_PLL_CONTROL2 0x48c7 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 -#define VOL_mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 -#define VOL_mmUNIPHY_PLL_SS_CNTL 0x48c9 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 -#define VOL_mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a -#define VOL_mmUNIPHY_REG_TEST_OUTPUT 0x48cb -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b -#define VOL_mmUNIPHY_ANG_BIST_CNTL 0x48cc -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c -#define VOL_mmUNIPHY_REG_TEST_OUTPUT2 0x48cd -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d -#define VOL_mmUNIPHY_TMDP_REG0 0x48ce -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e -#define VOL_mmUNIPHY_TMDP_REG1 0x48cf -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f -#define VOL_mmUNIPHY_TMDP_REG2 0x48d0 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 -#define VOL_mmUNIPHY_TMDP_REG3 0x48d1 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 -#define VOL_mmUNIPHY_TMDP_REG4 0x48d2 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 -#define VOL_mmUNIPHY_TMDP_REG5 0x48d3 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 -#define VOL_mmUNIPHY_TMDP_REG6 0x48d4 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 -#define VOL_mmUNIPHY_TPG_CONTROL 0x48d5 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 -#define VOL_mmUNIPHY_TPG_SEED 0x48d6 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 -#define VOL_mmUNIPHY_DEBUG 0x48d7 -#define VOL_mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 -#define VOL_mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 -#define VOL_mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 -#define VOL_mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 -#define VOL_mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 -#define VOL_mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 -#define VOL_mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 -#define VOL_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define VOL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -#define VOL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 -#define VOL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 -#define VOL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 -#define VOL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 -#define VOL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 -#define VOL_mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 -#define VOL_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define VOL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -#define VOL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 -#define VOL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 -#define VOL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 -#define VOL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 -#define VOL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 -#define VOL_mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 -#define VOL_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 -#define VOL_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 -#define VOL_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 -#define VOL_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 -#define VOL_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 -#define VOL_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 -#define VOL_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 -#define VOL_mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL 0x4732 -#define VOL_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 -#define VOL_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 -#define VOL_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 -#define VOL_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 -#define VOL_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 -#define VOL_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 -#define VOL_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 -#define VOL_mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL 0x4733 -#define VOL_mmDPG_PIPE_DPM_CONTROL 0x1b34 -#define VOL_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 -#define VOL_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 -#define VOL_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 -#define VOL_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 -#define VOL_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 -#define VOL_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 -#define VOL_mmDMIF_PG6_DPG_PIPE_DPM_CONTROL 0x4734 -#define VOL_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 -#define VOL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 -#define VOL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 -#define VOL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 -#define VOL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 -#define VOL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 -#define VOL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 -#define VOL_mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL 0x4735 -#define VOL_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define VOL_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -#define VOL_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 -#define VOL_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 -#define VOL_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 -#define VOL_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 -#define VOL_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 -#define VOL_mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 -#define VOL_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define VOL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -#define VOL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 -#define VOL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 -#define VOL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 -#define VOL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 -#define VOL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 -#define VOL_mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 -#define VOL_mmDPG_REPEATER_PROGRAM 0x1b3a -#define VOL_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a -#define VOL_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a -#define VOL_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a -#define VOL_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a -#define VOL_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a -#define VOL_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a -#define VOL_mmDMIF_PG6_DPG_REPEATER_PROGRAM 0x473a -#define VOL_mmDPG_HW_DEBUG_A 0x1b3b -#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b -#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b -#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b -#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b -#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b -#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b -#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_A 0x473b -#define VOL_mmDPG_HW_DEBUG_B 0x1b3c -#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c -#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c -#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c -#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c -#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c -#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c -#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_B 0x473c -#define VOL_mmDPG_HW_DEBUG_11 0x1b3d -#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d -#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d -#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d -#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d -#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d -#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d -#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_11 0x473d -#define VOL_mmDPG_TEST_DEBUG_INDEX 0x1b38 -#define VOL_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 -#define VOL_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 -#define VOL_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 -#define VOL_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 -#define VOL_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 -#define VOL_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 -#define VOL_mmDMIF_PG6_DPG_TEST_DEBUG_INDEX 0x4738 -#define VOL_mmDPG_TEST_DEBUG_DATA 0x1b39 -#define VOL_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 -#define VOL_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 -#define VOL_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 -#define VOL_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 -#define VOL_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 -#define VOL_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 -#define VOL_mmDMIF_PG6_DPG_TEST_DEBUG_DATA 0x4739 -#define VOL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define VOL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 -#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 -#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 -#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 -#define VOL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 -#define VOL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 -#define VOL_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a -#define VOL_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 -#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 -#define VOL_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 -#define VOL_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 -#define VOL_mmAZALIA_F0_CODEC_DEBUG 0x1836 -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c -#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d -#define VOL_mmGLOBAL_CAPABILITIES 0x0 -#define VOL_mmMINOR_VERSION 0x0 -#define VOL_mmMAJOR_VERSION 0x0 -#define VOL_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 -#define VOL_mmINPUT_PAYLOAD_CAPABILITY 0x1 -#define VOL_mmGLOBAL_CONTROL 0x2 -#define VOL_mmWAKE_ENABLE 0x3 -#define VOL_mmSTATE_CHANGE_STATUS 0x3 -#define VOL_mmGLOBAL_STATUS 0x4 -#define VOL_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -#define VOL_mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -#define VOL_mmINTERRUPT_CONTROL 0x8 -#define VOL_mmINTERRUPT_STATUS 0x9 -#define VOL_mmWALL_CLOCK_COUNTER 0xc -#define VOL_mmSTREAM_SYNCHRONIZATION 0xe -#define VOL_mmCORB_LOWER_BASE_ADDRESS 0x10 -#define VOL_mmCORB_UPPER_BASE_ADDRESS 0x11 -#define VOL_mmCORB_WRITE_POINTER 0x12 -#define VOL_mmCORB_READ_POINTER 0x12 -#define VOL_mmCORB_CONTROL 0x13 -#define VOL_mmCORB_STATUS 0x13 -#define VOL_mmCORB_SIZE 0x13 -#define VOL_mmRIRB_LOWER_BASE_ADDRESS 0x14 -#define VOL_mmRIRB_UPPER_BASE_ADDRESS 0x15 -#define VOL_mmRIRB_WRITE_POINTER 0x16 -#define VOL_mmRESPONSE_INTERRUPT_COUNT 0x16 -#define VOL_mmRIRB_CONTROL 0x17 -#define VOL_mmRIRB_STATUS 0x17 -#define VOL_mmRIRB_SIZE 0x17 -#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 -#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define VOL_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 -#define VOL_mmIMMEDIATE_COMMAND_STATUS 0x1a -#define VOL_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c -#define VOL_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d -#define VOL_mmWALL_CLOCK_COUNTER_ALIAS 0x80c -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 -#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 -#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 -#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 -#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 -#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c -#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 -#define VOL_ixAUDIO_DESCRIPTOR0 0x1 -#define VOL_ixAUDIO_DESCRIPTOR1 0x2 -#define VOL_ixAUDIO_DESCRIPTOR2 0x3 -#define VOL_ixAUDIO_DESCRIPTOR3 0x4 -#define VOL_ixAUDIO_DESCRIPTOR4 0x5 -#define VOL_ixAUDIO_DESCRIPTOR5 0x6 -#define VOL_ixAUDIO_DESCRIPTOR6 0x7 -#define VOL_ixAUDIO_DESCRIPTOR7 0x8 -#define VOL_ixAUDIO_DESCRIPTOR8 0x9 -#define VOL_ixAUDIO_DESCRIPTOR9 0xa -#define VOL_ixAUDIO_DESCRIPTOR10 0xb -#define VOL_ixAUDIO_DESCRIPTOR11 0xc -#define VOL_ixAUDIO_DESCRIPTOR12 0xd -#define VOL_ixAUDIO_DESCRIPTOR13 0xe -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 -#define VOL_ixSINK_DESCRIPTION0 0x5 -#define VOL_ixSINK_DESCRIPTION1 0x6 -#define VOL_ixSINK_DESCRIPTION2 0x7 -#define VOL_ixSINK_DESCRIPTION3 0x8 -#define VOL_ixSINK_DESCRIPTION4 0x9 -#define VOL_ixSINK_DESCRIPTION5 0xa -#define VOL_ixSINK_DESCRIPTION6 0xb -#define VOL_ixSINK_DESCRIPTION7 0xc -#define VOL_ixSINK_DESCRIPTION8 0xd -#define VOL_ixSINK_DESCRIPTION9 0xe -#define VOL_ixSINK_DESCRIPTION10 0xf -#define VOL_ixSINK_DESCRIPTION11 0x10 -#define VOL_ixSINK_DESCRIPTION12 0x11 -#define VOL_ixSINK_DESCRIPTION13 0x12 -#define VOL_ixSINK_DESCRIPTION14 0x13 -#define VOL_ixSINK_DESCRIPTION15 0x14 -#define VOL_ixSINK_DESCRIPTION16 0x15 -#define VOL_ixSINK_DESCRIPTION17 0x16 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 -#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 -#define VOL_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d -#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e -#define VOL_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 -#define VOL_mmAZALIA_AUDIO_DTO 0x17e5 -#define VOL_mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 -#define VOL_mmAZALIA_SCLK_CONTROL 0x17e7 -#define VOL_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 -#define VOL_mmAZALIA_DATA_DMA_CONTROL 0x17e9 -#define VOL_mmAZALIA_BDL_DMA_CONTROL 0x17ea -#define VOL_mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb -#define VOL_mmAZALIA_CORB_DMA_CONTROL 0x17ec -#define VOL_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 -#define VOL_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 -#define VOL_mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 -#define VOL_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 -#define VOL_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 -#define VOL_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 -#define VOL_mmAZALIA_CONTROLLER_DEBUG 0x17f9 -#define VOL_mmAZALIA_MEM_PWR_CTRL 0x1810 -#define VOL_mmAZALIA_MEM_PWR_STATUS 0x1811 -#define VOL_mmDCI_PG_DEBUG_CONFIG 0x1812 -#define VOL_mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb -#define VOL_mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc -#define VOL_mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd -#define VOL_mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe -#define VOL_mmAZALIA_INPUT_CRC0_RESULT 0x17ff -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 -#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 -#define VOL_mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 -#define VOL_mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 -#define VOL_mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 -#define VOL_mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 -#define VOL_mmAZALIA_INPUT_CRC1_RESULT 0x1804 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 -#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 -#define VOL_mmAZALIA_CRC0_CONTROL0 0x1805 -#define VOL_mmAZALIA_CRC0_CONTROL1 0x1806 -#define VOL_mmAZALIA_CRC0_CONTROL2 0x1807 -#define VOL_mmAZALIA_CRC0_CONTROL3 0x1808 -#define VOL_mmAZALIA_CRC0_RESULT 0x1809 -#define VOL_ixAZALIA_CRC0_CHANNEL0 0x0 -#define VOL_ixAZALIA_CRC0_CHANNEL1 0x1 -#define VOL_ixAZALIA_CRC0_CHANNEL2 0x2 -#define VOL_ixAZALIA_CRC0_CHANNEL3 0x3 -#define VOL_ixAZALIA_CRC0_CHANNEL4 0x4 -#define VOL_ixAZALIA_CRC0_CHANNEL5 0x5 -#define VOL_ixAZALIA_CRC0_CHANNEL6 0x6 -#define VOL_ixAZALIA_CRC0_CHANNEL7 0x7 -#define VOL_mmAZALIA_CRC1_CONTROL0 0x180a -#define VOL_mmAZALIA_CRC1_CONTROL1 0x180b -#define VOL_mmAZALIA_CRC1_CONTROL2 0x180c -#define VOL_mmAZALIA_CRC1_CONTROL3 0x180d -#define VOL_mmAZALIA_CRC1_RESULT 0x180e -#define VOL_ixAZALIA_CRC1_CHANNEL0 0x0 -#define VOL_ixAZALIA_CRC1_CHANNEL1 0x1 -#define VOL_ixAZALIA_CRC1_CHANNEL2 0x2 -#define VOL_ixAZALIA_CRC1_CHANNEL3 0x3 -#define VOL_ixAZALIA_CRC1_CHANNEL4 0x4 -#define VOL_ixAZALIA_CRC1_CHANNEL5 0x5 -#define VOL_ixAZALIA_CRC1_CHANNEL6 0x6 -#define VOL_ixAZALIA_CRC1_CHANNEL7 0x7 -#define VOL_mmAZ_TEST_DEBUG_INDEX 0x181f -#define VOL_mmAZ_TEST_DEBUG_DATA 0x1820 -#define VOL_mmAZALIA_STREAM_INDEX 0x1780 -#define VOL_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 -#define VOL_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 -#define VOL_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 -#define VOL_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 -#define VOL_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 -#define VOL_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a -#define VOL_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c -#define VOL_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e -#define VOL_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 -#define VOL_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 -#define VOL_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 -#define VOL_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 -#define VOL_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 -#define VOL_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca -#define VOL_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc -#define VOL_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce -#define VOL_mmAZALIA_STREAM_DATA 0x1781 -#define VOL_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 -#define VOL_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 -#define VOL_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 -#define VOL_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 -#define VOL_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 -#define VOL_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b -#define VOL_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d -#define VOL_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f -#define VOL_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 -#define VOL_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 -#define VOL_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 -#define VOL_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 -#define VOL_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 -#define VOL_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb -#define VOL_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd -#define VOL_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf -#define VOL_ixAZALIA_FIFO_SIZE_CONTROL 0x0 -#define VOL_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 -#define VOL_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 -#define VOL_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 -#define VOL_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 -#define VOL_ixAZALIA_STREAM_DEBUG 0x5 -#define VOL_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 -#define VOL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 -#define VOL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac -#define VOL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 -#define VOL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 -#define VOL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 -#define VOL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc -#define VOL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 -#define VOL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 -#define VOL_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 -#define VOL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 -#define VOL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad -#define VOL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 -#define VOL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 -#define VOL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 -#define VOL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd -#define VOL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 -#define VOL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd -#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe -#define VOL_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -#define VOL_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 -#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 -#define VOL_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 -#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a -#define VOL_ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b -#define VOL_ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c -#define VOL_ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d -#define VOL_ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e -#define VOL_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 -#define VOL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 -#define VOL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 -#define VOL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc -#define VOL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 -#define VOL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 -#define VOL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 -#define VOL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec -#define VOL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 -#define VOL_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 -#define VOL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 -#define VOL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 -#define VOL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd -#define VOL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 -#define VOL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 -#define VOL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 -#define VOL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed -#define VOL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 -#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 -#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 -#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 -#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 -#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a -#define VOL_mmBLND_CONTROL 0x1b6d -#define VOL_mmBLND0_BLND_CONTROL 0x1b6d -#define VOL_mmBLND1_BLND_CONTROL 0x1d6d -#define VOL_mmBLND2_BLND_CONTROL 0x1f6d -#define VOL_mmBLND3_BLND_CONTROL 0x416d -#define VOL_mmBLND4_BLND_CONTROL 0x436d -#define VOL_mmBLND5_BLND_CONTROL 0x456d -#define VOL_mmBLND6_BLND_CONTROL 0x476d -#define VOL_mmSM_CONTROL2 0x1b6e -#define VOL_mmBLND0_SM_CONTROL2 0x1b6e -#define VOL_mmBLND1_SM_CONTROL2 0x1d6e -#define VOL_mmBLND2_SM_CONTROL2 0x1f6e -#define VOL_mmBLND3_SM_CONTROL2 0x416e -#define VOL_mmBLND4_SM_CONTROL2 0x436e -#define VOL_mmBLND5_SM_CONTROL2 0x456e -#define VOL_mmBLND6_SM_CONTROL2 0x476e -#define VOL_mmBLND_CONTROL2 0x1b6f -#define VOL_mmBLND0_BLND_CONTROL2 0x1b6f -#define VOL_mmBLND1_BLND_CONTROL2 0x1d6f -#define VOL_mmBLND2_BLND_CONTROL2 0x1f6f -#define VOL_mmBLND3_BLND_CONTROL2 0x416f -#define VOL_mmBLND4_BLND_CONTROL2 0x436f -#define VOL_mmBLND5_BLND_CONTROL2 0x456f -#define VOL_mmBLND6_BLND_CONTROL2 0x476f -#define VOL_mmBLND_UPDATE 0x1b70 -#define VOL_mmBLND0_BLND_UPDATE 0x1b70 -#define VOL_mmBLND1_BLND_UPDATE 0x1d70 -#define VOL_mmBLND2_BLND_UPDATE 0x1f70 -#define VOL_mmBLND3_BLND_UPDATE 0x4170 -#define VOL_mmBLND4_BLND_UPDATE 0x4370 -#define VOL_mmBLND5_BLND_UPDATE 0x4570 -#define VOL_mmBLND6_BLND_UPDATE 0x4770 -#define VOL_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 -#define VOL_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 -#define VOL_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 -#define VOL_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 -#define VOL_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 -#define VOL_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 -#define VOL_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 -#define VOL_mmBLND6_BLND_UNDERFLOW_INTERRUPT 0x4771 -#define VOL_mmBLND_V_UPDATE_LOCK 0x1b73 -#define VOL_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 -#define VOL_mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 -#define VOL_mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 -#define VOL_mmBLND3_BLND_V_UPDATE_LOCK 0x4173 -#define VOL_mmBLND4_BLND_V_UPDATE_LOCK 0x4373 -#define VOL_mmBLND5_BLND_V_UPDATE_LOCK 0x4573 -#define VOL_mmBLND6_BLND_V_UPDATE_LOCK 0x4773 -#define VOL_mmBLND_REG_UPDATE_STATUS 0x1b77 -#define VOL_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 -#define VOL_mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 -#define VOL_mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 -#define VOL_mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 -#define VOL_mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 -#define VOL_mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 -#define VOL_mmBLND6_BLND_REG_UPDATE_STATUS 0x4777 -#define VOL_mmBLND_DEBUG 0x1b74 -#define VOL_mmBLND0_BLND_DEBUG 0x1b74 -#define VOL_mmBLND1_BLND_DEBUG 0x1d74 -#define VOL_mmBLND2_BLND_DEBUG 0x1f74 -#define VOL_mmBLND3_BLND_DEBUG 0x4174 -#define VOL_mmBLND4_BLND_DEBUG 0x4374 -#define VOL_mmBLND5_BLND_DEBUG 0x4574 -#define VOL_mmBLND6_BLND_DEBUG 0x4774 -#define VOL_mmBLND_TEST_DEBUG_INDEX 0x1b75 -#define VOL_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 -#define VOL_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 -#define VOL_mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 -#define VOL_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 -#define VOL_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 -#define VOL_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 -#define VOL_mmBLND6_BLND_TEST_DEBUG_INDEX 0x4775 -#define VOL_mmBLND_TEST_DEBUG_DATA 0x1b76 -#define VOL_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 -#define VOL_mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 -#define VOL_mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 -#define VOL_mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 -#define VOL_mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 -#define VOL_mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 -#define VOL_mmBLND6_BLND_TEST_DEBUG_DATA 0x4776 -#define VOL_mmWB_ENABLE 0x5e18 -#define VOL_mmWB_EC_CONFIG 0x5e19 -#define VOL_mmCNV_MODE 0x5e1a -#define VOL_mmCNV_WINDOW_START 0x5e1b -#define VOL_mmCNV_WINDOW_SIZE 0x5e1c -#define VOL_mmCNV_UPDATE 0x5e1d -#define VOL_mmCNV_SOURCE_SIZE 0x5e1e -#define VOL_mmCNV_CSC_CONTROL 0x5e1f -#define VOL_mmCNV_CSC_C11_C12 0x5e20 -#define VOL_mmCNV_CSC_C13_C14 0x5e21 -#define VOL_mmCNV_CSC_C21_C22 0x5e22 -#define VOL_mmCNV_CSC_C23_C24 0x5e23 -#define VOL_mmCNV_CSC_C31_C32 0x5e24 -#define VOL_mmCNV_CSC_C33_C34 0x5e25 -#define VOL_mmCNV_CSC_ROUND_OFFSET_R 0x5e26 -#define VOL_mmCNV_CSC_ROUND_OFFSET_G 0x5e27 -#define VOL_mmCNV_CSC_ROUND_OFFSET_B 0x5e28 -#define VOL_mmCNV_CSC_CLAMP_R 0x5e29 -#define VOL_mmCNV_CSC_CLAMP_G 0x5e2a -#define VOL_mmCNV_CSC_CLAMP_B 0x5e2b -#define VOL_mmCNV_TEST_CNTL 0x5e2c -#define VOL_mmCNV_TEST_CRC_RED 0x5e2d -#define VOL_mmCNV_TEST_CRC_GREEN 0x5e2e -#define VOL_mmCNV_TEST_CRC_BLUE 0x5e2f -#define VOL_mmWB_DEBUG_CTRL 0x5e30 -#define VOL_mmWB_DBG_MODE 0x5e31 -#define VOL_mmWB_HW_DEBUG 0x5e32 -#define VOL_mmCNV_INPUT_SELECT 0x5e33 -#define VOL_mmWB_SOFT_RESET 0x5e36 -#define VOL_mmCNV_TEST_DEBUG_INDEX 0x5e34 -#define VOL_mmCNV_TEST_DEBUG_DATA 0x5e35 -#define VOL_mmDCFE_CLOCK_CONTROL 0x1b00 -#define VOL_mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 -#define VOL_mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 -#define VOL_mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 -#define VOL_mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 -#define VOL_mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 -#define VOL_mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 -#define VOL_mmDCFE_SOFT_RESET 0x1b01 -#define VOL_mmDCFE0_DCFE_SOFT_RESET 0x1b01 -#define VOL_mmDCFE1_DCFE_SOFT_RESET 0x1d01 -#define VOL_mmDCFE2_DCFE_SOFT_RESET 0x1f01 -#define VOL_mmDCFE3_DCFE_SOFT_RESET 0x4101 -#define VOL_mmDCFE4_DCFE_SOFT_RESET 0x4301 -#define VOL_mmDCFE5_DCFE_SOFT_RESET 0x4501 -#define VOL_mmDCFE_DBG_CONFIG 0x1b02 -#define VOL_mmDCFE0_DCFE_DBG_CONFIG 0x1b02 -#define VOL_mmDCFE1_DCFE_DBG_CONFIG 0x1d02 -#define VOL_mmDCFE2_DCFE_DBG_CONFIG 0x1f02 -#define VOL_mmDCFE3_DCFE_DBG_CONFIG 0x4102 -#define VOL_mmDCFE4_DCFE_DBG_CONFIG 0x4302 -#define VOL_mmDCFE5_DCFE_DBG_CONFIG 0x4502 -#define VOL_mmDCFEV_CLOCK_CONTROL 0x46f4 -#define VOL_mmDCFEV_SOFT_RESET 0x46f5 -#define VOL_mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 -#define VOL_mmDCFEV_DBG_CONFIG 0x46f7 -#define VOL_mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 -#define VOL_mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 -#define VOL_mmDC_HPD_INT_STATUS 0x1898 -#define VOL_mmHPD0_DC_HPD_INT_STATUS 0x1898 -#define VOL_mmHPD1_DC_HPD_INT_STATUS 0x18a0 -#define VOL_mmHPD2_DC_HPD_INT_STATUS 0x18a8 -#define VOL_mmHPD3_DC_HPD_INT_STATUS 0x18b0 -#define VOL_mmHPD4_DC_HPD_INT_STATUS 0x18b8 -#define VOL_mmHPD5_DC_HPD_INT_STATUS 0x18c0 -#define VOL_mmDC_HPD_INT_CONTROL 0x1899 -#define VOL_mmHPD0_DC_HPD_INT_CONTROL 0x1899 -#define VOL_mmHPD1_DC_HPD_INT_CONTROL 0x18a1 -#define VOL_mmHPD2_DC_HPD_INT_CONTROL 0x18a9 -#define VOL_mmHPD3_DC_HPD_INT_CONTROL 0x18b1 -#define VOL_mmHPD4_DC_HPD_INT_CONTROL 0x18b9 -#define VOL_mmHPD5_DC_HPD_INT_CONTROL 0x18c1 -#define VOL_mmDC_HPD_CONTROL 0x189a -#define VOL_mmHPD0_DC_HPD_CONTROL 0x189a -#define VOL_mmHPD1_DC_HPD_CONTROL 0x18a2 -#define VOL_mmHPD2_DC_HPD_CONTROL 0x18aa -#define VOL_mmHPD3_DC_HPD_CONTROL 0x18b2 -#define VOL_mmHPD4_DC_HPD_CONTROL 0x18ba -#define VOL_mmHPD5_DC_HPD_CONTROL 0x18c2 -#define VOL_mmDC_HPD_FAST_TRAIN_CNTL 0x189b -#define VOL_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b -#define VOL_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 -#define VOL_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab -#define VOL_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 -#define VOL_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb -#define VOL_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 -#define VOL_mmDC_HPD_TOGGLE_FILT_CNTL 0x189c -#define VOL_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c -#define VOL_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 -#define VOL_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac -#define VOL_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 -#define VOL_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc -#define VOL_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 -#define VOL_mmDCO_SCRATCH0 0x184e -#define VOL_mmDCO_SCRATCH1 0x184f -#define VOL_mmDCO_SCRATCH2 0x1850 -#define VOL_mmDCO_SCRATCH3 0x1851 -#define VOL_mmDCO_SCRATCH4 0x1852 -#define VOL_mmDCO_SCRATCH5 0x1853 -#define VOL_mmDCO_SCRATCH6 0x1854 -#define VOL_mmDCO_SCRATCH7 0x1855 -#define VOL_mmDCE_VCE_CONTROL 0x1856 -#define VOL_mmDISP_INTERRUPT_STATUS 0x1857 -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f -#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 -#define VOL_mmDCO_MEM_PWR_STATUS 0x1861 -#define VOL_mmDCO_MEM_PWR_CTRL 0x1862 -#define VOL_mmDCO_MEM_PWR_CTRL2 0x1863 -#define VOL_mmDCO_CLK_CNTL 0x1864 -#define VOL_mmDCO_CLK_RAMP_CNTL 0x1865 -#define VOL_mmDPDBG_CNTL 0x1866 -#define VOL_mmDPDBG_INTERRUPT 0x1867 -#define VOL_mmDCO_POWER_MANAGEMENT_CNTL 0x1868 -#define VOL_mmDCO_SOFT_RESET 0x1871 -#define VOL_mmDIG_SOFT_RESET 0x1872 -#define VOL_mmDCO_STEREOSYNC_SEL 0x186e -#define VOL_mmDCO_TEST_DEBUG_INDEX 0x186f -#define VOL_mmDCO_TEST_DEBUG_DATA 0x1870 -#define VOL_mmDC_I2C_CONTROL 0x16d4 -#define VOL_mmDC_I2C_ARBITRATION 0x16d5 -#define VOL_mmDC_I2C_INTERRUPT_CONTROL 0x16d6 -#define VOL_mmDC_I2C_SW_STATUS 0x16d7 -#define VOL_mmDC_I2C_DDC1_HW_STATUS 0x16d8 -#define VOL_mmDC_I2C_DDC2_HW_STATUS 0x16d9 -#define VOL_mmDC_I2C_DDC3_HW_STATUS 0x16da -#define VOL_mmDC_I2C_DDC4_HW_STATUS 0x16db -#define VOL_mmDC_I2C_DDC5_HW_STATUS 0x16dc -#define VOL_mmDC_I2C_DDC6_HW_STATUS 0x16dd -#define VOL_mmDC_I2C_DDC1_SPEED 0x16de -#define VOL_mmDC_I2C_DDC1_SETUP 0x16df -#define VOL_mmDC_I2C_DDC2_SPEED 0x16e0 -#define VOL_mmDC_I2C_DDC2_SETUP 0x16e1 -#define VOL_mmDC_I2C_DDC3_SPEED 0x16e2 -#define VOL_mmDC_I2C_DDC3_SETUP 0x16e3 -#define VOL_mmDC_I2C_DDC4_SPEED 0x16e4 -#define VOL_mmDC_I2C_DDC4_SETUP 0x16e5 -#define VOL_mmDC_I2C_DDC5_SPEED 0x16e6 -#define VOL_mmDC_I2C_DDC5_SETUP 0x16e7 -#define VOL_mmDC_I2C_DDC6_SPEED 0x16e8 -#define VOL_mmDC_I2C_DDC6_SETUP 0x16e9 -#define VOL_mmDC_I2C_TRANSACTION0 0x16ea -#define VOL_mmDC_I2C_TRANSACTION1 0x16eb -#define VOL_mmDC_I2C_TRANSACTION2 0x16ec -#define VOL_mmDC_I2C_TRANSACTION3 0x16ed -#define VOL_mmDC_I2C_DATA 0x16ee -#define VOL_mmDC_I2C_DDCVGA_HW_STATUS 0x16ef -#define VOL_mmDC_I2C_DDCVGA_SPEED 0x16f0 -#define VOL_mmDC_I2C_DDCVGA_SETUP 0x16f1 -#define VOL_mmDC_I2C_EDID_DETECT_CTRL 0x16f2 -#define VOL_mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 -#define VOL_mmGENERIC_I2C_CONTROL 0x16f4 -#define VOL_mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 -#define VOL_mmGENERIC_I2C_STATUS 0x16f6 -#define VOL_mmGENERIC_I2C_SPEED 0x16f7 -#define VOL_mmGENERIC_I2C_SETUP 0x16f8 -#define VOL_mmGENERIC_I2C_TRANSACTION 0x16f9 -#define VOL_mmGENERIC_I2C_DATA 0x16fa -#define VOL_mmGENERIC_I2C_PIN_SELECTION 0x16fb -#define VOL_mmGENERIC_I2C_PIN_DEBUG 0x16fc -#define VOL_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 -#define VOL_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 -#define VOL_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 -#define VOL_mmXDMA_INTERRUPT 0x3e3 -#define VOL_mmXDMA_CLOCK_GATING_CNTL 0x3e4 -#define VOL_mmXDMA_MEM_POWER_CNTL 0x3e6 -#define VOL_mmXDMA_IF_BIF_STATUS 0x3e7 -#define VOL_mmXDMA_PERF_MEAS_STATUS 0x3e8 -#define VOL_mmXDMA_IF_STATUS 0x3e9 -#define VOL_mmXDMA_TEST_DEBUG_INDEX 0x3ea -#define VOL_mmXDMA_TEST_DEBUG_DATA 0x3eb -#define VOL_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 -#define VOL_mmXDMA_PG_CONTROL 0x3f9 -#define VOL_mmXDMA_PG_WDATA 0x3fa -#define VOL_mmXDMA_PG_STATUS 0x3fb -#define VOL_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc -#define VOL_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd -#define VOL_mmXDMA_MSTR_CNTL 0x3ec -#define VOL_mmXDMA_MSTR_STATUS 0x3ed -#define VOL_mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee -#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef -#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 -#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 -#define VOL_mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 -#define VOL_mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 -#define VOL_mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 -#define VOL_mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 -#define VOL_mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 -#define VOL_mmXDMA_MSTR_PIPE_CNTL 0x400 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 -#define VOL_mmXDMA_MSTR_READ_COMMAND 0x401 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 -#define VOL_mmXDMA_MSTR_CHANNEL_DIM 0x402 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 -#define VOL_mmXDMA_MSTR_HEIGHT 0x403 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 -#define VOL_mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 -#define VOL_mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 -#define VOL_mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 -#define VOL_mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 -#define VOL_mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 -#define VOL_mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 -#define VOL_mmXDMA_MSTR_CACHE 0x40a -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a -#define VOL_mmXDMA_MSTR_CHANNEL_START 0x40b -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b -#define VOL_mmXDMA_MSTR_PERFMEAS_STATUS 0x40e -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e -#define VOL_mmXDMA_MSTR_PERFMEAS_CNTL 0x40f -#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f -#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f -#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f -#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f -#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f -#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f -#define VOL_mmXDMA_SLV_CNTL 0x460 -#define VOL_mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 -#define VOL_mmXDMA_SLV_SLS_PITCH 0x462 -#define VOL_mmXDMA_SLV_READ_URGENT_CNTL 0x463 -#define VOL_mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 -#define VOL_mmXDMA_SLV_WB_RATE_CNTL 0x465 -#define VOL_mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 -#define VOL_mmXDMA_SLV_READ_LATENCY_AVE 0x467 -#define VOL_mmXDMA_SLV_PCIE_NACK_STATUS 0x468 -#define VOL_mmXDMA_SLV_MEM_NACK_STATUS 0x469 -#define VOL_mmXDMA_SLV_RDRET_BUF_STATUS 0x46a -#define VOL_mmXDMA_SLV_READ_LATENCY_TIMER 0x46b -#define VOL_mmXDMA_SLV_FLIP_PENDING 0x46c -#define VOL_mmXDMA_SLV_CHANNEL_CNTL 0x470 -#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 -#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 -#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 -#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 -#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 -#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 -#define VOL_mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 -#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 -#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 -#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 -#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 -#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 -#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 -#define VOL_mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 -#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 -#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a -#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 -#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a -#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 -#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a #endif /* DCE_10_0_D_H */