From 7fe04ec74b412aad6d4d50ab15b97cd486d2ac7b Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 14 Feb 2006 21:16:24 +0000 Subject: [PATCH] added retrace sync programming for NV12_IMAGE_BLIT command. Works OK it seems (testing in 3D add-on). git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16400 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index e61645333f..e6d3b874fb 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -890,6 +890,15 @@ status_t nv_acc_init_dma() ACCW(ABS_UCLP_XMAX, 0x00007fff); ACCW(ABS_UCLP_YMAX, 0x00007fff); + /* setup sync parameters for NV12_IMAGE_BLIT command for the current mode: + * values given are CRTC vertical counter limit values. The NV12 command will wait + * for the specified's CRTC's vertical counter to be in between the given values */ + if (si->ps.card_type >= NV11) + { + ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1); + ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1); + } + /*** PFIFO ***/ /* (setup caches) */ /* disable caches reassign */