From 82581f548da70f207b773fbbb08523cd6ccecd10 Mon Sep 17 00:00:00 2001
From: Rudolf Cornelissen <rudolf.cornelissen@gmail.com>
Date: Mon, 9 May 2005 08:51:22 +0000
Subject: [PATCH] added CRTC1 FIFO low-watermark/burstsize preliminary
 programming (not yet enabled: testing). This should be fixing high-res mode
 display sparking/noise/errors/DMA engine hangs in the (near) future.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12601 a95241bf-73f2-0310-859d-f6bbb57e9c96
---
 .../accelerants/nvidia/engine/nv_crtc.c       | 30 ++++++++++++++++++-
 .../accelerants/nvidia/engine/nv_info.c       |  3 +-
 .../accelerants/nvidia/engine/nv_proto.h      |  1 +
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
index dd76dd799b..21228dd42b 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
@@ -1,12 +1,40 @@
 /* CTRC functionality */
 /* Author:
-   Rudolf Cornelissen 11/2002-2/2005
+   Rudolf Cornelissen 11/2002-5/2005
 */
 
 #define MODULE_BIT 0x00040000
 
 #include "nv_std.h"
 
+/* doing general fail-safe default setup here */
+//fixme: this is a _very_ basic setup, and it's preliminary...
+status_t nv_crtc_update_fifo()
+{
+	/* we are only using this on coldstarted cards which really need this */
+	if ((si->settings.usebios) || (si->ps.card_arch != NV04A)) return B_OK;
+
+	/* enable access to primary head */
+	set_crtc_owner(0);
+
+	/* set CRTC FIFO burst size to 256 (is BIOS default) */
+	CRTCW(FIFO, 0x03);
+
+	/* set CRTC FIFO low watermark according to mode */
+	if ((si->dm.timing.h_display * si->dm.timing.v_display) > (1280 * 1024))
+	{
+		/* Instruct CRTC to fetch new data 'earlier' */
+		CRTCW(FIFO_LWM, 0x40);
+	}
+	else
+	{
+		/* BIOS default */
+		CRTCW(FIFO_LWM, 0x20);
+	}
+
+	return B_OK;
+}
+
 /* Adjust passed parameters to a valid mode line */
 status_t nv_crtc_validate_timing(
 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c
index 8f10c03b7a..3bf30d5027 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_info.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c
@@ -2038,13 +2038,12 @@ static status_t translate_ISA_PCI(uint32* reg)
 	return B_OK;
 }
 
-//fixme: move to crtc sourcefile, also setup for crtc2(?)
+/* doing general fail-safe default setup here */
 static status_t	nv_crtc_setup_fifo()
 {
 	/* enable access to primary head */
 	set_crtc_owner(0);
 
-	//fixme: setup according to colordepth and RAM bus width...
 	/* set CRTC FIFO burst size to 256 */
 	CRTCW(FIFO, 0x03);
 
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_proto.h b/src/add-ons/accelerants/nvidia/engine/nv_proto.h
index 107b5cc375..afe6bf25fc 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_proto.h
+++ b/src/add-ons/accelerants/nvidia/engine/nv_proto.h
@@ -60,6 +60,7 @@ status_t g100_g400max_maventv_vid_pll_find(
 int maventv_init(display_mode target);
 
 /* CRTC1 functions */
+status_t nv_crtc_update_fifo(void);
 status_t nv_crtc_validate_timing(
 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt