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Fix flushing the ATC, add flushing icache.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22709 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
2007-10-25 02:24:38 +00:00
parent 5d31dc1586
commit 829748d89d
2 changed files with 16 additions and 22 deletions
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headers/private/kernel/arch/m68k/arch_cpu.h
+5 -2
View File
@@ -204,9 +204,12 @@ extern bool m68k_set_fault_handler(addr_t *handlerLocation, addr_t handler)
} }
#endif #endif
#define m68k_nop() asm volatile("nop") /* flushes insn pipeline */ /* flushes insn pipeline */
#define pflush(addr) asm volatile("pflush (%0)" :: "a" (addr)) #define m68k_nop() asm volatile("nop")
/* no FC bit needed */
#define pflush(addr) asm volatile("pflush #0,#0,(%0)" :: "a" (addr))
#define pflusha() asm volatile("pflusha") #define pflusha() asm volatile("pflusha")
//#define //#define
#if 0 #if 0
src/system/kernel/arch/m68k/arch_cpu.cpp
+11 -20
View File
@@ -14,13 +14,12 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <boot/kernel_args.h> #include <boot/kernel_args.h>
static bool sHasTlbia;
status_t status_t
arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu) arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu)
{ {
// enable FPU // enable FPU
set_msr(get_msr() | MSR_FP_AVAILABLE); //ppc:set_msr(get_msr() | MSR_FP_AVAILABLE);
// The current thread must be NULL for all CPUs till we have threads. // The current thread must be NULL for all CPUs till we have threads.
// Some boot code relies on this. // Some boot code relies on this.
@@ -33,10 +32,6 @@ arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu)
status_t status_t
arch_cpu_init(kernel_args *args) arch_cpu_init(kernel_args *args)
{ {
// TODO: Let the boot loader put that info into the kernel args
// (property "tlbia" in the CPU node).
sHasTlbia = false;
return B_OK; return B_OK;
} }
@@ -60,25 +55,21 @@ arch_cpu_sync_icache(void *address, size_t len)
{ {
int l, off; int l, off;
char *p; char *p;
uint32 cacr;
off = (unsigned int)address & (CACHELINE - 1); off = (unsigned int)address & (CACHELINE - 1);
len += off; len += off;
l = len; l = len;
p = (char *)address - off; p = (char *)address - off;
asm volatile ("movec %%cacr,%0" : "=r"(cacr):);
cacr |= 0x00000004; /* ClearInstructionCacheEntry */
do { do {
asm volatile ("dcbst 0,%0" :: "r"(p)); asm volatile ("movec %0,%%caar" :: "r"(p));
asm volatile ("movec %0,%%cacr" :: "r"(cacr));
p += CACHELINE; p += CACHELINE;
} while ((l -= CACHELINE) > 0); } while ((l -= CACHELINE) > 0);
asm volatile ("sync"); m68k_nop();
p = (char *)address - off;
do {
asm volatile ("icbi 0,%0" :: "r"(p));
p += CACHELINE;
} while ((len -= CACHELINE) > 0);
asm volatile ("sync");
isync();
} }
@@ -99,10 +90,9 @@ void
arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages) arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)
{ {
int i; int i;
m68k_nop(); m68k_nop();
for (i = 0; i < num_pages; i++) { for (i = 0; i < num_pages; i++) {
asm volatile("tlbie %0" :: "r" (pages[i]));
pflush(pages[i]); pflush(pages[i]);
m68k_nop(); m68k_nop();
} }
@@ -114,7 +104,7 @@ void
arch_cpu_global_TLB_invalidate(void) arch_cpu_global_TLB_invalidate(void)
{ {
m68k_nop(); m68k_nop();
pflush(); pflusha();
m68k_nop(); m68k_nop();
} }
@@ -122,6 +112,7 @@ arch_cpu_global_TLB_invalidate(void)
void void
arch_cpu_user_TLB_invalidate(void) arch_cpu_user_TLB_invalidate(void)
{ {
// pflushfd ?
arch_cpu_global_TLB_invalidate(); arch_cpu_global_TLB_invalidate();
} }