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kernel/arm: add memory barriers for page table ops

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Introduce memory barriers according to ARMARM,
section G.5.3 TLB maintenance operations and barriers

Sequence for mapping memory in (both L1 and L2):
* DSB
* Invalidate i-cache (TODO)
* Insert new entry in page directory / page table
* DSB
* ISB

Sequence for mapping memory out:
* Remove page table entry
* DSB
* Invalidate TLB entry
* DSB
* ISB

Sequence for updating a page table entry:
* Update page table entry
* DSB
* Invalidate TLB entry
* Invalidate branch predictor (TODO)
* DSB
* ISB

Note: i-cache invalidation and branch predictor invalidation is
not implemented yet as this commit focuses on implementing memory
barriers.

Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Fredrik Holmqvist <[email protected]>
This commit is contained in:
David Karoly
2022-04-28 19:57:49 +00:00
committed by waddlesplash
parent cf5f513b3b
commit 83f755b5d8
3 changed files with 49 additions and 26 deletions
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headers/private/kernel/arch/arm/arch_cpu.h
+1 -14
View File
@@ -11,23 +11,9 @@
// TODO: Could be 32-bits sometimes?
#if __ARM_ARCH__ <= 5
#define isb() __asm__ __volatile__("" : : : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("" : : : "memory")
#elif __ARM_ARCH__ == 6
#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
: : "r" (0) : "memory")
#else /* ARMv7+ */
#define isb() __asm__ __volatile__("isb" : : : "memory")
#define dsb() __asm__ __volatile__("dsb" : : : "memory")
#define dmb() __asm__ __volatile__("dmb" : : : "memory")
#endif
#define set_ac()
#define clear_ac()
@@ -98,6 +84,7 @@ extern addr_t arm_get_fp(void);
extern int mmu_read_c1(void);
extern int mmu_write_c1(int val);
void arch_cpu_invalidate_TLB_page(addr_t page);
static inline void
arch_cpu_pause(void)