From 845faf5e8dd948ae8fb3471c4df019b099a75eca Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Mon, 4 Jul 2005 15:17:07 +0000 Subject: [PATCH] added some comments about the NV18 speedfix and resetting registers on NV28. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13424 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index 5bcbe14ed7..c46ea6f5b6 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -127,6 +127,17 @@ status_t nv_acc_init_dma() NV_REG32(NV32_PWRUPCTRL) = 0x13111111; /* don't try this on NV20 and later.. */ + /* note: + * the specific register that's responsible for the speedfix on NV18 is + * $00400ed8: bit 6 needs to be zero for fastest rendering (confirmed). */ + /* note also: + * on NV28 the following ranges could be reset (confirmed): + * $00400000 upto/incl. $004002fc; + * $00400400 upto/incl. $004017fc; + * $0040180c upto/incl. $00401948; + * $00401994 upto/incl. $00401a80; + * $00401a94 upto/incl. $00401ffc. + * The intermediate ranges hang the engine upon resetting. */ if (si->ps.card_arch < NV20A) { /* actively reset the PGRAPH registerset (acceleration engine) */