From 870017dedcf87e0fee4d15eaa08b4b45c72822bf Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 13 Sep 2005 08:49:45 +0000 Subject: [PATCH] modified PLL programming a bit to prevent unknown refresh during driver init. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14175 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/via/engine/dac.c | 14 ++++++++++++- src/add-ons/accelerants/via/engine/general.c | 21 +------------------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/add-ons/accelerants/via/engine/dac.c b/src/add-ons/accelerants/via/engine/dac.c index c06b624af5..9d73604068 100644 --- a/src/add-ons/accelerants/via/engine/dac.c +++ b/src/add-ons/accelerants/via/engine/dac.c @@ -181,7 +181,10 @@ status_t eng_dac_set_pix_pll(display_mode target) return result; } - /*reprogram (disable,select,wait for stability,enable)*/ + /* reset primary pixelPLL */ + SEQW(PLL_RESET, ((SEQR(PLL_RESET)) | 0x02)); + snooze(1000); + SEQW(PLL_RESET, ((SEQR(PLL_RESET)) & ~0x02)); /* program new frequency */ if (si->ps.card_arch != K8M800) @@ -198,6 +201,15 @@ status_t eng_dac_set_pix_pll(display_mode target) SEQW(PPLL_P_OTH, (p & 0x03)); } + /* reset primary pixelPLL (playing it safe) */ + SEQW(PLL_RESET, ((SEQR(PLL_RESET)) | 0x02)); + snooze(1000); + SEQW(PLL_RESET, ((SEQR(PLL_RESET)) & ~0x02)); + + /* now select pixelclock source D (the above custom VIA programmable PLL) */ + snooze(1000); + ENG_REG8(RG8_MISCW) = 0xcf; + /* Wait for the PIXPLL frequency to lock until timeout occurs */ //fixme: do VIA cards have a LOCK indication bit?? /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) diff --git a/src/add-ons/accelerants/via/engine/general.c b/src/add-ons/accelerants/via/engine/general.c index b91855692f..4e37c2d83f 100644 --- a/src/add-ons/accelerants/via/engine/general.c +++ b/src/add-ons/accelerants/via/engine/general.c @@ -90,7 +90,7 @@ status_t eng_general_powerup() { status_t status; - LOG(1,("POWERUP: Haiku VIA Accelerant 0.09 running.\n")); + LOG(1,("POWERUP: Haiku VIA Accelerant 0.10 running.\n")); /* preset no laptop */ si->ps.laptop = false; @@ -452,8 +452,6 @@ status_t eng_general_head_select(bool cross) * Should work from VGA BIOS POST init state. */ static status_t eng_general_bios_to_powergraphics() { - display_mode dummy; - /* let acc engine make power off/power on cycle to start 'fresh' */ // ENG_REG32(RG32_PWRUPCTRL) = 0x13110011; snooze(1000); @@ -529,23 +527,6 @@ static status_t eng_general_bios_to_powergraphics() /* setup sequencer clocking mode */ SEQW(CLKMODE, 0x21); - /* playing it safe (I hope): */ - /* reset primary pixelPLL */ - SEQW(PLL_RESET, ((SEQR(PLL_RESET)) | 0x02)); - snooze(1000); - SEQW(PLL_RESET, ((SEQR(PLL_RESET)) & ~0x02)); - /* set some valid pixelclock PLL speed (using 40Mhz) */ - dummy.timing.pixel_clock = 40000; - head1_set_pix_pll(dummy); - /* reset primary pixelPLL */ - SEQW(PLL_RESET, ((SEQR(PLL_RESET)) | 0x02)); - snooze(1000); - SEQW(PLL_RESET, ((SEQR(PLL_RESET)) & ~0x02)); - - /* now select pixelclock source D (the above custom VIA programmable PLL) */ - snooze(1000); - ENG_REG8(RG8_MISCW) = 0xcf; - /* setup AGP: * Note: * This may only be done when no transfers are in progress on the bus, so now