From 8841d8bcd10e4d7c965bf717de349b07c9df7d6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Axel=20D=C3=B6rfler?= Date: Thu, 1 Mar 2007 09:00:49 +0000 Subject: [PATCH] First of a set of patches by Euan Kirkhope: * Headers updated * PLL errata workarounds * Radeon asic type overhaul (consolidated) * Device IDs Updated. * support for X-series devices with legacy bios type * minor tidy ups / compiler warnings (casts) git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20271 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- headers/private/graphics/radeon/2d_regs.h | 2 +- .../private/graphics/radeon/buscntrl_regs.h | 2 +- headers/private/graphics/radeon/config_regs.h | 11 +- headers/private/graphics/radeon/fp_regs.h | 8 + .../private/graphics/radeon/memcntrl_regs.h | 8 +- .../private/graphics/radeon/overlay_regs.h | 4 +- headers/private/graphics/radeon/pll_access.h | 9 +- headers/private/graphics/radeon/pll_regs.h | 71 ++- .../graphics/radeon/radeon_interface.h | 74 ++- headers/private/graphics/radeon/version.h | 2 +- .../accelerants/radeon/ProposeDisplayMode.c | 2 + .../accelerants/radeon/SetDisplayMode.c | 4 + src/add-ons/accelerants/radeon/crtc.c | 1 + src/add-ons/accelerants/radeon/dpms.c | 5 +- .../accelerants/radeon/driver_wrapper.c | 3 + src/add-ons/accelerants/radeon/flat_panel.c | 6 +- .../accelerants/radeon/internal_tv_out.c | 3 +- .../accelerants/radeon/monitor_detection.c | 41 +- .../accelerants/radeon/monitor_routing.c | 98 +--- .../accelerants/radeon/overlay_management.c | 3 +- src/add-ons/accelerants/radeon/palette.c | 2 +- src/add-ons/accelerants/radeon/pll.c | 2 + .../accelerants/radeon/radeon_accelerant.h | 5 +- src/add-ons/accelerants/radeon/set_mode.h | 34 +- .../kernel/drivers/graphics/radeon/CP_setup.c | 45 +- .../kernel/drivers/graphics/radeon/bios.c | 4 +- .../kernel/drivers/graphics/radeon/detect.c | 509 +++++++++++++----- .../kernel/drivers/graphics/radeon/driver.c | 3 + .../kernel/drivers/graphics/radeon/init.c | 21 +- .../drivers/graphics/radeon/mem_controller.c | 3 +- .../drivers/graphics/radeon/pll_access.c | 71 ++- .../drivers/graphics/radeon/radeon_driver.h | 6 +- 32 files changed, 695 insertions(+), 367 deletions(-) diff --git a/headers/private/graphics/radeon/2d_regs.h b/headers/private/graphics/radeon/2d_regs.h index c818e743ab..6ccecbb759 100644 --- a/headers/private/graphics/radeon/2d_regs.h +++ b/headers/private/graphics/radeon/2d_regs.h @@ -183,7 +183,7 @@ #define RADEON_DST_LINE_START 0x1600 #define RADEON_DST_LINE_END 0x1604 #define RADEON_DST_LINE_PATCOUNT 0x1608 - +# define RADEON_BRES_CNTL_SHIFT 8 #define RADEON_DEFAULT_OFFSET 0x16e0 #define RADEON_DEFAULT_PITCH 0x16e4 diff --git a/headers/private/graphics/radeon/buscntrl_regs.h b/headers/private/graphics/radeon/buscntrl_regs.h index e381a234d5..da10292981 100644 --- a/headers/private/graphics/radeon/buscntrl_regs.h +++ b/headers/private/graphics/radeon/buscntrl_regs.h @@ -56,6 +56,6 @@ #define RADEON_HOST_PATH_CNTL 0x0130 # define RADEON_HDP_SOFT_RESET (1 << 26) - +# define RADEON_HDP_APER_CNTL (1 << 23) #endif diff --git a/headers/private/graphics/radeon/config_regs.h b/headers/private/graphics/radeon/config_regs.h index 9ddfca078a..db22ec6c6e 100644 --- a/headers/private/graphics/radeon/config_regs.h +++ b/headers/private/graphics/radeon/config_regs.h @@ -11,9 +11,16 @@ #define _CONFIG_REGS_H // mmio registers +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 + #define RADEON_CONFIG_CNTL 0x00e0 -#define RADEON_CFG_ATI_REV_ID_SHIFT 16 -#define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +# define RADEON_CFG_ATI_REV_A11 (0 << 16) +# define RADEON_CFG_ATI_REV_A12 (1 << 16) +# define RADEON_CFG_ATI_REV_A13 (2 << 16) +# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CFG_ATI_REV_ID_SHIFT 16 #define RADEON_CONFIG_MEMSIZE 0x00f8 # define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000 diff --git a/headers/private/graphics/radeon/fp_regs.h b/headers/private/graphics/radeon/fp_regs.h index 57c5e72f31..c3c17d932f 100644 --- a/headers/private/graphics/radeon/fp_regs.h +++ b/headers/private/graphics/radeon/fp_regs.h @@ -108,5 +108,13 @@ #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c #endif diff --git a/headers/private/graphics/radeon/memcntrl_regs.h b/headers/private/graphics/radeon/memcntrl_regs.h index 337699f3e4..096ae5688b 100644 --- a/headers/private/graphics/radeon/memcntrl_regs.h +++ b/headers/private/graphics/radeon/memcntrl_regs.h @@ -12,7 +12,11 @@ #define RADEON_AGP_BASE 0x0170 #define RADEON_MEM_CNTL 0x0140 - +# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +# define RADEON_MEM_USE_B_CH_ONLY (1<<1) +# define RV100_HALF_MODE (1<<3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1<<2) #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_MEM_INIT_LAT_TIMER 0x0154 @@ -20,7 +24,7 @@ # define RADEON_MEM_CFG_TYPE_MASK (1 << 30) # define RADEON_MEM_CFG_SDR (0 << 30) # define RADEON_MEM_CFG_DDR (1 << 30) -#define RADEON_GC_NB_TOM 0x015c +#define RADEON_NB_TOM 0x015c #define RADEON_DISPLAY_BASE_ADDRESS 0x023c #define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c #define RADEON_OV0_BASE_ADDRESS 0x043c diff --git a/headers/private/graphics/radeon/overlay_regs.h b/headers/private/graphics/radeon/overlay_regs.h index 4db9bdd229..96b5f3c93d 100644 --- a/headers/private/graphics/radeon/overlay_regs.h +++ b/headers/private/graphics/radeon/overlay_regs.h @@ -40,14 +40,14 @@ # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L # define R200_SCALER_TEMPORAL_DEINT 0x00002000L # define RADEON_SCALER_CRTC_SEL 0x00004000L -//# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L # define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L # define RADEON_SCALER_INT_EMU 0x20000000L # define RADEON_SCALER_ENABLE 0x40000000L # define RADEON_SCALER_SOFT_RESET 0x80000000L -# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L #define RADEON_OV0_V_INC 0x0424 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L diff --git a/headers/private/graphics/radeon/pll_access.h b/headers/private/graphics/radeon/pll_access.h index 3caee8a1b1..27b4e5fa25 100644 --- a/headers/private/graphics/radeon/pll_access.h +++ b/headers/private/graphics/radeon/pll_access.h @@ -13,10 +13,15 @@ #include "mmio.h" -// r300: to be called after each CLOCK_CNTL_INDEX access; +// to be called after each CLOCK_CNTL_INDEX access; // all functions declared in this header take care of that // (hardware bug fix suggested by XFree86) -void R300_PLLFix( vuint8 *regs, radeon_type asic ); +void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ); + +// to be called after each CLOCK_CNTL_DATA access; +// all functions declared in this header take care of that +// (hardware bug fix suggested by XFree86) +void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ); // in general: // - the PLL is connected via special port diff --git a/headers/private/graphics/radeon/pll_regs.h b/headers/private/graphics/radeon/pll_regs.h index a59d19ea19..4f1e98b445 100644 --- a/headers/private/graphics/radeon/pll_regs.h +++ b/headers/private/graphics/radeon/pll_regs.h @@ -19,7 +19,18 @@ # define RADEON_PLL_DIV_SEL_DIV1 (1 << 8) # define RADEON_PLL_DIV_SEL_DIV2 (2 << 8) # define RADEON_PLL_DIV_SEL_DIV3 (3 << 8) +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +# define RADEON_SCLK_DYN_START_CNTL (1 << 15) +// PLL Power management registers +#define RADEON_CLK_PWRMGT_CNTL 0x0014 +# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) +# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) +# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 +# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) +# define RADEON_DYN_STOP_MODE_MASK (7 << 21) +#define RADEON_PLL_PWRMGT_CNTL 0x0015 +# define RADEON_TCL_BYPASS_DISABLE (1 << 20) // indirect PLL registers #define RADEON_CLK_PIN_CNTL 0x0001 @@ -55,12 +66,46 @@ # define RADEON_ECP_DIV_VCLK_2 (1 << 8) # define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT 16 # define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_MASK (3 << 16) +# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + #define RADEON_HTOTAL_CNTL 0x0009 -#define RADEON_SCLK_CNTL 0x000d +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_SCLK_SRC_SEL_MASK 0x0007 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 -#define RADEON_SCLK_MORE_CNTL 0x0035 +# define RADEON_SCLK_FORCE_DISP2 (1<<15) +# define RADEON_SCLK_FORCE_CP (1<<16) +# define RADEON_SCLK_FORCE_HDP (1<<17) +# define RADEON_SCLK_FORCE_DISP1 (1<<18) +# define RADEON_SCLK_FORCE_TOP (1<<19) +# define RADEON_SCLK_FORCE_E2 (1<<20) +# define RADEON_SCLK_FORCE_SE (1<<21) +# define RADEON_SCLK_FORCE_IDCT (1<<22) +# define RADEON_SCLK_FORCE_VIP (1<<23) +# define RADEON_SCLK_FORCE_RE (1<<24) +# define RADEON_SCLK_FORCE_PB (1<<25) +# define RADEON_SCLK_FORCE_TAM (1<<26) +# define RADEON_SCLK_FORCE_TDM (1<<27) +# define RADEON_SCLK_FORCE_RB (1<<28) +# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) +# define RADEON_SCLK_FORCE_SUBPIC (1<<30) +# define RADEON_SCLK_FORCE_OV0 (1<<31) +# define R300_SCLK_FORCE_VAP (1<<21) +# define R300_SCLK_FORCE_SR (1<<25) +# define R300_SCLK_FORCE_PX (1<<26) +# define R300_SCLK_FORCE_TX (1<<27) +# define R300_SCLK_FORCE_US (1<<28) +# define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +# define R300_SCLK_FORCE_TCL (1<<13) +# define R300_SCLK_FORCE_CBA (1<<14) +# define R300_SCLK_FORCE_GA (1<<15) +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 # define RADEON_SCLK_MORE_FORCEON 0x0700 #define RADEON_MCLK_CNTL 0x0012 # define RADEON_FORCEON_MCLKA (1 << 16) @@ -69,6 +114,13 @@ # define RADEON_FORCEON_YCLKB (1 << 19) # define RADEON_FORCEON_MC (1 << 20) # define RADEON_FORCEON_AIC (1 << 21) +# define R300_DISABLE_MC_MCLKA (1 << 21) +# define R300_DISABLE_MC_MCLKB (1 << 21) +#define RADEON_MCLK_MISC 0x001f /* PLL */ +# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12) +# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) +# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_P2PLL_CNTL 0x002a # define RADEON_P2PLL_RESET (1 << 0) # define RADEON_P2PLL_SLEEP (1 << 1) @@ -90,8 +142,23 @@ # define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8) # define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8) # define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8) +# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +# define R300_DVOCLK_ALWAYS_ONb (1 << 10) +# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) +# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) #define RADEON_HTOTAL2_CNTL 0x002e diff --git a/headers/private/graphics/radeon/radeon_interface.h b/headers/private/graphics/radeon/radeon_interface.h index edc78da171..e3edf7115b 100644 --- a/headers/private/graphics/radeon/radeon_interface.h +++ b/headers/private/graphics/radeon/radeon_interface.h @@ -17,7 +17,7 @@ #include #include "video_overlay.h" #include "benaphore.h" - +#include "ddc.h" // magic code for ioctls #define RADEON_PRIVATE_DATA_MAGIC 'TKRA' @@ -94,31 +94,46 @@ typedef enum { // type of ASIC typedef enum { rt_r100, // original Radeon - rt_ve, // original VE version - rt_m6, // original mobile Radeon + rt_rv100, // original VE version rt_rs100, // IGP 320M rt_rv200, // Radeon 7500 - rt_m7, // mobile Radeon 7500 rt_rs200, // IGP 330M/340M/350M rt_r200, // Radeon 8500/9100 rt_rv250, // Radeon 9000 - rt_m9, // mobile Radeon 9000 - rt_rv280, // Radeon 9200 - rt_m9plus, // mobile Radeon 9200 - - // from here on, r300 and up must be located as ATI modified the PLL - // with r300 and the code only tests for >= rt_r300 + rt_rs300, // IGP rs300 + rt_rv280, // Radeon 9200 + // from here on, r300 and up must be located as ATI modified the + // PLL design and the PLL code only tests for >= rt_r300 rt_r300, // Radeon 9700 - rt_r300_4p, // Radeon 9500 - rt_rv350, // Radeon 9600 - rt_m10, // mobile Radeon 9600 - rt_rv360, // Radeon 9600 rt_r350, // Radeon 9800 - rt_r360, // Radeon 9800 - rt_m11 // Radeon 9700 Mobility + rt_rv350, // Radeon 9600 + rt_rv380, // X600 + rt_r420 // X800 } radeon_type; +#define IS_RV100_VARIANT ( \ + (ai->si->asic == rt_rv100) || \ + (ai->si->asic == rt_rv200) || \ + (ai->si->asic == rt_rs100) || \ + (ai->si->asic == rt_rs200) || \ + (ai->si->asic == rt_rv250) || \ + (ai->si->asic == rt_rv280) || \ + (ai->si->asic == rt_rs300)) +#define IS_DI_R300_VARIANT ( \ + (di->asic == rt_r300) || \ + (di->asic == rt_r350) || \ + (di->asic == rt_rv350) || \ + (di->asic == rt_rv380) || \ + (di->asic == rt_r420)) + +#define IS_R300_VARIANT ( \ + (ai->si->asic == rt_r300) || \ + (ai->si->asic == rt_r350) || \ + (ai->si->asic == rt_rv350) || \ + (ai->si->asic == rt_rv380) || \ + (ai->si->asic == rt_r420)) + // TV standard typedef enum { ts_off, @@ -390,22 +405,25 @@ typedef struct { benaphore lock; // engine lock } engine; - uint16 vendor_id; // PCI vendor id - uint16 device_id; // PCI device id - uint8 revision; // PCI device revision + uint16 vendor_id; // PCI vendor id + uint16 device_id; // PCI device id + uint8 revision; // PCI device revision - //bool has_crtc2; // has second CRTC - radeon_type asic; // ASIC version - bool is_mobility; // mobility version - tv_chip_type tv_chip; // type of TV-Out encoder - bool new_pll; // r300 style PLL - - uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable) + //bool has_crtc2; // has second CRTC + radeon_type asic; // ASIC version + bool is_mobility; // mobility version + bool is_igp; // might need to know if it's an integrated chip + bool is_atombios; + tv_chip_type tv_chip; // type of TV-Out encoder + bool new_pll; // r300 style PLL + bool has_no_i2c; // I2C is broken + uint16 panel_pwr_delay;// delay for LCD backlight to stabilise + uint8 theatre_channel;// VIP channel of Rage Theatre (if applicable) general_pll_info pll; - area_id regs_area; // area of memory mapped registers - area_id ROM_area; // area of ROM + area_id regs_area; // area of memory mapped registers + area_id ROM_area; // area of ROM //area_id fb_area; // area of frame buffer void *framebuffer_pci; // physical address of frame buffer (aka local memory) // this is a hack needed by BeOS diff --git a/headers/private/graphics/radeon/version.h b/headers/private/graphics/radeon/version.h index 23455a0711..fe74380493 100644 --- a/headers/private/graphics/radeon/version.h +++ b/headers/private/graphics/radeon/version.h @@ -8,4 +8,4 @@ */ // current version -#define RADEON_DRIVER_VERSION "Version: 5.1.0.1" +#define RADEON_DRIVER_VERSION "Version: 5.1.1.1" diff --git a/src/add-ons/accelerants/radeon/ProposeDisplayMode.c b/src/add-ons/accelerants/radeon/ProposeDisplayMode.c index 2026c0a56e..2efe86b80d 100644 --- a/src/add-ons/accelerants/radeon/ProposeDisplayMode.c +++ b/src/add-ons/accelerants/radeon/ProposeDisplayMode.c @@ -62,6 +62,8 @@ static const display_mode base_mode_list[] = { { { 108000, 1280, 1376, 1488, 1800, 960, 961, 964, 1000, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X960X8.Z1) - not in Be's list */ { { 148500, 1280, 1344, 1504, 1728, 960, 961, 964, 1011, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1280X960X8.Z1) - not in Be's list */ +{ { 147100, 1680, 1784, 1968, 2256, 1050, 1051, 1054, 1087, T_POSITIVE_SYNC}, B_CMAP8, 1680, 1050, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1680X1050) */ + { { 108000, 1280, 1328, 1440, 1688, 1024, 1025, 1028, 1066, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X1024X8.Z1) */ { { 135000, 1280, 1296, 1440, 1688, 1024, 1025, 1028, 1066, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1280X1024X8.Z1) */ { { 157500, 1280, 1344, 1504, 1728, 1024, 1025, 1028, 1072, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1280X1024X8.Z1) */ diff --git a/src/add-ons/accelerants/radeon/SetDisplayMode.c b/src/add-ons/accelerants/radeon/SetDisplayMode.c index 84e1777f9c..b41f52200b 100644 --- a/src/add-ons/accelerants/radeon/SetDisplayMode.c +++ b/src/add-ons/accelerants/radeon/SetDisplayMode.c @@ -20,11 +20,15 @@ #include "overlay_regs.h" #include "rbbm_regs.h" #include "dac_regs.h" +#include "fp_regs.h" +#include "gpiopad_regs.h" #include "set_mode.h" #include +void Radeon_SetMode( + accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params ); // round virtual width up to next valid size uint32 Radeon_RoundVWidth( diff --git a/src/add-ons/accelerants/radeon/crtc.c b/src/add-ons/accelerants/radeon/crtc.c index 0f01669c1e..2718a55a25 100644 --- a/src/add-ons/accelerants/radeon/crtc.c +++ b/src/add-ons/accelerants/radeon/crtc.c @@ -12,6 +12,7 @@ #include "crtc_regs.h" #include "GlobalData.h" #include "set_mode.h" +#include "generic.h" // hammer CRTC registers diff --git a/src/add-ons/accelerants/radeon/dpms.c b/src/add-ons/accelerants/radeon/dpms.c index 91b78420d7..64b8c3816c 100644 --- a/src/add-ons/accelerants/radeon/dpms.c +++ b/src/add-ons/accelerants/radeon/dpms.c @@ -16,6 +16,7 @@ #include "tv_out_regs.h" #include "theatre_regs.h" #include "GlobalData.h" +#include "generic.h" // public function: set DPMS mode @@ -78,13 +79,13 @@ static void Radeon_SetDPMS_LVDS( accelerator_info *ai, int mode ) old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL); // ASIC bug: when LVDS_ON is reset, LVDS_ALWAYS_ON must be zero - if( ai->si->is_mobility || ai->si->asic == rt_rs100 ) + if( ai->si->is_mobility || ai->si->is_igp ) Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb ); OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_DISPLAY_DIS, ~(RADEON_LVDS_DISPLAY_DIS | RADEON_LVDS_BLON | RADEON_LVDS_ON) ); - if( ai->si->is_mobility || ai->si->asic == rt_rs100 ) + if( ai->si->is_mobility || ai->si->is_igp ) Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl ); break; } diff --git a/src/add-ons/accelerants/radeon/driver_wrapper.c b/src/add-ons/accelerants/radeon/driver_wrapper.c index c50a742fa5..c89eebc560 100644 --- a/src/add-ons/accelerants/radeon/driver_wrapper.c +++ b/src/add-ons/accelerants/radeon/driver_wrapper.c @@ -9,6 +9,9 @@ #include "radeon_accelerant.h" #include +#include "rbbm_regs.h" +#include "mmio.h" + status_t Radeon_WaitForIdle( accelerator_info *ai, bool keep_lock ) { diff --git a/src/add-ons/accelerants/radeon/flat_panel.c b/src/add-ons/accelerants/radeon/flat_panel.c index e09009ea69..d9494638f2 100644 --- a/src/add-ons/accelerants/radeon/flat_panel.c +++ b/src/add-ons/accelerants/radeon/flat_panel.c @@ -13,6 +13,8 @@ #include "memcntrl_regs.h" #include "utils.h" #include "set_mode.h" +#include "pll_regs.h" +#include "pll_access.h" void Radeon_ReadRMXRegisters( @@ -125,7 +127,7 @@ void Radeon_ReadFPRegisters( values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ); values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ); - SHOW_FLOW( 2, "before: fp_gen_cntl=%lx, horz=%lx, vert=%lx, lvds_gen_cntl=%lx", + SHOW_FLOW( 2, "before: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx", values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch, values->lvds_gen_cntl ); } @@ -185,7 +187,7 @@ void Radeon_CalcFPRegisters( values->fp2_gen_cntl |= RADEON_FP2_DV0_EN; } - SHOW_FLOW( 2, "after: fp_gen_cntl=%lx, horz=%lx, vert=%lx, lvds_gen_cntl=%lx", + SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx", values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch, values->lvds_gen_cntl ); } diff --git a/src/add-ons/accelerants/radeon/internal_tv_out.c b/src/add-ons/accelerants/radeon/internal_tv_out.c index 4e962a3fe2..9ff49ecd27 100644 --- a/src/add-ons/accelerants/radeon/internal_tv_out.c +++ b/src/add-ons/accelerants/radeon/internal_tv_out.c @@ -122,6 +122,7 @@ static void writePLLRegList( // read timing FIFO +#if 0 static uint32 Radeon_InternalTVOutReadFIFO( accelerator_info *ai, uint16 addr ) { @@ -151,7 +152,7 @@ static uint32 Radeon_InternalTVOutReadFIFO( return res; } - +#endif // write to timing FIFO static void Radeon_InternalTVOutWriteFIFO( diff --git a/src/add-ons/accelerants/radeon/monitor_detection.c b/src/add-ons/accelerants/radeon/monitor_detection.c index 8b11525d8a..6c4253275b 100644 --- a/src/add-ons/accelerants/radeon/monitor_detection.c +++ b/src/add-ons/accelerants/radeon/monitor_detection.c @@ -16,11 +16,13 @@ #include "config_regs.h" #include "ddc_regs.h" #include "gpiopad_regs.h" +#include "fp_regs.h" #include "pll_access.h" #include "theatre_regs.h" #include "set_mode.h" #include "ddc.h" #include +#include "string.h" typedef struct { accelerator_info *ai; @@ -294,34 +296,31 @@ static bool Radeon_DetectTVCRT_R300( accelerator_info *ai ) // check whether there is a CRT connected to TV-DAC static bool Radeon_DetectTVCRT( accelerator_info *ai ) { + if (ai->si->is_mobility) + return dd_none; + switch( ai->si->asic ) { case rt_r100: - case rt_m6: - case rt_m7: - case rt_m9: - case rt_m9plus: - case rt_m10: // original Radeons have pure DVI only and mobility chips // have no DVI connector // TBD: can they have a docking station for CRT on TV-DAC? return dd_none; - case rt_ve: + case rt_rv100: case rt_rv200: case rt_rv250: case rt_rv280: // IGP is guessed case rt_rs100: case rt_rs200: + case rt_rs300: return Radeon_DetectTVCRT_RV200( ai ); case rt_r300: - case rt_r300_4p: - case rt_rv350: - case rt_rv360: case rt_r350: - case rt_r360: - case rt_m11: + case rt_rv350: + case rt_rv380: + case rt_r420: return Radeon_DetectTVCRT_R300( ai ); case rt_r200: @@ -662,27 +661,21 @@ static display_device_e Radeon_DetectTV( accelerator_info *ai, bool tv_crt_found case rt_r200: return Radeon_DetectTV_Theatre( ai ); - case rt_ve: - case rt_m6: + case rt_rv100: case rt_rv200: - case rt_m7: case rt_rv250: - case rt_m9: case rt_rv280: - case rt_m9plus: // IGP method is guessed case rt_rs100: case rt_rs200: + case rt_rs300: return Radeon_DetectTV_RV200( ai, tv_crt_found ); case rt_r300: - case rt_r300_4p: - case rt_rv350: - case rt_rv360: - case rt_m10: - case rt_m11: case rt_r350: - case rt_r360: + case rt_rv350: + case rt_rv380: + case rt_r420: return Radeon_DetectTV_R300( ai ); } @@ -812,8 +805,8 @@ static status_t Radeon_StoreFPEDID( accelerator_info *ai, const edid1_info *edid fp_info *fp = &ai->si->flatpanels[0]; uint32 max_hsize, max_vsize; - SHOW_FLOW0( 2, "EDID data read from DVI port via DDC2:" ); - edid_dump( edid ); + //SHOW_FLOW0( 2, "EDID data read from DVI port via DDC2:" ); + //edid_dump( edid ); // find detailed timing with maximum resolution max_hsize = max_vsize = 0; diff --git a/src/add-ons/accelerants/radeon/monitor_routing.c b/src/add-ons/accelerants/radeon/monitor_routing.c index 7b21753bb6..7e32dbb06c 100644 --- a/src/add-ons/accelerants/radeon/monitor_routing.c +++ b/src/add-ons/accelerants/radeon/monitor_routing.c @@ -37,16 +37,13 @@ void Radeon_ReadMonitorRoutingRegs( values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL ); switch( ai->si->asic ) { - case rt_ve: - case rt_m6: + case rt_rv100: case rt_rv200: - case rt_m7: case rt_rv250: - case rt_m9: case rt_rv280: - case rt_m9plus: case rt_rs100: case rt_rs200: + case rt_rs300: values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG ); break; @@ -55,13 +52,10 @@ void Radeon_ReadMonitorRoutingRegs( break; case rt_r300: - case rt_r300_4p: case rt_rv350: - case rt_m10: - case rt_rv360: case rt_r350: - case rt_r360: - case rt_m11: + case rt_rv380: + case rt_r420: values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A ); break; @@ -137,29 +131,23 @@ void Radeon_CalcMonitorRouting( values->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; switch( ai->si->asic ) { - case rt_ve: - case rt_m6: - case rt_rv200: - case rt_m7: + case rt_rv100: + case rt_rv200: case rt_rv250: - case rt_m9: case rt_rv280: - case rt_m9plus: case rt_rs100: case rt_rs200: + case rt_rs300: values->dac_cntl2 &= ~RADEON_DAC_CLK_SEL_MASK; values->dac_cntl2 |= crtc_idx == 0 ? 0 : RADEON_DAC_CLK_SEL_CRTC2; break; case rt_r200: case rt_r300: - case rt_r300_4p: case rt_rv350: - case rt_m10: - case rt_m11: - case rt_rv360: case rt_r350: - case rt_r360: + case rt_rv380: + case rt_r420: values->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK; values->disp_output_cntl |= (crtc_idx == 0 ? 0 : RADEON_DISP_DAC_SOURCE_CRTC2); @@ -203,22 +191,9 @@ void Radeon_CalcMonitorRouting( (2 << RADEON_TV_DAC_CNTL_DACADJ_SHIFT); // at least r300 needs magic bit set to switch between TV-CRT and TV-Out - switch( ai->si->asic ) { - case rt_r200: - case rt_r300: - case rt_r300_4p: - case rt_rv350: - case rt_m10: - case rt_m11: - case rt_rv360: - case rt_r350: - case rt_r360: + if (IS_R300_VARIANT) values->gpiopad_a |= 1; - break; - default: - ; - } - + } else if( (controlled_devices & dd_tv_crt) != 0 ) { values->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; } @@ -239,21 +214,9 @@ void Radeon_CalcMonitorRouting( values->dac_cntl2 |= RADEON_DAC2_CLK_SEL_TV; // at least r300 needs magic bit set to switch between TV-CRT and TV-Out - switch( ai->si->asic ) { - case rt_r200: - case rt_r300: - case rt_r300_4p: - case rt_rv350: - case rt_rv360: - case rt_m10: - case rt_m11: - case rt_r350: - case rt_r360: + if(IS_R300_VARIANT) values->gpiopad_a &= ~1; - break; - default: - ; - } + // the TV-DAC itself is under control of the TV-Out code values->skip_tv_dac = true; @@ -330,17 +293,14 @@ void Radeon_CalcMonitorRouting( int crtc_idx = (display_devices[1] & (dd_tv_crt | dd_ctv | dd_stv)) != 0; switch( ai->si->asic ) { - case rt_ve: - case rt_m6: + case rt_rv100: case rt_rv200: - case rt_m7: case rt_rv250: - case rt_m9: case rt_rv280: - case rt_m9plus: case rt_rs100: case rt_rs200: - values->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; + case rt_rs300: + values->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; // warning: meaning is wrong way around - 0 means crtc2, 1 means crtc1 values->disp_hw_debug |= crtc_idx == 0 ? RADEON_CRT2_DISP1_SEL : 0; break; @@ -354,13 +314,10 @@ void Radeon_CalcMonitorRouting( break; case rt_r300: - case rt_r300_4p: case rt_rv350: - case rt_m10: - case rt_m11: - case rt_rv360: case rt_r350: - case rt_r360: + case rt_rv380: + case rt_r420: values->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; values->disp_output_cntl |= crtc_idx == 0 ? 0 : RADEON_DISP_TVDAC_SOURCE_CRTC2; @@ -444,7 +401,8 @@ void Radeon_CalcMonitorRouting( case rt_r300: case rt_r350: case rt_rv350: - case rt_m10: + case rt_rv380: + case rt_r420: values->fp2_gen_cntl &= ~RADEON_FP2_SOURCE_SEL_CRTC2; values->fp2_gen_cntl |= crtc_idx == 0 ? 0 : RADEON_FP2_SOURCE_SEL_CRTC2; @@ -470,16 +428,13 @@ void Radeon_ProgramMonitorRouting( OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl ); switch( ai->si->asic ) { - case rt_ve: - case rt_m6: + case rt_rv100: case rt_rv200: - case rt_m7: case rt_rv250: - case rt_m9: case rt_rv280: - case rt_m9plus: case rt_rs100: case rt_rs200: + case rt_rs300: OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug ); break; @@ -488,13 +443,10 @@ void Radeon_ProgramMonitorRouting( break; case rt_r300: - case rt_r300_4p: case rt_rv350: - case rt_m10: - case rt_m11: - case rt_rv360: case rt_r350: - case rt_r360: + case rt_rv380: + case rt_r420: OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 ); break; @@ -589,7 +541,7 @@ void Radeon_ProgramMonitorRouting( // internal version of SetupDefaultMonitorRouting; // input and output are written to local variables -void assignDefaultMonitorRoute( +static void assignDefaultMonitorRoute( accelerator_info *ai, display_device_e display_devices, int whished_num_heads, bool use_laptop_panel, display_device_e *crtc1, display_device_e *crtc2 ) diff --git a/src/add-ons/accelerants/radeon/overlay_management.c b/src/add-ons/accelerants/radeon/overlay_management.c index 2ae3c67f92..6096532a8a 100644 --- a/src/add-ons/accelerants/radeon/overlay_management.c +++ b/src/add-ons/accelerants/radeon/overlay_management.c @@ -14,6 +14,7 @@ #include #include #include "overlay_regs.h" +#include "generic.h" // we could add support of planar modes and YUV modes // but I neither know how planar modes are defined nor @@ -148,7 +149,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER( color_space cs, uint16 width, uin node->mem_handle = am.handle; node->mem_offset = am.offset; buffer->buffer = si->local_mem + am.offset; - buffer->buffer_dma = si->framebuffer_pci + am.offset; + buffer->buffer_dma = (void *) ((unsigned long) si->framebuffer_pci + am.offset); // add to list of overlays node->next = vc->overlay_buffers; diff --git a/src/add-ons/accelerants/radeon/palette.c b/src/add-ons/accelerants/radeon/palette.c index 492b016417..ed8e99a590 100644 --- a/src/add-ons/accelerants/radeon/palette.c +++ b/src/add-ons/accelerants/radeon/palette.c @@ -14,7 +14,7 @@ #include "GlobalData.h" #include "dac_regs.h" #include "CP.h" - +#include "generic.h" // Radeon's DACs share same public registers, this function // selects the DAC you'll talk to diff --git a/src/add-ons/accelerants/radeon/pll.c b/src/add-ons/accelerants/radeon/pll.c index 4eeb767dba..1dc57aeaa5 100644 --- a/src/add-ons/accelerants/radeon/pll.c +++ b/src/add-ons/accelerants/radeon/pll.c @@ -477,6 +477,8 @@ void Radeon_ProgramPLL( OUTREGP( regs, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL_DIV3, ~RADEON_PLL_DIV_SEL_MASK ); + + RADEONPllErrataAfterIndex(regs, asic); if( ai->si->new_pll && crtc_idx == 0 ) { // starting with r300, the reference divider of the first PLL was diff --git a/src/add-ons/accelerants/radeon/radeon_accelerant.h b/src/add-ons/accelerants/radeon/radeon_accelerant.h index b4511a36a9..de54181708 100644 --- a/src/add-ons/accelerants/radeon/radeon_accelerant.h +++ b/src/add-ons/accelerants/radeon/radeon_accelerant.h @@ -78,7 +78,7 @@ extern const size_t vesa_mode_list_count; // SetDisplayMode.c uint32 Radeon_RoundVWidth( int virtual_width, int bpp ); status_t Radeon_MoveDisplay( accelerator_info *ai, uint16 h_display_start, uint16 v_display_start ); - +void Radeon_EnableIRQ( accelerator_info *ai, bool enable ); // multimon.c void Radeon_HideMultiMode( virtual_card *vc, display_mode *mode ); @@ -130,7 +130,7 @@ void Radeon_WriteSettings( virtual_card *vc ); // overlay.c void Radeon_HideOverlay( accelerator_info *ai ); status_t Radeon_UpdateOverlay( accelerator_info *ai ); - +void Radeon_InitOverlay( accelerator_info *ai, int crtc_idx ); // EngineManagement.c void Radeon_Spin( uint32 delay ); @@ -138,6 +138,7 @@ void Radeon_Spin( uint32 delay ); // monitor_detection.c void Radeon_DetectDisplays( accelerator_info *ai ); +bool Radeon_ReadEDID( accelerator_info *ai, uint32 ddc_port, edid1_info *edid ); // palette.c diff --git a/src/add-ons/accelerants/radeon/set_mode.h b/src/add-ons/accelerants/radeon/set_mode.h index ee742dc064..366adbaf43 100644 --- a/src/add-ons/accelerants/radeon/set_mode.h +++ b/src/add-ons/accelerants/radeon/set_mode.h @@ -25,19 +25,19 @@ typedef struct { // TV-timing typedef struct { uint32 freq; // TV sub carrier frequency x12 - uint16 h_total; - uint16 h_sync_len; - uint16 h_genclk_delay; - uint16 h_setup_delay; - uint16 h_active_delay; - uint16 h_active_len; - uint16 v_total; - uint16 v_active_lines; - uint16 v_field_total; - uint16 v_fields; - uint16 f_total; - uint16 frame_size_adjust; - uint32 scale; + uint16 h_total; + uint16 h_sync_len; + uint16 h_genclk_delay; + uint16 h_setup_delay; + uint16 h_active_delay; + uint16 h_active_len; + uint16 v_total; + uint16 v_active_lines; + uint16 v_field_total; + uint16 v_fields; + uint16 f_total; + uint16 frame_size_adjust; + uint32 scale; } tv_timing; @@ -64,7 +64,7 @@ typedef struct { pll_dividers tv_dividers; pll_dividers crt_dividers; - tv_timing timing; + tv_timing timing; } impactv_params; @@ -88,9 +88,9 @@ typedef struct { // pure information uint32 dot_clock_freq; // in 10 kHz - uint32 pll_output_freq;// in 10 kHz - int feedback_div; - int post_div; + uint32 pll_output_freq;// in 10 kHz + int feedback_div; + int post_div; } pll_regs; diff --git a/src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c b/src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c index fe285961dd..6f673a0b63 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c @@ -27,6 +27,8 @@ #include "pll_regs.h" #include "rbbm_regs.h" #include "buscntrl_regs.h" +#include "config_regs.h" +#include "memcntrl_regs.h" #include "utils.h" #include "pll_access.h" @@ -209,28 +211,9 @@ void Radeon_ResetEngine( device_info *di ) Radeon_FlushPixelCache( di ); clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); - R300_PLLFix( di->regs, di->asic ); - - // OUCH! - // XFree disables any kind of automatic power power management - // because of bugs of some ASIC revision (seems like the revisions - // cannot be read out) - // -> this is a very bad idea, especially when it comes to laptops - // I comment it out for now, let's hope noone takes notice - if( di->num_crtc > 1 ) { - Radeon_OUTPLLP( regs, di->asic, RADEON_SCLK_CNTL, - RADEON_CP_MAX_DYN_STOP_LAT | - RADEON_SCLK_FORCEON_MASK, - ~RADEON_DYN_STOP_LAT_MASK ); - -/* if( ai->si->asic == rt_rv200 ) { - Radeon_OUTPLLP( ai, RADEON_SCLK_MORE_CNTL, - RADEON_SCLK_MORE_FORCEON, ~0 ); - }*/ - } - + RADEONPllErrataAfterIndex( regs, di->asic ); // drm has no errata here! mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL ); - + // enable clock of units to be reset Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl | RADEON_FORCEON_MCLKA | @@ -288,7 +271,7 @@ void Radeon_ResetEngine( device_info *di ) OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); - R300_PLLFix( regs, di->asic ); + //R300_PLLFix( regs, di->asic ); Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl ); // reset ring buffer @@ -323,17 +306,13 @@ static void loadMicroEngineRAMData( device_info *di ) switch( di->asic ) { case rt_r300: - case rt_r300_4p: case rt_rv350: - case rt_rv360: - case rt_m11: case rt_r350: - case rt_r360: + case rt_rv380: + case rt_r420: microcode = r300_cp_microcode; break; case rt_r200: - //case rt_rv250: - //case rt_m9: microcode = r200_cp_microcode; break; case rt_rs100: @@ -343,16 +322,6 @@ static void loadMicroEngineRAMData( device_info *di ) Radeon_WaitForIdle( di, false, false ); -/* - // HACK start - Radeon_ResetEngine( di ); - OUTREG( di->regs, 0x30, 0x5133a3a0 ); // bus_cntl - OUTREGP( di->regs, 0xf0c, 0xff00, ~0xff ); // latency - Radeon_WaitForIdle( di, false, false ); - Radeon_ResetEngine( di ); - // HACK end -*/ - OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 ); for ( i = 0 ; i < 256 ; i++ ) { diff --git a/src/add-ons/kernel/drivers/graphics/radeon/bios.c b/src/add-ons/kernel/drivers/graphics/radeon/bios.c index fc1f629645..c671d1e51f 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/bios.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/bios.c @@ -17,8 +17,10 @@ #include "bios_regs.h" #include "config_regs.h" #include "memcntrl_regs.h" +#include "buscntrl_regs.h" #include "fp_regs.h" #include "crtc_regs.h" +#include "ddc_regs.h" #include "radeon_bios.h" #include "utils.h" @@ -483,7 +485,7 @@ static void Radeon_DetectRAM( device_info *di ) else { uint32 tom; - tom = INREG( regs, RADEON_GC_NB_TOM ); + tom = INREG( regs, RADEON_NB_TOM ); di->local_mem_size = ((tom >> 16) + 1 - (tom & 0xffff)) << 16; } diff --git a/src/add-ons/kernel/drivers/graphics/radeon/detect.c b/src/add-ons/kernel/drivers/graphics/radeon/detect.c index 0cff965d70..9209a14e70 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/detect.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/detect.c @@ -26,6 +26,9 @@ #define DEVICE_ID_RADEON_QY 0x5159 #define DEVICE_ID_RADEON_QZ 0x515a +#define DEVICE_ID_RN50_515E 0x515E +#define DEVICE_ID_RN50_5969 0x5969 + // M6 #define DEVICE_ID_RADEON_LY 0x4c59 #define DEVICE_ID_RADEON_LZ 0x4c5a @@ -52,26 +55,28 @@ #define DEVICE_ID_RADEON_Qk 0x516b #define DEVICE_ID_RADEON_BB 0x4242 +#define DEVICE_ID_RADEON_BC 0x4243 // RV250 -#define DEVICE_ID_RADEON_Id 0x4964 -#define DEVICE_ID_RADEON_Ie 0x4965 #define DEVICE_ID_RADEON_If 0x4966 #define DEVICE_ID_RADEON_Ig 0x4967 -// M9 +// M9 (RV250) #define DEVICE_ID_RADEON_Ld 0x4c64 #define DEVICE_ID_RADEON_Le 0x4c65 #define DEVICE_ID_RADEON_Lf 0x4c66 #define DEVICE_ID_RADEON_Lg 0x4c67 -// M9+ -#define DEVICE_ID_RADEON_5c61 0x5c61 - // RV280 -#define DEVICE_ID_RADEON_Zprea 0x5960 +#define DEVICE_ID_RADEON_5960 0x5960 #define DEVICE_ID_RADEON_Za 0x5961 +#define DEVICE_ID_RADEON_Zb 0x5962 // new #define DEVICE_ID_RADEON_Zd 0x5964 +#define DEVICE_ID_RADEON_Ze 0x5965 // new + +// M9+ (RV280) +#define DEVICE_ID_RADEON_5c61 0x5c61 +#define DEVICE_ID_RADEON_5c63 0x5c63 // new // r300 #define DEVICE_ID_RADEON_ND 0x4e44 @@ -79,10 +84,6 @@ #define DEVICE_ID_RADEON_NF 0x4e46 #define DEVICE_ID_RADEON_NG 0x4e47 -// m11 -#define DEVICE_ID_RADEON_NP 0x4e50 // Mobility 9700 -#define DEVICE_ID_RADEON_SE 0x4e52 // Mobility 9700 SE - // r300-4P #define DEVICE_ID_RADEON_AD 0x4144 #define DEVICE_ID_RADEON_AE 0x4145 @@ -92,144 +93,378 @@ // rv350 #define DEVICE_ID_RADEON_AP 0x4150 #define DEVICE_ID_RADEON_AQ 0x4151 -#define DEVICE_ID_RADEON_AS 0x4153 +#define DEVICE_ID_RADEON_AR 0x4152 // RS360 +#define DEVICE_ID_RADEON_AS 0x4153 // RV350 ?? on X.org +#define DEVICE_ID_RADEON_AT 0x4154 // new +#define DEVICE_ID_RADEON_4155 0x4155 // new +#define DEVICE_ID_RADEON_AV 0x4156 // new -// m10 -//#define DEVICE_ID_RADEON_NP 0x4e50 -// Mobility Fire GL T2 - any idea about the chip? +// m10 (rv350) +#define DEVICE_ID_RADEON_NP 0x4e50 +#define DEVICE_ID_RADEON_NQ 0x4e51 // new +#define DEVICE_ID_RADEON_NR 0x4e52 // new +#define DEVICE_ID_RADEON_NS 0x4e53 // new #define DEVICE_ID_RADEON_NT 0x4e54 - -// rv360 -#define DEVICE_ID_RADEON_AR 0x4152 +#define DEVICE_ID_RADEON_NV 0x4e56 // new // r350 #define DEVICE_ID_RADEON_AH 0x4148 +#define DEVICE_ID_RADEON_AI 0x4149 // new +#define DEVICE_ID_RADEON_AJ 0x414a // new +#define DEVICE_ID_RADEON_AK 0x414b // new #define DEVICE_ID_RADEON_NH 0x4e48 #define DEVICE_ID_RADEON_NI 0x4e49 +#define DEVICE_ID_RADEON_NK 0x4e4b // new // r360 #define DEVICE_ID_RADEON_NJ 0x4e4a +// rv370 X300 +//#define DEVICE_ID_RADEON_5b50 0x5b50 +#define DEVICE_ID_RADEON_5b60 0x5b60 +#define DEVICE_ID_RADEON_5b62 0x5b62 +#define DEVICE_ID_RADEON_5b64 0x5b64 // new +#define DEVICE_ID_RADEON_5b65 0x5b65 // new +#define DEVICE_ID_RADEON_5460 0x5460 +#define DEVICE_ID_RADEON_5464 0x5464 // new + +// rv380 X600 +#define DEVICE_ID_RADEON_3e50 0x3e50 +#define DEVICE_ID_RADEON_3e54 0x3e54 // new +#define DEVICE_ID_RADEON_3150 0x3150 // new +#define DEVICE_ID_RADEON_3154 0x3154 // new +#define DEVICE_ID_RADEON_5462 0x5462 // new X600SE on Toshiba M50 really an X300??? + +// rv380 X600AIW +#define DEVICE_ID_RADEON_5b62 0x5b62 + +// rv410 X700 pro +#define DEVICE_ID_RADEON_5e48 0x5e48 // new +#define DEVICE_ID_RADEON_564a 0x564a // new +#define DEVICE_ID_RADEON_564b 0x564b // new +#define DEVICE_ID_RADEON_564f 0x564f // new +#define DEVICE_ID_RADEON_5652 0x5652 // new +#define DEVICE_ID_RADEON_5653 0x5653 // new +#define DEVICE_ID_RADEON_5e4b 0x5e4b +#define DEVICE_ID_RADEON_5e4a 0x5e4a // new +#define DEVICE_ID_RADEON_5e4d 0x5e4d // new +#define DEVICE_ID_RADEON_5e4c 0x5e4c // new +#define DEVICE_ID_RADEON_5e4f 0x5e4f // new + + +// r420 X800 +#define DEVICE_ID_RADEON_JH 0x4a48 // new +#define DEVICE_ID_RADEON_JI 0x4a49 +#define DEVICE_ID_RADEON_JJ 0x4a4a +#define DEVICE_ID_RADEON_JK 0x4a4b +#define DEVICE_ID_RADEON_JL 0x4a4c // new mobility +#define DEVICE_ID_RADEON_JM 0x4a4d // new +#define DEVICE_ID_RADEON_JN 0x4a4e // new +#define DEVICE_ID_RADEON_JP 0x4a50 +#define DEVICE_ID_RADEON_4a4f 0x4a4f // new + +// r423 X800 +#define DEVICE_ID_RADEON_UH 0x5548 // new +#define DEVICE_ID_RADEON_UI 0x5549 +#define DEVICE_ID_RADEON_UJ 0x554a +#define DEVICE_ID_RADEON_UK 0x554b +#define DEVICE_ID_RADEON_UQ 0x5551 // new +#define DEVICE_ID_RADEON_UR 0x5552 // new +#define DEVICE_ID_RADEON_UT 0x5554 // new + +#define DEVICE_ID_RADEON_UM 0x554d // ? +#define DEVICE_ID_RADEON_UO 0x554f // ? + +#define DEVICE_ID_RADEON_5d57 0x5d57 +#define DEVICE_ID_RADEON_5550 0x5550 // new + +// r430 X850 +#define DEVICE_ID_RADEON_5d49 0x5d49 // new mob +#define DEVICE_ID_RADEON_5d4a 0x5d4a // new mob +#define DEVICE_ID_RADEON_5d48 0x5d48 // new mob +#define DEVICE_ID_RADEON_554f 0x554f // new +#define DEVICE_ID_RADEON_554d 0x554d // new +#define DEVICE_ID_RADEON_554e 0x554e // new +#define DEVICE_ID_RADEON_554c 0x554c // new + +// r480 +#define DEVICE_ID_RADEON_5d4c 0x5d4c // new +#define DEVICE_ID_RADEON_5d50 0x5d50 // new +#define DEVICE_ID_RADEON_5d4e 0x5d4e // new +#define DEVICE_ID_RADEON_5d4f 0x5d4f // new +#define DEVICE_ID_RADEON_5d52 0x5d52 // new +#define DEVICE_ID_RADEON_5d4d 0x5d4d // new + +// r481 +#define DEVICE_ID_RADEON_KJ 0x4b4a +#define DEVICE_ID_RADEON_KK 0x4b4b +#define DEVICE_ID_RADEON_KL 0x4b4c +#define DEVICE_ID_RADEON_KI 0x4b49 + // rs100 -#define DEVICE_ID_IGP320M 0x4336 +#define DEVICE_ID_RS100_4136 0x4136 +#define DEVICE_ID_RS100_4336 0x4336 // rs200 -#define DEVICE_ID_RADEON_C7 0x4337 -#define DEVICE_ID_RADEON_A7 0x4137 +#define DEVICE_ID_RS200_4337 0x4337 +#define DEVICE_ID_RS200_4137 0x4137 + +// rs250 +#define DEVICE_ID_RS250_4237 0x4237 +#define DEVICE_ID_RS250_4437 0x4437 + +// rs300 +#define DEVICE_ID_RS300_5834 0x5834 +#define DEVICE_ID_RS300_5835 0x5835 + +// rs350 +#define DEVICE_ID_RS350_7834 0x7834 +#define DEVICE_ID_RS350_7835 0x7835 + +// rs400 +#define DEVICE_ID_RS400_5a41 0x5a41 +#define DEVICE_ID_RS400_5a42 0x5a42 + +// rs410 +#define DEVICE_ID_RS410_5a61 0x5a61 +#define DEVICE_ID_RS410_5a62 0x5a62 + +// rs480/82 +#define DEVICE_ID_RS480_5954 0x5954 +#define DEVICE_ID_RS480_5955 0x5955 +#define DEVICE_ID_RS482_5974 0x5974 +#define DEVICE_ID_RS482_5975 0x5975 typedef struct { uint16 device_id; radeon_type asic; + uint32 features; char *name; } RadeonDevice; +#define STD_RADEON 0 // common as muck PC graphics card (if there is such a thing) +#define ISMOBILITY 1 // is mobility +#define INTEGRATED 2 // is IGP (Integrated Graphics Processor) built in to PC mainboard northbridge typically uses system RAM for graphics +#define MOBILE_IGP ISMOBILITY | INTEGRATED // 2 disabilites for the price of 1 + // list of supported devices RadeonDevice radeon_device_list[] = { // original Radeons, now called r100 - { DEVICE_ID_RADEON_QD, rt_r100, "Radeon 7200 / Radeon / ALL-IN-WONDER Radeon" }, - { DEVICE_ID_RADEON_QE, rt_r100, "Radeon QE" }, - { DEVICE_ID_RADEON_QF, rt_r100, "Radeon QF" }, - { DEVICE_ID_RADEON_QG, rt_r100, "Radeon QG" }, + { DEVICE_ID_RADEON_QD , rt_r100, STD_RADEON, "Radeon 7200 / Radeon / ALL-IN-WONDER Radeon" }, + { DEVICE_ID_RADEON_QE , rt_r100, STD_RADEON, "Radeon QE" }, + { DEVICE_ID_RADEON_QF , rt_r100, STD_RADEON, "Radeon QF" }, + { DEVICE_ID_RADEON_QG , rt_r100, STD_RADEON, "Radeon QG" }, + + // Radeon VE (low-cost, dual CRT, no TCL), was rt_ve now refered to as rv100 + { DEVICE_ID_RADEON_QY , rt_rv100, STD_RADEON, "Radeon 7000 / Radeon VE" }, + { DEVICE_ID_RADEON_QZ , rt_rv100, STD_RADEON, "Radeon QZ VE" }, + + { DEVICE_ID_RN50_515E , rt_rv100, STD_RADEON, "ES1000 515E (PCI)" }, // Evans and Sutherland something or other? + { DEVICE_ID_RN50_5969 , rt_rv100, STD_RADEON, "ES1000 5969 (PCI)" }, - // Radeon VE (low-cost, dual CRT, no TCL), now called RV100 - { DEVICE_ID_RADEON_QY, rt_ve, "Radeon 7000 / Radeon VE" }, - { DEVICE_ID_RADEON_QZ, rt_ve, "Radeon QZ VE" }, - // mobility version of original Radeon (based on VE), now called M6 - { DEVICE_ID_RADEON_LY, rt_m6, "Radeon Mobility" }, - { DEVICE_ID_RADEON_LZ, rt_m6, "Radeon Mobility M6 LZ" }, - - // rs100 (integrated Radeon, seems to be a Radeon VE) - { DEVICE_ID_IGP320M, rt_rs100, "IGP320M" }, - - // RV200 (dual CRT) - { DEVICE_ID_RADEON_QW, rt_rv200, "Radeon 7500 / ALL-IN-WONDER Radeon 7500" }, - { DEVICE_ID_RADEON_QX, rt_rv200, "Radeon 7500 QX" }, - - // M7 (based on RV200) - { DEVICE_ID_RADEON_LW, rt_m7, "Radeon Mobility 7500" }, - { DEVICE_ID_RADEON_LX, rt_m7, "Radeon Mobility 7500 GL" }, - - // R200 - { DEVICE_ID_RADEON_QH, rt_r200, "ATI Fire GL E1" }, // chip type: fgl8800 - { DEVICE_ID_RADEON_QI, rt_r200, "Radeon 8500 QI" }, - { DEVICE_ID_RADEON_QJ, rt_r200, "Radeon 8500 QJ" }, - { DEVICE_ID_RADEON_QK, rt_r200, "Radeon 8500 QK" }, - { DEVICE_ID_RADEON_QL, rt_r200, "Radeon 8500 / 8500LE / ALL-IN-WONDER Radeon 8500" }, - { DEVICE_ID_RADEON_QM, rt_r200, "Radeon 9100" }, + { DEVICE_ID_RADEON_LY , rt_rv100, ISMOBILITY, "Radeon Mobility" }, + { DEVICE_ID_RADEON_LZ , rt_rv100, ISMOBILITY, "Radeon Mobility M6 LZ" }, - { DEVICE_ID_RADEON_Qh, rt_r200, "Radeon 8500 Qh" }, - { DEVICE_ID_RADEON_Qi, rt_r200, "Radeon 8500 Qi" }, - { DEVICE_ID_RADEON_Qj, rt_r200, "Radeon 8500 Qj" }, - { DEVICE_ID_RADEON_Qk, rt_r200, "Radeon 8500 Qk" }, - { DEVICE_ID_RADEON_BB, rt_r200, "ALL-IN-Wonder Radeon 8500 DV" }, + // RV200 (dual CRT) + { DEVICE_ID_RADEON_QW , rt_rv200, STD_RADEON, "Radeon 7500 / ALL-IN-WONDER Radeon 7500" }, + { DEVICE_ID_RADEON_QX , rt_rv200, STD_RADEON, "Radeon 7500 QX" }, + + // M7 (based on RV200) was rt_m7 + { DEVICE_ID_RADEON_LW , rt_rv200, ISMOBILITY, "Radeon Mobility 7500" }, + { DEVICE_ID_RADEON_LX , rt_rv200, ISMOBILITY, "Radeon Mobility 7500 GL" }, + + // R200 + { DEVICE_ID_RADEON_QH , rt_r200, STD_RADEON, "Fire GL E1" }, // chip type: fgl8800 + { DEVICE_ID_RADEON_QI , rt_r200, STD_RADEON, "Radeon 8500 QI" }, + { DEVICE_ID_RADEON_QJ , rt_r200, STD_RADEON, "Radeon 8500 QJ" }, + { DEVICE_ID_RADEON_QK , rt_r200, STD_RADEON, "Radeon 8500 QK" }, + { DEVICE_ID_RADEON_QL , rt_r200, STD_RADEON, "Radeon 8500 / 8500LE / ALL-IN-WONDER Radeon 8500" }, + { DEVICE_ID_RADEON_QM , rt_r200, STD_RADEON, "Radeon 9100" }, + + { DEVICE_ID_RADEON_Qh , rt_r200, STD_RADEON, "Radeon 8500 Qh" }, + { DEVICE_ID_RADEON_Qi , rt_r200, STD_RADEON, "Radeon 8500 Qi" }, + { DEVICE_ID_RADEON_Qj , rt_r200, STD_RADEON, "Radeon 8500 Qj" }, + { DEVICE_ID_RADEON_Qk , rt_r200, STD_RADEON, "Radeon 8500 Qk" }, + + { DEVICE_ID_RADEON_BB , rt_r200, STD_RADEON, "ALL-IN-Wonder Radeon 8500 DV (BB)" }, + { DEVICE_ID_RADEON_BC , rt_r200, STD_RADEON, "ALL-IN-Wonder Radeon 8500 DV (BC)" }, // RV250 (cut-down R200 with integrated TV-Out) - { DEVICE_ID_RADEON_Id, rt_rv250, "Radeon 9000 Id" }, - { DEVICE_ID_RADEON_Ie, rt_rv250, "Radeon 9000 Ie" }, - { DEVICE_ID_RADEON_If, rt_rv250, "Radeon 9000" }, - { DEVICE_ID_RADEON_Ig, rt_rv250, "Radeon 9000 Ig" }, + { DEVICE_ID_RADEON_If , rt_rv250, STD_RADEON, "Radeon 9000" }, + { DEVICE_ID_RADEON_Ig , rt_rv250, STD_RADEON, "Radeon 9000 Ig" }, - // M9 (based on rv250) - { DEVICE_ID_RADEON_Ld, rt_m9, "Radeon Mobility 9000 Ld" }, - { DEVICE_ID_RADEON_Le, rt_m9, "Radeon Mobility 9000 Le" }, - { DEVICE_ID_RADEON_Lf, rt_m9, "Radeon Mobility 9000 Lf" }, - { DEVICE_ID_RADEON_Lg, rt_m9, "Radeon Mobility 9000 Lg" }, - - // RV280 (rv250 with higher frequency) - // this entry violates naming scheme, so it's probably wrong - { DEVICE_ID_RADEON_Zprea, rt_rv280, "Radeon 9200" }, - { DEVICE_ID_RADEON_Za, rt_rv280, "Radeon 9200" }, - { DEVICE_ID_RADEON_Zd, rt_rv280, "Radeon 9200 SE" }, - - // M9+ (based on rv280) - { DEVICE_ID_RADEON_5c61,rt_m9plus, "Radeon Mobility 9200" }, + // M9 (based on rv250) was rt_m9 + { DEVICE_ID_RADEON_Ld , rt_rv250, ISMOBILITY, "Radeon Mobility 9000 Ld" }, + { DEVICE_ID_RADEON_Le , rt_rv250, ISMOBILITY, "Radeon Mobility 9000 Le" }, + { DEVICE_ID_RADEON_Lf , rt_rv250, ISMOBILITY, "Radeon Mobility 9000 Lf" }, + { DEVICE_ID_RADEON_Lg , rt_rv250, ISMOBILITY, "Radeon Mobility 9000 Lg" }, + + // RV280 (rv250 but faster) + { DEVICE_ID_RADEON_5960 , rt_rv280, STD_RADEON, "Radeon 9200 Pro" }, + { DEVICE_ID_RADEON_Za , rt_rv280, STD_RADEON, "Radeon 9200" }, + { DEVICE_ID_RADEON_Zb , rt_rv280, STD_RADEON, "Radeon 9200" }, + { DEVICE_ID_RADEON_Zd , rt_rv280, STD_RADEON, "Radeon 9200 SE" }, + { DEVICE_ID_RADEON_Ze , rt_rv280, STD_RADEON, "Ati FireMV 2200" }, + + // M9+ (based on rv280) was rt_m9plus + { DEVICE_ID_RADEON_5c61 , rt_rv280, ISMOBILITY, "Radeon Mobility 9200" }, + { DEVICE_ID_RADEON_5c63 , rt_rv280, ISMOBILITY, "Radeon Mobility 9200" }, // R300 - { DEVICE_ID_RADEON_ND, rt_r300, "Radeon 9700 ND" }, - { DEVICE_ID_RADEON_NE, rt_r300, "Radeon 9700 NE" }, - { DEVICE_ID_RADEON_NF, rt_r300, "Radeon 9600 XT" }, - { DEVICE_ID_RADEON_NG, rt_r300, "Radeon 9700 NG" }, + { DEVICE_ID_RADEON_ND , rt_r300, STD_RADEON, "Radeon 9700 ND" }, + { DEVICE_ID_RADEON_NE , rt_r300, STD_RADEON, "Radeon 9700 NE" }, + { DEVICE_ID_RADEON_NF , rt_r300, STD_RADEON, "Radeon 9600 XT" }, + { DEVICE_ID_RADEON_NG , rt_r300, STD_RADEON, "Radeon 9700 NG" }, - { DEVICE_ID_RADEON_AD, rt_r300, "Radeon 9700 AD" }, - { DEVICE_ID_RADEON_AE, rt_r300, "Radeon 9700 AE" }, - { DEVICE_ID_RADEON_AF, rt_r300, "Radeon 9700 AF" }, - { DEVICE_ID_RADEON_AG, rt_r300, "Radeon 9700 AG" }, + // r300-4P + { DEVICE_ID_RADEON_AD , rt_r300, STD_RADEON, "Radeon 9700 AD" }, + { DEVICE_ID_RADEON_AE , rt_r300, STD_RADEON, "Radeon 9700 AE" }, + { DEVICE_ID_RADEON_AF , rt_r300, STD_RADEON, "Radeon 9700 AF" }, + { DEVICE_ID_RADEON_AG , rt_r300, STD_RADEON, "Radeon 9700 AG" }, // RV350 - { DEVICE_ID_RADEON_AP, rt_rv350, "Radeon 9600 AP" }, - { DEVICE_ID_RADEON_AQ, rt_rv350, "Radeon 9600 AQ" }, - { DEVICE_ID_RADEON_AS, rt_rv350, "Radeon 9600 AS" }, - - // M10 (based on rv350) -// { DEVICE_ID_RADEON_NP, rt_m10, "Radeon Mobility 9600 NP" }, - - // M11 (based on rv360) - { DEVICE_ID_RADEON_NP, rt_m11, "Radeon 9700 Mobility" }, - { DEVICE_ID_RADEON_SE, rt_m11, "Radeon 9700 Mobility SE" }, - - // not sure about that: ROM signature is "RADEON" which means r100 - { DEVICE_ID_RADEON_NT, rt_m10, "Radeon Mobility FireGL T2" }, + { DEVICE_ID_RADEON_AP , rt_rv350, STD_RADEON, "Radeon 9600 AP" }, + { DEVICE_ID_RADEON_AQ , rt_rv350, STD_RADEON, "Radeon 9600SE AQ" }, + { DEVICE_ID_RADEON_AR , rt_rv350, STD_RADEON, "Radeon 9600XT AR" }, + { DEVICE_ID_RADEON_AS , rt_rv350, STD_RADEON, "Radeon 9550 AS" }, + { DEVICE_ID_RADEON_AT , rt_rv350, STD_RADEON, "FireGL T2 AT" }, + { DEVICE_ID_RADEON_4155 , rt_rv350, STD_RADEON, "Radeon 9650 4155" }, + { DEVICE_ID_RADEON_AV , rt_rv350, STD_RADEON, "Radeon 9600 AQ" }, - // RV360 (probably minor revision of rv350) - { DEVICE_ID_RADEON_AR, rt_rv360, "Radeon 9600 AR" }, + // rv350 M10 (based on rv350) was rt_m10 + { DEVICE_ID_RADEON_NP , rt_rv350, ISMOBILITY, "Radeon Mobility 9600/9700 (M10/M11) NP " }, + { DEVICE_ID_RADEON_NQ , rt_rv350, ISMOBILITY, "Radeon Mobility 9600 (M10) NQ " }, + { DEVICE_ID_RADEON_NR , rt_rv350, ISMOBILITY, "Radeon Mobility 9600 (M11) NR " }, + { DEVICE_ID_RADEON_NS , rt_rv350, ISMOBILITY, "Radeon Mobility 9600 (M10) NS " }, + { DEVICE_ID_RADEON_NT , rt_rv350, ISMOBILITY, "ATI FireGL Mobility T2 (M10) NT" }, + { DEVICE_ID_RADEON_NV , rt_rv350, ISMOBILITY, "ATI FireGL Mobility T2e (M11) NV" }, // R350 - { DEVICE_ID_RADEON_AH, rt_r350, "Radeon 9800 AH" }, - { DEVICE_ID_RADEON_NH, rt_r350, "Radeon 9800 Pro NH" }, - { DEVICE_ID_RADEON_NI, rt_r350, "Radeon 9800 NI" }, + { DEVICE_ID_RADEON_AH , rt_r350, STD_RADEON, "Radeon 9800SE AH" }, + { DEVICE_ID_RADEON_AI , rt_r350, STD_RADEON, "Radeon 9800 AI" }, + { DEVICE_ID_RADEON_AJ , rt_r350, STD_RADEON, "Radeon 9800 AJ" }, + { DEVICE_ID_RADEON_AK , rt_r350, STD_RADEON, "FireGL X2 AK" }, + { DEVICE_ID_RADEON_NH , rt_r350, STD_RADEON, "Radeon 9800 Pro NH" }, + { DEVICE_ID_RADEON_NI , rt_r350, STD_RADEON, "Radeon 9800 NI" }, + { DEVICE_ID_RADEON_NK , rt_r350, STD_RADEON, "FireGL X2 NK" }, + { DEVICE_ID_RADEON_NJ , rt_r350, STD_RADEON, "Radeon 9800 XT" }, - // R360 (probably minor revision of r350) - { DEVICE_ID_RADEON_NJ, rt_r360, "Radeon 9800 XT" }, + // rv370 + { DEVICE_ID_RADEON_5b60 , rt_rv380, STD_RADEON, "Radeon X300 (RV370) 5B60" }, + { DEVICE_ID_RADEON_5b62 , rt_rv380, STD_RADEON, "Radeon X600 (RV370) 5B62" }, + { DEVICE_ID_RADEON_5b64 , rt_rv380, STD_RADEON, "FireGL V3100 (RV370) 5B64" }, + { DEVICE_ID_RADEON_5b65 , rt_rv380, STD_RADEON, "FireGL D1100 (RV370) 5B65" }, + { DEVICE_ID_RADEON_5460 , rt_rv380, ISMOBILITY, "Radeon Mobility M300 (M22) 5460" }, + { DEVICE_ID_RADEON_5464 , rt_rv380, ISMOBILITY, "FireGL M22 GL 5464" }, + + // rv380 + { DEVICE_ID_RADEON_3e50 , rt_rv380, STD_RADEON, "Radeon X600 (RV380) 3E50" }, + { DEVICE_ID_RADEON_3e54 , rt_rv380, STD_RADEON, "FireGL V3200 (RV380) 3E54" }, + { DEVICE_ID_RADEON_3150 , rt_rv380, ISMOBILITY, "Radeon Mobility X600 (M24) 3150" }, + { DEVICE_ID_RADEON_3154 , rt_rv380, ISMOBILITY, "FireGL M24 GL 3154" }, + { DEVICE_ID_RADEON_5462 , rt_rv380, ISMOBILITY, "Radeon X600SE (RV3?0) 5462" }, + + // rv380 + { DEVICE_ID_RADEON_5b62 , rt_rv380, STD_RADEON, "Radeon X600 AIW" }, + + // rv410 + { DEVICE_ID_RADEON_5e48 , rt_r420, STD_RADEON, "FireGL V5000 (RV410)" }, + { DEVICE_ID_RADEON_564a , rt_r420, ISMOBILITY, "Mobility FireGL V5000 (M26)" }, + { DEVICE_ID_RADEON_564b , rt_r420, ISMOBILITY, "Mobility FireGL V5000 (M26)" }, + { DEVICE_ID_RADEON_564f , rt_r420, ISMOBILITY, "Mobility Radeon X700 XL (M26)" }, + { DEVICE_ID_RADEON_5652 , rt_r420, ISMOBILITY, "Mobility Radeon X700 (M26)" }, + { DEVICE_ID_RADEON_5653 , rt_r420, ISMOBILITY, "Mobility Radeon X700 (M26)" }, + { DEVICE_ID_RADEON_5e4b , rt_r420, STD_RADEON, "Radeon X700 PRO (RV410)" }, + { DEVICE_ID_RADEON_5e4a , rt_r420, STD_RADEON, "Radeon X700 XT (RV410)" }, + { DEVICE_ID_RADEON_5e4d , rt_r420, STD_RADEON, "Radeon X700 (RV410)" }, + { DEVICE_ID_RADEON_5e4c , rt_r420, STD_RADEON, "Radeon X700 SE (RV410)" }, + { DEVICE_ID_RADEON_5e4f , rt_r420, STD_RADEON, "Radeon X700 SE (RV410)" }, + + // r420 + { DEVICE_ID_RADEON_JH , rt_r420, STD_RADEON, "Radeon X800 (R420) JH" }, + { DEVICE_ID_RADEON_JI , rt_r420, STD_RADEON, "Radeon X800PRO (R420) JI" }, + { DEVICE_ID_RADEON_JJ , rt_r420, STD_RADEON, "Radeon X800SE (R420) JJ" }, + { DEVICE_ID_RADEON_JK , rt_r420, STD_RADEON, "Radeon X800 (R420) JK" }, + { DEVICE_ID_RADEON_JL , rt_r420, STD_RADEON, "Radeon X800 (R420) JL" }, + { DEVICE_ID_RADEON_JM , rt_r420, STD_RADEON, "FireGL X3 (R420) JM" }, + { DEVICE_ID_RADEON_JN , rt_r420, ISMOBILITY, "Radeon Mobility 9800 (M18) JN" }, + { DEVICE_ID_RADEON_JP , rt_r420, STD_RADEON, "Radeon X800XT (R420) JP" }, + { DEVICE_ID_RADEON_4a4f , rt_r420, STD_RADEON, "Radeon X800 SE (R420)" }, + + // r423 + { DEVICE_ID_RADEON_UH , rt_r420, STD_RADEON, "Radeon X800 (R423) UH" }, + { DEVICE_ID_RADEON_UI , rt_r420, STD_RADEON, "Radeon X800PRO (R423) UI" }, + { DEVICE_ID_RADEON_UJ , rt_r420, STD_RADEON, "Radeon X800LE (R423) UJ" }, + { DEVICE_ID_RADEON_UK , rt_r420, STD_RADEON, "Radeon X800SE (R423) UK" }, + { DEVICE_ID_RADEON_UQ , rt_r420, STD_RADEON, "FireGL V7200 (R423) UQ" }, + { DEVICE_ID_RADEON_UR , rt_r420, STD_RADEON, "FireGL V5100 (R423) UR" }, + { DEVICE_ID_RADEON_UT , rt_r420, STD_RADEON, "FireGL V7100 (R423) UT" }, + + { DEVICE_ID_RADEON_UO , rt_r420, STD_RADEON, "Radeon X800 UO" }, + { DEVICE_ID_RADEON_UM , rt_r420, STD_RADEON, "Radeon X800 UM" }, + + { DEVICE_ID_RADEON_5d57 , rt_r420, STD_RADEON, "Radeon X800 XT" }, + { DEVICE_ID_RADEON_5550 , rt_r420, STD_RADEON, "FireGL V7100 (R423)" }, + + // r430 + { DEVICE_ID_RADEON_5d49 , rt_r420, ISMOBILITY, "Mobility FireGL V5100 (M28)" }, + { DEVICE_ID_RADEON_5d4a , rt_r420, ISMOBILITY, "Mobility Radeon X800 (M28)" }, + { DEVICE_ID_RADEON_5d48 , rt_r420, ISMOBILITY, "Mobility Radeon X800 XT (M28)" }, + { DEVICE_ID_RADEON_554f , rt_r420, STD_RADEON, "Radeon X800 (R430)" }, + { DEVICE_ID_RADEON_554d , rt_r420, STD_RADEON, "Radeon X800 XL (R430)" }, + { DEVICE_ID_RADEON_554e , rt_r420, STD_RADEON, "Radeon X800 SE (R430)" }, + { DEVICE_ID_RADEON_554c , rt_r420, STD_RADEON, "Radeon X800 XTP (R430)" }, + + // r480 + { DEVICE_ID_RADEON_5d4c , rt_r420, STD_RADEON, "Radeon X850 5D4C" }, + { DEVICE_ID_RADEON_5d50 , rt_r420, STD_RADEON, "Radeon FireGL (R480) GL 5D50" }, + { DEVICE_ID_RADEON_5d4e , rt_r420, STD_RADEON, "Radeon X850 SE (R480)" }, + { DEVICE_ID_RADEON_5d4f , rt_r420, STD_RADEON, "Radeon X850 PRO (R480)" }, + { DEVICE_ID_RADEON_5d52 , rt_r420, STD_RADEON, "Radeon X850 XT (R480)" }, + { DEVICE_ID_RADEON_5d4d , rt_r420, STD_RADEON, "Radeon X850 XT PE (R480)" }, + + // r481 + { DEVICE_ID_RADEON_KJ , rt_r420, STD_RADEON, "Radeon X850 PRO (R480)" }, + { DEVICE_ID_RADEON_KK , rt_r420, STD_RADEON, "Radeon X850 SE (R480)" }, + { DEVICE_ID_RADEON_KL , rt_r420, STD_RADEON, "Radeon X850 XT (R480)" }, + { DEVICE_ID_RADEON_KI , rt_r420, STD_RADEON, "Radeon X850 XT PE (R480)" }, // rs100 (aka IGP 320) - { DEVICE_ID_IGP320M, rt_rs100, "Radeon IGP 320M" }, - + { DEVICE_ID_RS100_4136 , rt_rs100, INTEGRATED, "Radeon IGP320 (A3) 4136" }, + { DEVICE_ID_RS100_4336 , rt_rs100, MOBILE_IGP, "Radeon IGP320M (U1) 4336" }, + // rs200 (aka IGP 340) - { DEVICE_ID_RADEON_C7, rt_rs200, "IGP330M/340M/350M (U2) 4337" }, - { DEVICE_ID_RADEON_A7, rt_rs200, "IGP 340" }, - - { 0, 0, NULL } + { DEVICE_ID_RS200_4137 , rt_rs200, INTEGRATED, "Radeon IGP330/340/350 (A4) 4137" }, + { DEVICE_ID_RS200_4337 , rt_rs200, MOBILE_IGP, "Radeon IGP330M/340M/350M (U2) 4337" }, + + // rs250 (aka 7000 IGP) + { DEVICE_ID_RS250_4237 , rt_rs200, INTEGRATED, "IGP330M/340M/350M (U2) 4337" }, + { DEVICE_ID_RS250_4437 , rt_rs200, MOBILE_IGP, "Radeon Mobility 7000 IGP 4437" }, + + // rs300 + { DEVICE_ID_RS300_5834 , rt_rs300, INTEGRATED, "Radeon 9100 IGP (A5) 5834" }, + { DEVICE_ID_RS300_5835 , rt_rs300, MOBILE_IGP, "Radeon Mobility 9100 IGP (U3) 5835" }, + + // rs350 + { DEVICE_ID_RS350_7834 , rt_rs300, INTEGRATED, "Radeon 9100 PRO IGP 7834" }, + { DEVICE_ID_RS350_7835 , rt_rs300, MOBILE_IGP, "Radeon Mobility 9200 IGP 7835" }, + + // rs400 + { DEVICE_ID_RS400_5a41 , rt_rv380, STD_RADEON, "Radeon XPRESS 200 5A41" }, // X.org people unsure what this is for now + { DEVICE_ID_RS400_5a42 , rt_rv380, ISMOBILITY, "Radeon XPRESS 200M 5A42" }, + + // rs410 + { DEVICE_ID_RS410_5a61 , rt_rv380, STD_RADEON, "Radeon XPRESS 200 5A61" }, // X.org people unsure what this is for now + { DEVICE_ID_RS410_5a62 , rt_rv380, ISMOBILITY, "Radeon XPRESS 200M 5A62" }, + + // rs480 + { DEVICE_ID_RS480_5954 , rt_rv380, STD_RADEON, "Radeon XPRESS 200 5954" }, // X.org people unsure what this is for now + { DEVICE_ID_RS480_5955 , rt_rv380, ISMOBILITY, "Radeon XPRESS 200M 5955" }, + { DEVICE_ID_RS482_5974 , rt_rv380, STD_RADEON, "Radeon XPRESS 200 5974" }, // X.org people unsure what this is for now + { DEVICE_ID_RS482_5975 , rt_rv380, ISMOBILITY, "Radeon XPRESS 200M 5975" }, + + { 0, 0, 0, NULL } }; @@ -293,32 +528,25 @@ static struct { const char *name; // name of ASIC tv_chip_type tv_chip; // TV-Out chip (if any) bool has_crtc2; // has second CRTC - bool is_mobility; // mobility chip bool has_vip; // has VIP/I2C bool new_pll; // reference divider of PPLL moved to other location - bool is_igp; // integrated graphics } asic_properties[] = { - { "r100", tc_external_rt1, false, false, true, false, false }, // only original Radeons have one crtc only - { "ve", tc_internal_rt1, true, false, true, false, false }, - { "m6", tc_internal_rt1, true, true, false, false, false }, - { "rs100", tc_internal_rt1, true, true, false, false, true }, - { "rv200", tc_internal_rt2, true, false, true, false, false }, - { "m7", tc_internal_rt1, true, true, false, false, false }, - { "rs200", tc_internal_rt1, true, true, false, false, true }, - { "r200", tc_external_rt1, true, false, true, false, false }, // r200 has external TV-Out encoder - { "rv250", tc_internal_rt2, true, false, true, false, false }, - { "m9", tc_internal_rt2, true, true, false, false, false }, - { "rv280", tc_internal_rt2, true, false, true, false, false }, - { "m9plus", tc_internal_rt2, true, true, false, false, false }, - { "r300", tc_internal_rt2, true, false, true, true, false }, - { "r300_4p",tc_internal_rt2, true, false, true, true, false }, - { "rv350", tc_internal_rt2, true, false, true, true, false }, - { "m10", tc_internal_rt2, true, true, false, true, false }, - { "rv360", tc_internal_rt2, true, false, true, true, false }, - { "r350", tc_internal_rt2, true, false, true, true, false }, - { "r360", tc_internal_rt2, true, false, true, true, false }, - { "m11", tc_internal_rt2, true, true, false, true, false } + { "r100", tc_external_rt1, false, true, false,}, + { "rv100", tc_internal_rt1, true, true, false,}, + { "rs100", tc_internal_rt1, true, false, false,}, + { "rv200", tc_internal_rt2, true, true, false,}, + { "rs200", tc_internal_rt1, true, false, false,}, + { "r200", tc_external_rt1, true, true, false,}, + { "rv250", tc_internal_rt2, true, true, false,}, + { "rs300", tc_internal_rt1, true, false, false,}, + { "rv280", tc_internal_rt2, true, true, false,}, + { "r300", tc_internal_rt2, true, true, true, }, + { "r350", tc_internal_rt2, true, true, true, }, + { "rv350", tc_internal_rt2, true, true, true, }, + { "rv380", tc_internal_rt2, true, true, true, }, + { "r420", tc_internal_rt2, true, true, true, } + }; @@ -342,11 +570,28 @@ static bool probeDevice( device_info *di ) di->num_crtc = asic_properties[device->asic].has_crtc2 ? 2 : 1; di->tv_chip = asic_properties[device->asic].tv_chip; di->asic = device->asic; - di->is_mobility = asic_properties[device->asic].is_mobility; + di->is_mobility = (device->features & ISMOBILITY) ? true : false; di->has_vip = asic_properties[device->asic].has_vip; di->new_pll = asic_properties[device->asic].new_pll; - di->is_igp = asic_properties[device->asic].is_igp; - + di->is_igp = (device->features & INTEGRATED) ? true : false; + + // detect chips with broken I2C + switch( device->device_id) + { + case DEVICE_ID_RADEON_LY: + case DEVICE_ID_RADEON_LZ: + case DEVICE_ID_RADEON_LW: + case DEVICE_ID_RADEON_LX: + case DEVICE_ID_RADEON_If: + case DEVICE_ID_RADEON_Ig: + case DEVICE_ID_RADEON_5460: + case DEVICE_ID_RADEON_5464: + di->has_no_i2c = true; + default: + di->has_no_i2c = false; + + } + if( Radeon_MapBIOS( &di->pcii, &di->rom ) != B_OK ) // give up checking this device - no BIOS, no fun return false; diff --git a/src/add-ons/kernel/drivers/graphics/radeon/driver.c b/src/add-ons/kernel/drivers/graphics/radeon/driver.c index 979caa644b..1287bec8ef 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/driver.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/driver.c @@ -14,8 +14,11 @@ #include #include #include +#include "AGP.h" #include "mmio.h" #include "version.h" +#include +#include // for strtoXX // tell the kernel what revision of the driver API we support int32 api_version = 2; diff --git a/src/add-ons/kernel/drivers/graphics/radeon/init.c b/src/add-ons/kernel/drivers/graphics/radeon/init.c index 9cd3fee118..7aac99b57f 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/init.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/init.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2002-2004, Thomas Kurschel + * Copyright (c) 2006-2007, Euan Kirkhope + * * Distributed under the terms of the MIT license. */ @@ -13,8 +15,9 @@ */ #include "dac_regs.h" -#include "radeon_driver.h" +#include "fp_regs.h" #include "mmio.h" +#include "radeon_driver.h" #include @@ -242,6 +245,12 @@ status_t Radeon_FirstOpen( device_info *di ) si->is_mobility = di->is_mobility; si->tv_chip = di->tv_chip; si->new_pll = di->new_pll; + si->is_igp = di->is_igp; + si->has_no_i2c = di->has_no_i2c; + si->is_atombios = di->is_atombios; + si->is_mobility = di->is_mobility; + si->panel_pwr_delay = di->si->panel_pwr_delay; + // detecting theatre channel in kernel would lead to code duplication, // so we let the first accelerant take care of it @@ -302,7 +311,7 @@ status_t Radeon_FirstOpen( device_info *di ) // save dac2_cntl register // on M6, we need to restore that during uninit, else you only get // garbage on screen on reboot if both CRTCs are used - if( di->asic == rt_m6 ) + if( di->asic == rt_rv100 && di->is_mobility) di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 ); result = Radeon_InitPCIGART( di ); @@ -347,7 +356,7 @@ status_t Radeon_FirstOpen( device_info *di ) di->memmgr[mt_AGP] = NULL; // fix AGP settings for IGP chipset - if( di->asic == rt_rs100 || di->asic == rt_rs200 ) + if( di->asic == rt_rs100 || di->asic == rt_rs200 || di->asic == rt_rs300) Radeon_Fix_AGP(); // time to init Command Processor @@ -397,9 +406,9 @@ void Radeon_LastClose( device_info *di ) // M6 fix - unfortunately, the device is never closed by app_server, // not even before reboot - if( di->asic == rt_m6 ) - OUTREG( di->regs, RADEON_DAC_CNTL2, di->dac2_cntl ); - + if( di->asic == rt_rv100 && di->is_mobility) + OUTREG( di->regs, RADEON_DAC_CNTL2, di->dac2_cntl ); + mem_destroy( di->memmgr[mt_local] ); diff --git a/src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c b/src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c index efce952148..6f5ffc7d11 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c @@ -17,6 +17,7 @@ #include "radeon_driver.h" #include "buscntrl_regs.h" +#include "config_regs.h" #include "mmio.h" #include "memcntrl_regs.h" @@ -109,7 +110,7 @@ static void Radeon_SetupMCAddresses_IGP( device_info *di ) // the frame buffer memory address range is read from TOM register // it located at end of physical RAM (at least it seems so) - tom = INREG( di->regs, RADEON_GC_NB_TOM ); + tom = INREG( di->regs, RADEON_NB_TOM ); si->memory[mt_local].virtual_addr_start = (tom & 0xffff) << 16; si->memory[mt_local].virtual_size = (((tom >> 16) + 1) << 16) - diff --git a/src/add-ons/kernel/drivers/graphics/radeon/pll_access.c b/src/add-ons/kernel/drivers/graphics/radeon/pll_access.c index d76e7b2055..ece3598bbf 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/pll_access.c +++ b/src/add-ons/kernel/drivers/graphics/radeon/pll_access.c @@ -10,17 +10,60 @@ #include "radeon_interface.h" #include "pll_access.h" #include "pll_regs.h" +#include "crtc_regs.h" #include "utils.h" +void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ) +{ + if (! ((asic == rt_rv200) || (asic == rt_rs200))) + return; + + /* This workaround is necessary on rv200 and RS200 or PLL + * reads may return garbage (among others...) + */ + INREG( regs, RADEON_CLOCK_CNTL_DATA); + INREG( regs, RADEON_CRTC_GEN_CNTL); +} + +void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ) +{ + uint32 save, tmp; + + /* This workarounds is necessary on RV100, RS100 and RS200 chips + * or the chip could hang on a subsequent access + */ + if ((asic == rt_rv100) || (asic == rt_rs100) || (asic == rt_rs200)) + { + /* we can't deal with posted writes here ... */ + snooze(5000); + } + + /* This function is required to workaround a hardware bug in some (all?) + * revisions of the R300. This workaround should be called after every + * CLOCK_CNTL_INDEX register access. If not, register reads afterward + * may not be correct. + */ + + if( asic != rt_r300 ) + return; + + save = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); + tmp = save & ~(0x3f | RADEON_PLL_WR_EN); + OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp ); + tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA ); + OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save ); + +} + // read value "val" from PLL-register "addr" uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ) { uint32 res; OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, addr & 0x3f ); + RADEONPllErrataAfterIndex(regs, asic); res = INREG( regs, RADEON_CLOCK_CNTL_DATA ); - - R300_PLLFix( regs, asic ); + RADEONPllErrataAfterData(regs, asic); return res; } @@ -31,12 +74,10 @@ void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ) OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f ) | RADEON_PLL_WR_EN)); - + RADEONPllErrataAfterIndex(regs, asic); OUTREG( regs, RADEON_CLOCK_CNTL_DATA, val ); - - // TBD: on XFree, there is no call of R300_PLLFix here, - // though it should as we've accessed CLOCK_CNTL_INDEX - //R300_PLLFix( ai ); + RADEONPllErrataAfterData(regs, asic); + } // write "val" to PLL-register "addr" keeping bits "mask" @@ -48,19 +89,3 @@ void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, tmp |= val; Radeon_OUTPLL( regs, asic, addr, tmp ); } - -// r300: to be called after each CLOCK_CNTL_INDEX access -// (hardware bug fix suggested by XFree86) -void R300_PLLFix( vuint8 *regs, radeon_type asic ) -{ - uint32 save, tmp; - - if( asic != rt_r300 ) - return; - - save = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); - tmp = save & ~(0x3f | RADEON_PLL_WR_EN); - OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp ); - tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA ); - OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save ); -} diff --git a/src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h b/src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h index 587eca680b..3a0c39cac7 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h +++ b/src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h @@ -11,7 +11,7 @@ #include #include - +#include "AGP.h" // logging helpers extern int debug_level_flow; @@ -108,6 +108,7 @@ typedef struct device_info { bool new_pll; bool has_vip; bool is_igp; + bool has_no_i2c; //display_type_e disp_type[2]; fp_info fp_info; @@ -116,7 +117,8 @@ typedef struct device_info { char ram_type[32]; // human-readable name of ram type uint32 local_mem_size; - rom_info rom; + rom_info rom; + bool is_atombios; // legacy ROM, or "AtomBios" GART_info pci_gart; // PCI GART GART_info agp_gart; // AGP GART (unsupported)