From 88d73c6cf84541c711c44cb65cf36156fe040cc9 Mon Sep 17 00:00:00 2001 From: Adrien Destugues Date: Tue, 28 Jan 2020 18:56:59 +0100 Subject: [PATCH] intel_extreme: set the "image size" register on generation 4 and below This is undocumented, but required for GMA 945 and probably earlier devices as well. The register is reserved in later generation 4 devices, and not mentionned at all in later versions. Fixes #15655. --- src/add-ons/accelerants/intel_extreme/Pipes.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index 396c3335dc..683cb5ab59 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -235,14 +235,14 @@ Pipe::ConfigureTimings(display_mode* target, bool hardware) // Set the plane size as well while we're at it (this is independant, we // could have a larger plane and scroll through it). - if (gInfo->shared_info->device_type.Generation() == 5 - || gInfo->shared_info->device_type.Generation() > 6) { - // FIXME check which generations actually need this. - // This is "reserved" on G45 and below. - // This register does not exist on generation 6. + if (gInfo->shared_info->device_type.Generation() <= 4) { + // This is "reserved" on G35 and GMA965, but needed on 945 (for which + // there is no public documentation), and I assume earlier devices as + // well. Note that the height and width are swapped when compared to + // the other registers. write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset, - ((uint32)(target->virtual_width - 1) << 16) - | ((uint32)target->virtual_height - 1)); + ((uint32)(target->virtual_height - 1) << 16) + | ((uint32)target->virtual_width - 1)); } if (fHasTranscoder && hardware) {