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intel_extreme: improve brightness setting support

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- Newer devices use a different layout for the backlight PWM registers
- Get the min brightness level from the BDB

Change-Id: I99745a022dd38733a4c2386f91c4c57016dd2acd
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5162
Reviewed-by: Jérôme Duval <[email protected]>
Tested-by: Commit checker robot <[email protected]>
This commit is contained in:
PulkoMandy
2022-04-03 08:39:47 +00:00
committed by Jérôme Duval
parent 83cb10bcbc
commit 890aa41134
6 changed files with 148 additions and 32 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+14 -3
View File
@@ -293,6 +293,7 @@ struct intel_shared_info {
uint32 bytes_per_row;
uint32 bits_per_pixel;
uint32 dpms_mode;
uint16 min_brightness;
area_id registers_area; // area of memory mapped registers
uint32 register_blocks[REGISTER_BLOCK_COUNT];
@@ -1178,11 +1179,21 @@ struct intel_free_graphics_memory {
#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
// Backlight control registers
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED)
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED)
#define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED)
// These have moved around, initially they were per pipe, then they were moved in the "north" part
// of the PCH with a single backlight control (independant of pipes), and then moved again to the
// "south" part of the PCH, with a simplified register layout.
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
// Devices after Cannonlake have a new register layout, with separate registers for the period
// and duty cycle instead of having two 16bit values in a 32bit register
#define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
#define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
#define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
#define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT)
// Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be
// programmed for use on either pipe)
// ring buffer commands
headers/private/graphics/intel_extreme/lock.h
+2 -2
View File
@@ -12,10 +12,10 @@
#include <OS.h>
typedef struct lock {
struct lock {
sem_id sem;
int32 count;
} lock;
};
static inline status_t