From 8dfc5dbb26e2eec03428fa97f0e6429b8fee4e1d Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Wed, 4 Apr 2012 10:40:59 -0500 Subject: [PATCH] radeon_hd: Complete move to common DisplayPort header * Non-spec DP stuff in accelerant displayport.h * Common DisplayPort header still has TODO's however --- headers/private/graphics/common/dp_raw.h | 46 ++++++++++++++- .../graphics/radeon_hd/displayport_reg.h | 58 ------------------- .../accelerants/radeon_hd/accelerant.h | 2 +- .../accelerants/radeon_hd/displayport.cpp | 25 ++++---- .../accelerants/radeon_hd/displayport.h | 3 +- 5 files changed, 59 insertions(+), 75 deletions(-) delete mode 100644 headers/private/graphics/radeon_hd/displayport_reg.h diff --git a/headers/private/graphics/common/dp_raw.h b/headers/private/graphics/common/dp_raw.h index 03501cb1ad..556c1b163b 100644 --- a/headers/private/graphics/common/dp_raw.h +++ b/headers/private/graphics/common/dp_raw.h @@ -149,7 +149,47 @@ /* *** DPCD Link / Sink Status Field (0x0200) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ -// TODO +// DP Sink Count (0x0200) +#define DP_SINK_COUNT 0x0200 // Reg +#define DP_SINK_COUNT_MASK (63 << 0) // Mask +#define DP_SINK_COUNT_CP_READY (1 << 6) // Bool +// DP Service IRQ Vector (0x0201) +#define DP_SINK_IRQ_VECTOR 0x0201 // Reg +#define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool +#define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool +#define DP_SINK_IRQ_VENDOR (1 << 6) // Bool +// DP Lane Status A B +#define DP_LANE_STATUS_0_1 0x0202 // Reg +#define DP_LANE_STATUS_2_3 0x0203 // Reg +#define DP_LINK_STATUS_SIZE 6 // Size +#define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool +#define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool +#define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool +#define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool +#define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool +#define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool +// DP Lane Align Status (0x0204) +#define DP_LANE_ALIGN 0x0204 // Reg +#define DP_LANE_ALIGN_DONE (1 << 0) // Bool +#define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool +#define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool +// DP Sink Status (0x0205) +#define DP_SINK_STATUS 0x0205 // Reg +#define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool +#define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool +// DP Adjust Request A B +#define DP_ADJ_REQUEST_0_1 0x0206 // Reg +#define DP_ADJ_REQUEST_2_3 0x0207 // Reg +#define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift +#define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask +#define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift +#define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask +#define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift +#define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask +#define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift +#define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask + +// TODO: 0x0210 - 0x0217 /* *** DPCD Automated Self-testing Field (0x0218) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ @@ -174,7 +214,9 @@ /* *** DPCD Sink Control Field (0x0600) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ -// TODO +#define DP_SET_POWER 0x0600 // Reg +#define DP_SET_POWER_D0 (1 << 0) // Value +#define DP_SET_POWER_D3 (1 << 1) // Value /* *** DPCD Reserved (0x0700+) *** */ /* ****************************************************** */ diff --git a/headers/private/graphics/radeon_hd/displayport_reg.h b/headers/private/graphics/radeon_hd/displayport_reg.h deleted file mode 100644 index c0b8b97117..0000000000 --- a/headers/private/graphics/radeon_hd/displayport_reg.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2011, Haiku, Inc. All Rights Reserved. - * Distributed under the terms of the MIT License. - * - * Authors: - * Alexander von Gluck, kallisti5@unixzen.com - * - * DisplayPort DRM Specifications: - * Copyright © 2008 Keith Packard - */ -#ifndef __DISPLAYPORT_REG_H__ -#define __DISPLAYPORT_REG_H__ - - -/* TODO: get access to DisplayPort specifications and - * place this into graphic private common code - */ - -#define DP_TPS3_SUPPORTED (1 << 6) - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -#define DP_LANE_CR_DONE (1 << 0) -#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -#define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE \ - | DP_LANE_CHANNEL_EQ_DONE \ - | DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) -#define DP_LINK_STATUS_SIZE 6 - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_SET_POWER 0x600 -#define DP_SET_POWER_D0 0x1 - - -#endif /*__DISPLAYPORT_REG_H__*/ diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.h b/src/add-ons/accelerants/radeon_hd/accelerant.h index ddc467a847..8da527dcf4 100644 --- a/src/add-ons/accelerants/radeon_hd/accelerant.h +++ b/src/add-ons/accelerants/radeon_hd/accelerant.h @@ -14,7 +14,7 @@ #include #include "atom.h" -#include "displayport_reg.h" +#include "dp_raw.h" #include "encoder.h" #include "mode.h" #include "pll.h" diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp b/src/add-ons/accelerants/radeon_hd/displayport.cpp index 0a75deb471..e114818c93 100644 --- a/src/add-ons/accelerants/radeon_hd/displayport.cpp +++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp @@ -13,7 +13,6 @@ #include "accelerant_protos.h" #include "connector.h" -#include "dp_raw.h" #include "mode.h" @@ -425,7 +424,7 @@ dp_setup_connectors() static bool dp_get_link_status(dp_info* dp) { - int result = dp_aux_read(dp->auxPin, DP_LANE0_1_STATUS, + int result = dp_aux_read(dp->auxPin, DP_LANE_STATUS_0_1, dp->linkStatus, DP_LINK_STATUS_SIZE, 100); if (result <= 0) { @@ -440,9 +439,9 @@ dp_get_link_status(dp_info* dp) static uint8 dp_get_lane_status(dp_info* dp, int lane) { - int i = DP_LANE0_1_STATUS + (lane >> 1); + int i = DP_LANE_STATUS_0_1 + (lane >> 1); int s = (lane & 1) * 4; - uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS]; + uint8 l = dp->linkStatus[i - DP_LANE_STATUS_0_1]; return (l >> s) & 0xf; } @@ -455,7 +454,7 @@ dp_clock_recovery_ok(dp_info* dp) for (lane = 0; lane < dp->laneCount; lane++) { laneStatus = dp_get_lane_status(dp, lane); - if ((laneStatus & DP_LANE_CR_DONE) == 0) + if ((laneStatus & DP_LANE_STATUS_CR_DONE_A) == 0) return false; } return true; @@ -478,10 +477,10 @@ dp_update_vs_emph(dp_info* dp) static uint8 dp_get_adjust_request_voltage(dp_info* dp, int lane) { - int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); - int s = (((lane & 1) != 0) ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT - : DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); - uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS]; + int i = DP_ADJ_REQUEST_0_1 + (lane >> 1); + int s = (((lane & 1) != 0) ? DP_ADJ_VCC_SWING_LANEB_SHIFT + : DP_ADJ_VCC_SWING_LANEA_SHIFT); + uint8 l = dp->linkStatus[i - DP_LANE_STATUS_0_1]; return ((l >> s) & 0x3) << DP_TRAIN_VCC_SWING_SHIFT; } @@ -490,10 +489,10 @@ dp_get_adjust_request_voltage(dp_info* dp, int lane) static uint8 dp_get_adjust_request_pre_emphasis(dp_info* dp, int lane) { - int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); - int s = (((lane & 1) != 0) ? DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT - : DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); - uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS]; + int i = DP_ADJ_REQUEST_0_1 + (lane >> 1); + int s = (((lane & 1) != 0) ? DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT + : DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT); + uint8 l = dp->linkStatus[i - DP_LANE_STATUS_0_1]; return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; } diff --git a/src/add-ons/accelerants/radeon_hd/displayport.h b/src/add-ons/accelerants/radeon_hd/displayport.h index c5fb60492f..4cfd3e8a9f 100644 --- a/src/add-ons/accelerants/radeon_hd/displayport.h +++ b/src/add-ons/accelerants/radeon_hd/displayport.h @@ -14,11 +14,12 @@ #include #include "accelerant.h" -#include "displayport_reg.h" +#include "dp_raw.h" // Radeon HD specific DisplayPort Configuration Data #define DP_TRAINING_AUX_RD_INTERVAL 0x000e +#define DP_TPS3_SUPPORTED (1 << 6) // Stored within MAX_LANE_COUNT int dp_aux_write(uint32 hwPin, uint16 address, uint8* send,