diff --git a/headers/private/graphics/radeon_hd/evergreen_reg.h b/headers/private/graphics/radeon_hd/evergreen_reg.h index 0cab35522c..9183414597 100644 --- a/headers/private/graphics/radeon_hd/evergreen_reg.h +++ b/headers/private/graphics/radeon_hd/evergreen_reg.h @@ -47,6 +47,14 @@ */ +#define EVERGREEN_HDP_HOST_PATH_CNTL 0x2C00 +#define EVERGREEN_HDP_NONSURFACE_BASE 0x2C04 +#define EVERGREEN_HDP_NONSURFACE_INFO 0x2C08 +#define EVERGREEN_HDP_NONSURFACE_SIZE 0x2C0C +#define EVERGREEN_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 +#define EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define EVERGREEN_HDP_TILING_CONFIG 0x2F3C + #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 #define EVERGREEN_D3VGA_CONTROL 0x3e0 diff --git a/headers/private/graphics/radeon_hd/r600_reg.h b/headers/private/graphics/radeon_hd/r600_reg.h index 2def1ce08a..5c27c01947 100644 --- a/headers/private/graphics/radeon_hd/r600_reg.h +++ b/headers/private/graphics/radeon_hd/r600_reg.h @@ -29,164 +29,173 @@ #define __R600_REG_H__ -#define R600_CRTC0_REGISTER_OFFSET 0x0 -#define R600_CRTC1_REGISTER_OFFSET 0x800 +/* Scratch Registers */ +#define R600_BIOS_0_SCRATCH 0x1724 +#define R600_BIOS_1_SCRATCH 0x1728 +#define R600_BIOS_2_SCRATCH 0x172c +#define R600_BIOS_3_SCRATCH 0x1730 +#define R600_BIOS_4_SCRATCH 0x1734 +#define R600_BIOS_5_SCRATCH 0x1738 +#define R600_BIOS_6_SCRATCH 0x173c +#define R600_BIOS_7_SCRATCH 0x1740 -#define R600_PCIE_PORT_INDEX 0x0038 -#define R600_PCIE_PORT_DATA 0x003c +#define R600_CRTC0_REGISTER_OFFSET 0x0 +#define R600_CRTC1_REGISTER_OFFSET 0x800 -#define R600_MC_VM_FB_LOCATION 0x2180 -#define R600_MC_FB_BASE_MASK 0x0000FFFF -#define R600_MC_FB_BASE_SHIFT 0 -#define R600_MC_FB_TOP_MASK 0xFFFF0000 -#define R600_MC_FB_TOP_SHIFT 16 -#define R600_MC_VM_AGP_TOP 0x2184 -#define R600_MC_AGP_TOP_MASK 0x0003FFFF -#define R600_MC_AGP_TOP_SHIFT 0 -#define R600_MC_VM_AGP_BOT 0x2188 -#define R600_MC_AGP_BOT_MASK 0x0003FFFF -#define R600_MC_AGP_BOT_SHIFT 0 -#define R600_MC_VM_AGP_BASE 0x218c -#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 -#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF -#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 +#define R600_PCIE_PORT_INDEX 0x0038 +#define R600_PCIE_PORT_DATA 0x003c + +#define R600_MC_VM_FB_LOCATION 0x2180 +#define R600_MC_FB_BASE_MASK 0x0000FFFF +#define R600_MC_FB_BASE_SHIFT 0 +#define R600_MC_FB_TOP_MASK 0xFFFF0000 +#define R600_MC_FB_TOP_SHIFT 16 +#define R600_MC_VM_AGP_TOP 0x2184 +#define R600_MC_AGP_TOP_MASK 0x0003FFFF +#define R600_MC_AGP_TOP_SHIFT 0 +#define R600_MC_VM_AGP_BOT 0x2188 +#define R600_MC_AGP_BOT_MASK 0x0003FFFF +#define R600_MC_AGP_BOT_SHIFT 0 +#define R600_MC_VM_AGP_BASE 0x218c +#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF +#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 -#define R600_RAMCFG 0x2408 -# define R600_CHANSIZE (1 << 7) -# define R600_CHANSIZE_OVERRIDE (1 << 10) +#define R600_RAMCFG 0x2408 +#define R600_CHANSIZE (1 << 7) +#define R600_CHANSIZE_OVERRIDE (1 << 10) -#define R600_GENERAL_PWRMGT 0x618 -# define R600_OPEN_DRAIN_PADS (1 << 11) +#define R600_GENERAL_PWRMGT 0x618 +#define R600_OPEN_DRAIN_PADS (1 << 11) -#define R600_LOWER_GPIO_ENABLE 0x710 -#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 -#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c -#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 -#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 +#define R600_LOWER_GPIO_ENABLE 0x710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 -#define R600_D1GRPH_SWAP_CONTROL 0x610C -# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) +#define R600_D1GRPH_SWAP_CONTROL 0x610C +#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) -#define R600_HDP_NONSURFACE_BASE 0x2c04 +#define R600_HDP_HOST_PATH_CNTL 0x2C00 +#define R600_HDP_NONSURFACE_BASE 0x2C04 +#define R600_HDP_NONSURFACE_INFO 0x2C08 +#define R600_HDP_NONSURFACE_SIZE 0x2C0C +#define R600_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define R600_HDP_TILING_CONFIG 0x2F3C +#define R600_HDP_DEBUG1 0x2F34 -#define R600_BUS_CNTL 0x5420 -# define R600_BIOS_ROM_DIS (1 << 1) -#define R600_CONFIG_CNTL 0x5424 -#define R600_CONFIG_MEMSIZE 0x5428 -#define R600_CONFIG_F0_BASE 0x542C -#define R600_CONFIG_APER_SIZE 0x5430 +#define R600_BUS_CNTL 0x5420 +#define R600_BIOS_ROM_DIS (1 << 1) +#define R600_CONFIG_CNTL 0x5424 +#define R600_CONFIG_MEMSIZE 0x5428 +#define R600_CONFIG_F0_BASE 0x542C +#define R600_CONFIG_APER_SIZE 0x5430 -#define R600_ROM_CNTL 0x1600 -# define R600_SCK_OVERWRITE (1 << 1) -# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 -# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) +#define R600_ROM_CNTL 0x1600 +#define R600_SCK_OVERWRITE (1 << 1) +#define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 +#define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) -#define R600_CG_SPLL_FUNC_CNTL 0x600 -# define R600_SPLL_BYPASS_EN (1 << 3) -#define R600_CG_SPLL_STATUS 0x60c -# define R600_SPLL_CHG_STATUS (1 << 1) +#define R600_CG_SPLL_FUNC_CNTL 0x600 +#define R600_SPLL_BYPASS_EN (1 << 3) +#define R600_CG_SPLL_STATUS 0x60c +#define R600_SPLL_CHG_STATUS (1 << 1) -#define R600_BIOS_0_SCRATCH 0x1724 -#define R600_BIOS_1_SCRATCH 0x1728 -#define R600_BIOS_2_SCRATCH 0x172c -#define R600_BIOS_3_SCRATCH 0x1730 -#define R600_BIOS_4_SCRATCH 0x1734 -#define R600_BIOS_5_SCRATCH 0x1738 -#define R600_BIOS_6_SCRATCH 0x173c -#define R600_BIOS_7_SCRATCH 0x1740 /* Audio, these regs were reverse enginered, * so the chance is high that the naming is wrong * R6xx+ ??? */ /* Audio clocks */ -#define R600_AUDIO_PLL1_MUL 0x0514 -#define R600_AUDIO_PLL1_DIV 0x0518 -#define R600_AUDIO_PLL2_MUL 0x0524 -#define R600_AUDIO_PLL2_DIV 0x0528 -#define R600_AUDIO_CLK_SRCSEL 0x0534 +#define R600_AUDIO_PLL1_MUL 0x0514 +#define R600_AUDIO_PLL1_DIV 0x0518 +#define R600_AUDIO_PLL2_MUL 0x0524 +#define R600_AUDIO_PLL2_DIV 0x0528 +#define R600_AUDIO_CLK_SRCSEL 0x0534 /* Audio general */ -#define R600_AUDIO_ENABLE 0x7300 -#define R600_AUDIO_TIMING 0x7344 +#define R600_AUDIO_ENABLE 0x7300 +#define R600_AUDIO_TIMING 0x7344 /* Audio params */ -#define R600_AUDIO_VENDOR_ID 0x7380 -#define R600_AUDIO_REVISION_ID 0x7384 -#define R600_AUDIO_ROOT_NODE_COUNT 0x7388 -#define R600_AUDIO_NID1_NODE_COUNT 0x738c -#define R600_AUDIO_NID1_TYPE 0x7390 -#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 -#define R600_AUDIO_SUPPORTED_CODEC 0x7398 -#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c -#define R600_AUDIO_NID2_CAPS 0x73a0 -#define R600_AUDIO_NID3_CAPS 0x73a4 -#define R600_AUDIO_NID3_PIN_CAPS 0x73a8 +#define R600_AUDIO_VENDOR_ID 0x7380 +#define R600_AUDIO_REVISION_ID 0x7384 +#define R600_AUDIO_ROOT_NODE_COUNT 0x7388 +#define R600_AUDIO_NID1_NODE_COUNT 0x738c +#define R600_AUDIO_NID1_TYPE 0x7390 +#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 +#define R600_AUDIO_SUPPORTED_CODEC 0x7398 +#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c +#define R600_AUDIO_NID2_CAPS 0x73a0 +#define R600_AUDIO_NID3_CAPS 0x73a4 +#define R600_AUDIO_NID3_PIN_CAPS 0x73a8 /* Audio conn list */ -#define R600_AUDIO_CONN_LIST_LEN 0x73ac -#define R600_AUDIO_CONN_LIST 0x73b0 +#define R600_AUDIO_CONN_LIST_LEN 0x73ac +#define R600_AUDIO_CONN_LIST 0x73b0 /* Audio verbs */ -#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 -#define R600_AUDIO_PLAYING 0x73c4 -#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 -#define R600_AUDIO_CONFIG_DEFAULT 0x73cc -#define R600_AUDIO_PIN_SENSE 0x73d0 -#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 -#define R600_AUDIO_STATUS_BITS 0x73d8 +#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 +#define R600_AUDIO_PLAYING 0x73c4 +#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 +#define R600_AUDIO_CONFIG_DEFAULT 0x73cc +#define R600_AUDIO_PIN_SENSE 0x73d0 +#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 +#define R600_AUDIO_STATUS_BITS 0x73d8 /* HDMI base register addresses */ -#define R600_HDMI_BLOCK1 0x7400 -#define R600_HDMI_BLOCK2 0x7700 -#define R600_HDMI_BLOCK3 0x7800 +#define R600_HDMI_BLOCK1 0x7400 +#define R600_HDMI_BLOCK2 0x7700 +#define R600_HDMI_BLOCK3 0x7800 /* HDMI registers */ -#define R600_HDMI_ENABLE 0x00 -#define R600_HDMI_STATUS 0x04 -# define R600_HDMI_INT_PENDING (1 << 29) -#define R600_HDMI_CNTL 0x08 -# define R600_HDMI_INT_EN (1 << 28) -# define R600_HDMI_INT_ACK (1 << 29) -#define R600_HDMI_UNKNOWN_0 0x0C -#define R600_HDMI_AUDIOCNTL 0x10 -#define R600_HDMI_VIDEOCNTL 0x14 -#define R600_HDMI_VERSION 0x18 -#define R600_HDMI_UNKNOWN_1 0x28 -#define R600_HDMI_VIDEOINFOFRAME_0 0x54 -#define R600_HDMI_VIDEOINFOFRAME_1 0x58 -#define R600_HDMI_VIDEOINFOFRAME_2 0x5c -#define R600_HDMI_VIDEOINFOFRAME_3 0x60 -#define R600_HDMI_32kHz_CTS 0xac -#define R600_HDMI_32kHz_N 0xb0 -#define R600_HDMI_44_1kHz_CTS 0xb4 -#define R600_HDMI_44_1kHz_N 0xb8 -#define R600_HDMI_48kHz_CTS 0xbc -#define R600_HDMI_48kHz_N 0xc0 -#define R600_HDMI_AUDIOINFOFRAME_0 0xcc -#define R600_HDMI_AUDIOINFOFRAME_1 0xd0 -#define R600_HDMI_IEC60958_1 0xd4 -#define R600_HDMI_IEC60958_2 0xd8 -#define R600_HDMI_UNKNOWN_2 0xdc -#define R600_HDMI_AUDIO_DEBUG_0 0xe0 -#define R600_HDMI_AUDIO_DEBUG_1 0xe4 -#define R600_HDMI_AUDIO_DEBUG_2 0xe8 -#define R600_HDMI_AUDIO_DEBUG_3 0xec +#define R600_HDMI_ENABLE 0x00 +#define R600_HDMI_STATUS 0x04 +#define R600_HDMI_INT_PENDING (1 << 29) +#define R600_HDMI_CNTL 0x08 +#define R600_HDMI_INT_EN (1 << 28) +#define R600_HDMI_INT_ACK (1 << 29) +#define R600_HDMI_UNKNOWN_0 0x0C +#define R600_HDMI_AUDIOCNTL 0x10 +#define R600_HDMI_VIDEOCNTL 0x14 +#define R600_HDMI_VERSION 0x18 +#define R600_HDMI_UNKNOWN_1 0x28 +#define R600_HDMI_VIDEOINFOFRAME_0 0x54 +#define R600_HDMI_VIDEOINFOFRAME_1 0x58 +#define R600_HDMI_VIDEOINFOFRAME_2 0x5c +#define R600_HDMI_VIDEOINFOFRAME_3 0x60 +#define R600_HDMI_32kHz_CTS 0xac +#define R600_HDMI_32kHz_N 0xb0 +#define R600_HDMI_44_1kHz_CTS 0xb4 +#define R600_HDMI_44_1kHz_N 0xb8 +#define R600_HDMI_48kHz_CTS 0xbc +#define R600_HDMI_48kHz_N 0xc0 +#define R600_HDMI_AUDIOINFOFRAME_0 0xcc +#define R600_HDMI_AUDIOINFOFRAME_1 0xd0 +#define R600_HDMI_IEC60958_1 0xd4 +#define R600_HDMI_IEC60958_2 0xd8 +#define R600_HDMI_UNKNOWN_2 0xdc +#define R600_HDMI_AUDIO_DEBUG_0 0xe0 +#define R600_HDMI_AUDIO_DEBUG_1 0xe4 +#define R600_HDMI_AUDIO_DEBUG_2 0xe8 +#define R600_HDMI_AUDIO_DEBUG_3 0xec /* HDMI additional config base register addresses */ -#define R600_HDMI_CONFIG1 0x7600 -#define R600_HDMI_CONFIG2 0x7a00 +#define R600_HDMI_CONFIG1 0x7600 +#define R600_HDMI_CONFIG2 0x7a00 /* Thermal information */ -#define R600_CG_THERMAL_STATUS 0x7F4 -#define R600_ASIC_T(x) ((x) << 0) -#define R600_ASIC_T_MASK 0x1FF -#define R600_ASIC_T_SHIFT 0 +#define R600_CG_THERMAL_STATUS 0x7F4 +#define R600_ASIC_T(x) ((x) << 0) +#define R600_ASIC_T_MASK 0x1FF +#define R600_ASIC_T_SHIFT 0 -#endif + +#endif /* __R600_REG_H__ */ \ No newline at end of file diff --git a/headers/private/graphics/radeon_hd/r700_reg.h b/headers/private/graphics/radeon_hd/r700_reg.h index 2e014df932..39ecf49f8c 100644 --- a/headers/private/graphics/radeon_hd/r700_reg.h +++ b/headers/private/graphics/radeon_hd/r700_reg.h @@ -24,191 +24,189 @@ * Alex Deucher * Jerome Glisse */ -#ifndef RV770_H -#define RV770_H +#ifndef R700_H +#define R700_H -#define R7XX_MAX_SH_GPRS 256 -#define R7XX_MAX_TEMP_GPRS 16 -#define R7XX_MAX_SH_THREADS 256 -#define R7XX_MAX_SH_STACK_ENTRIES 4096 -#define R7XX_MAX_BACKENDS 8 -#define R7XX_MAX_BACKENDS_MASK 0xff -#define R7XX_MAX_SIMDS 16 -#define R7XX_MAX_SIMDS_MASK 0xffff -#define R7XX_MAX_PIPES 8 -#define R7XX_MAX_PIPES_MASK 0xff +#define R700_MAX_SH_GPRS 256 +#define R700_MAX_TEMP_GPRS 16 +#define R700_MAX_SH_THREADS 256 +#define R700_MAX_SH_STACK_ENTRIES 4096 +#define R700_MAX_BACKENDS 8 +#define R700_MAX_BACKENDS_MASK 0xff +#define R700_MAX_SIMDS 16 +#define R700_MAX_SIMDS_MASK 0xffff +#define R700_MAX_PIPES 8 +#define R700_MAX_PIPES_MASK 0xff -#if 0 /* Registers */ -#define CB_COLOR0_BASE 0x28040 -#define CB_COLOR1_BASE 0x28044 -#define CB_COLOR2_BASE 0x28048 -#define CB_COLOR3_BASE 0x2804C -#define CB_COLOR4_BASE 0x28050 -#define CB_COLOR5_BASE 0x28054 -#define CB_COLOR6_BASE 0x28058 -#define CB_COLOR7_BASE 0x2805C -#define CB_COLOR7_FRAG 0x280FC +#define R700_CB_COLOR0_BASE 0x28040 +#define R700_CB_COLOR1_BASE 0x28044 +#define R700_CB_COLOR2_BASE 0x28048 +#define R700_CB_COLOR3_BASE 0x2804C +#define R700_CB_COLOR4_BASE 0x28050 +#define R700_CB_COLOR5_BASE 0x28054 +#define R700_CB_COLOR6_BASE 0x28058 +#define R700_CB_COLOR7_BASE 0x2805C +#define R700_CB_COLOR7_FRAG 0x280FC -#define CC_GC_SHADER_PIPE_CONFIG 0x8950 -#define CC_RB_BACKEND_DISABLE 0x98F4 -#define BACKEND_DISABLE(x) ((x) << 16) -#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 +#define R700_CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define R700_CC_RB_BACKEND_DISABLE 0x98F4 +#define R700_BACKEND_DISABLE(x) ((x) << 16) +#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3F88 -#define CGTS_SYS_TCC_DISABLE 0x3F90 -#define CGTS_TCC_DISABLE 0x9148 -#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 -#define CGTS_USER_TCC_DISABLE 0x914C +#define R700_CGTS_SYS_TCC_DISABLE 0x3F90 +#define R700_CGTS_TCC_DISABLE 0x9148 +#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3F94 +#define R700_CGTS_USER_TCC_DISABLE 0x914C -#define CP_ME_CNTL 0x86D8 -#define CP_ME_HALT (1<<28) -#define CP_PFP_HALT (1<<26) -#define CP_ME_RAM_DATA 0xC160 -#define CP_ME_RAM_RADDR 0xC158 -#define CP_ME_RAM_WADDR 0xC15C -#define CP_MEQ_THRESHOLDS 0x8764 -#define STQ_SPLIT(x) ((x) << 0) -#define CP_PERFMON_CNTL 0x87FC -#define CP_PFP_UCODE_ADDR 0xC150 -#define CP_PFP_UCODE_DATA 0xC154 -#define CP_QUEUE_THRESHOLDS 0x8760 -#define ROQ_IB1_START(x) ((x) << 0) -#define ROQ_IB2_START(x) ((x) << 8) -#define CP_DEBUG 0xC1FC -#define CP_RB_BASE 0xC100 -#define CP_RB_CNTL 0xC104 -#define RB_BUFSZ(x) ((x) << 0) -#define RB_BLKSZ(x) ((x) << 8) -#define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) -#define BUF_SWAP_32BIT (2 << 16) -#define CP_RB_RPTR 0x8700 -#define CP_RB_RPTR_ADDR 0xC10C -#define CP_RB_RPTR_ADDR_HI 0xC110 -#define CP_RB_RPTR_WR 0xC108 -#define CP_RB_WPTR 0xC114 -#define CP_RB_WPTR_ADDR 0xC118 -#define CP_RB_WPTR_ADDR_HI 0xC11C -#define CP_RB_WPTR_DELAY 0x8704 -#define CP_SEM_WAIT_TIMER 0x85BC +#define R700_CP_ME_CNTL 0x86D8 +#define R700_CP_ME_HALT (1<<28) +#define R700_CP_PFP_HALT (1<<26) +#define R700_CP_ME_RAM_DATA 0xC160 +#define R700_CP_ME_RAM_RADDR 0xC158 +#define R700_CP_ME_RAM_WADDR 0xC15C +#define R700_CP_MEQ_THRESHOLDS 0x8764 +#define STQ_SPLIT(x) ((x) << 0) +#define R700_CP_PERFMON_CNTL 0x87FC +#define R700_CP_PFP_UCODE_ADDR 0xC150 +#define R700_CP_PFP_UCODE_DATA 0xC154 +#define R700_CP_QUEUE_THRESHOLDS 0x8760 +#define R700_ROQ_IB1_START(x) ((x) << 0) +#define R700_ROQ_IB2_START(x) ((x) << 8) +#define R700_CP_DEBUG 0xC1FC +#define R700_CP_RB_BASE 0xC100 +#define R700_CP_RB_CNTL 0xC104 +#define R700_RB_BUFSZ(x) ((x) << 0) +#define R700_RB_BLKSZ(x) ((x) << 8) +#define R700_RB_NO_UPDATE (1 << 27) +#define R700_RB_RPTR_WR_ENA (1 << 31) +#define R700_BUF_SWAP_32BIT (2 << 16) +#define R700_CP_RB_RPTR 0x8700 +#define R700_CP_RB_RPTR_ADDR 0xC10C +#define R700_CP_RB_RPTR_ADDR_HI 0xC110 +#define R700_CP_RB_RPTR_WR 0xC108 +#define R700_CP_RB_WPTR 0xC114 +#define R700_CP_RB_WPTR_ADDR 0xC118 +#define R700_CP_RB_WPTR_ADDR_HI 0xC11C +#define R700_CP_RB_WPTR_DELAY 0x8704 +#define R700_CP_SEM_WAIT_TIMER 0x85BC -#define DB_DEBUG3 0x98B0 -#define DB_CLK_OFF_DELAY(x) ((x) << 11) -#define DB_DEBUG4 0x9B8C -#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) +#define R700_DB_DEBUG3 0x98B0 +#define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) +#define R700_DB_DEBUG 0x9B8C +#define R700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) -#define DCP_TILING_CONFIG 0x6CA0 -#define PIPE_TILING(x) ((x) << 1) -#define BANK_TILING(x) ((x) << 4) -#define GROUP_SIZE(x) ((x) << 6) -#define ROW_TILING(x) ((x) << 8) -#define BANK_SWAPS(x) ((x) << 11) -#define SAMPLE_SPLIT(x) ((x) << 14) -#define BACKEND_MAP(x) ((x) << 16) +#define R700_DCP_TILING_CONFIG 0x6CA0 +#define R700_PIPE_TILING(x) ((x) << 1) +#define R700_BANK_TILING(x) ((x) << 4) +#define R700_GROUP_SIZE(x) ((x) << 6) +#define R700_ROW_TILING(x) ((x) << 8) +#define R700_BANK_SWAPS(x) ((x) << 11) +#define R700_SAMPLE_SPLIT(x) ((x) << 14) +#define R700_BACKEND_MAP(x) ((x) << 16) -#define GB_TILING_CONFIG 0x98F0 +#define R700_GB_TILING_CONFIG 0x98F0 -#define GC_USER_SHADER_PIPE_CONFIG 0x8954 -#define INACTIVE_QD_PIPES(x) ((x) << 8) -#define INACTIVE_QD_PIPES_MASK 0x0000FF00 -#define INACTIVE_SIMDS(x) ((x) << 16) -#define INACTIVE_SIMDS_MASK 0x00FF0000 +#define R700_GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define R700_INACTIVE_QD_PIPES(x) ((x) << 8) +#define R700_INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define R700_INACTIVE_SIMDS(x) ((x) << 16) +#define R700_INACTIVE_SIMDS_MASK 0x00FF0000 -#define GRBM_CNTL 0x8000 -#define GRBM_READ_TIMEOUT(x) ((x) << 0) -#define GRBM_SOFT_RESET 0x8020 -#define SOFT_RESET_CP (1<<0) -#define GRBM_STATUS 0x8010 -#define CMDFIFO_AVAIL_MASK 0x0000000F -#define GUI_ACTIVE (1<<31) -#define GRBM_STATUS2 0x8014 -#endif +#define R700_GRBM_CNTL 0x8000 +#define R700_GRBM_READ_TIMEOUT(x) ((x) << 0) +#define R700_GRBM_SOFT_RESET 0x8020 +#define R700_SOFT_RESET_CP (1<<0) +#define R700_GRBM_STATUS 0x8010 +#define R700_CMDFIFO_AVAIL_MASK 0x0000000F +#define R700_GUI_ACTIVE (1<<31) +#define R700_GRBM_STATUS2 0x8014 -#define R700_CG_MULT_THERMAL_STATUS 0x740 -#define R700_ASIC_T(x) ((x) << 16) -#define R700_ASIC_T_MASK 0x3FF0000 -#define R700_ASIC_T_SHIFT 16 +#define R700_CG_MULT_THERMAL_STATUS 0x740 +#define R700_ASIC_T(x) ((x) << 16) +#define R700_ASIC_T_MASK 0x3FF0000 +#define R700_ASIC_T_SHIFT 16 -#define HDP_HOST_PATH_CNTL 0x2C00 -#define HDP_NONSURFACE_BASE 0x2C04 -#define HDP_NONSURFACE_INFO 0x2C08 -#define HDP_NONSURFACE_SIZE 0x2C0C -#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 -#define HDP_TILING_CONFIG 0x2F3C -#define HDP_DEBUG1 0x2F34 +#define R700_HDP_HOST_PATH_CNTL 0x2C00 +#define R700_HDP_NONSURFACE_BASE 0x2C04 +#define R700_HDP_NONSURFACE_INFO 0x2C08 +#define R700_HDP_NONSURFACE_SIZE 0x2C0C +#define R700_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define R700_HDP_TILING_CONFIG 0x2F3C +#define R700_HDP_DEBUG1 0x2F34 #define R700_MC_SHARED_CHMAP 0x2004 -#define NOOFCHAN_SHIFT 12 -#define NOOFCHAN_MASK 0x00003000 +#define R700_NOOFCHAN_SHIFT 12 +#define R700_NOOFCHAN_MASK 0x00003000 #define R700_MC_SHARED_CHREMAP 0x2008 #define R700_MC_ARB_RAMCFG 0x2760 -#define NOOFBANK_SHIFT 0 -#define NOOFBANK_MASK 0x00000003 -#define NOOFRANK_SHIFT 2 -#define NOOFRANK_MASK 0x00000004 -#define NOOFROWS_SHIFT 3 -#define NOOFROWS_MASK 0x00000038 -#define NOOFCOLS_SHIFT 6 -#define NOOFCOLS_MASK 0x000000C0 -#define CHANSIZE_SHIFT 8 -#define CHANSIZE_MASK 0x00000100 -#define BURSTLENGTH_SHIFT 9 -#define BURSTLENGTH_MASK 0x00000200 -#define CHANSIZE_OVERRIDE (1 << 11) +#define R700_NOOFBANK_SHIFT 0 +#define R700_NOOFBANK_MASK 0x00000003 +#define R700_NOOFRANK_SHIFT 2 +#define R700_NOOFRANK_MASK 0x00000004 +#define R700_NOOFROWS_SHIFT 3 +#define R700_NOOFROWS_MASK 0x00000038 +#define R700_NOOFCOLS_SHIFT 6 +#define R700_NOOFCOLS_MASK 0x000000C0 +#define R700_CHANSIZE_SHIFT 8 +#define R700_CHANSIZE_MASK 0x00000100 +#define R700_BURSTLENGTH_SHIFT 9 +#define R700_BURSTLENGTH_MASK 0x00000200 +#define R700_CHANSIZE_OVERRIDE (1 << 11) #define R700_MC_VM_AGP_TOP 0x2028 #define R700_MC_VM_AGP_BOT 0x202C #define R700_MC_VM_AGP_BASE 0x2030 #define R700_MC_VM_FB_LOCATION 0x2024 -#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 -#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 -#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C -#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 -#define ENABLE_L1_TLB (1 << 0) -#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) -#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) -#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) -#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) -#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) -#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) -#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) -#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) +#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 +#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 +#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C +#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 +#define R700_ENABLE_L1_TLB (1 << 0) +#define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define R700_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) +#define R700_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) +#define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) +#define R700_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) +#define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) +#define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) +#define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C -#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C -#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 -#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 +#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C +#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 +#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 -#define PA_CL_ENHANCE 0x8A14 -#define CLIP_VTX_REORDER_ENA (1 << 0) -#define NUM_CLIP_SEQ(x) ((x) << 1) -#define PA_SC_AA_CONFIG 0x28C04 -#define PA_SC_CLIPRECT_RULE 0x2820C -#define PA_SC_EDGERULE 0x28230 -#define PA_SC_FIFO_SIZE 0x8BCC -#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) -#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) -#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 -#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) -#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) -#define PA_SC_LINE_STIPPLE 0x28A0C -#define PA_SC_LINE_STIPPLE_STATE 0x8B10 -#define PA_SC_MODE_CNTL 0x28A4C -#define PA_SC_MULTI_CHIP_CNTL 0x8B20 -#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) +#define R700_PA_CL_ENHANCE 0x8A14 +#define R700_CLIP_VTX_REORDER_ENA (1 << 0) +#define R700_NUM_CLIP_SEQ(x) ((x) << 1) +#define R700_PA_SC_AA_CONFIG 0x28C04 +#define R700_PA_SC_CLIPRECT_RULE 0x2820C +#define R700_PA_SC_EDGERULE 0x28230 +#define R700_PA_SC_FIFO_SIZE 0x8BCC +#define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) +#define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) +#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 +#define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) +#define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) +#define R700_PA_SC_LINE_STIPPLE 0x28A0C +#define R700_PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define R700_PA_SC_MODE_CNTL 0x28A4C +#define R700_PA_SC_MULTI_CHIP_CNTL 0x8B20 +#define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) -#define R700_SCRATCH_REG0 0x8500 -#define R700_SCRATCH_REG1 0x8504 -#define R700_SCRATCH_REG2 0x8508 -#define R700_SCRATCH_REG3 0x850C -#define R700_SCRATCH_REG4 0x8510 -#define R700_SCRATCH_REG5 0x8514 -#define R700_SCRATCH_REG6 0x8518 -#define R700_SCRATCH_REG7 0x851C -#define R700_SCRATCH_UMSK 0x8540 -#define R700_SCRATCH_ADDR 0x8544 +#define R700_SCRATCH_REG0 0x8500 +#define R700_SCRATCH_REG1 0x8504 +#define R700_SCRATCH_REG2 0x8508 +#define R700_SCRATCH_REG3 0x850C +#define R700_SCRATCH_REG4 0x8510 +#define R700_SCRATCH_REG5 0x8514 +#define R700_SCRATCH_REG6 0x8518 +#define R700_SCRATCH_REG7 0x851C +#define R700_SCRATCH_UMSK 0x8540 +#define R700_SCRATCH_ADDR 0x8544 #if 0 #define SMX_DC_CTL0 0xA020 @@ -358,49 +356,50 @@ #define SRBM_STATUS 0x0E50 #endif -#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 -#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 -#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 -#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 -#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c -#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c +#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 +#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 +#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c +#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c /* PCIE link stuff */ -#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ -#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ -# define LC_LINK_WIDTH_SHIFT 0 -# define LC_LINK_WIDTH_MASK 0x7 -# define LC_LINK_WIDTH_X0 0 -# define LC_LINK_WIDTH_X1 1 -# define LC_LINK_WIDTH_X2 2 -# define LC_LINK_WIDTH_X4 3 -# define LC_LINK_WIDTH_X8 4 -# define LC_LINK_WIDTH_X16 6 -# define LC_LINK_WIDTH_RD_SHIFT 4 -# define LC_LINK_WIDTH_RD_MASK 0x70 -# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) -# define LC_RECONFIG_NOW (1 << 8) -# define LC_RENEGOTIATION_SUPPORT (1 << 9) -# define LC_RENEGOTIATE_EN (1 << 10) -# define LC_SHORT_RECONFIG_EN (1 << 11) -# define LC_UPCONFIGURE_SUPPORT (1 << 12) -# define LC_UPCONFIGURE_DIS (1 << 13) -#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ -# define LC_GEN2_EN_STRAP (1 << 0) -# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) -# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) -# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) -# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) -# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 -# define LC_CURRENT_DATA_RATE (1 << 11) -# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) -# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) -# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) -# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) -#define MM_CFGREGS_CNTL 0x544c -# define MM_WR_TO_CFG_EN (1 << 3) -#define LINK_CNTL2 0x88 /* F0 */ -# define TARGET_LINK_SPEED_MASK (0xf << 0) -# define SELECTABLE_DEEMPHASIS (1 << 6) +#define R700_PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ +#define R700_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ +#define R700_LC_LINK_WIDTH_SHIFT 0 +#define R700_LC_LINK_WIDTH_MASK 0x7 +#define R700_LC_LINK_WIDTH_X0 0 +#define R700_LC_LINK_WIDTH_X1 1 +#define R700_LC_LINK_WIDTH_X2 2 +#define R700_LC_LINK_WIDTH_X4 3 +#define R700_LC_LINK_WIDTH_X8 4 +#define R700_LC_LINK_WIDTH_X16 6 +#define R700_LC_LINK_WIDTH_RD_SHIFT 4 +#define R700_LC_LINK_WIDTH_RD_MASK 0x70 +#define R700_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) +#define R700_LC_RECONFIG_NOW (1 << 8) +#define R700_LC_RENEGOTIATION_SUPPORT (1 << 9) +#define R700_LC_RENEGOTIATE_EN (1 << 10) +#define R700_LC_SHORT_RECONFIG_EN (1 << 11) +#define R700_LC_UPCONFIGURE_SUPPORT (1 << 12) +#define R700_LC_UPCONFIGURE_DIS (1 << 13) +#define R700_PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ +#define R700_LC_GEN2_EN_STRAP (1 << 0) +#define R700_LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) +#define R700_LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) +#define R700_LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) +#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) +#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 +#define R700_LC_CURRENT_DATA_RATE (1 << 11) +#define R700_LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) +#define R700_LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) +#define R700_LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) +#define R700_LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) +#define R700_MM_CFGREGS_CNTL 0x544c +#define R700_MM_WR_TO_CFG_EN (1 << 3) +#define R700_LINK_CNTL2 0x88 /* F0 */ +#define R700_TARGET_LINK_SPEED_MASK (0xf << 0) +#define R700_SELECTABLE_DEEMPHASIS (1 << 6) -#endif + +#endif /* R700_H */ \ No newline at end of file diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp b/src/add-ons/accelerants/radeon_hd/display.cpp index 47e8a32fed..a175adffbd 100644 --- a/src/add-ons/accelerants/radeon_hd/display.cpp +++ b/src/add-ons/accelerants/radeon_hd/display.cpp @@ -116,13 +116,13 @@ init_registers(register_info* regs, uint8 crtcID) offset = R600_CRTC0_REGISTER_OFFSET; regs->vgaControl = AVIVO_D1VGA_CONTROL; regs->grphPrimarySurfaceAddrHigh - = D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + = R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; break; case 1: offset = R600_CRTC1_REGISTER_OFFSET; regs->vgaControl = AVIVO_D2VGA_CONTROL; regs->grphPrimarySurfaceAddrHigh - = D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + = R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; break; default: ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", @@ -137,9 +137,9 @@ init_registers(register_info* regs, uint8 crtcID) regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset; regs->grphPrimarySurfaceAddr - = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; + = R700_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; regs->grphSecondarySurfaceAddr - = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; + = R700_D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; regs->grphPitch = AVIVO_D1GRPH_PITCH + offset; regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset; diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp b/src/add-ons/accelerants/radeon_hd/gpu.cpp index 14afe5fda0..ecd60a1dc2 100644 --- a/src/add-ons/accelerants/radeon_hd/gpu.cpp +++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp @@ -262,7 +262,7 @@ radeon_gpu_mc_setup_r600() Write32(OUT, (0x2c20 + j), 0x00000000); Write32(OUT, (0x2c24 + j), 0x00000000); } - Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0); + Write32(OUT, R600_HDP_REG_COHERENCY_FLUSH_CNTL, 0); // idle the memory controller struct gpu_state gpuState; @@ -282,9 +282,9 @@ radeon_gpu_mc_setup_r600() tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF); Write32(OUT, R600_MC_VM_FB_LOCATION, tmp); - Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); - Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7)); - Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF); + Write32(OUT, R600_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); + Write32(OUT, R600_HDP_NONSURFACE_INFO, (2 << 7)); + Write32(OUT, R600_HDP_NONSURFACE_SIZE, 0x3FFFFFFF); // is AGP? // Write32(OUT, R600_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22); @@ -322,7 +322,7 @@ radeon_gpu_mc_setup_r700() } // On r7xx read from HDP_DEBUG1 vs write HDP_REG_COHERENCY_FLUSH_CNTL - Read32(OUT, HDP_DEBUG1); + Read32(OUT, R700_HDP_DEBUG1); // idle the memory controller struct gpu_state gpuState; @@ -344,9 +344,9 @@ radeon_gpu_mc_setup_r700() tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF); Write32(OUT, R700_MC_VM_FB_LOCATION, tmp); - Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); - Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7)); - Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF); + Write32(OUT, R700_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); + Write32(OUT, R700_HDP_NONSURFACE_INFO, (2 << 7)); + Write32(OUT, R700_HDP_NONSURFACE_SIZE, 0x3FFFFFFF); // is AGP? // Write32(OUT, R700_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22); @@ -382,7 +382,7 @@ radeon_gpu_mc_setup_evergreen() Write32(OUT, (0x2c20 + j), 0x00000000); Write32(OUT, (0x2c24 + j), 0x00000000); } - Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0); + Write32(OUT, EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL, 0); // idle the memory controller struct gpu_state gpuState; @@ -415,9 +415,9 @@ radeon_gpu_mc_setup_evergreen() tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF); Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp); - Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); - Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); - Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF); + Write32(OUT, EVERGREEN_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8)); + Write32(OUT, EVERGREEN_HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + Write32(OUT, EVERGREEN_HDP_NONSURFACE_SIZE, 0x3FFFFFFF); // is AGP? // Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 16); diff --git a/src/add-ons/accelerants/radeon_hd/gpu.h b/src/add-ons/accelerants/radeon_hd/gpu.h index 73772194be..d9586c9ae1 100644 --- a/src/add-ons/accelerants/radeon_hd/gpu.h +++ b/src/add-ons/accelerants/radeon_hd/gpu.h @@ -14,12 +14,6 @@ #include -#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 -#define HDP_NONSURFACE_BASE 0x2C04 -#define HDP_NONSURFACE_INFO 0x2C08 -#define HDP_NONSURFACE_SIZE 0x2C0C - - // GPU Control registers. These are combined as // the registers exist on all models, some flags // are different though and are commented as such