Complete code for DIG transmitter control
* Record external clock frequency (aka, DP non-pll) * Add function to control DIG transmitter * Cleanup duplicated is external code in encoder mode set
This commit is contained in:
Alexander von Gluck IV
@@ -282,60 +282,46 @@ encoder_mode_set(uint8 id, uint32 pixelClock)
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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if (info.dceMajor >= 4) {
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if (info.dceMajor >= 4) {
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//atombios_dig_transmitter_setup(encoder,
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// Disable DIG transmitter
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// ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
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transmitter_dig_setup(connectorIndex, pixelClock, 0, 0,
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// TODO: Disable the dig transmitter
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ATOM_TRANSMITTER_ACTION_DISABLE);
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// Setup DIG encoder
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encoder_dig_setup(connectorIndex, pixelClock,
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encoder_dig_setup(connectorIndex, pixelClock,
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ATOM_ENCODER_CMD_SETUP);
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ATOM_ENCODER_CMD_SETUP);
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// Setup and enable the dig encoder
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// Enable DIG transmitter
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transmitter_dig_setup(connectorIndex, pixelClock, 0, 0,
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//atombios_dig_transmitter_setup(encoder,
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ATOM_TRANSMITTER_ACTION_ENABLE);
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// ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
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// TODO: Enable the dig transmitter
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} else {
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} else {
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//atombios_dig_transmitter_setup(encoder,
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// Disable DIG transmitter
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// ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
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transmitter_dig_setup(connectorIndex, pixelClock, 0, 0,
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// Disable the dig transmitter
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ATOM_TRANSMITTER_ACTION_DISABLE);
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// Disable DIG encoder
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encoder_dig_setup(connectorIndex, pixelClock, ATOM_DISABLE);
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encoder_dig_setup(connectorIndex, pixelClock, ATOM_DISABLE);
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// Disable the dig encoder
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// Enable the DIG encoder
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/* setup and enable the encoder and transmitter */
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encoder_dig_setup(connectorIndex, pixelClock, ATOM_ENABLE);
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encoder_dig_setup(connectorIndex, pixelClock, ATOM_ENABLE);
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// Setup and enable the dig encoder
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//atombios_dig_transmitter_setup(encoder,
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// Setup and enable DIG transmitter
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// ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
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transmitter_dig_setup(connectorIndex, pixelClock, 0, 0,
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//atombios_dig_transmitter_setup(encoder,
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ATOM_TRANSMITTER_ACTION_SETUP);
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// ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
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transmitter_dig_setup(connectorIndex, pixelClock, 0, 0,
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// TODO: Setup and Enable the dig transmitter
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ATOM_TRANSMITTER_ACTION_ENABLE);
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}
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}
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TRACE("%s: TODO for DIG encoder setup\n", __func__);
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break;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_DDI:
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case ENCODER_OBJECT_ID_INTERNAL_DDI:
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case ENCODER_OBJECT_ID_INTERNAL_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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TRACE("%s: TODO for DVO encoder setup\n", __func__);
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TRACE("%s: TODO for DVO encoder setup\n", __func__);
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break;
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break;
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case ENCODER_OBJECT_ID_TRAVIS: // external DP -> LVDS encoder
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}
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case ENCODER_OBJECT_ID_NUTMEG: // external DP -> VGA encoder
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case ENCODER_OBJECT_ID_SI170B:
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if (gConnector[connectorIndex]->encoder.isExternal == true) {
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case ENCODER_OBJECT_ID_CH7303:
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if (info.dceMajor >= 4 && info.dceMinor >= 1) {
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case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
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encoder_external_setup(connectorIndex, pixelClock,
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case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
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EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
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case ENCODER_OBJECT_ID_TITFP513:
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} else {
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case ENCODER_OBJECT_ID_VT1623:
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encoder_external_setup(connectorIndex, pixelClock,
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case ENCODER_OBJECT_ID_HDMI_SI1930:
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ATOM_ENABLE);
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if (info.dceMajor >= 4 && info.dceMinor >= 1) {
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}
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encoder_external_setup(connectorIndex, pixelClock,
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EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
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} else {
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encoder_external_setup(connectorIndex, pixelClock,
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ATOM_ENABLE);
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}
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break;
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default:
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TRACE("%s: TODO for unknown encoder setup!\n", __func__);
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}
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}
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encoder_apply_quirks(id);
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encoder_apply_quirks(id);
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@@ -950,6 +936,349 @@ encoder_analog_load_detect(uint32 connectorIndex)
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}
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}
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status_t
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transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
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uint8 laneNumber, uint8 laneSet, int command)
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{
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uint16 encoderID = gConnector[connectorIndex]->encoder.objectID;
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int index;
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switch (encoderID) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
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break;
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default:
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ERROR("%s: called on non-dig encoder!\n", __func__);
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return B_ERROR;
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}
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uint8 tableMajor;
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uint8 tableMinor;
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if (atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor)
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!= B_OK)
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return B_ERROR;
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// Prepare AtomBIOS arguments
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union digTransmitterControl {
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DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
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};
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union digTransmitterControl args;
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memset(&args, 0, sizeof(args));
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int connectorObjectID
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= (gConnector[connectorIndex]->objectID & OBJECT_ID_MASK)
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>> OBJECT_ID_SHIFT;
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uint32 encoderObjectID = gConnector[connectorIndex]->encoder.objectID;
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uint32 digEncoderID = encoder_pick_dig(connectorIndex);
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pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
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bool isDP = connector_is_dp(connectorIndex);
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bool linkB = gConnector[connectorIndex]->encoder.linkEnumeration
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== GRAPH_OBJECT_ENUM_ID2 ? true : false;
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uint8 dpClock = 0;
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int dpLaneCount = 0;
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if (gDPInfo[connectorIndex]->valid == true) {
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dpClock = gDPInfo[connectorIndex]->clock;
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dpLaneCount = gDPInfo[connectorIndex]->laneCount;
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}
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switch (tableMajor) {
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case 1:
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switch (tableMinor) {
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case 1:
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args.v1.ucAction = command;
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if (command == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v1.usInitInfo
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= B_HOST_TO_LENDIAN_INT16(connectorObjectID);
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} else if (command
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== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v1.asMode.ucLaneSel = laneNumber;
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args.v1.asMode.ucLaneSet = laneSet;
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} else {
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if (isDP) {
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args.v1.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(dpClock / 10);
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} else if (pixelClock > 165000) {
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args.v1.usPixelClock = B_HOST_TO_LENDIAN_INT16(
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(pixelClock / 2) / 10);
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} else {
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args.v1.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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}
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}
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args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
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if (digEncoderID > 0) {
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
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} else {
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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}
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// TODO: IGP DIG Transmitter setup
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#if 0
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if ((rdev->flags & RADEON_IS_IGP) && (encoderObjectID
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== ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
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if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
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if (igp_lane_info & 0x1)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else if (igp_lane_info & 0x2)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
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else if (igp_lane_info & 0x4)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
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else if (igp_lane_info & 0x8)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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} else {
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if (igp_lane_info & 0x3)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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else if (igp_lane_info & 0xc)
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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}
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}
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#endif
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if (linkB == true)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
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if (isDP)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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else if ((gConnector[connectorIndex]->encoder.flags
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& ATOM_DEVICE_DFP_SUPPORT) != 0) {
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if (1) {
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// if coherentMode, i've only ever seen it true
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_COHERENT;
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}
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if (pixelClock > 165000) {
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args.v1.ucConfig
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|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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}
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}
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break;
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case 2:
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args.v2.ucAction = command;
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if (command == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v2.usInitInfo
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= B_HOST_TO_LENDIAN_INT16(connectorObjectID);
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} else if (command
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== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v2.asMode.ucLaneSel = laneNumber;
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args.v2.asMode.ucLaneSet = laneSet;
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} else {
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if (isDP) {
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args.v2.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(dpClock / 10);
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} else if (pixelClock > 165000) {
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args.v2.usPixelClock = B_HOST_TO_LENDIAN_INT16(
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(pixelClock / 2) / 10);
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} else {
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args.v2.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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}
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}
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args.v2.acConfig.ucEncoderSel = digEncoderID;
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if (linkB)
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args.v2.acConfig.ucLinkSel = 1;
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switch (encoderObjectID) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v2.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v2.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v2.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (isDP) {
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args.v2.acConfig.fCoherentMode = 1;
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args.v2.acConfig.fDPConnector = 1;
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} else if ((gConnector[connectorIndex]->encoder.flags
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& ATOM_DEVICE_DFP_SUPPORT) != 0) {
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if (1) {
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// if coherentMode, i've only ever seen it true
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args.v2.acConfig.fCoherentMode = 1;
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}
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if (pixelClock > 165000)
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args.v2.acConfig.fDualLinkConnector = 1;
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}
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break;
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case 3:
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args.v3.ucAction = command;
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if (command == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v3.usInitInfo
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= B_HOST_TO_LENDIAN_INT16(connectorObjectID);
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} else if (command
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== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v3.asMode.ucLaneSel = laneNumber;
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args.v3.asMode.ucLaneSet = laneSet;
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} else {
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if (isDP) {
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args.v3.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(dpClock / 10);
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} else if (pixelClock > 165000) {
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args.v3.usPixelClock = B_HOST_TO_LENDIAN_INT16(
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(pixelClock / 2) / 10);
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} else {
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args.v3.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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}
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}
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if (isDP)
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args.v3.ucLaneNum = dpLaneCount;
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else if (pixelClock > 165000)
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args.v3.ucLaneNum = 8;
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else
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args.v3.ucLaneNum = 4;
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if (linkB == true)
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args.v3.acConfig.ucLinkSel = 1;
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if (digEncoderID & 1)
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args.v3.acConfig.ucEncoderSel = 1;
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// Select the PLL for the PHY
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// DP PHY to be clocked from external src if possible
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if (isDP && pll->dpExternalClock) {
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// use external clock source
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args.v3.acConfig.ucRefClkSource = 2;
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} else
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args.v3.acConfig.ucRefClkSource = pll->id;
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switch (encoderObjectID) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v3.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v3.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v3.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (isDP)
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args.v3.acConfig.fCoherentMode = 1;
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else if ((gConnector[connectorIndex]->encoder.flags
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& ATOM_DEVICE_DFP_SUPPORT) != 0) {
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if (1) {
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// if coherentMode, i've only ever seen it true
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args.v3.acConfig.fCoherentMode = 1;
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}
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if (pixelClock > 165000)
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args.v3.acConfig.fDualLinkConnector = 1;
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}
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break;
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case 4:
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args.v4.ucAction = command;
|
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if (command == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v4.usInitInfo
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= B_HOST_TO_LENDIAN_INT16(connectorObjectID);
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} else if (command
|
||||||
|
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
|
||||||
|
args.v4.asMode.ucLaneSel = laneNumber;
|
||||||
|
args.v4.asMode.ucLaneSet = laneSet;
|
||||||
|
} else {
|
||||||
|
if (isDP) {
|
||||||
|
args.v4.usPixelClock
|
||||||
|
= B_HOST_TO_LENDIAN_INT16(dpClock / 10);
|
||||||
|
} else if (pixelClock > 165000) {
|
||||||
|
args.v4.usPixelClock = B_HOST_TO_LENDIAN_INT16(
|
||||||
|
(pixelClock / 2) / 10);
|
||||||
|
} else {
|
||||||
|
args.v4.usPixelClock
|
||||||
|
= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isDP)
|
||||||
|
args.v4.ucLaneNum = dpLaneCount;
|
||||||
|
else if (pixelClock > 165000)
|
||||||
|
args.v4.ucLaneNum = 8;
|
||||||
|
else
|
||||||
|
args.v4.ucLaneNum = 4;
|
||||||
|
|
||||||
|
if (linkB == true)
|
||||||
|
args.v4.acConfig.ucLinkSel = 1;
|
||||||
|
if (digEncoderID & 1)
|
||||||
|
args.v4.acConfig.ucEncoderSel = 1;
|
||||||
|
|
||||||
|
// Select the PLL for the PHY
|
||||||
|
// DP PHY to be clocked from external src if possible
|
||||||
|
if (isDP) {
|
||||||
|
if (pll->dpExternalClock > 0) {
|
||||||
|
args.v4.acConfig.ucRefClkSource
|
||||||
|
= ENCODER_REFCLK_SRC_EXTCLK;
|
||||||
|
} else {
|
||||||
|
args.v4.acConfig.ucRefClkSource
|
||||||
|
= ENCODER_REFCLK_SRC_DCPLL;
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
args.v4.acConfig.ucRefClkSource = pll->id;
|
||||||
|
|
||||||
|
switch (encoderObjectID) {
|
||||||
|
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
|
||||||
|
args.v4.acConfig.ucTransmitterSel = 0;
|
||||||
|
break;
|
||||||
|
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
|
||||||
|
args.v4.acConfig.ucTransmitterSel = 1;
|
||||||
|
break;
|
||||||
|
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
|
||||||
|
args.v4.acConfig.ucTransmitterSel = 2;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isDP)
|
||||||
|
args.v4.acConfig.fCoherentMode = 1;
|
||||||
|
else if ((gConnector[connectorIndex]->encoder.flags
|
||||||
|
& ATOM_DEVICE_DFP_SUPPORT) != 0) {
|
||||||
|
if (1) {
|
||||||
|
// if coherentMode, i've only ever seen it true
|
||||||
|
args.v4.acConfig.fCoherentMode = 1;
|
||||||
|
}
|
||||||
|
if (pixelClock > 165000)
|
||||||
|
args.v4.acConfig.fDualLinkConnector = 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
ERROR("%s: unknown table version\n", __func__);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
ERROR("%s: unknown table version\n", __func__);
|
||||||
|
}
|
||||||
|
|
||||||
|
return atom_execute_table(gAtomContext, index, (uint32*)&args);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void
|
void
|
||||||
encoder_crtc_scratch(uint8 crtcID)
|
encoder_crtc_scratch(uint8 crtcID)
|
||||||
{
|
{
|
||||||
|
|||||||
@@ -30,6 +30,8 @@ status_t encoder_tv_setup(uint32 connectorIndex,
|
|||||||
|
|
||||||
bool encoder_analog_load_detect(uint32 connectorIndex);
|
bool encoder_analog_load_detect(uint32 connectorIndex);
|
||||||
void encoder_output_lock(bool lock);
|
void encoder_output_lock(bool lock);
|
||||||
|
status_t transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
|
||||||
|
uint8 laneNumber, uint8 laneSet, int command);
|
||||||
void encoder_crtc_scratch(uint8 crtcID);
|
void encoder_crtc_scratch(uint8 crtcID);
|
||||||
void encoder_dpms_scratch(uint8 crtcID, bool power);
|
void encoder_dpms_scratch(uint8 crtcID, bool power);
|
||||||
void encoder_dpms_set(uint8 crtcID, uint8 encoderID, int mode);
|
void encoder_dpms_set(uint8 crtcID, uint8 encoderID, int mode);
|
||||||
|
|||||||
@@ -37,6 +37,8 @@ extern "C" void _sPrintf(const char* format, ...);
|
|||||||
status_t
|
status_t
|
||||||
pll_limit_probe(pll_info* pll)
|
pll_limit_probe(pll_info* pll)
|
||||||
{
|
{
|
||||||
|
radeon_shared_info &info = *gInfo->shared_info;
|
||||||
|
|
||||||
uint8 tableMajor;
|
uint8 tableMajor;
|
||||||
uint8 tableMinor;
|
uint8 tableMinor;
|
||||||
uint16 tableOffset;
|
uint16 tableOffset;
|
||||||
@@ -114,6 +116,12 @@ pll_limit_probe(pll_info* pll)
|
|||||||
pll->pllInMax = B_LENDIAN_TO_HOST_INT16(
|
pll->pllInMax = B_LENDIAN_TO_HOST_INT16(
|
||||||
firmwareInfo->info.usMaxPixelClockPLL_Input) * 10;
|
firmwareInfo->info.usMaxPixelClockPLL_Input) * 10;
|
||||||
|
|
||||||
|
if (info.dceMajor >= 4) {
|
||||||
|
pll->dpExternalClock = B_LENDIAN_TO_HOST_INT16(
|
||||||
|
firmwareInfo->info_21.usUniphyDPModeExtClkFreq);
|
||||||
|
} else
|
||||||
|
pll->dpExternalClock = 0;
|
||||||
|
|
||||||
TRACE("%s: referenceFreq: %" B_PRIu16 "; pllOutMin: %" B_PRIu16 "; "
|
TRACE("%s: referenceFreq: %" B_PRIu16 "; pllOutMin: %" B_PRIu16 "; "
|
||||||
" pllOutMax: %" B_PRIu16 "; pllInMin: %" B_PRIu16 ";"
|
" pllOutMax: %" B_PRIu16 "; pllInMin: %" B_PRIu16 ";"
|
||||||
"pllInMax: %" B_PRIu16 "\n", __func__, pll->referenceFreq,
|
"pllInMax: %" B_PRIu16 "\n", __func__, pll->referenceFreq,
|
||||||
|
|||||||
@@ -48,6 +48,9 @@ struct pll_info {
|
|||||||
/* pixel clock to be programmed (kHz)*/
|
/* pixel clock to be programmed (kHz)*/
|
||||||
uint32 pixelClock;
|
uint32 pixelClock;
|
||||||
|
|
||||||
|
/* external DisplayPort clock freq */
|
||||||
|
uint32 dpExternalClock;
|
||||||
|
|
||||||
/* flags for the current clock */
|
/* flags for the current clock */
|
||||||
uint32 flags;
|
uint32 flags;
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user